Multiplex Patents (Class 341/141)
  • Patent number: 10979030
    Abstract: The invention provides a system improving signal handling, e.g., transmission and/or processing. In an embodiment, the system may include a filter circuit, a magnitude bit truncation circuit and a utility circuit. The filter circuit may be coupled to a target signal which contains one or more desired signals at one or more interested bands, for attenuating each said interested band to form a filtered signal. The magnitude bit truncation circuit may be coupled to the filter circuit, for truncating one or more bits of each sample of the filtered signal to form a truncated signal. The utility circuit may be coupled to the magnitude bit truncation circuit, for handling the truncated signal to implement handling of the target signal, so as to reduce resource requirement and enhance error tolerance comparing with directly handling the target signal.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: April 13, 2021
    Assignee: MediaTek Inc.
    Inventors: Jen-Huan Tsai, Chih-Hong Lou
  • Patent number: 10951848
    Abstract: An image sensing system is disclosed. The image sensing system includes an array of pixel circuits and a multiplexer configured to convey an output signal from a selected one of the pixel circuits. The output signal from the selected one of the plurality of pixel circuits is converted from analog to digital by a successive approximation register (SAR) analog-to-digital converter (ADC). A control circuit is provided to cause the SAR ADC power cycling with shaped power control signal. The SAR ADC comparator pre-amp with integrate-reset causes reduced power to the theoretical limit for imaging systems. The control circuit causes quantization process of selected ones of the pixel circuits to be repeated one or more times during the processing.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: March 16, 2021
    Assignee: Apple, Inc.
    Inventors: Hyunsik Park, Ali Mesgarani, Mansour Keramat, Dusan Stepanovic, Ashirwad Bahukhandi
  • Patent number: 10917104
    Abstract: An analog to digital converter (ADC) sampling time control method includes: grouping, by an electronic control unit, analog sensor signals received from a plurality of sensors based on a similar signal; setting, by the electronic control unit, a sampling time for converting the grouped analog sensor signals into digital signals; and obtaining, by the electronic control unit, a sensor value by converting the grouped analog sensor signals into the digital signals based on the set sampling time.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: February 9, 2021
    Assignee: HYUNDAI AUTRON CO., LTD.
    Inventor: Tae Gyu Kang
  • Patent number: 10902767
    Abstract: A driving circuit of display apparatus includes an operational amplifier (OP), comprising a plurality of input terminals; a digital-to-analog converter (DAC); a multiplexer, coupled to the OP and the DAC, comprising a plurality of switches; and a boosting module, configured to decrease an equivalent time constant between the DAC and the OP to increase an output slew rate of the OP in a boosting period; wherein the boosting period is enabled before a steady state of the OP.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: January 26, 2021
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Tsung-Hau Chang, Chi-Wei Liu, Ping Chen
  • Patent number: 10868560
    Abstract: An ACD device comprises a comparator having an output, a first input, and a second input. The ADC includes a successive approximation register (SAR) configured to receive the output of the comparator as an input and to generate based thereon a parallel digital output having a most significant bit (MSB) and a plurality of less significant bits associated with a reference voltage Vref=M*VDD, where M<1. The ADC also includes a digital-to-analog converter (DAC) configured to receive the parallel digital output from the SAR and to generate based thereon an internal analog signal, the internal analog signal applied as the first input to the comparator.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Mei-Chen Chuang
  • Patent number: 10855305
    Abstract: A comparator is described. The comparator includes a differential pair having first and second transistors to respectively receive first and second input signals. The comparator also includes a current sink or source transistor coupled to respective source nodes of the first and second transistors. The current sink or source transistor is coupled to receive a fixed bias to keep the current sink transistor active so that large voltage changes on the source nodes is avoided. The comparator circuit includes a latch circuit coupled to respective drain nodes of the first and second transistors. The latch circuit is to reach a final state to present the comparator's output signal. The comparator includes a first switch circuit coupled between the first transistor's drain node and the latch circuit, and a second switch circuit coupled between the second transistor's drain node and the latch circuit.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: December 1, 2020
    Assignee: Intel Corporation
    Inventors: Roee Eitan, Ahmad B. Khairi, Yosi Sanhedrai, Ram Livne, Ilya Kraimer, Hen Sallem, Idan Lotan, Ariel Cohen, Dror Lazar
  • Patent number: 10833693
    Abstract: It is provided a provided a time-interleaved analog-to-digital converter (ADC) system comprising an input port configured to receive an analog signal, an ADC-array comprising M, M?2, ADCs arranged in parallel. Each ADC is configured to receive and to convert a portion of the analog signal into a digital signal at a sample rate fs. The ADC-system further comprises a reference ADC configured to receive and to convert the analog signal into a digital reference signal at an average sampling rate fref lower than fs. Each sampling instant of the reference ADC corresponds to a sampling instant of an ADC in the array of ADCs, and the ADC to select for each reference ADC sampling instant is randomized over time. The ADC-system also comprises a correction module configured to adjust the digital signal outputs of the ADC-array into a corrected digital output signal based on samples of the digital reference signal and the digital signals from the corresponding selected ADCs.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: November 10, 2020
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Vimar Björk, Claes Rolén
  • Patent number: 10763883
    Abstract: A digital-to-analog conversion circuit (DAC) is operable to convert an input digital signal to an output analog signal. The DAC includes a digital signal processing circuit operable to process the input digital signal according to a first transfer function to generate a first processed digital signal and process the digital input signal according to a second transfer function to generate a second processed digital signal. The DAC includes a first unit DAC operable to convert the first processed digital signal to a first intermediate analog signal, and a second unit DAC operable to convert the second processed digital signal to a second intermediate analog signal. The DAC includes switching circuits and a combiner circuit to generate the output analog signal from the intermediate analog signals.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: September 1, 2020
    Inventors: Baradwaj Vigraham, Rakesh Kumar Palani, Suman Sah
  • Patent number: 10740267
    Abstract: A digital interface circuit includes a queue block configured to be coupled between an analog-to-digital converter (ADC) and a Direct Memory Access (DMA) controller of a processor, where the queue block comprises a command buffer and is configured to: receive a first command from the DMA controller; store the first command in the command buffer; modify the first command in accordance with first control bits of the first command to generate a modified first command; and send the modified first command to the ADC.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: August 11, 2020
    Assignees: STMICROELECTRONICS INTERNATIONAL N.V., STMICROELECTRONICS APPLICATION GMBH
    Inventors: Nirav Prashantkumar Trivedi, Sandip Atal, Rolf Nandlinger
  • Patent number: 10727855
    Abstract: An analog-to-digital conversion apparatus includes a controller. The controller is configured to execute first control processing to cause the selection circuit of each of the circuit sets to perform switching which involves cyclically changing an analog signal to be selected at sampling timings with a predetermined time difference, and second control processing to calculate a digital data item at a reference sampling timing for each of the analog signals based on digital data items obtained from the analog-to-digital converter of the plurality of circuit sets, in accordance with the digital data items with the predetermined time difference, the sampling timings, and the time difference.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: July 28, 2020
    Assignee: CASIO COMPUTER CO., LTD.
    Inventor: Junichi Sugiyama
  • Patent number: 10700691
    Abstract: A circuit includes a first external terminal, a first lower resolution analog-to-digital converter (LRADC) coupled to the external terminal and configured to perform a first conversion of an analog signal received at the external terminal to a digital value, and a higher resolution analog-to-digital converter (HRADC). The HRADC is configured to selectively receive the analog signal from the first external terminal based on the digital value. When the digital value outputted by the first LRADC indicates a change in value of the received analog signal, the HRADC is provided with the analog signal and performs a second conversion of the analog signal to a second digital value. The first LRADC has a lower conversion resolution as compared to the HRADC.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: June 30, 2020
    Assignee: NXP USA, INC.
    Inventors: Srikanth Jagannathan, Christopher James Micielli, George Rogers Kunnen, Carl Culshaw
  • Patent number: 10630310
    Abstract: An integrated charge redistribution successive approximate register (CR-SAR) analog-to-digital converter (ADC) includes a sample-and-hold switch, a digital-to-analog converter (DAC), a comparator and a logic circuit. The sample-and-hold switch obtains a sample input voltage (Vin). The DAC includes a plurality of digital multiplexers that selects between a superposition phase, which superimposes an analog offset voltage onto Vin, and a conversion phase which determines values for a digital output register which determines the input values to each control line. Each digital multiplexer presents input values to a control line. The comparator has two inputs coupled to the sample-and-hold switch and to the DAC such that the output of the converter determines a value of each successive bit in the digital output register. The logic circuit is coupled to the comparator and to digital multiplexers and includes the digital output register.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: April 21, 2020
    Assignee: NXP B.V.
    Inventors: Alphons Litjes, Erik Olieman, Ibrahim Candan
  • Patent number: 10523154
    Abstract: An oscillator and method for operation of the oscillator are provided. The oscillator includes a control voltage generator configured to generate a control voltage based on dividing a power voltage that was received, an offset voltage generator configured to generate an offset voltage based on dividing the power voltage that was received, a phase locked loop (PLL) including a varactor circuit configured to modify a capacitance based on the control voltage and the offset voltage, and a calibration logic circuit configured to provide a selection control signal to the control voltage generator based on the oscillation signal, and configured to provide an offset control signal to the offset voltage generator based on the oscillation signal.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: December 31, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gyeongseok Song, Kang-jik Kim, Chang-kyung Seong, Hyung-jun Jung
  • Patent number: 10506182
    Abstract: An imaging device includes imaging elements 12 arranged in two-dimensional matrix in a first direction and a second direction, an analog-digital (AD) converter 13, and a pixel signal reading device 16. The pixel signal reading device 16 selects spatially at random the imaging element 12 that outputs a pixel signal to the AD converter 13, and randomly outputs the pixel signal of the imaging element 12 from the AD converter 13.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: December 10, 2019
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Kyoko Izuha, Kouichi Harada, Tomoo Mitsunaga, Hayato Wakabayashi, Koji Kadono
  • Patent number: 10483996
    Abstract: Apparatus and associated methods relate to modulating polarity on sample outputs from a time-interleaved analog-to-digital converter (TIADC) as an input to a time skew extractor in a clock skew calibration control loop. In an illustrative example, a multiplier-mixer may impart a polarity change to every other data sample transmitted between the TIADC and the time skew extractor. In some examples, a multiplexer may select between the polarity modulated samples and non-polarity modulated samples before the multiplier-mixer. Selection between the polarity modulated samples and the non-polarity modulated samples may be based on, for example, determination of specific frequency bands of an analog input signal. Various embodiments may improve convergence of clock skew calibration control loops for analog input signals sampled with a TIADC near a Nyquist frequency.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: November 19, 2019
    Assignee: XILINX, INC.
    Inventors: Christophe Erdmann, Bob W. Verbruggen, Ali Boumaalif, Bruno Miguel Vaz
  • Patent number: 10382111
    Abstract: Embodiments described herein include devices, methods, and instructions for managing beam interpolation in massive multiple-input multiple-output (MIMO) communications. In one example embodiment, an evolved node B is configured to transmit to a UE using massive MIMO by transmitting multiple beamformed reference signals on multiple transmission beams each associated with a different plurality of antennas. The eNB receives beam interpolation information back from the UE, and then generates a data transmission that is sent to the UE using an interpolated transmission beam from a first and second transmission beam.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: August 13, 2019
    Assignee: Intel IP Corporation
    Inventors: Yushu Zhang, Yuan Zhu, Huaning Niu, Qinghua Li, Jong-Kae Fwu
  • Patent number: 10333644
    Abstract: A method (10) of encapsulating digital communications signals for transmission on a communications link, comprising steps: a. receiving a first signal of a first signal type and comprising a first clock signal and receiving a second signal of a second signal type, different to the first, and comprising a second clock signal different to the first clock signal, each clock signal having a respective clock value and accuracy (12); b. obtaining the first clock signal (14); c. obtaining a difference between at least one of the clock values of the clock signals and the accuracies of the clock signals (16) and buffering the second signal for a time at least long enough to compensate for the difference (18); and d. assembling the first signal and the buffered second signal into a frame comprising an overhead and a payload comprising a first portion and a second portion, mapping the first signal into the first portion and the second signal into the second portion (20), wherein step d.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: June 25, 2019
    Assignee: Telefonaktiebolaget LM Ericsson (Publ)
    Inventors: Fabio Cavaliere, Giulio Bottari, Stefano Stracca
  • Patent number: 10291247
    Abstract: An example time-skew calibration circuit includes a plurality of first circuits, each including a first accumulator and a second accumulator. The time-skew calibration circuit further includes a plurality of second circuits, each including a first adder coupled to outputs of the first accumulator and the second accumulator, and a first subtractor coupled to the outputs of the first accumulator and the second accumulator. The time-skew calibration circuit further includes a decision circuit configured to combine an output of the first adder and an output of the first subtractor.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: May 14, 2019
    Assignee: XILINX, INC.
    Inventors: Bob W. Verbruggen, Christophe Erdmann, Bruno Miguel Vaz
  • Patent number: 10263635
    Abstract: Method and apparatus for nonlinear signal processing include mitigation of outlier noise in the process of analog-to-digital conversion and adaptive real-time signal conditioning, processing, analysis, quantification, comparison, and control. Methods, processes and apparatus for real-time measuring and analysis of variables include statistical analysis and generic measurement systems and processes which are not specially adapted for any specific variables, or to one particular environment. Methods and corresponding apparatus for mitigation of electromagnetic interference, for improving properties of electronic devices, and for improving and/or enabling coexistence of a plurality of electronic devices include post-processing analysis of measured variables and post-processing statistical analysis.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: April 16, 2019
    Inventor: Alexei V. Nikitin
  • Patent number: 10205388
    Abstract: An electronic device includes a power management integrated circuit (PMIC) including a plurality of regulators. Each of the plurality of regulators has a current meter configured to measure a respective load current. A load device is configured to receive real-time load current information from the PMIC and to perform a performance improvement operation based on the real-time load current information.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: February 12, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Minho Choi, Yus Ko, Dongjin Keum, Hwa Yeal Yu, Younghoon Lee
  • Patent number: 10181859
    Abstract: An Analog-to-Digital-Conversion control system includes a first sample and hold circuit configured to provide a first sampled output to be converted by an Analog-to-Digital-Converter, which comprises a first sampling control circuit configured to receive a first trigger information to trigger sampling of a first analog input and to receive a first collision detection information from the Analog-to-Digital-Converter to detect a collision, a first sample and hold stage coupled to the first sampling control circuit and configured to sample the first analog input, only if no collision has been detected by the first sampling control circuit, wherein the first sampling control circuit is further configured to check predefined first sampling criteria and to output a first conversion request to the Analog-to-Digital-Converter, only if the predefined first sampling criteria are fulfilled.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: January 15, 2019
    Assignee: Infineon Technologies AG
    Inventors: Jens Barrenscheen, Peter Bogner, Juergen Schaefer
  • Patent number: 10176747
    Abstract: A display driver is configured to drive a display device according to a video signal. The display signal includes a plurality of first to N-th output amplifiers (N is an integer greater than two) and an output electrical current capacity setting portion. The first to N-th output amplifiers are configured to amplify first to N-th gradation voltages a representing brightness level per pixel according to the video signal, so that the first to N-th output amplifiers obtain first to N-th pixel drive voltages. Further, the first to N-th output amplifiers are configured to output the first to N-th pixel drive voltages to the display device. The output electrical current capacity setting portion is configured to set an output electrical current capacity of each of the first to N-th output amplifiers individually or in a group of a plurality of output amplifiers.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: January 8, 2019
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Hideaki Hasegawa, Hideki Masai
  • Patent number: 10178617
    Abstract: A method of performing a hail communication attempt includes checking capacitor voltage of a capacitor in a battery pack powering a hailing device to determine whether the capacitor voltage equals or exceeds a threshold voltage, and responsive to determining that the capacitor voltage equals or exceeds the threshold voltage, transmitting a hail (ping) message to a target device, determining whether the hailing device has received a responsive pong message from the target device, and responsive to determining that the hailing device has received a responsive pong message, terminating the hail communication attempt in preparation for sending data to the target device. Hail communication attempts are limited according to a predetermined number of consecutive groups of consecutive hail messages, with the capacitor voltage check occurring before the sending of each group.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: January 8, 2019
    Assignee: Mueller International, LLC
    Inventors: David Edwin Splitz, Dale McLeod Magley
  • Patent number: 10117024
    Abstract: An audio processing device that includes a first ADC, a second ADC, a register and a processing circuit is provided. The processing circuit executes a first audio application program corresponding to a first analog input audio stream and assigns the first analog input audio stream to the first ADC. When the processing circuit identifies that a second audio application program also corresponds to the first analog input audio stream, the processing circuit control the first ADC to process the first analog input audio stream. When second audio application program corresponds to a second analog input audio stream, the processing circuit assigns the second analog input audio stream to the second ADC for processing such that the first and the second ADCs process the first and the second analog input audio stream respectively.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: October 30, 2018
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Yi-Huan Wang, Jin-Rong Chen
  • Patent number: 10116318
    Abstract: A method and apparatus are disclosed for asynchronous clock generation in analog-to-digital converters (ADCs). For example, an ADC may comprise a comparator, a first logic gate, a second logic gate, a first memory element, a second memory element, and a digital-to-analog converter (DAC). The comparator may initiate an evaluation or precharge operation of comparator inputs. The first logic gate may generate, based on comparator outputs, a first output signal indicating validity of first logic gate output. The second logic gate may generate a second output signal indicating timing reference of bit conversion. The first memory element may generate a third output signal indicating a current state of a bit. The second memory element may generate a plurality of next state bits based on the second output signal and the comparator outputs. The second logic gate may generate the second output signal based on the first and third output signals.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: October 30, 2018
    Assignee: Infinera Corporation
    Inventors: Shah Sharif, Fu-Tai An
  • Patent number: 10084469
    Abstract: A control system for an analog to digital converter (ADC) including a programmable configuration memory, a trigger selector, an input selector, and a conversion controller. The ADC is configurable for adjusting multiple operating parameters including speed and accuracy. The programmable configuration memory stores at least one configuration variable and an input value. The trigger selector enables at least one trigger input. The input selector selects from among multiple analog inputs according to the programmed input value. The conversion controller configures the ADC using the configuration variable, interfaces the input selector to provide an analog input to the ADC, and interfaces the trigger selector to prompt the ADC to perform a conversion process to provide a digital output sample in response to the enabled trigger input.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: September 25, 2018
    Assignee: SILICON LABORATORIES INC.
    Inventor: Marty Lynn Pflum
  • Patent number: 10079984
    Abstract: When imaging bright objects, a conventional detector array can saturate, making it difficult to produce an image with a dynamic range that equals the scene's dynamic range. Conversely, a digital focal plane array (DFPA) with one or more m-bit counters can produce an image whose dynamic range is greater than the native dynamic range. In one example, the DFPA acquires a first image over a relatively brief integration period at a relatively low gain setting. The DFPA then acquires a second image over longer integration period and/or a higher gain setting. During this second integration period, counters may roll over, possibly several times, to capture a residue modulus 2m of the number of counts (as opposed to the actual number of counts). A processor in or coupled to the DFPA generates a high-dynamic range image based on the first image and the residues modulus 2m.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: September 18, 2018
    Assignee: Massachusetts Institute of Technology
    Inventors: Michael W. Kelly, Megan H. Blackwell, Curtis B. Colonero, James Wey, Christopher David, Justin Baker, Joseph Costa
  • Patent number: 10075071
    Abstract: An electronic device includes a load device and a power management integrated circuit. The power management integrated circuit is configured to calculate a load power value and provide the load power value to the load device in response to a request from the load device. The power management integrated circuit includes a plurality of regulators and a controller. Each of the plurality of regulators includes a current meter for measuring a load current value to be provided to the load device, and the controller is configured to calculate the load power value by using the load current value measured by the current meter and a load voltage value provided from each of the plurality of regulators to the load device.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: September 11, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young Min Park, Young Hoon Lee, Yus Ko, Hwa Yeal Yu, Min Ho Choi
  • Patent number: 10075179
    Abstract: A multiple impedance string, multiple output digital-to-analog converter (DAC) circuit that can include a shared coarse resolution DAC, two first fine resolution DACs to receive outputs of the MSB DAC, and a multiplexer to multiplex outputs of the first and second fine resolution DACs to output terminals. The multiplexer can be configured to interchange coupling of the outputs of the first and second fine resolution DACs using one or more MSBs.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: September 11, 2018
    Assignee: Analog Devices Global
    Inventors: Michael D. Keane, Johan H. Mansson, Dennis A. Dempsey
  • Patent number: 10044360
    Abstract: Embodiments of the present disclosure may include an ADC circuit including channel register sets, a conversion request flip-flop, a priority encoder circuit, and a controller circuit. The controller circuit may be configured to receive a conversion request signal, latch the conversion request signal into the conversion request flip-flop, determine by the priority encoder circuit a highest priority pending conversion request, and output an active channel identifier code. The channel identifier code may be configured to select the data channel register sets that are active by identifying received selection bits. The embodiments may include logic to store a converted value from a selected analog input to a data output register based on the channel identifier code.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: August 7, 2018
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventor: Bryan Kris
  • Patent number: 10007244
    Abstract: A system includes an apparatus and a processor. The apparatus includes a set of actuator elements that move between two positions. Each actuator element is comprised in: exactly one first subset out of a plurality of non-empty first subsets and exactly one second subset out of a plurality of non-empty second subsets. The processor is configured to generate one or more control commands for a group of subsets out of the first and the second pluralities of subsets in response to a number of moving elements which, if released from the first extreme position during a second sampling cycle, enables production by the apparatus during the second sampling cycle of a sound.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: June 26, 2018
    Assignee: AUDIO PIXELS LTD.
    Inventors: Daniel Lewin, Yuval Cohen, Eric Andreas Haber, Shay Kaplan, Meir Ben Simon, Raanan Zacher
  • Patent number: 9973203
    Abstract: An interleaved DAC utilizes a set of positive sub-DACs and a set of negative sub-DACs for converting digital inputs in parallel without return to zero. For each digital input, a positive sub-DAC performs conversion and drives its analog output for a duration of N/fs; and a negative sub-DAC performs conversion and drives its analog output for a duration of (N?1)/fs; and by a delay of 1/fs. By combining the outputs from the two sets of sub-DACs, the output from the positive sub-DAC is effectively removed when it is no longer needed at the combined output. As a result, the combined analog signal has each data point valid only for a duration of T, thereby achieving the desired data conversion speed of fs.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: May 15, 2018
    Assignee: MACOM Connectivity Solutions, LLC.
    Inventors: Yehuda Azenkot, Nanda Govind Jayamaran
  • Patent number: 9946683
    Abstract: Techniques for reducing precision timing message uncertainty are described herein. A method includes resetting an elastic buffer of a first device in response to a second device linked with the first device sending SKIP (SKP) ordered sets to the first device. The method also includes initiating a PTM handshake with the second device in response to resetting the elastic buffer. Additionally, the method includes sending PTM messages to the second device immediately after receiving the SKP ordered sets.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: April 17, 2018
    Assignee: Intel Corporation
    Inventors: Daniel Froelich, David J. Harriman
  • Patent number: 9941893
    Abstract: An ADC includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: April 10, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Srinivas Kumar Reddy Naru, Visvesvaraya Pentakota Appala, Shagun Dusad, Neeraj Shrivastava, Viswanathan Nagarajan, Ani Xavier, Rishi Soundararajan, Sai Aditya Nurani, Roswald Francis
  • Patent number: 9906233
    Abstract: There is disclosed herein analogue-to-digital converter circuitry, comprising a set of sub-ADC units each for carrying out analogue-to-digital conversion operations, the set comprising a given number of core sub-ADC units for carrying out said given number of core conversion operations. Also provided is control circuitry operable, when a said sub-ADC unit is determined to be a defective sub-ADC unit, to cause the core conversion operations to be carried by the sub-ADC units of the set sub-ADC units other than the defective sub-ADC unit.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: February 27, 2018
    Assignee: SOCIONEXT INC.
    Inventors: John James Danson, Ian Juso Dedic, Prabhu Ashwin Harold Rebello
  • Patent number: 9843257
    Abstract: A controller for controlling a power converter includes an analog-to-digital converter (ADC) configured to output, based on a received analog voltage, a first digital value defined by a first resolution. The controller also includes a digital filter configured to adjust, based at least in part on the first digital value, a second digital value, wherein the second digital value is defined by a second resolution different from the first resolution. The controller further includes a pulse modulation device configured to output, based on a sum of the first digital value and the second digital value, a pulse modulated signal, wherein a frequency of the pulse modulated signal is defined by the second resolution.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: December 12, 2017
    Assignee: Infineon Technologies Austria AG
    Inventor: Pierrick Ausseresse
  • Patent number: 9838028
    Abstract: An A/D conversion circuit includes a reference voltage source to generate a calibration voltage, a multiplexer to receive an analog signal and the calibration voltage, and output the analog signal selected in a normal mode and the calibration voltage selected in a calibration mode or a self-diagnosis mode, an A/D converter to convert an output signal from the multiplexer into a digital signal, a non-volatile memory to hold the digital signal and calibration data, a digital calibration part to calibrate the digital signal in case of inputting the analog signal to the A/D converter in the normal mode based on the calibration data, and a self-diagnosis circuit to diagnose the A/D converter based on the digital signal in case of inputting the calibration voltage to the A/D converter in the self-diagnosis mode, and the digital signal stored in the non-volatile memory.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: December 5, 2017
    Assignee: ROHM CO., LTD.
    Inventors: Haruhisa Yamaguchi, Kinji Ito
  • Patent number: 9832493
    Abstract: A method and apparatus for processing an audio/video file. By determining an audio/video file to be processed and then determining loadable audio/video promotion information for the audio/video file according to at least one of attribute information about a target user and attribute information about the audio/video file, the disclosed embodiments can carry out a merge operation on the audio/video file and the audio/video promotion information.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: November 28, 2017
    Assignee: BEIJING YINZHIBANG CULTURE TECHNOLOGY CO., LTD.
    Inventors: Huaiyin Guo, Xu Zhang, Ming Xi
  • Patent number: 9767778
    Abstract: An apparatus for combining input signals produced by a plurality of electric musical devices includes a plurality of audio buses and a plurality of segments. Each segment includes input circuitry configured to receive at least one input signal from at least one electric musical device and to deliver the at least one input signal to one of the plurality of audio buses; a plurality of variable adjustment devices each associated with a corresponding one of the audio buses and each configured to change at least one property of an input signal received by another of the plurality of segments and carried on the corresponding one of the audio buses independent from input signals carried on other of the plurality of audio buses; and a mixer configured to combine the input signals carried on each of the plurality of audio buses into an output signal.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: September 19, 2017
    Assignee: JAMHUB CORPORATION
    Inventor: Steve Skillings
  • Patent number: 9743029
    Abstract: An analog to digital converting device includes an analog to digital converting unit suitable for converting an image signal into a digital signal; and a digital arithmetic unit suitable for calculating a difference between a reset voltage and a signal voltage, which correspond to the digital signal.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: August 22, 2017
    Assignees: SK Hynix Inc., Industry-University Cooperation Foundation Hanyang University
    Inventors: Ja Seung Gou, Oh Kyong Kwon, Min Kyu Kim
  • Patent number: 9652064
    Abstract: A touch display module, a driving method thereof and a source driver are provided. The touch display module includes a touch display panel and at least one source driver. The source driver is coupled to a plurality of data lines of the touch display panel. In a display mode, the source driver respectively outputs a plurality of pixel driving signals to the data lines for driving the touch display panel to display a corresponding image. In a touch mode, the source driver clusters the data lines into multiple groups, and respectively outputs a plurality of touch driving signals to the groups. The data lines belonging to a same group are provided with a same touch driving signal in the touch mode.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: May 16, 2017
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventors: Zhu-Rong Li, Yaw-Guang Chang
  • Patent number: 9588157
    Abstract: A current sense circuit for a PWM driver comprises: a PWM control circuit comprising: a first switching device arranged to receive a PWM signal from the PWM driver whose current is to be sensed; and a second switching device whose supply current is arranged to track the sensed current of the PWM driver. An ADC is operably coupled to the first and second switching device. The ADC comprises: a DAC arranged to provide a current sense to the second switching device that tracks the current passing through the PWM driver; a first comparator arranged to receive and compare an output current from the DAC and an output current from the first switching device; and a first successive approximation register arranged to receive an output from the comparator and provide: a first output to the ADC; and a second output that provides a representation of the sensed current.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: March 7, 2017
    Assignee: NXP USA, Inc.
    Inventors: Benoit Alcouffe, Jerome Casters, Tarek Hakam, Bernard Pierre Francois Pechaud
  • Patent number: 9537502
    Abstract: A system for calibrating time interleaved ADCs is disclosed and may include a time interleaved analog-to-digital converter (ADC) for converting analog signals to digital signals, the time interleaved ADC comprising: a plurality of active slices, and a plurality of reference slices, each reference slice associated with a corresponding one of the plurality of active slices. An output of each reference slice may be used to correct distortion in an output of the corresponding active slice. Each active slice may sample an input signal at a first rate and each associated reference slice may sample the input signal at a second rate, the second rate being slower than the first rate. Each sample taken by one of the plurality of reference slices may then be taken concurrent with a sample taken by the associated active slice. Each reference slice may include a reference sampling module and a dummy load.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: January 3, 2017
    Assignee: Entropic Communications, LLC
    Inventors: Josephus Van Engelen, Aaron Buchwald, Ralph Duncan
  • Patent number: 9479188
    Abstract: An example programmable multichannel data converter includes a multiplexer having a plurality of input channels, an output and a channel selector input, a converter having an input coupled to the output of the multiplexer, and a controller having a user-configurable memory stack and control circuitry, the controller having a channel selector output coupled to the multiplexer.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: October 25, 2016
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Martin T. Mason, Jamaal Mitchell
  • Patent number: 9444483
    Abstract: A switch circuit includes: a sampling transistor including a source connected to an input node and a drain connected to an output node; a control circuit which is connected to a gate of the sampling transistor and configured to control turning on or off of the sampling transistor; a voltage holding circuit which is provided between the gate and the source of the sampling transistor and configured to maintain a voltage between the gate and the source of the sampling transistor constant when the sampling transistor is turned on; and a protection circuit which is provided in parallel to the control circuit and configured to lower a voltage that is applied to the gate of the sampling transistor when the sampling transistor makes a transition from on to off.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: September 13, 2016
    Assignee: SOCIONEXT INC.
    Inventor: Seiji Okamoto
  • Patent number: 9432035
    Abstract: Multichannel successive approximation register (SAR) analog-to-digital converters (ADC), along with methods and systems for multichannel SAR analog-to-digital conversion, are disclosed herein. An exemplary multichannel SAR ADC can include a first SAR ADC for each of a plurality of input channels, and a second SAR ADC, a multiplexer, and a residue amplifier shared among the plurality of input channels. The multiplexer can select an analog residue signal from one of the first SAR ADCs for conversion by the second SAR ADC. The residue amplifier can amplify the selected analog residue signal. The second SAR ADC, multiplexer, and/or residue amplifier may be shared among all of the plurality of input channels. Where the multichannel SAR ADC includes N input channels, the second SAR ADC, multiplexer, and/or residue amplifier may be shared among b channels of the N input channels.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: August 30, 2016
    Assignee: Analog Devices, Inc.
    Inventors: Bhargav R. Vyas, Arvind Madan, Sandeep Monangi
  • Patent number: 9413394
    Abstract: An Interleaved Radio Frequency Digital-to-Analog Converter (RF DAC) suitable for use in cellular base stations and optimized to give both a wide RF tuning range and a wide RF bandwidth is disclosed. The RF DAC uses two levels of interleaving, the first providing a direct conversion path from Base Band (BB) to RF, and the second providing a variable interleaving factor through the use of summation to optimize the output bandwidth as a function of the RF center frequency. Digital Interpolation, including an arbitrary sample rate conversion filter, allows the RF DAC to operate from a wide range of possible BB sample rates and the DAC sample rate is a fixed ratio of the RF center frequency. As a result, the spurious outputs from the RF DAC are in known locations that are relatively easy to filter out, minimizing the frequency planning tasks required for a complete RF system design.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: August 9, 2016
    Assignee: Microsemi Storage Solutions (U.S.), Inc.
    Inventors: William Michael Lye, John B. Groe
  • Patent number: 9374102
    Abstract: A method and apparatus are configured to receive at a control input of an analog to digital converter (ADC) circuit, from a control output of a control circuit, a first instance of control information that indicates a conversion characteristic of the ADC, wherein the conversion characteristic is one of a first conversion rate and a first conversion resolution, to provide at a status output of the ADC status information regarding the conversion of a first analog signal by the ADC circuit, to receive at the control input of the ADC a second instance of the control information that adjusts the conversion characteristic to allocate a first portion of an ADC circuit bandwidth of the ADC circuit to continuing receiving the first analog signal and to allocate a second portion of the ADC circuit bandwidth to receiving a second analog signal.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: June 21, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Jeffrey T. Loeliger, Mark J. Stachew
  • Patent number: 9369142
    Abstract: The present invention provides a multi-channel time-interleaved analog-to-digital converter, including: a clock generation circuit, configured to generate a work clock of the analog-to-digital converter; a channel ADC group, including M ADC channels, and configured to convert, under the control of the clock generation circuit and in a time division multiplexing manner, one high-speed analog input signal into M low-speed digital output signals; a channel mismatch detection circuit, configured to detect in real time timing skew errors of output signals of the M ADC channels; a signal compensation and reconstruction circuit, configured to perform, according to the timing skew parameters detected, compensation and reconstruction on the digital output signals output by the channel ADC group; and a signal combining circuit, configured to combine the M low-speed output signals that are of the channels and generated after the compensation by the signal compensation and reconstruction circuit.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: June 14, 2016
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Bingsen Qiu
  • Patent number: 9337944
    Abstract: Systems and techniques for digital processing of FM stereo signals are described. According to an aspect, a method includes determining whether a received digital signal is a mono signal or a stereo signal, using a digital signal processor to process the received digital signal based on stereo transmission when the received digital signal is determined to be a stereo signal, and using the same digital signal processor to process the received digital signal based on mono transmission when the received digital signal is determined to be a mono signal.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: May 10, 2016
    Assignee: Marvell International Ltd.
    Inventor: Hui-Ling Lou