METHOD OF SELECTIVE OXYGEN IMPLANTATION TO DIELECTRICALLLY ISOLATE SEMICONDUCTOR DEVICES USING NO EXTRA MASKS
A method of fabricating integrated circuit structures utilizes selective oxygen implantation to dielectrically isolate semiconductor structures using no extra masks. Existing masks are utilized to introduce oxygen into bulk silicon with subsequent thermal oxide growth. Since the method uses bulk silicon, it is cheaper than silicon-on-insulator (SOI) techniques. It also results in bulk silicon that is latch-up immune.
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This application is a divisional of co-pending application Ser. No. 11/891,170, filed on Aug. 9, 2007, and which is the subject of a Notice of Allowance mailed on Feb. 17, 2010. application Ser. No. 11/891,170 is hereby incorporated by reference herein in its entirety.FIELD OF THE INVENTION
The present invention relates to integrated circuits and, in particular, to integrated circuit fabrication techniques that use existing masks to dielectrically isolate semiconductor devices using oxygen implantation and subsequent thermal oxide growth.DISCUSSION OF THE RELATED ART
One way to prevent latch-up in these structures is to move the N-well 108 and the n+ source/drain regions of the p-channel device 102 farther apart. This increases the width of the base of parasitic transistor Q2 and reduces Beta. Unfortunately, this approach also reduces circuit density, resulting in a larger die size.
Another approach to preventing latch-up in CMOS circuit structures is to utilize silicon-on-insulator (SOI) technology. SOI refers to the use of a layered silicon-insulator-silicon substrate in place of the bulk silicon approach discussed above. That is, in an SOI-based device, the silicon junctions of the n-channel device and the p-channel device are built above a layer of electrical insulator, typically silicon dioxide, that separates these devices from the bulk silicon substrate. One of the benefits of SOI technology relative to conventional bulk CMOS processing is a resistance to the latch-up phenomenon due to complete electrical isolation of the N-well and P-substrate structures.
U.S. Pat. No. 4,975,126, issued on Dec. 4, 1990, is an example of a publication that discloses techniques, including the well known SIMOX process, for forming SOI structures by implanting oxygen ions beneath the surface of a bulk silicon substrate, followed by a subsequent high temperature annealing step to form a buried layer of silicon dioxide.
A drawback of SOI-based technologies is the relatively high cost required to fabricate the SOI structure.SUMMARY OF THE INVENTION
The present invention provides a method of forming isolation dielectric for an integrated circuit structure. In general, the method comprises forming a mask over a silicon substrate, using the mask to implant oxygen into a the substrate, using the same mask to perform a further step in the integrated circuit fabrication process, and then performing a subsequent thermal step to cause the implanted oxygen to react to form a silicon oxide isolation structure.
In one embodiment of the invention, the general method is used to provide isolation dielectric for a bulk silicon CMOS circuit structure. In this particular embodiment, the oxygen implant is performed prior to formation of the CMOS circuit's buried layer using the buried layer mask, thereby avoiding the need for a high energy oxygen implant. The implanted oxygen is converted to isolating silicon oxide in the buried layer thermal anneal drive step. The isolation of the subsequently formed CMOS active device regions can be completed with the formation of a deep trench isolation structure. If the technology in use does not include deep trench isolation, then isolation can be achieved using suitable oxygen implant techniques, such as tilt implant, in combination with other isolation techniques if needed. Formation of a dielectric isolation structure for a bulk CMOS circuit in accordance with the concepts of the invention provides latch-up immunity for the circuit.
The features and advantages of the various aspects of the present invention will be more fully understood and appreciated upon consideration of the following detailed description of the invention and the accompanying drawings, which set forth an illustrative embodiment in which the concepts of the invention are utilized.
The present invention provides a method of selective oxygen implantation into a silicon substrate to electrically isolate semiconductor devices using existing masks.
More specifically, with reference to
In accordance with the concepts of the present invention, the photoresist mask PR utilized for introduction of the oxygen into the selected regions 306 of the silicon substrate 304 is also utilized to perform additional fabrication steps for the integrated circuit structure 300. For example, as shown in
With reference to
Those skilled in the art will appreciate that processing of the integrated circuit structure can then proceed in accordance with well known techniques to complete a desired final integrated circuit structure.
As discussed above, the concepts of the present invention are most applicable and easy to implement in the case of integrated circuit technologies that utilized buried layers, deep trench isolation and/or epitaxial silicon growth. For example, as stated above, the oxygen can be implanted into the substrate silicon using the buried layer mask before the buried layer implant, thus not requiring very high energy for the oxygen implant. By subsequent oxidation, a completely isolated device region can be achieved when the deep trench isolation meets the oxide.
With reference to
It should be understood that the particular embodiments of the invention described above have been provided by way of example and that other modifications may occur to those skilled in the art without departing from the scope and spirit of the invention as express in the appended claims and their equivalents.
1. A method of fabricating isolation dielectric in an integrated circuit structure, the method comprising:
- forming a patterned mask over a p-type silicon substrate;
- using the patterned mask to introduce oxygen into a first selected region of the silicon substrate, the first selected region being beneath an upper surface area of the silicon substrate that is exposed by the patterned mask;
- using the patterned mask to introduce p-type dopant into a second selected region of the silicon substrate to form a p-type buried layer in the silicon substrate, the second selected region being beneath the upper surface area of the silicon substrate that is exposed by the patterned mask and above the first selected region into which the oxygen has been introduced;
- performing a buried layer thermal anneal step that causes the oxygen in the first selected region to react to form a silicon oxide layer beneath the buried layer;
- forming an epitaxial silicon layer over the buried layer;
- forming a deep trench isolation structure in the silicon substrate that intersects with the silicon oxide layer to define an active device region that includes the buried layer and the epitaxial layer.
2. The method of claim 2, wherein the step of forming a deep trench isolation structure comprises forming spaced-apart deep trench isolation structures that intersect with the silicon oxide layer to form a first active device region and a second active device region that is separated from the first active device region by intervening deep trench isolation structure and such that the second active device region includes a well of p-type conductivity formed therein, the method further comprising:
- forming a well of n-type conductivity in the first active device region;
- forming a PMOS device structure in the n-type well; and
- forming a NMOS device in the p-type well.
3. A method of fabricating dielectric isolation for an integrated circuit structure, the method comprising:
- forming a patterned mask over a silicon substrate;
- using the patterned mask to introduce oxygen into a selected region of the silicon substrate, the selected region having an upper surface that extends to a first depth beneath an upper surface of the silicon substrate and a lower surface that extends to a second depth beneath the upper surface of the silicon substrate, the second depth being greater than the first depth;
- using the patterned mask to perform a further step in the formation of the integrated circuit structure;
- performing a thermal step to cause the oxygen in the selected region of the silicon substrate to react to form a silicon oxide layer having upper and lower surfaces beneath the upper surface of the silicon substrate; and
- forming a deep trench isolation structure in the silicon substrate that intersects with the silicon oxide layer to define an active device region.
4. The method of claim 3, wherein the patterned mask comprises resist.
International Classification: H01L 21/762 (20060101);