Using Trench Refilling With Dielectric Materials (epo) Patents (Class 257/E21.546)
  • Patent number: 11171206
    Abstract: An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate to form an active area of the apparatus. The first source/drain region and the second source/drain region are separated by a channel. The apparatus includes a gate opposing the channel. A sense line is coupled to the first source/drain region and a storage node is coupled to the second source/drain region. An isolation trench is adjacent to the active area. The trench includes a dielectric material with a conductive bias opposing the conductive bias of the channel in the active area.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: November 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Haitao Liu, Si-Woo Lee, Fatma Arzum Simsek-Ege, Deepak Chandra Pandey, Chandra V. Mouli, John A. Smythe, III
  • Patent number: 11164959
    Abstract: A method of forming a semiconductor device and resulting structures having an etch-resistant interlayer dielectric (ILD) that maintains height during a top epitaxy clean by forming a dielectric layer on a semiconductor structure; wherein the dielectric layer includes a first dielectric material; converting at least a portion of the dielectric layer to a second dielectric material; and exposing the portion of the dielectric layer to an etch material; wherein the etch material includes a first etch characteristic defining a first rate at which the etch material etches the first dielectric material; and wherein the etch material further includes a second etch characteristic defining a second rate at which the etch material etches the portion of the dielectric layer; wherein the first rate is different than the second rate.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: November 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 11069774
    Abstract: A shallow trench isolation structure and a semiconductor device. The shallow trench isolation structure includes a substrate; at least one trench located at a top surface of the substrate; and a first dielectric layer, a second dielectric layer and a third dielectric layer that are sequentially stacked on an inner wall of each of the at least one trench. A topmost surface of the first dielectric layer is lower than a topmost surface of the second dielectric layer and the top surface of the substrate, to form a first groove between the second dielectric layer and the substrate. An edge corner between the top surface of the substrate and the inner wall of each of the at least one trench is in a shape of a fillet curve. The fillet structure is smooth and round without a sharp corner, reducing point discharge and improving reliability of the shallow trench isolation structure.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: July 20, 2021
    Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Huixian Lai, Yu Cheng Tung, Chao-Wei Lin, Chiayi Chu
  • Patent number: 11018049
    Abstract: A manufacturing method of an isolation structure includes the following steps. A semiconductor substrate is provided. A trench is formed in the semiconductor substrate. A first film forming process is performed to form a first dielectric layer conformally on the semiconductor substrate and conformally in the trench. An annealing process is performed to densify the first dielectric layer and convert the first dielectric layer into a second dielectric layer. A thickness of the second dielectric layer is less than a thickness of the first dielectric layer. A second film forming process is performed after the annealing process to form a third dielectric layer on the second dielectric layer and in the trench. The trench is filled with the second dielectric layer and the third dielectric layer.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: May 25, 2021
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yu-Shan Su, Chia-Wei Wu
  • Patent number: 11011547
    Abstract: A method for forming an electronic device comprising a first transistor and a second transistor, from a stack of layers comprising an isolating layer surmounted on an active layer made of a semi-conductive material, the method comprising at least the following steps: Forming an isolating trench to define, in the active layer, at least one first active region and at least one second active region, said isolating trench protruding with respect to the active layer of the second active region; Forming a masking layer without covering the active layer of the second active region and without covering a portion of the isolating trench; Etching: of a portion of the thickness of the active layer of the second active region, and of at least one portion of the thickness of said portion of the isolating trench.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: May 18, 2021
    Assignee: X-FAB France
    Inventors: Pascal Costaganna, Pierre De Person, Michel Aube, Corentin Boulo
  • Patent number: 10885623
    Abstract: A method of detecting a joint failure of a semiconductor die stack is provided. The method may include providing the semiconductor die stack including a base substrate, a lower semiconductor die stacked on the base substrate, and an upper semiconductor die stacked on the lower semiconductor die opposite to the base substrate. The lower semiconductor die may include first through silicon vias (TSVs). Heat may be supplied to a bottom surface of the base substrate opposite to the lower semiconductor die. A thermographic image of a top surface of the upper semiconductor die opposite to the lower semiconductor die may be obtained. Whether the joint failure exists in the semiconductor die stack may be discriminated, with the thermographic image, based on a temperature difference between regions of the thermographic image corresponding with regions of the first TSVs.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: January 5, 2021
    Assignee: SK hynix Inc.
    Inventor: Hae Won Jung
  • Patent number: 10879106
    Abstract: A method for fabricating conductive deep trenches in conjunction with shallow trench isolations in a semiconductor device. The disclosed method introduces an integrated sequence during which a shallow trench is etched and filled before a deep trench is etched and filled. The disclosed method advantageously reduces cone defects and process complexity associated with the formation of a conductive deep trench within a shallow trench isolation structure. Fabricated under the integrated sequence, the conductive deep trench may extend through a shallow trench dielectric layer and into the substrate, where the top surfaces of both the conductive deep trench and shallow trench dielectric layer are substantially cone free.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: December 29, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Thomas Edward Lillibridge
  • Patent number: 10854713
    Abstract: A method includes forming a flowable dielectric layer in a trench of a substrate; curing the flowable dielectric layer; and annealing the cured flowable dielectric layer to form an insulation structure and a liner layer. The insulation structure is formed in the trench, the liner layer is formed between the insulation structure and the substrate, and the liner layer includes nitrogen.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: December 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jia-Ming Lin, Shiu-Ko Jangjian, Chun-Che Lin, Ying-Lang Wang, Wei-Ken Lin, Chuan-Pu Liu
  • Patent number: 10847612
    Abstract: A method of manufacturing a memory structure including the following steps is provided. Stacked structures are formed on a substrate, and each of the stacked structures includes a first dielectric layer and a first conductive layer sequentially disposed on the substrate. A first opening is located between two adjacent stacked structure, and the first opening extends into the substrate. At least one isolation structure is formed in the first opening. The isolation structure covers a sidewall of the first dielectric layer. The isolation structure has a recess therein, such that a top profile of the isolation structure is shaped as a funnel. A second dielectric layer is formed on the stacked structures. A second conductive layer is formed on the second dielectric layer and fills the first opening.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: November 24, 2020
    Assignee: Winbond Electronics Corp.
    Inventors: Chung-Hsien Liu, Chun-Hsu Chen, Lu-Ping Chiang
  • Patent number: 10818511
    Abstract: The disclosure provides a plane polishing method and a processing method of the silicon wafer. The plane polishing method includes steps of: depositing a hard mask on a silicon substrate to form a silicon wafer base material; forming an opening on the hard mask by photolithography or etching; carrying out an oxidation reaction on a portion of the silicon substrate exposed by the opening, forming an oxide layer having a bottom embedded in the silicon substrate and a top protruding and exposed outside the hard mask by oxidizing the silicon substrate; and polishing the oxide layer by chemical mechanical planarization. In the present disclosure, the surface formed by the oxide layer and the hard mask flat is flat, without a recess even in the case of large structures, thereby precisely controlling a shape and a depth of the cavity in accordance with an oxidation rate on a silicon substrate.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: October 27, 2020
    Assignee: AAC Acoustic Technologies (Shenzhen) Co., Ltd.
    Inventors: Lieng Loo, Wooicheang Goh, Kahkeen Lai
  • Patent number: 10784144
    Abstract: A disclosed example to modulate slit stress in a semiconductor substrate includes a first controller to, after obtaining a wafer stress measurement of the semiconductor substrate, control a first process to apply a first material to the semiconductor substrate based on the wafer stress measurement, the semiconductor substrate including a slit between adjacent stacked transistor layers, the first material coating walls of the slit to reduce a first width of the slit between the adjacent stacked transistor layers to a second width; and a second controller to control a second process to apply a second material to the semiconductor substrate, the second material to be deposited in the second width of the slit, the first material and the second material to form a solid structure in the slit between the adjacent stacked transistor layers.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: September 22, 2020
    Assignee: Intel Corporation
    Inventors: James Mathew, Yunjun Ho, Zhiqiang Xie, Hyun Sik Kim
  • Patent number: 10622442
    Abstract: The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: April 14, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Zailong Bian, Janos Fucsko
  • Patent number: 10597290
    Abstract: A process for filling one or more etched holes defined in a frontside surface of a wafer substrate. The process includes the steps of: depositing a layer of a thermoplastic first polymer onto the frontside surface and into each hole until the holes are overfilled with the first polymer; depositing a layer of a photoimageable second polymer different than the first polymer; selectively removing the second polymer from regions outside a periphery of the holes; exposing the wafer substrate to a controlled oxidative plasma so as to reveal the frontside surface of the wafer substrate; and planarizing the frontside surface to provide holes filled with a plug of the first polymer only, each plug having a respective upper surface coplanar with the frontside surface.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: March 24, 2020
    Assignee: Memjet Technology Limited
    Inventors: Angus North, Ronan O'Reilly, Gregory McAvoy
  • Patent number: 10593801
    Abstract: Semiconductor devices and methods of fabricating the same are provided. The methods of fabricating the semiconductor devices may include providing a substrate including an active pattern protruding from the substrate, forming a first liner layer and a field isolating pattern on the substrate to cover a lower portion of the active pattern, forming a second liner layer on an upper portion of the active pattern and the field isolation pattern, and forming a dummy gate on the second liner layer.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: March 17, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Jong Lee, Sanghyuk Hong, TaeYong Kwon, Sunjung Kim, Cheol Kim
  • Patent number: 10593773
    Abstract: A laterally diffused metal oxide silicon (LDMOS) transistor and a method of making the LDMOS transistor are disclosed. The LDMOS transistor includes a drain drift region formed in a substrate and containing a drain contact region. A gate structure overlies a channel region in the substrate and a first shallow-trench isolation (STI) structure is formed between the drain contact region and the channel region. The first STI structure contains a high-k dielectric and a second STI structure contains silicon dioxide.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: March 17, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Umamaheswari Aghoram, Pushpa Mahalingam, Alexei Sadovnikov, Eugene C Davis
  • Patent number: 10571631
    Abstract: A photonic structure can include in one aspect one or more waveguides formed by patterning of waveguiding material adapted to propagate light energy. Such waveguiding material may include one or more of silicon (single-, poly-, or non-crystalline) and silicon nitride.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: February 25, 2020
    Assignee: THE RESEARCH FOUNDATION FOR THE STATE UNIVERSITY OF NEW YORK
    Inventors: Douglas Coolbaugh, Thomas Adam, Gerald L. Leake
  • Patent number: 10566194
    Abstract: Methods, systems, and computer programs are presented for selective deposition of etch-stop layers for enhanced patterning during semiconductor manufacturing. One method includes an operation for adding a photo-resist material (M2) on top of a base material (M1) of a substrate, M2 defining a pattern for etching M1 in areas where M2 is not present above M1. The method further includes operations for conformally capping the substrate with an oxide material (M3) after adding M2, and for gap filling the substrate with filling material M4 after the conformally capping. Further, a stop-etch material (M5) is selectively grown on exposed surfaces of M3 and not on surfaces of M4 after the gap filling. Additionally, the method includes operations for removing M4 from the substrate after selectively growing M5, and for etching the substrate after removing M4 to transfer the pattern into M1. M5 adds etching protection to enable deeper etching into M1.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: February 18, 2020
    Assignee: Lam Research Corporation
    Inventors: Nagraj Shankar, Kapu Sirish Reddy, Jon Henri, Pengyi Zhang, Elham Mohimi, Bhavin Jariwala, Arpan Pravin Mahorowala
  • Patent number: 10559496
    Abstract: A method of device processing. The method may include providing a cavity in a layer, directing energetic flux to a bottom surface of the cavity, performing an exposure of the cavity to a moisture-containing ambient, and introducing a fill material in the cavity using an atomic layer deposition (ALD) process, wherein the fill material is selectively deposited on the bottom surface of the cavity with respect to a sidewall of the cavity.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: February 11, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Kurtis Leschkies, Steven Verhaverbeke
  • Patent number: 10522365
    Abstract: Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and protrusions over the substrate. The protrusions are interposed by trenches. The method further includes depositing a first dielectric layer over the protrusions and filling the trenches. The first dielectric layer has a first hardness. The method further includes treating the first dielectric layer with an oxidizer. The method further includes performing a chemical mechanical planarization (CMP) process to the first dielectric layer.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wan-Chun Pan, William Weilun Hong, Ying-Tsung Chen
  • Patent number: 10504965
    Abstract: Solid-state imaging devices, electronic apparatuses, and methods of forming image sensors are provided. A solid-state imaging device or an electronic apparatus incorporating a solid-state imaging device can include a substrate and at least a first photoelectric conversion element formed in the substrate. In addition, a region with a low dielectric constant is formed. The region can include a locally thin region formed in the substrate. An insulating film is at the first side of the substrate. Where the region includes a locally thin region, the interlayer insulating film can extend into that locally thin region. A first electrode is at a side of the interlayer insulating film opposite the substrate. The device further includes a second electrode, and a photoelectric conversion layer at least partially between the first electrode and the second electrode.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: December 10, 2019
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Tetsuji Yamaguchi, Satoshi Keino
  • Patent number: 10475700
    Abstract: A method for reducing wiggling in a line includes forming a first patterning layer over a metal feature and depositing a first mask layer over the first patterning layer. The first mask layer is patterned to form a first set of one or more openings therein and then thinned. The pattern of the first mask layer is transferred to the first patterning layer to form a second set of one or more openings therein. The first patterning layer is etched to widen the second set of one or more openings. The first patterning layer may be comprised of silicon or an oxide material. The openings in the first patterning layer may be widened while a mask layer is over the first patterning layer.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: November 12, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Wei Huang, Cheng-Li Fan, Yu-Yu Chen
  • Patent number: 10453677
    Abstract: A method of forming an oxide layer includes the following steps. A substrate is provided. A surface of the substrate is treated to form an oxygen ion-rich surface. A spin-on-dielectric layer is formed on the oxygen ion-rich surface of the substrate. The present invention also provides a method of forming an oxide layer including the following steps. A substrate is provided. A surface of the substrate is treated with a hydrogen peroxide (H2O2) solution or a surface of the substrate is treated with oxygen containing gas, to form an oxygen ion-rich surface. A spin-on-dielectric layer is formed on the oxygen ion-rich surface of the substrate.
    Type: Grant
    Filed: July 9, 2017
    Date of Patent: October 22, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Cheng-Hsu Huang, Jui-Min Lee, Ching-Hsiang Chang, Yi-Wei Chen, Wei-Hsin Liu, Shih-Fang Tzou
  • Patent number: 10424574
    Abstract: A method is presented for forming a layout of a MOSFET (metal oxide semiconductor field effect transistor) circuit. The method includes forming a plurality of gate conductors, forming a plurality of active areas, and forming at least one gate contact (CB contact) within an active region of the plurality of active regions. The method further includes placing a marker over the at least one gate contact to identify a location of the at least one gate contact. Additionally, a distance between the at least one gate contact and at least one TS contact is optimized based on device specifications.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: September 24, 2019
    Assignee: International Business Machines Corporation
    Inventors: Albert M. Chu, Myung-Hee Na, Ravikumar Ramachandran
  • Patent number: 10424576
    Abstract: A method is presented for forming a layout of a MOSFET (metal oxide semiconductor field effect transistor) circuit. The method includes forming a plurality of gate conductors, forming a plurality of active areas, and forming at least one gate contact (CB contact) within an active region of the plurality of active regions. The method further includes placing a marker over the at least one gate contact to identify a location of the at least one gate contact. Additionally, a distance between the at least one gate contact and at least one TS contact is optimized based on device specifications.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: September 24, 2019
    Assignee: International Business Machines Corporation
    Inventors: Albert M. Chu, Myung-Hee Na, Ravikumar Ramachandran
  • Patent number: 10355088
    Abstract: The present invention provides a MOS (Metal-Oxide-Silicon) device having mitigated threshold voltage roll-off and a threshold voltage roll-off mitigation method therefor. The MOS device includes: a substrate, a well region, an isolation region, a gate, two LDDs (Lightly-Doped-Drains), a source, a drain and a compensation doped region. The compensation doped region is substantially in contact with at least a part of a recessed portion along the channel length direction. Viewing from a cross-section view, at a boundary where the compensation doped region is in contact with the isolation region along the channel length direction, the compensation doped region has two doped region widths along the channel width direction, wherein, the two doped region widths of the compensation doped region are both not greater than 10% of the width of the operation region. Two doped region widths are defined as distances within an interior part and an exterior part of the operation region, respectively.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: July 16, 2019
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Tsung-Yi Huang, Ying-Shiou Lin
  • Patent number: 10332882
    Abstract: A semiconductor device and a method for fabricating the semiconductor device are provided in the present disclosure. The semiconductor device includes a substrate including a first active region and a second active region divided by a shallow trench isolation (STI) region, a protective structure located on the STI region, a first semiconductor structure on the first active region, and a second semiconductor structure on the second active region of the substrate including a high-k dielectric layer and a metal gate layer over the high-k dielectric layer. The method for fabricating the semiconductor device is a process of the high-k dielectric layer deposited before the formation of the first and second semiconductor structures.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: June 25, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Harry Hak-Lay Chuang, Wei-Cheng Wu
  • Patent number: 10304925
    Abstract: An object of the invention is to provide a semiconductor device having improved performance. A method of manufacturing a semiconductor device includes: forming a trench and then forming a first insulating film made of a silicon oxide film through CVD using a gas containing an O3 gas and a TEOS gas to cover the side surface of the trench with the insulating film; forming a second insulating film made of a silicon oxide film through PECVD to cover the side surface of the trench with the second insulating film via the first insulating film; and forming a third insulating film made of a silicon oxide film through CVD using a gas containing an O3 gas and a TEOS gas to close the trench with the third insulating film while leaving a space in the trench.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: May 28, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tatsunori Murata, Takahiro Maruyama
  • Patent number: 10302504
    Abstract: The disclosure provides simple, low-cost but accurate systems and related methods for on-die temperature sensing typically using calibration and without the need for precision voltage references. In some implementations, the system utilizes two user selectable temperature sensing elements and two user selectable DACs to provide a digital code for the sensed temperature. In some implementations, the two sensing elements can be used to calibrate against each other. For example, calibration can be useful to account for silicon local/global variation. Typically, one of the temperature sensors is diode-based, while the other is resistor-based. However, those of skill in the art will recognize that, in accordance with the disclosure, more than two sensors can be provided that can be calibrated against one another.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: May 28, 2019
    Assignee: XILINX, INC.
    Inventors: Suresh P. Parameswaran, Boon Y. Ang, Ankur Jain
  • Patent number: 10217742
    Abstract: A semiconductor device includes circuit active fin lines and circuit gate lines intersecting each other in a circuit active region, dummy active fin lines and dummy gate lines intersecting each other in a dummy active region, the active fin lines and the dummy active fin lines having same width and pitch, and the circuit gate lines and the dummy gate lines having same width and pitch, wherein at least some of the dummy active fin lines are aligned with and collinear with respective circuit active fin lines, and at least some of the dummy gate lines are aligned with and collinear with respective circuit gate lines.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: February 26, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: In Wook Oh, Jae Seok Yang, Jong Hyun Lee, Hyun Jae Lee, Sung Wook Hwang
  • Patent number: 10115640
    Abstract: A method of manufacturing an integrated circuit device includes providing a substrate with a pattern structure, the pattern structure including a plurality of first patterns that extend in a first direction, are parallel to one another, and are separated from one another with a space therebetween. At least one support structure that contacts an upper surface of the pattern structure and extends on the pattern structure in a second direction that crosses the first direction is formed. A buried layer that fills the spaces between the plurality of first patterns while the at least one support structure contacts the upper surface of the pattern structure is formed. The at least one support structure is separated from the pattern structure.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: October 30, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hee-don Hwang, Young-wook Park, Min-woo Kim, Yoo-jin Jeong
  • Patent number: 10103141
    Abstract: A method includes forming a plurality of trenches extending from a top surface of a semiconductor substrate into the semiconductor substrate, with semiconductor strips formed between the plurality of trenches. The plurality of trenches includes a first trench and second trench wider than the first trench. A first dielectric material is filled in the plurality of trenches, wherein the first trench is substantially fully filled, and the second trench is filled partially. A second dielectric material is formed over the first dielectric material. The second dielectric material fills an upper portion of the second trench, and has a shrinkage rate different from the first shrinkage rate of the first dielectric material. A planarization is performed to remove excess second dielectric material. The remaining portions of the first dielectric material and the second dielectric material form a first and a second STI region in the first and the second trenches, respectively.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: October 16, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Tang Peng, Tai-Chun Huang, Hao-Ming Lien
  • Patent number: 9984893
    Abstract: A method of making a semiconductor device includes patterning a fin in a substrate; performing a first etching process to remove a portion of the fin to cut the fin into a first and second cut fin, the first cut fin having a first and second fin end and the second cut fin having a first and second fin end; forming an oxide layer along an endwall of the first fin end and an endwall of the second fin end of the first cut fin, and an endwall of the first fin end and an endwall of the second fin end of the second cut fin; disposing a liner onto the oxide layer disposed onto the endwall of the first fin end of the first cut fin to form a bilayer liner; and performing a second etching process to remove a portion of the second cut fin.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: May 29, 2018
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC.
    Inventors: Kangguo Cheng, Ruilong Xie, Tenko Yamashita
  • Patent number: 9953858
    Abstract: To provide a semiconductor device having improved performance. The semiconductor device has a first insulating film formed on the main surface of a semiconductor substrate and a second insulating film formed on the first insulating film. The semiconductor device further has a first opening portion penetrating through the second insulating film and reaching the first insulating film, a second opening portion penetrating through the first insulating film and reaching the semiconductor substrate, and a trench portion formed in the semiconductor substrate. A first opening width of the first opening portion and a second opening width of the second opening portion are greater than a trench width of the trench portion. The trench portion is closed by a third insulating film while leaving a space in the trench portion.
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: April 24, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tadashi Yamaguchi
  • Patent number: 9953861
    Abstract: A method includes a patterned hard mask layer formed over a substrate. The substrate is etched using the patterned hard mask layer to form a trench therein but leaving at least one elongated portion of the substrate inside the trench. A first isolation layer is formed over the patterned hard mask layer. The first isolation layer fills the trench and covers the at least one elongated portion of the substrate. A portion of the first isolation layer is removed to expose the at least one elongated portion of the substrate. The at least one elongated portion of the substrate is thereafter removed to form a first opening. A second isolation layer is formed over the first opening, the patterned hard mask layer, and the first isolation layer, the second isolation layer sealing the first opening to form an air gap.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: April 24, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Li Lin, Yi-Fang Li, Geng-Shuoh Chang, Chun-Sheng Wu, Po-Hsiung Leu, Ding-I Liu
  • Patent number: 9951418
    Abstract: Disclosed is a method for preparing structured graphene on a SiC substrate on the basis of Cl2 reaction, the procedures are as follows: firstly, performing standard cleaning to a SiC sample chip; depositing a layer of SiO2 on the surface of the SiC sample chip and engraving a figure window on the SiO2 layer; then arranging the windowed sample chip in a quartz tube, introducing a mixed gas of Ar and Cl2 into the quartz tube, reacting the bare SiC with Cl2 for 3-8 min at 700-1100° C. to generate a carbon film; arranging the generated carbon film in Ar gas, annealing for 10-30 min at 1000-1200° C. to generate the structured graphene on the window on the carbon film. The method is simple and safe; the generated structured graphene has a smooth surface and low porosity and can be used for making microelectronic devices.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: April 24, 2018
    Assignee: XIDIAN UNIVERSITY
    Inventors: Hui Guo, Keji Zhang, Yuming Zhang, Pengfei Deng, Tianmin Lei, Fengqi Zhang
  • Patent number: 9935000
    Abstract: A disclosed example to modulate slit stress in a semiconductor substrate includes controlling a first process to apply a first material to a semiconductor substrate. The semiconductor substrate includes a slit between adjacent stacked transistor layers. The first material coats walls of the slit to reduce a first width of the slit between the adjacent stacked transistor layers to a second width. A second process is controlled to apply a second material to the semiconductor substrate. The second material is to be deposited in the second width of the slit. The first material and the second material are to form a solid structure in the slit between the adjacent stacked transistor layers.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: April 3, 2018
    Assignee: Intel Corporation
    Inventors: James Mathew, Yunjun Ho, Zhiqiang Xie, Hyun Sik Kim
  • Patent number: 9935180
    Abstract: A method of making a semiconductor device includes patterning a fin in a substrate; performing a first etch to remove a portion of the fin to cut the fin into a first cut fin and a second cut fin, the first cut fin having a first and second fin end and the second cut fin having a first and second fin ends; forming an oxide layer along an endwall of the first fin end and an endwall of the second fin end of the first cut fin, and an endwall of the first fin end and an endwall of the second fin end of the second cut fin; disposing a liner onto the oxide layer disposed onto the endwall of the first fin end of the first cut fin to form a bilayer liner; and performing a second etch to remove a portion of the second cut fin.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: April 3, 2018
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Kangguo Cheng, Ruilong Xie, Tenko Yamashita
  • Patent number: 9922868
    Abstract: Integrated circuits and methods for manufacturing the same are provided. A method for producing an integrated circuit includes forming a deep isolation block in an SOI substrate, where the SOI substrate includes a substrate layer overlying a buried insulator that in turn overlies a carrier wafer. The deep isolation block extends through the substrate layer and contacts the buried insulator. A shallow isolation block is formed in the substrate layer, where the shallow isolation block overlies a portion of the substrate layer. An isolation mask is formed overlying at least a portion of the deep isolation block to form a masked isolation block and an exposed isolation block, where the exposed isolation block includes the shallow isolation block. The exposed isolation block is removed such that a trough is defined in the substrate layer where the shallow isolation block was removed, and a gate is formed within the trough.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: March 20, 2018
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Rui Tze Toh, Guan Huei See, Shaoqiang Zhang, Raj Verma Purakh
  • Patent number: 9893190
    Abstract: A fin field effect transistor (fin FET) is formed using a bulk silicon substrate and sufficiently guarantees a top channel length formed under a gate, by forming a recess having a predetermined depth in a fin active region and then by forming the gate in an upper part of the recess. A device isolation film is formed to define a non-active region and a fin active region in a predetermined region of the substrate. In a portion of the device isolation film a first recess is formed, and in a portion of the fin active region a second recess having a depth shallower than the first recess is formed. A gate insulation layer is formed within the second recess, and a gate is formed in an upper part of the second recess. A source/drain region is formed in the fin active region of both sides of a gate electrode.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: February 13, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Keun-Nam Kim, Hung-Mo Yang, Choong-Ho Lee
  • Patent number: 9847422
    Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: December 19, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Hwan Kim, Hun-Hyeoung Leam, Tae-Hyun Kim, Seok-Woo Nam, Hyun Namkoong, Yong-Seok Kim, Tea-Kwang Yu
  • Patent number: 9831154
    Abstract: The present disclosure provides a semiconductor structure. The structure includes a first substrate; a first dielectric layer having a first surface in proximity to the first substrate and a second surface away from the first substrate; a first interconnect penetrating the first surface of the first dielectric layer; and a protection layer extending along a portion of a sidewall of the first interconnect. A thickness of the protection layer is in a range of from about 0.02 ?m to about 0.2 ?m.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: November 28, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tsung-Han Tsai, Volume Chien, Yung-Lung Hsu, Chung-Bin Tseng, Keng-Ying Liao, Po-Zen Chen
  • Patent number: 9793268
    Abstract: The present disclosure provides a method for forming a semiconductor structure. The method includes providing a substrate including a plurality of fin structures on the substrate; coating a first solution on the substrate to form a first dielectric layer; and coating a second solution on the first dielectric layer to form a second dielectric layer to cover the fin structures. The first solution has a first viscosity. The second solution has a second viscosity. In some embodiments, the second viscosity is greater than the first viscosity.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: October 17, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ying-Hao Su, Yu-Chung Su, Yu-Lun Liu, Chi-Kang Chang, Chia-Chu Liu, Kuei-Shun Chen
  • Patent number: 9786542
    Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate having an upper surface. The semiconductor device also includes a recess extending from the upper surface into the semiconductor substrate. The semiconductor device further includes an isolation structure in the recess, and the isolation structure has an upper portion and a lower portion.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: October 10, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zih-I Chuang, Chun-Ta Wu, Chia-Lun Chang
  • Patent number: 9728570
    Abstract: The present disclosure relates to a BSI image sensor with improved DTI structures, and an associated method of formation. In some embodiments, the BSI image sensor comprises a plurality of image sensing elements disposed within a substrate corresponding to a plurality of pixel regions. A deep trench isolation (DTI) grid is disposed between adjacent image sensing elements and extending from an upper surface of the substrate to positions within the substrate. The DTI grid comprises air-gaps disposed under the upper surface of the substrate, the air-gaps having lower portions surrounded by a first dielectric layer and some upper portions sealed by a second dielectric layer.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: August 8, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Ting Chiang, Ching-Chun Wang, Dun-Nian Yaung, Hsiao-Hui Tseng, Chih-Hui Huang, Shyh-Fann Ting, Shih Pei Chou, Sheng-Chan Li
  • Patent number: 9698154
    Abstract: A semiconductor device includes a substrate, a plurality of memory cell arrays, and an air gap structure. The substrate includes a cell region, a peripheral circuit region, and a boundary region. The boundary region is between the cell region and the peripheral circuit region. The plurality of memory cell arrays are on the cell region. The air gap structure includes a trench formed in the boundary region of the substrate. The air gap structure defines an air gap.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: July 4, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joon Sung Lim, Kyu Baik Chang, Sung Hoi Hur, Woo Jung Kim
  • Patent number: 9691767
    Abstract: A manufacturing method of a semiconductor device according to a disclosed embodiment includes: implanting a first impurity into a first region of a semiconductor substrate, forming a semiconductor layer on the semiconductor substrate, forming a trench in the semiconductor layer and the semiconductor substrate, forming an isolation insulating film in the trench, implanting a second impurity into a second region of the semiconductor layer, forming a first gate insulating film and a first gate electrode in the first region, forming a second gate insulating film and a second gate electrode in the second region, forming a first source region and a first drain region at both sides of the first gate electrode, and forming a second source region and a second drain region at both sides of the second gate electrode.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: June 27, 2017
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Kazushi Fujita, Taiji Ema, Mitsuaki Hori, Yasunobu Torii
  • Patent number: 9659785
    Abstract: A method of making a semiconductor device includes patterning a fin in a substrate; performing a first etching process to remove a portion of the fin to cut the fin into a first cut fin and a second cut fin, the first cut fin having a first fin end and a second fin end and the second cut fin having a first fin end and a second fin end; forming an oxide layer along an endwall of the first fin end and an endwall of the second fin end of the first cut fin, and an endwall of the first fin end and an endwall of the second fin end of the second cut fin; disposing a liner onto the oxide layer disposed onto the endwall of the first fin end of the first cut fin to form a bilayer liner; and performing a second etching process to remove a portion of the second cut fin.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: May 23, 2017
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDIRES INC.
    Inventors: Kangguo Cheng, Ruilong Xie, Tenko Yamashita
  • Patent number: 9647093
    Abstract: A method of making a semiconductor device includes patterning a fin in a substrate; performing a first etching process to remove a portion of the fin to cut the fin into a first cut fin and a second cut fin, the first cut fin having a first fin end and a second fin end and the second cut fin having a first fin end and a second fin end; forming an oxide layer along an endwall of the first fin end and an endwall of the second fin end of the first cut fin, and an endwall of the first fin end and an endwall of the second fin end of the second cut fin; disposing a liner onto the oxide layer disposed onto the endwall of the first fin end of the first cut fin to form a bilayer liner; and performing a second etching process to remove a portion of the second cut fin.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: May 9, 2017
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC.
    Inventors: Kangguo Cheng, Ruilong Xie, Tenko Yamashita
  • Patent number: 9583356
    Abstract: A method for forming a semiconductor device structure is provided. The semiconductor device structure includes forming a film over a substrate. The semiconductor device structure includes forming a first mask layer over the film. The semiconductor device structure includes forming a second mask layer over the first mask layer. The second mask layer exposes a first portion of the first mask layer. The semiconductor device structure includes performing a plasma etching and deposition process to remove the first portion of the first mask layer and to form a protection layer over a first sidewall of the second mask layer. The first mask layer exposes a second portion of the film after the plasma etching and deposition process. The semiconductor device structure includes removing the second portion using the first mask layer and the second mask layer as an etching mask.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: February 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Keng-Ying Liao, Chung-Bin Tseng, Po-Zen Chen, Yi-Hung Chen, Yi-Jie Chen
  • Patent number: 9549465
    Abstract: Provided are a printed circuit board and a method of manufacturing the same, the printed circuit board according to the present invention, the printed circuit board, including: an insulating substrate having a plurality of circuit pattern grooves formed on a surface thereof; and a plurality of circuit patterns formed by burying the circuit pattern grooves, wherein the circuit patterns protrude as much as a predetermined thickness from an upper surface of the insulating substrate.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: January 17, 2017
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Chang Woo Yoo, Yeong Uk Seo, Byeong Ho Kim, Hyun Seok Seo, Sang Myung Lee, Ki Do Chun