NON-LINEAR CONDUCTOR MEMORY

Abstract

A high-speed, low-power memory device comprises an array of non-linear conductors wherein the storage, address decoding, and output detection are all accomplished with diodes or other non-linear conductors. In various embodiments, the row and column resistors are switchable between a high resistance when connected to a row or column that is non-selected, and a low resistance when connected to the selected row and column.

Description

FIELD OF THE INVENTION

The present invention relates to the design of memory devices and, in particular, to the design of high-performance, low-power memory devices utilizing an array of non-linear conductors.

CROSS-REFERENCE TO RELEVANT PATENTS

This application makes reference to U.S. Pat. No. 5,673,218 by Shepard titled “Dual-Addressed Rectifier Storage Device,” issued Sep. 30, 1997, which is hereby incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

Diode-based information-processing devices have existed for more than half a century and many forms of diode-decoded devices have been disclosed in the prior art. See, e.g., U.S. Pat. Nos. 2,686,299; 2,872,664; and 4,661,927. These prior-art approaches have both advantages and limitations.

SUMMARY OF THE INVENTION

In accordance with embodiments of the present invention, a low-power diode memory device comprises an array of non-linear conductors (e.g., diodes). The storage, address decoding, and output detection are all accomplished with diodes or other non-linear conductors, and the device can operate at high speed while consuming low power. By decoding and selecting a single row and column within the storage array (or within a tiled sub-region of the array), it is possible to place a desired voltage (or voltage range) across a storage bit within that storage array (or tiled sub-region) for reading or writing.

Accordingly, in a first aspect, the invention features an electronic memory device including information circuitry for storing and facilitating retrieval of information, row and column switches, and selection circuitry for reading or writing to the information circuitry by selecting a row and column switch. The information circuitry includes two overlapping pluralities of generally parallel conductors, storage locations at each point of overlap, and nonlinear conductive devices disposed at least at some of the storage locations.

Embodiments of the invention may include one or more of the following features. The selection circuitry for selecting one of the row switches may include circuitry for increasing the impedance of the non-selected row switches relative to that of the selected row switch. The circuitry for increasing the impedance of the non-selected row switches may include a first array of nonlinear conductive elements connected to the row switches. Each nonlinear conductive element in the first array may include a diode. The selection circuitry for selecting one of the column switches may include circuitry for increasing the impedance of the non-selected column switches relative to that of the selected column switch. The circuitry for increasing the impedance of the non-selected column switches may include a second array of nonlinear conductive elements connected to the column switches. Each nonlinear conductive element in the second array may include a diode.

In an embodiment, each row switch and/or column switch includes or consists essentially of an enhancement-mode NMOS transistor. At least one of the nonlinear conductive devices may be connected to the first and second pluralities of generally parallel conductors at approximately a point of overlap of the two pluralities. Each of the nonlinear conductive devices may include a diode, a fuse, an antifuse, or a phase-change material.

Some embodiments of the invention include row decoder circuitry between the row switches and the first plurality of generally parallel conductors, as well as column decoder circuitry between the column switches and the second plurality of generally parallel conductors. The row decoder circuitry may include a third array of nonlinear conductive elements, each of which may include a diode. The column decoder circuitry may include a fourth array of nonlinear conductive elements, each of which may include a diode.

In a second aspect, the invention features a method including providing an electronic memory device which includes a grid of memory locations and selection circuitry therefor. The grid includes a plurality of rows and row switches associated therewith, as well as a plurality of columns and column switches associated therewith A pre-charge voltage is applied to the row and column switches. A row switch is selected by discharging the pre-charge voltage on all but the selected row switch, and a column switch is selected by discharging the pre-charge voltage on all but the selected column switch. A row voltage is applied to the row switches, thereby increasing the voltage on the selected row connected to the selected row switch. A column voltage is applied to the column switches, thereby decreasing the voltage on the selected column connected to the selected column switch.

In an embodiment, application of the row and column voltages changes the state of the nonlinear conductive device located at the memory location proximate the intersection of the selected row and the selected column. In another embodiment, application of the row and column voltages outputs the state of the nonlinear conductive device located at the memory location proximate the intersection of the selected row and the selected column.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 schematically illustrates a prior-art dual-addressed rectifier storage device;

FIG. 2 schematically illustrates a diode-decoded storage device in accordance with an embodiment of the invention;

FIG. 3 is a timing diagram of the diode-decoded storage device in accordance with an embodiment of the invention;

FIG. 4 schematically illustrates a simplified variation of a diode-decoded storage device in accordance with an embodiment of the invention; and

FIG. 5 schematically illustrates a simplified variation on the output circuitry of a diode-decoded storage device in accordance with an embodiment of the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

A device in accordance with U.S. Pat. No. 5,673,218 is shown in FIG. 1. In that patent, power 109, in the form of V_PP, is applied to row lines 110-117 through resistors 101, and that power is diverted away from all but one row line by diode decoder 102 when complementary address input bits 103 are applied. Complementary address input bits 103 are applied as low-voltage signals (typically, zero volts or “Ground”) on one of each row address signal pair inputs (here A0 through A2 and their complements). Specifically, for row lines 110-117, an address is applied to row-address inputs 103. If the row address to be applied is “000” then a zero-volt signal is applied to A0, A1 and A2 while A0, A1, and A2 are left floating (e.g., floating or connected to a high impedance or a high voltage near or above V_PP). When these inputs are applied through diode row-address decoder 102, A0 causes rows 111, 113, 115, and 117 to be pulled low (to within one diode forward voltage drop of Ground), A1 causes rows 112, 113, 116, and 117 to be pulled low, and A2 causes rows 114-117 to be pulled low. Only selected row 110 remains at the applied high voltage V_PP. Furthermore, complementary input bits are applied as high-voltage signals on one of each column-address signal-pair inputs (here A3 through A5 and their complements). Specifically, for column lines 120-127, an address is applied to column-address inputs 104. If the column address to be applied is “000” then a higher voltage signal (for example, about 3 volts) is applied to A3, A4, and A5, while A3, A4 and A5 are left low (e.g., floating or connected to a high impedance or to a voltage at or near Ground). When these inputs are applied through diode column-address decoder 108, A3 causes columns 122, 124, 126, and 128 to be forced high (to within one diode forward-voltage drop of the column-address input voltage), A4 causes columns 120, 121, 124, 125 to be forced high, and A5 causes columns 120-123 to be forced high. Only column 127 remains selected at the applied low-voltage input 106 of Ground supplied through one of resistors 105. This approach carries a tradeoff between operating speed and power. For high-speed operation, resistors 101 and 105 should be small so that the parasitic capacitances of the diode storage matrix 107 will not cause operation to be slower than desired (since operation speed is a function of the RC time constant of those resistors and the parasitic capacitances of the diodes and the array, among other things). But, for low power consumption, the resistors 101, 105 should be large so that power loss is minimized when the row decoder 102 pulls the non-selected rows low and the column decoder 108 forces the non-selected columns high. A feature of embodiments of the present invention is improvement upon this tradeoff by making these resistors 101, 105 effectively switchable between a high resistance when connected to a row or column that is non-selected and a low resistance when connected to a selected row or column.

FIG. 2 shows a simplified schematic of an embodiment of the present invention. Through the introduction of switches 201, 205, the above-mentioned tradeoff between speed and power can be controlled. In an embodiment, switches 201, 205 include or consist essentially of enhancement-mode NMOS transistors. As such, the terms “switch” and “transistor” are utilized interchangeably herein in reference to switches 201, 205, and 233. In various embodiments, other switching devices, such as bipolar, depletion-mode, and/or PMOS transistors, may be utilized. In some embodiments, all transistors in the circuit are of the same type to facilitate manufacturing and to decrease complexity and cost, while in other embodiments, two or more different types of switching devices are included. In addition, other functionality, such as the generation of complementary row-address inputs (e.g., with transistors 231 as shown in FIG. 4) and the generation of complementary column-address inputs (e.g., with transistors 232 as shown in FIG. 4), may be added. In an exemplary embodiment, all of the transistor gates are turned on at once by pre-charging the gates of the transistors through pre-charge diodes 237 by applying a positive pre-charge voltage at the pre-charge (PCH) input 238. This PCH input voltage is preferably high enough to switch on the transistors, allowing for the forward voltage drop of pre-charge diodes 237 and threshold voltages of the transistors, if any. Switches 201, along with diode decoder 234, are analogous to resistors 101 in FIG. 1. Likewise, switches 205, along with diode decoder 235, are analogous to resistors 105 in FIG. 1.

The operation of diode decoders 234 and 235 is similar to the operation of those described with reference to FIG. 1 (i.e., diode row-address decoder 102 and diode column-address decoder 108). The gates of transistors 201 are pre-charged to a voltage (one that will enable array voltage V_PP 209 to be passed through transistors 201 to the storage array), and then all but one of those transistor gates are discharged to ground through diode decoder 234 as a function of row-address inputs 203 applied to A0-A2 and A0, A1, and A2. When the gate of one of transistors 201 is discharged (as all but one will be during normal operation), that transistor acts like a very high-resistance resistor (i.e., it is shut off) supplying V_PP to its corresponding row line. The one remaining transistor having its gate charged will act like a very low-resistance resistor supplying V_PP to its selected row line. The row-address diode decoder 202 operates just as row-address diode decoder 102 does in FIG. 1. The diodes in internal row-address decoder 202 act as clamps against rising voltages and work in complementary fashion with the transistor to each row: the transistor is available to drive the row voltage high and the diodes are available to pull the row voltage low.

For the columns of the storage array, the gates of transistors 205 are pre-charged to a voltage that will enable voltage on the columns in the array to be passed through those transistors 205 through transistor 206 to ground when G_PP has a high turn-on voltage applied, and then all but one of those transistor gates are discharged to ground through diode decoder 235 as a function of column-address inputs 204 applied to A3-A5 and A3- A5. If the gate of one of transistors 205 is discharged (as all but one will be during normal operation), that transistor acts like a very high-resistance resistor supplying ground to its corresponding column line. The one remaining transistor having its gate charged will act like a very low-resistance resistor supplying ground to its selected column line. The column-address diode decoder 235 operates just as column address diode decoder 108 does in FIG. 1. The diodes in internal column address decoder 208 act as clamps against falling voltages and work in complementary fashion with the transistor to each column: the transistor is available to pull the column voltage low and the diodes are available to clamp the column voltage high. To provide the internal column decoder with the complementary address-pair high voltages, transistors 233 act as voltage inverters to low-going address lines A3-A5 and A3- A5; specifically, the gates of transistors 233 are pre-charged through diodes 237 (as are all other transistor gates) and then are selectively discharged through the diode selector 236 to provide the high-voltage complementary address pairs (as is done on address inputs 104 in FIG. 1) to internal column address decoder 208.

The timing diagram shown in FIG. 3 illustrates the sequence of operation for both reading and writing the array according to one embodiment of the invention. In this figure, the time durations and signal heights are for illustration only and are not to scale. Referring to both FIGS. 2 and 3, a write cycle begins at time t₀ with the application of high-voltage PCH at input PCH 238. This causes the gates (G and G′) of transistors to be charged (where G′ is the voltage on the gates of transistors to drive the selected row and the selected column). The voltage on the gates rises until time t₁ and has fully settled by t₂, at which point the PCH voltage is removed. In an embodiment of the invention, the interval t₁→t₂ is approximately zero seconds. At time t₃, the address inputs are applied to row-address inputs 203 and column-address inputs 204. These inputs are only low- (e.g., ground-) going inputs and may, for example, be driven by open collector or single-sided MOS driver circuits. Row-address signals A0-A2 and complementary row-address signals A0- A2 discharge the gates to transistors 201 through diode decoder 234. By time t₄, the voltage G on non-selected gates of transistors 201 is discharged. At the same time, column address signals A3-A5 and complementary column address signals A3- A5 discharge the gates to transistors 205 through diode decoder 235. By time t₄, the voltage G on non-selected gates of transistors 205 is discharged.

By time t₅, the charge on the gates of all transistors has settled and the low voltages to the rows have been established by means of diode clamping through diode row decoder 202. At time t₅, the column bias voltage V_CB is applied to input 239 and high voltages to the columns are established by diode clamping through diode column decoder 208 (note COL and COL′ at interval t₅→t₆). This voltage is selected to bias the non-selected columns in storage array 207 such that the voltage across the diodes connecting the selected row (once V_PP is applied) and the non-selected columns is at zero volts or lower (i.e., the diodes are reverse-biased). In an embodiment of the invention, column bias voltage V_CB is approximately equal to V_PP. In an embodiment of the invention, column bias voltage V_CB is approximately equal to V_PP plus one forward voltage drop of a diode, V_f (i.e., V_PP is V_f greater than V_CB). By time t₆, one row transistor and one column transistor will be switched on; the non-selected columns will be biased to a high voltage and the non-selected rows will be biased to a low voltage.

During a write cycle, at time t₆, the programming voltages V_PP and G_PP are applied and held until time t₇. V_PP will cause the selected row (ROW′) to be driven high and G_PP will cause the selected column (COL′) to be pulled low. The duration of the interval t₆→t₇ is determined by the time needed to change the state of the programmable material in series with the diodes of the storage array 207. In an embodiment, the programmable material is an antifuse, e.g., a 20 Angstrom (Å) SiO₂ antifuse that can change states in approximately 1 to 2 microseconds at a V_PP programming voltage of greater than approximately 6 volts. In other embodiments, the programmable material includes at least one of a fuse, a phase-change material such as a chalcogenide, or other materials that (i) change resistivity as a function of the current passed therethrough, (ii) change resistivity as a function of the voltage placed thereacross, or (iii) change resistivity as a function of the temperature applied thereto. At time t₈, the write cycle is complete. The read cycle timing is very similar to the write cycle except that the voltages PCH, V_CB, and V_PP are lower and the time interval t₆→t₇ may be much shorter (merely long enough for the row and column voltages to settle and be sensed at the output or outputs 240; in an embodiment, the time interval is less than approximately 1 microsecond) and the output is sensed at time t₇ after removing V_PP and just prior to removing voltage inputs V_CB and G_PP. In an embodiment of the invention, voltage input G_PP is applied approximately as V_PP is removed; in this way, the selected row is charged up to approximately V_PP and V_PP is removed. Then, if a nonlinear element (e.g., a diode) is present at the addressed location, the row is discharged to ground when G_PP is applied (if no connection via a nonlinear element is present at the addressed location, the row remains charged up to approximately V_PP).

To minimize power consumption, as is indicated in FIG. 3 by the dim traces for COL, COL′ and G′, the columns and gates of the selected transistors can be left charged between read and write cycles. Also, the address inputs may be either asserted low or are high-impedance. This is an advantage for the address inputs because, to fully turn on the transistors 201, 205 to drive the row lines and the column lines, respectively, the voltage needed on the transistor gates is a function of the voltages on the sources and drains of those transistors (which varies depending upon whether the device is being read or written). A controller or control logic to this device which can switch the voltage level on V_PP is present in one embodiment of the invention. This capability may add complexity to that signal's circuitry, but the address bits' signal circuitry can be made the same for both modes of operation.

It should be noted that the exemplary embodiment of the invention shows address decoding and line selection being made for both the row lines and the column lines with output detection being made with complementary outputs from the array. One output signal is generated on a single conductor that is connected to every row line by a non-linear conductor (e.g., a diode), and the other output signal is generated on a single conductor that is connected to every column line by a non-linear conductor (e.g., a diode). Variations on this output embodiment include implementing only the row-connected output without the column-connected output (or vice versa), whereby the voltage level on the selected line (or the current that can be drawn by virtue of the voltage level on the selected line) is detected. Other variations on this output embodiment include address decoding and line selection along one dimension of the array, whereby data bit information is available in parallel on another plane of the array upon which data bit bit-address decoding and selection is performed.

In another embodiment, shown in FIG. 4, the output circuit 241 connects each row to the gate of a field-effect transistor (“FET”). The sources of these output FETs connected to each row may be wired together, the drains may be wired together, and these parallel row output transistors may be biased such that if one row is at a higher voltage, that row's FET is switched on. In this variation, V_PP is preferably turned off prior to reading, as the V_PP signal would resist being pulled low by the selected column if a diode connection were present. With V_PP turned off, the voltage on the selected row line will be pulled down by a diode connected to the selected column. FIG. 4 also shows complementary address generation where the gates of transistors 231, 232 are pre-charged by diodes 237 and selectively discharged when address inputs 203, 204 are applied.

In yet another embodiment, shown in FIG. 5, the output circuit 242 is utilized. The ground signal to the columns is turned off, thereby allowing the selected column to be pulled high if a nonlinear element (e.g., a diode) is connected to the selected column line from the selected row line (typically, V_PP would be continuously applied but could be switched off, in which case the charge balancing, if any, between the selected column and selected row would be measured). It should be noted that by putting the output FETs on the row lines, the selected column may be retained when V_PP is turned off, thereby enabling a new row line to be selected without selecting a new column line (separate pre-charge input paths are preferred for the row lines and the column lines). Conversely, by putting the output FETs on the column lines, the selected row can be retained when Ground is turned off, thereby enabling a new column line to be selected without selecting a new row line. As will be clear to one skilled in the art, with the output FETs on the rows, each FET's source and drain may be biased to switch on when its gate is at a high voltage and off when the gate are at a low voltage; with only one row high (enabled) at a time, only one row FET may be switched on at a time. With the output FETs on the columns, depletion-mode FETs are preferably used for the output transistors, each FET's source and drain may be biased to switch off when its gate is at a high voltage and on when its gate is at a low voltage; with only one column low (enabled) at a time, only one column FET may be switched on at a time. These two output variations may be used together by switching off both V_PP and Ground.

In another embodiment of this invention, either or both of the internal row decoders 202 and column decoders 208 of FIG. 2, 4, or 5 are excluded. This is because the switches 201, 205 are sufficient to select one row and one column of the array while keeping the remaining rows and columns in a high-impedance state. When removing the internal row and column decoders, V_CB can be turned off at time t₆ (as it could be even when the internal decoders are present) to conserve power (i.e., prevent power consumption by leakage). However, internal row and column decoders may be preferred because they guard against leakage currents from the switches 201, 205. The internal row and column decoders also guard against bad bits in the storage array that leak currents that could energize rows and columns other than the selected row and column. To maximally protect against such a fault, multiple internal row and column decoders can be incorporated. These decoders may be present on either or both sides of the array; the top and/or bottom of the array; or even within the area of the array. V_CB may be turned off at time t₇ to guard against this type of bad-bit fault.

In another embodiment, the transistors are present in a layer other than the layer comprising the storage array. Embodiments of the present invention find applicability in memory devices implemented in a three-dimensional (3-D) configuration, for example, as is disclosed in U.S. Pat. No. 6,956,757, the entire disclosure of which is hereby incorporated by reference. In yet another embodiment, the switching devices include or consist essentially of devices other than enhancement-mode NMOS transistors, e.g., NMOS, PMOS, bi-polar, enhancement-mode, depletion-mode, BJT, JFET, MOSFET, FET, thin-film, TFT, SCR, UJT, triac, vacuum tube, gated field emitter, and/or MEMS-based switching devices.

Embodiments of the present invention find applicability in memory devices comprising an array of multiple sub-arrays whereby the device is tiled into many sub-arrays. One or more of these sub-arrays is accessed at the same time for reading or writing multiple bits of information; fewer than all of the sub-arrays may be accessed at one time to conserve power. Embodiments of the present invention also find applicability in memory devices comprising an array of multiple sub-arrays whereby the device is tiled into many sub-arrays for other purposes. These memory devices may be designed and produced using well known techniques including the use of CAD and CAM tools, photolithographic processing, topography based lithographic processing, inkjet-printed or organic semiconductor processing, and/or MEMS processing, among others.

The approach of the present invention may be applied to memory devices and systems for storing digital text, digital books, digital music, digital audio, digital photographs (wherein one or more digital still images can be stored including sequences of digital images), digital video, digital cartography (wherein one or more digital maps can be stored), and any other digital or digitized information as well as any combinations thereof. Devices incorporating embodiments of the invention may be embedded or removable, and may be interchangeable among other devices that can access the data therein. Embodiments of the invention may be packaged in any variety of industry-standard form factor, including Compact Flash, Secure Digital, MultiMedia Cards, PCMCIA Cards, Memory Stick, any of a large variety of integrated circuit packages including Ball Grid Arrays, Dual In-Line Packages (DIPs), SOICs, PLCC, TQFPs and the like, as well as in proprietary form factors and custom designed packages. These packages can contain just the memory chip, multiple memory chips, one or more memory chips along with other logic devices or other storage devices such as PLDs, PLAs, micro-controllers, microprocessors, controller chips or chip-sets or other custom or standard circuitry.

The foregoing description of an example of the preferred embodiment of the invention and the variations thereon have been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by any claims appended hereto.

Claims

1-23. (canceled)

24. A system for storing and retrieving digital information, the system comprising:

a first array of nonlinear conductive devices for information storage therein and retrieval therefrom, each device being addressable by one of a plurality of row lines and one of a plurality of column lines;

a plurality of row switches, each row switch providing a variable-impedance connection between one of the plurality of row lines and a row voltage source; and

a row-address decoder for selecting, using a second array of nonlinear conductive devices, one of the plurality of row switches, thereby causing an impedance of the selected row switch to be lower than impedances of the non-selected row switches.

25. The system of claim 24, further comprising an internal row-address decoder for clamping, using a fourth array of nonlinear conductive devices, voltages of the non-selected row lines.

26. The system of claim 24, further comprising:

a plurality of column switches, each column switch providing a variable-impedance connection between one of the plurality of column lines and a column voltage source; and

a column-address decoder for selecting, using a third array of nonlinear conductive devices, one of the plurality of column switches, thereby causing an impedance of the selected column switch to be lower than impedances of the non-selected column switches.

27. The system of claim 26, further comprising an internal column-address decoder for clamping, using a fourth array of nonlinear conductive devices, voltages of the non-selected column lines.

28. The system of claim 24, wherein the row and column switches are disposed in a first layer and the first array of nonlinear conductive devices is disposed in a second layer.

29. The system of claim 24, wherein the first array of nonlinear conductive devices comprises a plurality of sub-arrays simultaneously addressable by the row and column lines.

30. The system of claim 29, wherein the sub-arrays are tiled.

31. The system of claim 24, wherein the nonlinear conductive devices comprise at least one of a diode, a fuse, an antifuse, a phase-change material, a resistance-change material, or a chalcogenide material.

32. The system of claim 24, wherein a first row switch comprises an enhancement-mode transistor, a depletion-mode transistor, an NMOS transistor, a PMOS transistor, or a bipolar transistor.

33. The system of claim 32, wherein a second row switch comprises an enhancement-mode transistor, a depletion-mode transistor, an NMOS transistor, a PMOS transistor, or a bipolar transistor, and wherein the second row switch is a device different from the first row switch.

34. A method for addressing a first array of nonlinear conductive devices, the method comprising:

decoding, using a second array of nonlinear conductive devices, a row address;

selecting, using the decoded row address, one of a plurality of row switches, thereby causing the selected row switch to have an impedance lower than impedances of non-selected row switches;

applying, using the selected row switch, a row voltage to one of a plurality of row lines, thereby selecting one of a plurality of rows in the first array of nonlinear conductive devices for reading or writing.

35. The method of claim 34, further comprising:

decoding, using a third array of nonlinear conductive devices, a column address;

selecting, using the decoded column address, one of a plurality of column switches, thereby causing the selected column switch to have an impedance lower than impedances of non-selected column switches;

applying, using the selected column switch, a column voltage to one of a plurality of column lines, thereby selecting one of a plurality of columns in the first array of nonlinear conductive devices for reading or writing.

36. The method of claim 35, further comprising retaining the selected row line and selecting a new column line.

37. The method of claim 34, further comprising changing a state of a nonlinear conductive device in the first array by applying the row voltage, the nonlinear conductive device being in electrical communication with the selected row line and a selected column line.

38. The method of claim 37, wherein changing the state of the nonlinear conductive device comprises applying a write pulse having a duration of less than one microsecond thereto.

39. The method of claim 34, further comprising detecting a state of a nonlinear conductive device in the first array by applying the row voltage, the nonlinear conductive device being in electrical communication with the selected row line and a selected column line.

40. The method of claim 34, further comprising detecting a state of each of a plurality of nonlinear conductive devices in the first array by applying the row voltage, the plurality of nonlinear conductive devices being in electrical communication with the selected row line.

41. The method of claim 34, further comprising applying, prior to selecting one of the plurality of row switches, a pre-charge voltage to each of the plurality of row switches.

42. The method of claim 34, further comprising reading a complimentary bit output from the first array of nonlinear conductive devices.

43. The method of claim 34, wherein each of the plurality of row lines are complementary.

44. The method of claim 34, wherein the row voltage is one of a read voltage or a write voltage.

45. A digital memory device comprising:

an input port for receiving a memory address;

row and column address decoders for decoding the memory address, each address decoder comprising a decoder array of nonlinear conductive devices;

a plurality of row switches for causing, based on the decoded memory address, an impedance of a selected row switch to be lower than impedances of the non-selected row switches, thereby selecting one of a plurality of row lines connected thereto;

a plurality of column switches for causing, based on the decoded memory address, an impedance of a selected column switch to be lower than impedances of the non-selected column switches, thereby selecting one of a plurality of column lines connected thereto;

an storage array of nonlinear conductive devices, each device being addressable by one of the plurality of row lines and one of the plurality of column lines; and

an input/output port for accessing data stored at the selected row and column lines corresponding to the memory address.

46. The device of claim 45, wherein the device is compatible with the interface standard for at least one of Compact Flash data, Secure Digital data, USB memory stick data, or PCMCIA data.

47. The device of claim 45, wherein the device comprises one of a ball-grid array, dual-in-line package, SOIC, PLCC, or TQFP.

48. The device of claim 45, wherein the device is embedded in a memory chip, processor, PLD, PLA, microcontroller, or chipset.