Diodes Patents (Class 365/175)
  • Patent number: 11127457
    Abstract: The memory device includes a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row control circuit including a plurality of row switches corresponding to the word lines, a column control circuit including a plurality of column switches corresponding to the bit lines, and a control logic circuit configured to control pre-charge operations on a word line and a bit line of a selected memory cell and perform a control operation to float the word line and the bit line together after a pre-charge period during a data reading operation. One of the word line and the bit line is floated after the pre-charge period and the other one is pseudo-floated after the pre-charge period.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: September 21, 2021
    Inventors: Jongryul Kim, Taehui Na, Dueung Kim, Jongmin Baek
  • Patent number: 10832752
    Abstract: A random access memory (RAM) includes a bit-line, a source-line, a memory cell connected to the bit-line and the source-line, and a read/write circuit connected to the bit-line and the source-line and including a negative differential resistance (NDR) device.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: November 10, 2020
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Puneet Gupta, Andrew S. Pan, Shaodi Wang
  • Patent number: 10643976
    Abstract: An electronic component includes: a plurality of first substrates that are connected in series along a coupling path; and a second substrate that is connected with one first substrate of the plurality of first substrates. The second substrate is in line with the one first substrate along a connection direction intersecting the coupling path, and the plurality of first substrates and the second substrate are configured to be foldable such that they are stacked.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: May 5, 2020
    Assignee: NEC CORPORATION
    Inventors: Yurika Otsuka, Tsutomu Takeda, Hironobu Ikeda, Yuki Matsumoto
  • Patent number: 10460789
    Abstract: A volatile memory array using vertical thyristors is disclosed together with methods of operating the array to read data from and write data to the array.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: October 29, 2019
    Assignee: TC Lab, Inc.
    Inventors: Harry Luan, Bruce L. Bateman, Valery Axelrad, Charlie Cheng
  • Patent number: 10354728
    Abstract: After programming a set of resistive memory cells in a resistive memory device, the programmed states and the functionality of each resistive memory cell in the programmed set can be verified by a primary determination method and a secondary determination method. The primary determination method employs the step of determining whether a measured electrical current at a preset read voltage for the selected resistive memory cell is within electrical current specification for the selected resistive state. If the selected cell fails the primary determination method, the second determination method is performed, which includes determining whether a measured threshold voltage for the selected resistive memory cell is within threshold voltage specification for the selected resistive state. If the selected cell fails both methods, the selected cell is identified as a non-functional resistive memory cell. Otherwise, the selected cell is identified as an operational cell.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: July 16, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Bijesh Rajamohanan, Juan Pablo Saenz
  • Patent number: 10332886
    Abstract: Memory cells are formed with vertical thyristors to create a volatile memory array. Power consumption in such arrays is reduced or controlled for an operation on a set of memory cells in an array, sequentially engaging subsets of memory cells for the operation while keeping the remaining memory cells of the set on hold until all the memory cells of the set have been operated on.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: June 25, 2019
    Assignee: TC Lab, Inc.
    Inventors: Harry Luan, Bruce L. Bateman, Valery Axelrad, Charlie Cheng
  • Patent number: 10290760
    Abstract: In one form, a process of manufacturing an avalanche photodiode includes forming an insulating layer over an active region of a semiconductor substrate. A shallow terminal of the avalanche photodiode is defined using a first patterned mask. A first dopant is implanted through the first patterned mask and the insulating layer to form the shallow terminal. The first patterned mask is removed. A deep terminal of the avalanche photodiode is defined using second patterned mask. A second dopant is implanted through the second patterned mask and insulating layer to form the deep terminal of the avalanche photodiode. A respective terminal of at least one of the shallow terminal and the deep terminal is defined using a respective patterned mask that forms at least two regions that are spatially separated from each other with no implanted structure located in a space therebetween.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: May 14, 2019
    Assignee: SensL Technologies Ltd.
    Inventors: Kevin Michael O'Neill, John Carlton Jackson, Liam Wall
  • Patent number: 10026477
    Abstract: In one example, a volatile selector is switched from a low conduction state to a first high conduction state with a first voltage level and then the first voltage level is removed to activate a relaxation time for the volatile selector. The relaxation time is defined as the time the first volatile selector transitions from the high conduction state back to the low conduction state. The volatile selector is switched with a second voltage level of opposite polarity to the first voltage level to significantly reduce the relaxation time of the volatile selector.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: July 17, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Jianhua Yang, Ning Ge, John Paul Strachan, Gary Gibson, Warren Jackson
  • Patent number: 9959927
    Abstract: A memory device and method comprising a metal oxide material disposed between and in electrical contact with first and second conductive electrodes, and a voltage source configured to apply a plurality of voltage pulses spaced apart in time across the first and second electrodes. For each one of the voltage pulses, an amplitude of the voltage increases during the voltage pulse.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: May 1, 2018
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Feng Zhou, Xian Liu, Nhan Do, Hieu Van Tran, Hung Quoc Nguyen, Mark Reiten, Zhixian Chen, Wang Xinpeng, Guo-Qiang Lo
  • Patent number: 9548109
    Abstract: Junction diodes or MOS devices fabricated in standard FinFET technologies can be used as program selectors or One-Time Programmable (OTP) element in a programmable resistive device, such as interconnect fuse, contact/via fuse, anti-fuse, or emerging nonvolatile memory such as MRAM, PCRAM, CBRAM, or RRAM. The MOS or diode can be built on at least one fin structure or at least one active region that has at least one first active region and a second active region. The first and the second active regions can be isolated by a dummy MOS gate or silicide block layer (SBL)to construct a diode.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: January 17, 2017
    Assignee: Attopsemi Technology Co., LTD
    Inventor: Shine C. Chung
  • Patent number: 9541456
    Abstract: A temperature sensor circuit has a reference voltage generator that is trimmable at two temperatures for increased accuracy. The reference voltage generation section generates a reference voltage, the level of which is trimmable. A voltage divider section is connected to receive the reference voltage from the reference voltage generation section and generate a plurality of comparison voltage levels determined by the reference voltage and a trimmable resistance. An analog-to-digital converter can then be connected to a temperature dependent voltage section to receive the temperature dependent output voltage, such as a proportional to absolute temperature type (PTAT) behavior, and connected to the voltage divider section to receive the comparison voltage levels. The analog to digital converter generates an output indicative of the temperature based upon a comparison of the temperature dependent output voltage to the comparison voltage levels.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: January 10, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Masahide Matsumoto, Ryuji Yamashita
  • Patent number: 9509205
    Abstract: DC-DC current mode switching power converters that have negative current capability are presented. The power converters comprise: an output node, a pass device connected to the output node of the power converter, the pass device being configured to operate in accordance with a PWM signal and to supply at least a portion of an output current of the power converter, a PWM comparator for generating the PWM signal for controlling operation of the pass device in accordance with a current conducted by the pass device and a difference between an output voltage of the power converter and a reference voltage. The converters have push pull class B (or AB) current sensing, dynamic biasing of a current sense amplifier using error information, and using operational transconductance amplifiers that are fed an error voltage. This results in a lower quiescent current at zero load.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: November 29, 2016
    Assignee: Dialog Semiconductor (UK) Limited
    Inventor: Pietro Gabriele Gambetta
  • Patent number: 9509716
    Abstract: The invention is a method and system for detecting attackers that are interested in attacking an organization's infrastructure during the reconnaissance phase of an Advanced Persistent Threat (APT). APTs are very sophisticated attacks and incorporate advanced methods for evading current security mechanisms. Therefore, the present invention uses an innovative social network honeypot.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: November 29, 2016
    Assignee: Deutsche Telekom AG
    Inventors: Asaf Shabtai, Rami Puzis, Yuval Elovici
  • Patent number: 9502422
    Abstract: A semiconductor device includes an insulating layer on a semiconductor substrate, a bit line including TiAl and disposed on the insulating layer, a sidewall layer disposed on opposite sides of the bit line, a word line including TiN and disposed on the sidewall layer intersecting the bit line, and an air gap in an intersection region of the bit line and the word line. The thickness of the sidewall layer is larger than the thickness of the bit line. By having the TiAl bit line and TiN word line, the uniformity of the bit line and word line can be easily controlled to improve the performance of the semiconductor device.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: November 22, 2016
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Zhenghao Gan
  • Patent number: 9496021
    Abstract: Memory cells are formed with vertical thyristors to create a volatile memory array. Power consumption in such arrays is reduced or controlled with various techniques including encoding the data stored in the arrays.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: November 15, 2016
    Assignee: Kilopass Technology, Inc.
    Inventors: Harry Luan, Bruce L. Bateman, Valery Axelrad, Charlie Cheng
  • Patent number: 9496020
    Abstract: A memory cell based upon cross-coupled thyristors for an SRAM integrated circuit can be implemented in different combinations of MOS and bipolar select transistors with the thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM cells.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: November 15, 2016
    Assignee: Kilopass Technology, Inc.
    Inventors: Harry Luan, Bruce L. Bateman, Valery Axelrad, Charlie Cheng, Christophe J. Chevallier
  • Patent number: 9460771
    Abstract: A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with the thyristor in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM cells.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: October 4, 2016
    Assignee: Kilopass Technology, Inc.
    Inventors: Harry Luan, Bruce L. Bateman, Valery Axelrad, Charlie Cheng, Christophe J. Chevallier
  • Patent number: 9449669
    Abstract: A memory cell based upon thyristors for an SRAM integrated circuit can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM cells. Special circuitry provides lowered power consumption during standby.
    Type: Grant
    Filed: January 6, 2015
    Date of Patent: September 20, 2016
    Assignee: Kilopass Technology, Inc.
    Inventors: Harry Luan, Bruce L. Bateman, Valery Axelrad, Charlie Cheng, Christophe J. Chevallier
  • Patent number: 9355712
    Abstract: A semiconductor device includes an insulating layer on a semiconductor substrate, a bit line including TiAl and disposed on the insulating layer, a sidewall layer disposed on opposite sides of the bit line, a word line including TiN and disposed on the sidewall layer intersecting the bit line, and an air gap in an intersection region of the bit line and the word line. The thickness of the sidewall layer is larger than the thickness of the bit line. By having the TiAl bit line and TiN word line, the uniformity of the bit line and word line can be easily controlled to improve the performance of the semiconductor device.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: May 31, 2016
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Zhenghao Gan
  • Patent number: 9343145
    Abstract: Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In one embodiment, a memory cell includes a wordline, a first bitline, a second bitline, and a memory element. The memory element is electrically connected to the wordline and selectively electrically connected to the first bitline and the second bitline. The memory element stores information via a resistive state of the memory element. The memory cell is configured to convey the resistive state of the memory element via either a first current flowing from the first bitline through the memory element to the wordline or a second current flowing from the wordline through the memory element to the second bitline.
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: May 17, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Jun Liu
  • Patent number: 9299410
    Abstract: According to one embodiment, a magnetic memory includes a cell array includes a plurality of memory cells, each memory cell including a magnetoresistive effect element; and a read circuit to read data from a memory cell selected based on an address signal from among the memory cells. The read circuit selects one determination level from among a plurality of determination levels corresponding to a position of a magnetoresistive effect element in the cell array and uses the selected determination level to perform reading of the data.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: March 29, 2016
    Inventors: Shintaro Sakai, Masahiko Nakayama
  • Patent number: 9025372
    Abstract: A monolithic three-dimensional memory array is provided that includes a first memory level and a second memory level disposed above or below the first memory level. The first memory level includes a plurality of vertically oriented p-i-n diodes that each include a bottom heavily doped p type region. The second memory level includes a plurality of vertically oriented p-i-n diodes that each include a bottom heavily doped n type region. Numerous other aspects are also provided.
    Type: Grant
    Filed: April 10, 2014
    Date of Patent: May 5, 2015
    Assignee: SanDisk 3D LLC
    Inventor: Scott Brad Herner
  • Patent number: 9013913
    Abstract: According to various embodiments, a resistive-switching memory element and memory element array that uses a bipolar switching includes a select element comprising only a single diode that is not a Zener diode. The resistive-switching memory elements described herein can switch even when a switching voltage less than the breakdown voltage of the diode is applied in the reverse-bias direction of the diode. The memory elements are able to switch during the very brief period when a transient pulse voltage is visible to the memory element, and therefore can use a single diode per memory cell.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: April 21, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Yun Wang, Tony P. Chiang, Prashant B. Phatak
  • Patent number: 9001555
    Abstract: The present invention discloses a small-grain three-dimensional memory (3D-MSG). Each of its memory cells comprises a thin-film diode with critical dimension no larger than 40 nm. The thin-film diode comprises at least a small-grain material, whose grain size G is substantially smaller than the diode size D. The small-grain material is preferably a nano-crystalline material or an amorphous material. The critical dimension f of the small-grain diode is smaller than the critical dimension F of the single-crystalline transistor.
    Type: Grant
    Filed: March 20, 2013
    Date of Patent: April 7, 2015
    Assignees: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao Zhang
  • Patent number: 9001580
    Abstract: A nonvolatile memory (“NVM”) bitcell includes a capacitor, an asymmetrically doped transistor, and a gated diode device. The capacitor, transistor, and gated diode device are each electrically coupled to different active regions and metal contacts. The three devices are coupled by a floating gate that traverses the three active regions. The gated diode device allows for erasure of an entire NVM memory more efficiently and using less substrate space than a similar device that uses a transistor. The asymmetric transistor, in conjunction with the capacitor, is used to both program and read the logical state of the floating gate. The capacitor and floating gate are capacitively coupled together, removing the need for a separate selection device to perform read and write operations.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: April 7, 2015
    Assignee: Synopsys, Inc.
    Inventor: Andrew E. Horch
  • Patent number: 8988925
    Abstract: A nonvolatile semiconductor memory device in accordance with an embodiment comprises a plurality of first, second lines, a plurality of memory cells, and a control circuit. The plurality of second lines extend so as to intersect the first lines. The plurality of memory cells are disposed at intersections of the first, second lines, and each includes a variable resistor. The control circuit is configured to control a voltage applied to the memory cells. The control circuit applies a first pulse voltage to the variable resistor during a forming operation. In addition, the control circuit applies a second pulse voltage to the variable resistor during a setting operation, the second pulse voltage having a polarity opposite to the first pulse voltage. Furthermore, the control circuit applies a third pulse voltage to the variable resistor during a resetting operation, the third pulse voltage having a polarity identical to the first pulse voltage.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: March 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Reika Ichihara, Takayuki Tsukamoto
  • Patent number: 8982605
    Abstract: A phase change memory device having a multi-level and a method of driving the same are presented. The disclosed phase change memory device includes variable resistors and shifting units. The variable resistors are interchanged into set and reset states in response to an applied current. The shifting units, which are connected to the variable resistors, shift resistance distribution in the set and reset state of the variable resistors by a predetermined level.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: March 17, 2015
    Assignee: SK hynix Inc.
    Inventors: Hae Chan Park, Se Ho Lee
  • Patent number: 8976565
    Abstract: MIMCAP diodes are provided that can be suitable for memory device applications, such as current selector devices for cross point memory array. The MIMCAP diodes can have lower thermal budget as compared to Schottky diodes and controllable lower barrier height and lower series resistance as compared to MIMCAP tunneling diodes. The MIMCAP diode can include a barrier height modification layer, a low leakage dielectric layer and a high leakage dielectric layer. The layers can be sandwiched between two electrodes.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: March 10, 2015
    Assignee: Intermolecular, Inc.
    Inventor: Prashant B Phatak
  • Patent number: 8958235
    Abstract: This semiconductor memory device comprises: a memory cell array configured as an arrangement of memory cells disposed at intersections of a plurality of first lines disposed substantially in parallel and a plurality of second lines disposed to intersect the first lines, each of the memory cells including a variable resistance element; and a control circuit configured to control the memory cell array. The control circuit is configured to change a voltage value of a resetting verify voltage applied for confirming completion of the resetting operation according to a degree of change of resistance of the memory cell when performing the resetting operation to change the memory cell from a low-resistance state to a high-resistance state.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: February 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Junya Matsunami
  • Patent number: 8953370
    Abstract: A memory cell with a decoupled read/write path includes a switch comprising a first terminal connected to a first line and a second terminal connected to a second line, a resistive switching device connected between a gate of the switch and a third line, and a conductive path between the gate of the switch and the second line.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: February 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Wei Ting, Kuo-Ching Huang, Chun-Yang Tsai
  • Patent number: 8953363
    Abstract: A cross point nonvolatile memory device capable of suppressing sneak-current-caused reduction in sensitivity of detection of a resistance value of a memory element is provided. The device includes perpendicular bit and word lines; a cross-point cell array including memory cells each having a resistance value reversibly changing between at least two resistance states according to electrical signals, arranged on cross-points of the word and bit lines; an offset detection cell array including an offset detection cell having a resistance higher than that of the memory cell in a high resistance state, the word lines being shared by the offset detection cell array; a read circuit (a sense amplifier) that determines a resistance state of a selected memory cell based on a current through the selected bit line; and a current source which supplies current to the offset detection cell array in a read operation period.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: February 10, 2015
    Assignee: Panasonic Intellectural Property Management Co., Ltd.
    Inventors: Kazuhiko Shimakawa, Kiyotaka Tsuji, Ryotaro Azuma
  • Patent number: 8947927
    Abstract: A gated diode memory cell is provided, including one or more transistors, such as field effect transistors (“FETs”), and a gated diode in signal communication with the FETs such that the gate of the gated diode is in signal communication with the source of a first FET, wherein the gate of the gated diode forms one terminal of the storage cell and the source of the gated diode forms another terminal of the storage cell, the drain of the first FET being in signal communication with a bitline (“BL”) and the gate of the first FET being in signal communication with a write wordline (“WLw”), and the source of the gated diode being in signal communication with a read wordline (“WLr”).
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Wing K. Luk, Robert H. Dennard
  • Publication number: 20150016185
    Abstract: A non-volatile electro-mechanical diode memory cell is described for implementation of compact (4F2) cross-point memory arrays. The electro-mechanical diode memory cells operate with relatively low set/reset voltages and excellent retention characteristics, and are multi-time programmable. Due to its simplicity, this electro-mechanical diode memory cell is attractive for implementation of three-dimensional memory arrays for higher storage density.
    Type: Application
    Filed: September 12, 2012
    Publication date: January 15, 2015
    Applicant: The Regents Of The University Of California
    Inventors: Tsu-Jae King Liu, Wookhyun Kwon
  • Patent number: 8929122
    Abstract: Junction diodes fabricated in standard CMOS logic technologies can be used as program selectors for a programmable resistive device, such as electrical fuse, contact/via fuse, anti-fuse, or emerging nonvolatile memory such as MRAM, PCM, CBRAM, or RRAM. The diode can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diode. By applying a high voltage to the P terminal of a diode and switching the N terminal of a diode to a low voltage for proper duration of time, a current flows through a resistive element in series with the program selector may change the resistance state. The P+ active region of the diode can be isolated from the N+ active region in the N well by using dummy MOS gate, SBL, or STI isolations. If the resistive element is an interconnect fuse based on CMOS gate material, the resistive element can be coupled to the P+ active region by an abutted contact such that the element, active region, and metal can be connected in a single rectangular contact.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: January 6, 2015
    Inventor: Shine C. Chung
  • Patent number: 8907318
    Abstract: A resistance change memory includes a first conductive line extending in a first direction, a second conductive line extending in a second direction which is crossed to the first direction, a cell unit including a memory element and a rectifying element connected in series between the first and second conductive lines, and a control circuit which is connected to both of the first and second conductive lines. The control circuit controls a voltage to change a resistance of the memory element between first and second values reversibly. The rectifying element is a diode including an anode layer, a cathode layer and an insulating layer therebetween.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: December 9, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Sonehara, Takayuki Okamura, Takashi Shigeoka, Masaki Kondo
  • Patent number: 8902690
    Abstract: A system and method for operating a unipolar memory cell array including a bidirectional access diode. An example embodiment is a method including determining if the operating state of the unipolar memory cell is in a select state or a deselect state and the programming state is a read state or a write state. The method switches a column voltage switch based on the operating state and the programming state of the unipolar memory cell. The method further switches a row voltage switch based on the operating state and the programming state of the unipolar memory cell.
    Type: Grant
    Filed: August 13, 2012
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kailash Gopalakrishnan, Chung H. Lam, Jing Li, Robert K. Montoye
  • Patent number: 8897059
    Abstract: A resistance change memory device includes: a memory cell formed of a variable resistance element and a diode connected in series, the state of the variable resistance element being reversibly changed in accordance with applied voltage or current; and a stabilizing circuit so coupled in series to the current path of the memory cell as to serve for stabilizing the state change of the memory cell passively.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: November 25, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Haruki Toda
  • Patent number: 8897056
    Abstract: A pillar-shaped memory cell is provided that includes a steering element, and a non-volatile state change element coupled in series with the steering element. Other aspects are also provided.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: November 25, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Mark G. Johnson, Thomas H. Lee, Vivek Subramanian, Paul Michael Farmwald, James M. Cleeves
  • Patent number: 8883590
    Abstract: A phase change memory apparatus is provided that includes a first electrode that is longer than it is wide, the first electrode having a trench formed on an active region of a semiconductor substrate, a second electrode formed in a bottom portion of the trench, and a bottom electrode contact formed on the second electrode.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: November 11, 2014
    Assignee: SK Hynix Inc.
    Inventor: Jang Uk Lee
  • Patent number: 8878236
    Abstract: In a first embodiment, an ultra-fast breakover diode has a turn on time TON that is less than 0.3 microseconds, where the forward breakover voltage is greater than +400 volts and varies less than one percent per ten degrees Celsius change. In a second embodiment, a breakover diode has a reverse breakdown voltage that is greater, in absolute magnitude, than the forward breakover voltage, where the forward breakover voltage is greater than +400 volts. In a third embodiment, a string of series-connected breakover diode dice is provided, along with a resistor string, in a packaged circuit. The packaged circuit acts like a single breakover diode having a large forward breakover voltage and a comparably large reverse breakdown voltage, even though the packaged circuit includes no discrete high voltage reverse breakdown diode. The packaged circuit is usable to supply a triggering current to a thyristor in a voltage protection circuit.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: November 4, 2014
    Assignee: IXYS Corporation
    Inventor: Subhas Chandra Bose Jayappa Veeramma
  • Patent number: 8879314
    Abstract: Memory cell comprising two conductors, with a serially connected magnetic storage element and a Schottky diode between the two conductors. The Schottky diode provides a unidirectional conductive path between the two conductors and through the element. The Schottky diode is formed between a metal layer in one of the two conductors and a processed junction layer. Methods for process and for operation of the memory cell are also disclosed. The memory cell using the Schottky diode can be designed for high speed operation and with high density of integration. Advantageously, the junction layer can also be used as a hard mask for defining the individual magnetic storage element in the memory cell. The memory cell is particularly useful for magnetic random access memory (MRAM) circuits.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: November 4, 2014
    Assignee: III Holdings 1, LLC
    Inventor: Krishnakumar Mani
  • Patent number: 8879300
    Abstract: Various embodiments of the present invention are directed to nanoscale electronic devices that provide nonvolatile memristive switching. In one aspect, a two-terminal device (600) comprises a first electrode (602), a second electrode (604), and an active region (606) disposed between the first electrode and the second electrode. The active region includes a mobile dopant (608), and a fast drift ionic species (610). The fast drift ionic species drifts into a diode-like electrode/active region interface temporarily increasing conductance across the interface when a write voltage is applied to the two-terminal device to switch the device conductance.
    Type: Grant
    Filed: April 22, 2010
    Date of Patent: November 4, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jianhua Yang, Wei Wu, Qiangfei Xia
  • Patent number: 8872686
    Abstract: The present disclosure relates to a method and architecture to minimize a transient glitch within a current digital-to-analog converter (DAC) comprising an array of identical current unit cells. The current DAC is configured with individual column decoders for even and odd rows of current unit cells, thus allowing for independent control of adjacent rows. The even row and odd row column decoders further comprise thermal decoders with coupled timing encoding which establishes synergy between an adjacent pair of rows. As current units cells within an active row are activated across the row by a counting up of a first column decoder, the current units cells within a next row adjacent the active row are returned to an initial state of the active row by counting down in a second column decoder. Other devices and methods are also disclosed.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: October 28, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Yu Chou, Wei Lun Tao, Shang-Fu Yeh, Yi-Che Chen, Calvin Yi-Ping Chao
  • Patent number: 8867267
    Abstract: Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied across the wordline and the bitline and to decrease the current if the voltage is increased or decreased. Some embodiments include memory devices having a wordline, a bitline, memory element selectively configurable in one of two or more different resistive states, a first diode configured to inhibit a first current from flowing from the bitline to the wordline responsive to a first voltage, and a second diode comprising a dielectric material and configured to allow a second current to flow from the wordline to the bitline responsive to a second voltage.
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: October 21, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Chandra Mouli
  • Patent number: 8842462
    Abstract: A resistive random access memory (RRAM) device and operating method are disclosed herein. The RRAM device includes at least one RRAM cell and a control circuit. The RRAM cell includes a bottom electrode, an amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) layer, a Ti layer and a top electrode. The a-IGZO layer is disposed on the bottom layer. The Ti layer is disposed on the a-IGZO layer. The top electrode is disposed on the Ti layer. The control circuit is configured to provide at least one electrical signal to the RRAM cell, so as to change the resistance value of the RRAM cell.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: September 23, 2014
    Assignee: National Chiao Tung University
    Inventors: Po-Tsun Liu, Ching-Hui Hsu, Yang-Shun Fan
  • Patent number: 8842491
    Abstract: A system and method for operating a unipolar memory cell array including a bidirectional access diode. The system includes a column voltage switch electrically coupled to a plurality of column voltages. The column voltage switch includes an output electrically coupled to the bidirectional access diode. The plurality of column voltages includes at least one select column voltage and one deselect column voltage. The system includes a row voltage switch electrically coupled to a plurality of row voltages. The row voltage switch includes an output electrically coupled to the bidirectional access diode. The plurality of row voltages includes at least one select row voltage and one deselect row voltage. The system includes a column and row decoder electrically coupled to a select line of the column and row voltage switches, respectively.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: September 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kailash Gopalakrishnan, Chung H. Lam, Jing Li, Robert K. Montoye
  • Patent number: 8824201
    Abstract: A semiconductor memory apparatus includes: a read current supply unit configured to supply a read current; a resistive memory cell configured to pass a current having a magnitude corresponding to a resistance value thereof in a data read mode; a voltage transfer unit coupled between the read current supply unit and the resistive memory cell and configured to transfer the read current to the resistive memory cell, wherein a voltage corresponding to the magnitude of the passed current is formed at a sensing node; and a feedback unit configured to pull-down drive a connection node, which is coupled between the voltage transfer unit and the resistive memory cell, when a voltage level of the sensing node reaches a predefined level.
    Type: Grant
    Filed: December 31, 2010
    Date of Patent: September 2, 2014
    Assignee: SK Hynix Inc.
    Inventors: Hyun Joo Lee, Dong Keun Kim
  • Patent number: 8797794
    Abstract: Apparatuses and methods can include write schemes for a thyristor memory cell in which an access pulse applied to the gate of the thyristor memory cell is adjusted relative to the data pulse to write data into the thyristor memory cell. Some of the write schemes may substantially reduce or eliminate an unselected data line disturb. In various embodiments, the thyristor memory cell can be structured with two control nodes and its cathode or anode coupled to a reference voltage node common to all thyristor memory cells in a memory array. Additional apparatuses and methods are disclosed.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: August 5, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Rajesh N. Gupta
  • Patent number: RE45345
    Abstract: A nonvolatile semiconductor memory device include: a two terminal structured variable resistive element, wherein resistive characteristics defined by current-voltage characteristics at both ends transit between low and high resistance states stably by applying a voltage satisfying predetermined conditions to the both ends. A transition from the low resistance state to the high resistance state occurs by applying a voltage of a first polarity whose absolute value is at or higher than first threshold voltage, and the reverse transition occurs by applying a voltage of a second polarity whose absolute value is at or higher than a second threshold voltage. A load circuit is connected to the variable resistive element in series having an adjustable load resistance. A voltage generation circuit applies a voltage to both ends of a serial circuit. The variable resistive element can transit between the states by adjusting a resistance of the load circuit.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: January 20, 2015
    Assignee: Xenogenic Development Limited Liability Company
    Inventors: Shinobu Yamazaki, Yasunari Hosoi, Nobuyoshi Awaya, Shinichi Sato, Kenichi Tanaka
  • Patent number: RE46110
    Abstract: A semiconductor device has a DRAM cell configured from an information charge accumulating capacitor and a memory cell selecting transistor, the threshold voltage value of a MOS transistor that constitutes a sense circuit is monitored, and the monitored threshold voltage value of the MOS transistor is converted through the use of a transfer ratio that is determined based on the capacitance of the information charge accumulating capacitor and the parasitic capacitance of the bit line. The converted voltage value is level-shifted so that the pre-charge voltage of a pre-charge circuit is a pre-set voltage, a current feeding capability is added to the level-shifted voltage value, and the voltage is fed as the pre-charge voltage.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: August 16, 2016
    Assignee: PS4 LUXCO S.A.R.L.
    Inventor: Kazuhiko Kajigaya