Shielded Gate Trench FET with the Shield and Gate Electrodes Connected Together in Non-active Region
A field effect transistor (FET) in a semiconductor die including an active region housing active cells, a non-active region with no active cells therein, a drift region of a first conductivity type, a body region of a second conductivity type over the drift region, and a plurality of trenches extending through the body region and into the drift region. Each trench includes a shield electrode and a gate electrode, the shield electrode being disposed below the gate electrode. The FET further includes source regions of the first conductivity type in the body region adjacent to each trench, heavy body regions of the second conductivity type in the body regions adjacent the source regions, and a source interconnect layer contacting the source regions and heavy body regions. The shield electrode and the gate electrode extend out of each trench and into the non-active region where the shield electrode and gate electrode are electrically connected together by a gate interconnect layer.
This application is a continuation of U.S. application Ser. No. 12/268,616, filed Nov. 11, 2008, which is a continuation of U.S. application Ser. No. 11/938,583, filed Nov. 12, 2007, now U.S. Pat. No. 7,473,603, which is a division of U.S. application Ser. No. 11/471,279, filed Jun. 19, 2006, now U.S. Pat. No. 7,319,256, all of which are incorporated herein by reference in their entirety for all purposes.
BACKGROUNDThe present invention relates in general to semiconductor power field effect transistors (FETs) and in particular to shielded gate trench FETs with their shield and gate electrodes connected together.
Shielded gate trench FETs are advantageous over conventional FETs in that the shield electrode reduces the gate-drain capacitance (Cgd) and improves the breakdown voltage of the transistor.
The gate and shield electrodes are insulated from one another by a dielectric layer 116 also referred to as inter-electrode dielectric or IED. IED layer 116 must be of sufficient quality and thickness to support the potential difference that may exist between shield electrode 114 and gate electrode 122. In addition, interface trap charges and dielectric trap charges in IED layer 116 or at the interface between the shield electrode 114 and IED layer 116 are associated primarily with the methods for forming the IED layer.
The IED is typically formed by various processing methods. However, insuring a high-quality IED that is sufficiently robust and reliable enough to provide the required electrical characteristics results in complicated processes for forming the shielded gate trench FET. Accordingly, there is a need for structure and method of forming shielded gate trench FET that eliminate the need for a high-quality IED while maintaining or improving such electrical characteristics as on-resistance.
BRIEF SUMMARYAccording to an embodiment of the invention, a field effect transistor (FET) includes a plurality of trenches extending into a semiconductor region. Each trench includes a gate electrode and a shield electrode with an inter-electrode dielectric therebetween. A body region extends between each pair of adjacent trenches, and source regions extend in each body region adjacent to the trenches. A first interconnect layer contacts the source and body regions. The plurality of trenches extends in an active region of the FET, and the shield electrode and gate electrode extend out of each trench and into a non-active region of the FET where the shield electrodes and gate electrodes are electrically connected together by a second interconnect layer. The electrical connection between the shield and gate electrodes is made through periodic contact openings formed in a gate runner region of the non-active region.
In one embodiment, the FET of claim further includes a substrate and a drift region bounded by the body regions and the substrate, and the plurality of trenches terminate within the drift region. In another embodiment, the plurality of trenches extends through the drift region and terminates within the substrate.
In yet another embodiment, the shield electrode and the gate electrode in each trench are electrically connected together by an additional connection through the IED in each trench.
In still another embodiment, the first interconnect layer is a source interconnect layer and the second interconnect layer is a gate interconnect layer.
In
As shown in the right cross section view of
In
During recessing of the conductive material, a mask 211 is used to protect portions of the conductive material extending in the non-active region of the die. As a result, shield electrode 214 is thicker inside trench 210 than over the mesa surfaces in the non-active region of the die, as depicted in the right cross section view in
In
In
In
During recessing of the second conductive layer, a mask 219 is used to protect portions of the second conductive material extending in the non-active region of the die. As a result, gate electrode 222 is thicker inside trench 210 than over the mesa surfaces in the non-active region of the die, as depicted in the right cross section view in
In
In
In
Thus, contrary to conventional shielded gate FETs wherein the shield electrode either floats (i.e., is electrically unbiased) or is biased to the source potential (e.g., ground potential), in the FET embodiment shown in
The electrical contact between the gate and shield electrodes may be formed in any non-active region, such as in the termination or edge regions of the die, or in the middle of the die where the gate runners extend as shown in
The gate runner region 340 is structurally symmetrical about line 3-3, with each half being structurally similar to that shown in
Contact openings 321 expose surface areas of shield electrode 314 to which gate interconnect layer 326B (e.g., comprising metal) makes electrical contact. Additionally, gate interconnect layer 326B makes electrical contact with surface areas 332 of gate electrodes 322 exposed through dielectric layer 324. It is desirable to minimize the gate resistance in order to minimize the delay in biasing the individual gate electrodes inside the trenches. For the same reasons, it is desirable to minimize the delay in biasing the individual shield electrodes inside the trenches. Accordingly, the frequency and shape of contact openings 321 in gate runner region 340 can be optimized to minimize the resistance and thus the delay from the gate pad to each of the gate and shield electrodes. The delay in biasing the shield and gate electrodes can be further reduced by forming the gate electrode to shield electrode contacts in both the gate runner regions and in the termination or edge regions of the die.
The shield and gate electrodes may be electrically connected in other ways according to other embodiments of the invention. For example, the IED in each trench may be etched in certain places before forming the gate electrode over the IED. In this embodiment, contact openings as shown in
The principles of the invention may be applied to any shielded gate FET structures such as those shown in FIGS. 3A, 3B, 4A, 4C, 6-8, 9A-9C, 11, 12, 15, 16, 24 and 26A-26C of patent application Ser. No. 11/026,276, titled “Power Semiconductor Devices and Methods of Manufacture,” which disclosure is incorporated herein by reference in its entirety for all purposes.
While the above provides a complete description of the preferred embodiments of the invention, many alternatives, modifications, and equivalents are possible. Those skilled in the art will appreciate that the same techniques can apply to other types of super junction structures as well as more broadly to other kinds of devices including lateral devices. For example, while embodiments of the invention are described in the context of n-channel MOSFETs, the principles of the invention may be applied to p-channel MOSFETs by merely reversing the conductivity type of the various regions. Therefore, the above description should not be taken as limiting the scope of the invention, which is defined by the appended claims.
Claims
1-5. (canceled)
6. A field effect transistor (FET) in a semiconductor die comprising:
- an active region housing active cells;
- a non-active region with no active cells therein;
- a drift region of a first conductivity type;
- a body region of a second conductivity type over the drift region;
- a plurality of trenches extending through the body region and into the drift region, each trench including a shield electrode and a gate electrode, the shield electrode being disposed below the gate electrode;
- source regions of the first conductivity type in the body region adjacent to each trench;
- heavy body regions of the second conductivity type in the body regions adjacent the source regions; and
- a source interconnect layer contacting the source regions and heavy body regions;
- wherein the shield electrode and the gate electrode extend out of each trench and into the non-active region where the shield electrode and gate electrode are electrically connected together by a gate interconnect layer.
7. The FET of claim 6 wherein the gate electrode is recessed in the trench to below a top surface of the source regions, the FET further comprising a dielectric material over the gate electrode for insulating the gate electrode and the source interconnect layer from one another.
8. The FET of claim 6 further comprising a substrate of the first conductivity type, the drift region extending over the substrate, wherein each trench terminates within the drift region.
9. The FET of claim 6 further comprising a substrate of the first conductivity type, the drift region extending over the substrate, wherein each trench extends through the drift region and terminates within the substrate.
10. The FET of claim 6 further comprising an inter-electrode dielectric between the shield electrode and the gate electrode in each trench, wherein the shield electrode is electrically connected to the gate electrode by an additional connection through the inter-electrode dielectric.
11. The FET of claim 6 wherein the non-active region includes a gate runner region extending through a middle portion of the die, the shield electrode and gate electrode extending out of each trench and into the gate runner region where the shield electrode and gate electrode are electrically connected together by the gate interconnect layer.
12. The FET of claim 6 wherein the non-active region includes a termination region extending along a perimeter of the die, the shield electrode and gate electrode extending out of each trench and into the termination region where the shield electrode and gate electrode are electrically connected together by the gate interconnect layer.
Type: Application
Filed: Dec 27, 2010
Publication Date: Aug 25, 2011
Inventors: Nathan Kraft (Pottsville, PA), Christopher Boguslaw Kocon (Mountaintop, PA), Paul Thorup (West Jordan, UT)
Application Number: 12/978,824
International Classification: H01L 29/78 (20060101);