Abstract: A semiconductor device includes a semiconductor layer having a main surface in which a trench is formed, a first-conductivity-type body region formed along a sidewall of the trench in a surface layer portion of the main surface of the semiconductor layer, a second-conductivity-type impurity region formed along the sidewall of the trench in a surface layer portion of the body region, a gate insulating layer formed on an inner wall of the trench, a gate electrode that is embedded in the trench and that faces the body region and the impurity region with the gate insulating layer placed between the gate electrode and the body region and between the gate electrode and the impurity region, a contact electrode that passes through the sidewall of the trench from inside the trench and is drawn out to the surface layer portion of the main surface of the semiconductor layer and is electrically connected to the body region and to the impurity region, and an embedded insulating layer that is interposed between the gate el

Abstract: A semiconductor device structure including a doped region under an isolation feature is provided. The semiconductor device structure includes a first substrate, a first well region, a first gate structure, a second gate structure, a first doped region, and a first conductive feature. The substrate has a first surface and a second surface opposite to the first surface. The first well region is in the first substrate. The first well region has a first conductive type. The first gate structure is disposed on the second surface. The second gate structure is disposed on the second surface. The first doped region includes a second conductive type different from the first conductive type. The first doped region is disposed between the first gate structure and the second gate structure. The first conductive feature extends between the first surface of the first substrate and the first doped region.

Abstract: A semiconductor device includes a vertical field-effect transistor including: a low-concentration impurity layer; a body region; a gate trench; a gate insulating film; and a gate conductor. The body region includes: a first body portion containing an active region and has a constant depth; and a second body portion adjacent to the first body portion and includes a zone that has a limited length in a second direction orthogonal to the first direction along the top surface of the low-concentration impurity layer, and has a constant depth at a position shallower than the constant depth of the first body portion. The second body portion includes a portion in which a region having relatively high concentration of an impurity and a region having relatively low concentration of an impurity are alternately and periodically present in the first direction in a cross-sectional view of a plane orthogonal to the second direction.

Abstract: A super junction structure includes a substrate, wherein the substrate has a first conductivity type. The super junction structure includes an epitaxial layer over the substrate, wherein the epitaxial layer has a second conductivity type opposite the first conductivity type. The super junction structure further includes a bury layer between the epitaxial layer and the substrate, wherein the bury layer has the second conductivity type. The super junction structure further includes a conductive pillar in the epitaxial layer, wherein the conductive pillar has the first conductivity type, sidewalls of the conductive pillar are angled with respect to a top-most surface of the epitaxial layer, a bottom surface of the conductive pillar is rounded, and a top-most surface of the conductive pillar is coplanar with the top-most surface of the epitaxial layer.

Abstract: The present disclosure provides a semiconductor structure comprising one or more fins formed on a substrate and extending along a first direction; one or more gates formed on the one or more fins and extending along a second direction substantially perpendicular to the first direction, the one or more gates including an first isolation gate and at least one functional gate; source/drain features formed on two sides of each of the one or more gates; an interlayer dielectric (ILD) layer formed on the source/drain features and forming a coplanar top surface with the first isolation gate. A first height of the first isolation gate is greater than a second height of each of the at least one functional gate.

Abstract: An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.

Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes a substrate; a gate electrode disposed within the substrate; a gate dielectric layer disposed within the substrate and surrounding the gate electrode; a plurality of first protection structures disposed over the gate electrode; a second protection structure disposed over the gate dielectric layer and contacting the gate dielectric layer; and a pair of source/drain regions on opposing sides of the gate dielectric layer.

Abstract: Some embodiments include an integrated assembly having a first deck which has first memory cells, and having a second deck which has second memory cells. The first memory cells have first control gate regions which include a first conductive material vertically between horizontally-extending bars of a second conductive material. The second memory cells have second control gate regions which include a fourth conductive material along an outer surface of a third conductive material. A pillar passes through the first and second decks. The pillar includes a dielectric-barrier material laterally surrounding a channel material. The first and fourth materials are directly against the dielectric-barrier material. Some embodiments include methods of forming integrated assemblies.

Abstract: A semiconductor device includes a semiconductor part; first and second electrodes respectively on back and front surfaces of the semiconductor part; and a control electrode between the semiconductor part and the second electrode. The control electrode is provided inside a trench of the semiconductor part. The control electrode is electrically insulated from the semiconductor part by a first insulating film and electrically insulated from the second electrode by a second insulating film. The control electrode includes an insulator at a position apart from the first insulating film and the second insulating film. The semiconductor part includes a first layer of a first conductivity type provided between the first and second electrodes, the second layer of a second conductivity type provided between the first layer and the second electrode and the third layer of the first conductivity type selectively provided between the second layer and the second electrode.

Abstract: A method includes forming an ion-implanted capping layer in a first epitaxial layer disposed on a silicon substrate. The ion-implanted capping layer is doped with a second dopant of a same conductivity type as a first dopant in the silicon substrate. The second dopant has a lower diffusivity than the diffusivity of the first dopant. The ion-implanted capping layer has a thickness configured to contain up-diffusion of the first dopant from the silicon wafer in the first epitaxial layer in thermal processes for fabricating a vertical MOSFET device in the substrate. The ion-implanted capping layer is configured to limit up-diffusion of the first dopant from the silicon wafer through the ion-implanted capping layer into a second epitaxial layer such that a concentration of the first dopant in the second epitaxial layer is lower than a concentration of the first dopant in the first epitaxial layer.

Abstract: An apparatus includes a semiconductor substrate; a line-shaped trench in the semiconductor substrate, an inner wall of the line-shaped trench being covered with an insulating film; a first conductive member including first and second line-shaped portions, the first line-shaped portion filling a lower portion of the line-shaped trench; and line-shaped second and third conductive members extending along the inner wall of the line-shaped trench and facing each other, the line-shaped second and third conductive members having a void therebetween; wherein the second line-shaped portion of the first conductive member protrudes from a central portion of the first line-shaped portion to fill the void.

Abstract: A semiconductor is disclosed that may include: a first drift region; a base region arranged on the first semiconductor layer; a source region arranged on the base region; a main electrode electrically connected to the source region; and a gate electrode structure that penetrates the source region and base region and reaches the first drift region, wherein the gate electrode structure comprises: a gate electrode; and an insulating material that insulates the gate electrode from the first drift region and the base region; and a field plate structure reaching the first drift region deeper than the gate electrode structure, wherein the field plate structure comprises: a field plate; a resistive part that electrically connects the main electrode to the field plate; and an insulating material that insulates the field plate and the resistive part section from the first drift region and the base region.

Abstract: A semiconductor device according to an embodiment includes first to third semiconductor regions, a structure body, a gate electrode, and a high resistance part. The structure body includes an insulating part and a conductive part. The insulating part is arranged with the third semiconductor region, the second semiconductor region, and a portion of the first semiconductor region. The conductive part is located in the insulating part. The conductive part includes a portion facing the first semiconductor region. The high resistance part is located in the first semiconductor region and has a higher electrical resistance than the first semiconductor region. A plurality of the structure bodies includes first to third structure bodies. The second and third structure bodies are next to the first structure body. The high resistance part overlaps a circle center of an imaginary circle passing through centers of the first to third structure bodies.

Abstract: A semiconductor device includes a semiconductor fin, a gate structure, and a dielectric isolation plug. The semiconductor fin extends along a first direction above a substrate and includes a silicon germanium layer and a silicon layer over the silicon germanium layer. The gate structure extends across the semiconductor fin along a second direction perpendicular to the first direction. The dielectric isolation plug extends downwardly from a top surface of the silicon layer into the silicon germanium layer when viewed in a cross section taken along the first direction.

Abstract: A semiconductor device includes a polycrystalline silicon part buried in a termination region of a silicon layer. The polycrystalline silicon part contacts the silicon layer, has a higher crystal grain density than the silicon layer, and includes a heavy metal. The silicon layer includes a drift layer located in a cell region and the termination region. The drift layer has a lower first-conductivity-type impurity concentration than a silicon substrate. The drift layer includes a same element of heavy metal as the heavy metal included in the polycrystalline silicon part.

Abstract: A semiconductor device includes: a silicon carbide semiconductor body having a source region of a first conductivity type and a body region of a second conductivity type; and a trench structure extending from a first surface into the silicon carbide semiconductor body along a vertical direction, the trench structure having a gate electrode and a gate dielectric. The trench structure is stripe-shaped and runs along a longitudinal direction that is perpendicular to the vertical direction. The source region includes a first source sub-region and a second source sub-region alternately arranged along the longitudinal direction. A doping concentration profile of the first source sub-region along the vertical direction differs from a doping concentration profile of the second source sub-region along the vertical direction. A corresponding method of manufacturing the semiconductor device is also described.

Abstract: Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof. According to embodiments of the present disclosure, a height of the work function layer, especially a height of the second portion of the work function layer, is significantly increased, and a height of the first gate material layer is significantly reduced, so that the height ratio of the second portion of the work function layer to the first gate material layer to the second gate material layer is maintained at 3 to 8:1 to 1.5:1; therefore, it can be ensured that the work function of the WL groove filling material layer of the recessed gate structure with a small WL width will be significantly increased, thereby greatly weakening the row hammer effect at the bottom of the WL groove and obviously reducing the GIDL effect at the upper part of the WL groove.

Abstract: A manufacturing method for a semiconductor device is provided. The method includes: forming a recess at a top surface of a substrate; forming a channel layer and a barrier layer in order, to conformally cover surfaces of the recess; filling up the recess with a conductive material; removing a top portion of the conductive material, such that a lower portion of the conductive material remained in the recess forms a gate electrode; and forming an insulating structure on the gate electrode. A hetero junction formed at an interface of the channel layer and the barrier layer is external to the substrate, and a two dimensional electron gas or a two dimensional hole gas is induced along the hetero junction external to the substrate.

Abstract: Methods of forming transistors include providing a substrate material, forming a recess to a first depth in the substrate material, the recess corresponding to a gate region and extending in a channel length direction and a channel width direction that is perpendicular to the channel length direction, forming a trench structure in the substrate material by deepening the recess to a second depth using an isotropic process, forming an isolation layer on the substrate material, forming a gate portion of the isolation layer on the substrate material such that the gate portion of the isolation layer extends into the trench structure, and forming a gate on the isolation layer such that the gate extends into the trench structure.

Abstract: The present disclosure provides a method for manufacturing a semiconductor device having a buried wordline. The method includes forming a first recessed portion in a first dielectric layer in a substrate; forming a second recessed portion spaced apart from the first recessed portion and in the substrate; disposing a protection layer on the substrate to cover the second recessed portion; and disposing a second dielectric layer on the first dielectric layer.

Abstract: The present application provides a method of manufacturing a memory device having a word line (WL) with improved adhesion between a work function member and a conductive layer. The method includes steps of providing a semiconductor substrate defined with an active area and including an isolation structure surrounding the active area; forming a recess extending into the semiconductor substrate and across the active area; forming a first insulating layer conformal to the recess; disposing a first conductive material conformal to the first insulating layer; forming a conductive member surrounded by the first conductive material; disposing a second conductive material over the conductive member and removing a portion of the first conductive material above the second conductive material to form a conductive layer enclosing the conductive member; and forming a second insulating layer over the conductive layer and conformal to the first insulating layer.

Abstract: Disclosed is a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a drift region on a substrate, a well region on the drift region, a source-end doped region in the well region, a drain-end doped region on the drift region, and a gate structure which is located between a source end and a drain end, located at a position of the well region, and forms a channel region in the well region. The source-end doped region comprises a first doped region and a second doped region with opposite doping types, the channel region connects the first doped region and the drift region. The first doped region and the second doped region of the source end are equivalently close to the gate structure, a distance between the second doped region and a PN junction surface formed by the drift region and the well region is reduced.

Abstract: An integrated circuit device includes a substrate having an active region and a word line trench therein. The word line trench includes a lower portion having a first width, and an upper portion, which extends between the lower portion and a surface of the substrate and has a second width that is greater than the first width. A word line is provided, which extends in and adjacent a bottom of the word line trench. A gate insulation layer is provided, which extends between the word line and sidewalls of the lower portion of the word line trench. An electrically insulating gate capping layer is provided in the upper portion of the word line trench. An insulation liner is provided, which extends between the gate capping layer and sidewalls of the upper portion of the word line trench. The gate insulation layer extends between the insulation liner and a portion of the gate capping layer, which extends within the upper portion of the word line trench.

Abstract: Merged-PiN-Schottky, MPS, device comprising: a substrate of SiC with a first conductivity; a drift layer of SiC with the first conductivity, on the substrate; an implanted region with a second conductivity, extending at a top surface of the drift layer to form a junction-barrier, JB, diode with the substrate; and a first electrical terminal in ohmic contact with the implanted region and in direct contact with the top surface to form a Schottky diode with the drift layer. The JB diode and the Schottky diode are alternated to each other along an axis: the JB diode has a minimum width parallel to the axis with a first value, and the Schottky diode has a maximum width parallel to the axis with a second value smaller than, or equal to, the first value. A breakdown voltage of the MPS device is greater than, or equal to, 115% of a maximum working voltage of the MPS device in an inhibition state.

Abstract: A power electronics converter includes a multi-layer planar carrier substrate having a plurality of electrically conductive layers, at least one electrical connection, and a converter commutation cell comprising a power circuit and a gate driver circuit. The power circuit includes at least one power semiconductor switching element and at least one capacitor. Each power semiconductor switching element is included in a power semiconductor prepackage having one or more power semiconductor switching elements embedded in a solid insulating material. The power electronics converter includes a heat sink configured to remove heat from the power semiconductor prepackage. A converter parameter ? is greater than or 20 equal to 100 kW/m3K, ? being defined as a heat transfer coefficient between the heat removal side of the power semiconductor prepackage and a cooling medium of the heat sink divided by the size of a gap between the power semiconductor prepackage and the heat sink.

Abstract: A transistor device includes field plate contacts that electrically connect a final metallization layer to field electrodes in underlying trenches, and mesa contacts that electrically connect the final metallization layer to semiconductor mesas confined by the trenches. Each field plate contact is divided into field plate contact segments that are separated from one another. Each mesa contact is divided into mesa contact segments that are separated from one another. In a first area adjacent to an end of the trenches, a first line that runs perpendicular to the trenches intersects a first field plate contact segment of the field plate contacts and a first mesa contact segment of the mesa contacts. In a second area spaced inward from the first area, a second line that runs perpendicular to the trenches intersects a second field plate contact segment of the field plate contacts and a second mesa contact segment of the mesa contacts.

Abstract: A split gate MOSFET is provided. The split gate MOSFET may have a low capacitance between a gate electrode and a source electrode. The trench MOSFET includes a substrate; a gate trench formed on the substrate; a sidewall insulating layer formed on a sidewall of the gate trench; a source electrode surrounded by the sidewall insulating layer; a first upper electrode provided above the source electrode; a first inter-electrode insulating layer formed between the source electrode and the first upper electrode; a second upper electrode formed adjacent to a side of the first upper electrode and surrounding the first upper electrode; and an interlayer insulating layer formed on the first upper electrode and the second upper electrode.

Abstract: A method for manufacturing a nitride semiconductor device includes: selectively ion-implanting an element that is other than p-type impurities and n-type impurities into a first region in a first primary surface of a gallium nitride layer so as to generate crystal defects in the first region; selectively ion-implanting a p-type impurity into a second region in the gallium nitride layer, the second region being shallower than the first region in a depth direction and being within the first region in a plan view; and thermally treating said gallium nitride layer that has been ion-implanted with said element and said p-type impurity so as to thermally diffuse said p-type impurity in the second region into a third region that is within the first region and that surrounds a bottom and sides of the second region.

Abstract: A method for manufacturing a buried gate and a method for manufacturing a semiconductor device are disclosed. The method for manufacturing the buried gate includes that: a trench is provided on an active region of a substrate; a gate structure is filled in a bottom of the trench, and a trench sidewall above the gate structure is exposed; an epitaxial layer is grown on the exposed trench sidewall with an epitaxial growth process, in which the epitaxial layer does not close the trench; and an isolation layer is filled in the trench.

Abstract: A semiconductor device, and a method of fabricating the semiconductor device including forming on a substrate a device isolation layer defining a plurality of active regions; and forming a plurality of gate lines intersecting the active regions and buried in the substrate. The forming of the gate lines includes forming on the substrate a trench that intersects the active regions; forming a work-function control layer on a sidewall and a bottom surface of the trench; forming a conductive layer on the work-function control layer; sequentially forming a barrier layer and a source layer on the work-function control layer and the conductive layer, the source layer including a work-function control element; and diffusing the work-function control element from the source layer into an upper portion of the work-function control layer.

Abstract: An IGBT chip having a ?-shape mixed gate structure includes a plurality of mixed gate units. Each of the mixed gate units includes a gate region and two active regions located at two sides of the gate region. The gate region includes a trench gate and a planar gate that is located on a surface of the gate region, and the planar gate is connected with the trench gate and formed a ?-shape mixed structure. In this way, the IGBT chip can have a significantly improved chip density, while retaining features of low power consumption and high current density of the trench gate and a feature of a wide safe operating area of the planar gate.

Abstract: A MOSFET includes: a semiconductor base substrate having an n-type column region and a p-type column region, the n-type column region and the p-type column region forming a super junction structure; and a gate electrode formed by way of a gate insulation film. Assuming a region of the semiconductor base substrate which provides a main operation of the MOSFET as an active region, a region of the semiconductor base substrate maintaining a withstand voltage of the MOSFET as an outer peripheral region, and a region of the semiconductor base substrate disposed between the active region and the outer peripheral region as an active connecting region, out of the active region, the active connecting region, and the outer peripheral region of the semiconductor base substrate, the crystal defects are formed only in the active region and the active connecting region.

Abstract: A semiconductor device includes pads arrayed between a region where a transistor portion or a diode portion is disposed and a first end side on an upper surface of a semiconductor substrate, and a gate runner portion that transfers a gate voltage to the transistor portion. The gate runner portion has a first gate runner disposed passing between the first end side of the semiconductor substrate and at least one of the pads in the top view, and a second gate runner disposed passing between at least one of the pads and the transistor portion in the top view. The transistor portion is also disposed in the inter-pad regions, the gate trench portion disposed in the inter-pad regions is connected to the first gate runner, and the gate trench portion arranged so as to face the second gate runner is connected to the second gate runner.

Abstract: A semiconductor device includes a substrate, a drift layer provided on an upper surface side of the substrate, a base layer provided on the upper surface side of the drift layer, an upper semiconductor layer provided on the upper surface side of the base layer, a first electrode provided on the upper surface of the substrate, a second electrode provided on a rear surface of the substrate, a trench extending to the drift layer from the upper surface of the substrate and a gate electrode provided inside the trench, wherein an inner side surface of the trench has a first surface and a second surface provided below the first surface, the second surface tilts inward of the trench with respect to the first surface, and an intersection point of the first surface and the second surface is provided below the base layer.

Abstract: A semiconductor device is provided. The semiconductor device includes a base substrate; and a first gate structure and doped source/drain layers on the base substrate. The doped source/drain layers are on both sides of the first gate structure. The semiconductor device further includes a dielectric layer on a surface of the base substrate. The dielectric layer covers the doped source/drain layers, and the dielectric layer contains a first trench on the doped source/drain layer. The first trench includes a first region filled by an insulation layer and a second region filled by first conductive structure under the insulation layer. A top size of the insulation layer in the first region is larger than a bottom size of the insulation layer in the first region. A maximum size of the first conductive structure in the second region is smaller than the bottom size of the insulation layer in the first region.

Abstract: A resistive random access memory cell includes a first electrode layer, an oxygen reservoir layer, a variable resistance layer, and a second electrode. The first electrode layer is located on a dielectric layer, and includes a body part extending in a first direction and multiple extension parts connected to a sidewall of the body part and extending in a second direction. The second direction is perpendicular to the first direction. The oxygen reservoir layer covers the first electrode layer. The variable resistance layer is located between the first electrode layer and the oxygen reservoir layer. The second electrode is located above a top surface of the oxygen reservoir layer and around an upper sidewall of the oxygen reservoir layer.

Abstract: A method used in forming a memory array comprises forming a stack comprising vertically-alternating first tiers and second tiers. A first insulator tier is above the stack. First insulator material of the first insulator tier comprises at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. Channel-material strings are in the stack and in the first insulator tier. Conducting material is in the first insulator tier directly against sides of individual of the channel-material strings. A second insulator tier is formed above the first insulator tier and the conducting material. Second insulator material of the second insulator tier comprises at least one of the (a) and the (b). Conductive vias are formed and extend through the second insulator tier and that are individually directly electrically coupled to the individual channel-material strings through the conducting material.

Abstract: An inverter includes a transistor, an additional transistor overlying the transistor, and a hybrid gate electrode interposed between and shared by the transistor and the additional transistor. The hybrid gate electrode includes a region overlying a channel structure of the transistor, an additional region overlying the region and underlying an additional channel structure of the additional transistor, and further region interposed between the region and the additional region. The region has a first material composition. The additional region has a second material composition different than the first material composition of the region. Memory devices and electronic systems are also described.

Abstract: A semiconductor device is described. The semiconductor device includes: a Si substrate having a first main surface; a plurality of gate trenches extending from the first main surface into the Si substrate; a semiconductor mesa between adjacent gate trenches; a first interlayer dielectric on the first main surface; a plurality of first metal contacts extending through the first interlayer dielectric and contacting gate electrodes disposed in the gate trenches; a plurality of second metal contacts extending through the first interlayer dielectric and contacting the semiconductor mesas; and an air gap or a dielectric material having a lower dielectric constant than the first interlayer dielectric between adjacent first and second metal contacts. Methods of producing the semiconductor device are also described.

Abstract: An improved SiC trench MOSFET having first and second type gate trenches for formation of a gate electrode, and a grounded P-shield region under the gate electrode for gate oxide electric-field reduction is disclosed. The gate electrodes are disposed into the first type gate trench having a thick oxide layer on trench bottom. The grounded P-shield region surrounding the second type gate trench filled up with the thick oxide layer is connected with a source metal through a grounded P region. The device further comprises a current spreading region surrounding the first type gate trench for on-resistance reduction.

Abstract: This disclosure relates to semiconductor devices, and, more particularly, to a semiconductor structure that improves the switching speed of a switch for which the turn-off process depends on the recombination speed of charge carriers. The disclosure describes a semiconductor device formed on a semiconductor substrate that includes a power semiconductor switch having a drift region in the semiconductor substrate, an Extraction Plug in electrical contact with the drift region of the power semiconductor switch, and an extraction device electrically coupled to the Extraction Plug. The extraction device is structured to remove charge carriers from the drift region through the Extraction Plug when the extraction device is turned on. Methods are also described.

Abstract: A silicon carbide substrate is provided that includes a drift layer of a first conductivity type and a trench extending from a main surface of the silicon carbide substrate into the drift layer. First dopants are implanted through a first trench sidewall of the trench. The first dopants have a second conductivity type and are implanted at a first implant angle into the silicon carbide substrate, wherein at the first implant angle channeling occurs in the silicon carbide substrate. The first dopants form a first compensation layer extending parallel to the first trench sidewall.

Abstract: The present disclosure provides a semiconductor memory structure. The semiconductor memory structure includes a substrate, a gate structure, a drain stressor and a source stressor. The gate structure is disposed in the substrate. Each of the source stressor and the drain stressor includes a strained part disposed in the substrate.

Abstract: Some embodiments include an integrated assembly having a first deck which has first memory cells, and having a second deck which has second memory cells. The first memory cells have first control gate regions which include a first conductive material vertically between horizontally-extending bars of a second conductive material. The second memory cells have second control gate regions which include a fourth conductive material along an outer surface of a third conductive material. A pillar passes through the first and second decks. The pillar includes a dielectric-barrier material laterally surrounding a channel material. The first and fourth materials are directly against the dielectric-barrier material. Some embodiments include methods of forming integrated assemblies.

Abstract: A semiconductor device may include a substrate including a recess, a gate insulation layer on a surface of the recess, an impurity barrier layer on a surface of the gate insulation layer to cover the surface of the gate insulation layer, a first gate pattern on impurity barrier layer to fill a lower portion of the recess, a second gate pattern on the first gate pattern in the recess, a capping insulation pattern on the second gate pattern to fill the recess, and impurity regions at the substrate adjacent to an upper sidewall of the recess. The impurity barrier layer may have a concentration of nitrogen higher than a concentration of nitrogen included in the gate insulation layer. The second gate pattern may include a material different from a material of the first gate pattern. A lower surface of the impurity regions may be higher than an upper surface of the first gate pattern. Thus, the semiconductor device may have good characteristics.

Abstract: A power semiconductor device first trench structures extending from a first main surface into a semiconductor body up to a first depth. The first trench structures extend in parallel along a first lateral direction. Each first trench structure includes a first dielectric and a first electrode. The power semiconductor device further includes second trench structures extending from the first main surface into the semiconductor body up to a second depth that is smaller than the first depth. The second trench structures extend in parallel along a second lateral direction and intersect the first trenches at intersection positions. Each second trench structure includes a second dielectric and a second electrode. The second dielectric is arranged between the first electrode and the second electrode at the intersection positions.

Abstract: A thin film transistor array substrate and an electronic device including the thin film transistor array are disclosed. The thin film transistor comprises a substrate, a first active layer on the substrate, a gate electrode on the first active layer, a second active layer on the gate electrode such that the gate electrode is between the first active layer and the second active layer. The gate electrode is configured to drive the first active layer and the second active layer. Thereby, it is possible to provide the thin film transistor array substrate including one or more thin film transistors having high current characteristics in a small area, and the electronic device including the thin film transistor array substrate.

Abstract: Transistor device and method of making thereof comprising a substrate heavily doped with a first conductivity type and an epitaxial layer lightly doped with the first conductivity type on top of the substrate. A body region doped with a second conductivity type is formed in the epitaxial layer wherein the second conductivity type is opposite the first conductivity type and a source region doped with the first conductivity type is formed in the body region of the epitaxial layer. An integrated planar-trench gate having a planar gate portion is formed on the surface of the epitaxial layer that is contiguous with a gate trench portion formed in the epitaxial layer.

Abstract: A semiconductor device includes a semiconductor part, first to third electrodes, and first and second control electrodes. The semiconductor part is provided between the first and second electrodes. On the second electrode side of the semiconductor part, the first control electrode and the third electrode are provided in a first trench, and the second control electrode is provided in a second trench. The first control electrode is provided between the second and third electrode. In a first direction from the first control electrode toward the second control electrode, the first trench has first and second widths. The first width is a combined width of the third electrode and insulating portions provided on both sides of the third electrode. The second width is a combined width of the first control electrode and the gate insulating films on both sides thereof. The first width is greater than the second width.

Abstract: A SiC Schottky rectifier with surge current ruggedness is described. The Schottky rectifier includes one or more multi-layer bodies that provide multiple types of surge current protection.