Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes: a substrate; a doped region within the substrate; a pair of source/drain regions extending along a first direction on opposite sides of the doped region; a gate electrode disposed in the doped region, wherein the gate electrode has a plurality of first segments between the pair of source/drain regions; and a protection structure overlapping the gate electrode.

Abstract: The present application provides a method for manufacturing a memory device having word lines with improved resistance, and a manufacturing method of the memory device. The method includes providing a semiconductor substrate defined with a peripheral region and an array region at least partially surrounded by the peripheral region; forming a first recess extending into the semiconductor substrate and disposed in the array region; and forming a word line disposed within the first recess. The formation of the word line includes disposing an insulating layer conformal to the first recess, and forming a conductive member surrounded by the insulating layer and having a second recess extending into the conductive member and toward the semiconductor substrate.

Abstract: A high voltage superjunction MOSFET includes a semiconductor substrate and a semiconductor layer having columns of first and second conductivity. A buffer layer of the first conductivity is between the semiconductor substrate and semiconductor layer. A plug region of the second conductivity is formed at a semiconductor layer surface and extends to the columns. A source/drain region is formed at the semiconductor layer surface and is connected to the plug region. The source/drain region has a concentration of the first conductivity between about 1×1019 cm?3 and 1.5×1020 cm?3. A body region of the second conductivity is between the source/drain region and the first column and is connected to the plug region. A gate trench is formed in the semiconductor layer surface and extends toward the first column and has a trench gate electrode disposed therein. A dielectric layer separates the trench gate electrode from the first column.

Abstract: A power device includes a gate, and a segmented source adjacent to the gate, wherein the segmented source includes segments having a first threshold voltage and includes segments having a second threshold voltage different from the first threshold voltage.

Abstract: A semiconductor process system etches gate metals on semiconductor wafers. The semiconductor process system includes a machine learning based analysis model. The analysis model dynamically selects process conditions for an etching process. The process system then uses the selected process conditions data for the next etching process.

Abstract: A semiconductor memory device includes a substrate, an active structure, a shallow trench isolation and a plurality of word lines. The active structure is disposed in the substrate, and includes a plurality of first active fragments and a plurality of second active fragments extended parallel to each other along a first direction and the second active fragments are disposed outside a periphery of all of the first active fragments. The shallow trench isolation is disposed in the substrate to surround the active structure, and which includes a plurality of first portions and a plurality of second portions. The word lines are disposed in the substrate, parallel with each other to extend along a second direction, wherein at least one of the word lines are only intersected with the second active fragments, or at least one of the word lines does not pass through any one of the second portions.

Abstract: A semiconductor device includes a substrate, a passing word line in the substrate, and a dielectric structure surrounding the passing word line. The dielectric structure has an enlargement portion at a bottom of the dielectric structure, and a maximum width of the enlargement portion of the dielectric structure is wider than a width of a top of the dielectric structure.

Abstract: The present disclosure relates to an integrated chip comprising a substrate having a first pair of opposing sidewalls that define a trench. The trench extends into a front-side surface of the substrate. A first source/drain region is disposed along the front-side surface of the substrate. A second source/drain region is disposed along the front-side surface of the substrate. A gate structure is disposed within the trench and is arranged laterally between the first source/drain region and the second source/drain region. The gate structure fills the trench and extends along the first pair of opposing sidewalls to an upper surface of the substrate. A bottom surface of the gate structure is disposed below a bottom surface of the first source/drain region.

Abstract: A semiconductor device according to an embodiment includes first to third semiconductor regions, a structure body, a gate electrode, and a high resistance part. The structure body includes an insulating part and a conductive part. The insulating part is arranged with the third semiconductor region, the second semiconductor region, and a portion of the first semiconductor region. The conductive part is located in the insulating part. The conductive part includes a portion facing the first semiconductor region. The high resistance part is located in the first semiconductor region and has a higher electrical resistance than the first semiconductor region. A plurality of the structure bodies includes first to third structure bodies. The second and third structure bodies are next to the first structure body. The high resistance part overlaps a circle center of an imaginary circle passing through centers of the first to third structure bodies.

Abstract: The present disclosure provides a semiconductor device and a manufacturing method thereof. The method for manufacturing a semiconductor device includes: providing a semiconductor substrate, with a plurality of trench isolation structures and a plurality of functional regions between the trench isolation structures being formed; forming a buried bit line structure, the buried bit line structure being formed in the semiconductor substrate; and forming a word line structure and a plurality of active regions, the word line structures and the active regions being formed on a surface of the semiconductor substrate and located above the functional regions.

Abstract: An integrated circuit device includes a substrate having an active region and a word line trench therein. The word line trench includes a lower portion having a first width, and an upper portion, which extends between the lower portion and a surface of the substrate and has a second width that is greater than the first width. A word line is provided, which extends in and adjacent a bottom of the word line trench. A gate insulation layer is provided, which extends between the word line and sidewalls of the lower portion of the word line trench. An electrically insulating gate capping layer is provided in the upper portion of the word line trench. An insulation liner is provided, which extends between the gate capping layer and sidewalls of the upper portion of the word line trench. The gate insulation layer extends between the insulation liner and a portion of the gate capping layer, which extends within the upper portion of the word line trench.

Abstract: This disclosure provides a semiconductor structure and a method of forming buried field plate structures. The semiconductor structure includes a substrate, buried field plate structures, and a gate. The substrate incudes a first surface and a second surface opposite the first surface. Each of the buried field plate structures include a conductive structure and an insulation structure surrounding the conductive structure. The gate is embedded in the substrate and extend into the substrate from the first surface of the substrate, wherein the gate is configured between the two neighboring buried field plate structures. The conductive structure includes portions arranging along a direction perpendicular to the first surface of the substrate and having different widths in a direction parallel to the first surface of the substrate.

Abstract: There is provided a semiconductor device including: a drift region of a first conductivity type disposed in a semiconductor substrate; a base region of a second conductivity type disposed above the drift region; an emitter region of the first conductivity type disposed above the base region; a plurality of trench portions arrayed in a predetermined array direction on a front surface side of the semiconductor substrate; a trench contact disposed on the front surface side of the semiconductor substrate between two adjacent trench portions; and a contact layer of the second conductivity type disposed under the trench contact and having a higher doping concentration than the base region, wherein a lower end of the trench contact is deeper than a lower end of the emitter region, and the emitter region and the contact layer are in contact with each other at a side wall of the trench contact.

Abstract: A semiconductor device includes: a semiconductor substrate; an epitaxial layer or layer stack on the semiconductor substrate; a plurality of transistor cells of a first type formed in a first region of the epitaxial layer or layer stack and electrically coupled in parallel to form a vertical power transistor; a plurality of transistor cells of a second type different than the first type and formed in a second region of the epitaxial layer or layer stack; and an isolation structure that laterally and vertically delimits the second region of the epitaxial layer or layer stack. Sidewalls and a bottom of the isolation structure include a dielectric material that electrically isolates the plurality of transistor cells of the second type from the plurality of transistor cells of the first type in the epitaxial layer or layer stack. Methods of producing the semiconductor device are also described.

Abstract: A semiconductor device structure including a doped region under an isolation feature is provided. The semiconductor device structure includes a first substrate, a first well region, a first gate structure, a second gate structure, a first doped region, and a first conductive feature. The substrate has a first surface and a second surface opposite to the first surface. The first well region is in the first substrate. The first well region has a first conductive type. The first gate structure is disposed on the second surface. The second gate structure is disposed on the second surface. The first doped region includes a second conductive type different from the first conductive type. The first doped region is disposed between the first gate structure and the second gate structure. The first conductive feature extends between the first surface of the first substrate and the first doped region.

Abstract: A semiconductor device includes a stacked line structure including a bit line over a substrate, an active layer positioned at a higher level than the stacked line structure and parallel to the bit line, a capacitor positioned at a higher level than the active layer, a first plug extending downwardly to be coupled to the bit line through the active layer, a second plug formed between the active layer and the capacitor, and a word line extending in a direction that intersects with the bit line while intersecting with the active layer.

Abstract: A semiconductor structure includes a substrate, an isolation structure formed in the substrate, and a word line including a first convex portion and a second convex portion. The first convex portion and the second convex portion are located in the isolation structure, and a depth of the first convex portion is greater than a depth of the second convex portion.

Abstract: A semiconductor rectifier device comprises: an epitaxial layer having a top surface and a bottom surface; a first trench comprising a first side wall, a second side wall, and a first bottom surface; a second trench adjacent to the first trench, the second trench comprising a third side wall, a fourth side wall, and a second bottom surface; a first doped region abutting against the first side wall and at least a part of the first bottom surface of the first trench; a second doped region adjacent to and separated from the first doped region, wherein the second doped region abuts against the third side wall, the fourth side wall and the second bottom surface of the second trench; a gate structure disposed on the top surface between the first trench and the second trench; and a contact metal layer disposed on the top surface of the epitaxial layer.

Abstract: An electronic device can include a substrate, an active region of a transistor, and a shield electrode. The substrate can define a trench and include a mesa adjacent to the trench, and the shield electrode can be within the trench. In an embodiment, the electronic device can further include an active region of a transistor within the mesa and an insulating layer including a thicker section and a thinner section closer to a bottom of the trench. In another embodiment, the electronic device can include a body region and a doped region within the mesa and spaced apart from the body region by a semiconductor region. The doped region can have a dopant concentration that is higher than a dopant concentration of the semiconductor region and a portion of the substrate underlying the doped region.

Abstract: A semiconductor device is described. The semiconductor device includes: a semiconductor substrate having a first main surface; a plurality of gate trenches extending from the first main surface into the semiconductor substrate; a semiconductor mesa between adjacent gate trenches; a first interlayer dielectric on the first main surface; a plurality of first metal contacts extending through the first interlayer dielectric and contacting gate electrodes disposed in the gate trenches; a plurality of second metal contacts extending through the first interlayer dielectric and contacting the semiconductor mesas; and an air gap or a dielectric material having a lower dielectric constant than the first interlayer dielectric between adjacent first and second metal contacts. Methods of producing the semiconductor device are also described.

Abstract: A semiconductor device includes a vertical field-effect transistor including: a first gate trench and a second gate trench extending in a first direction, the second gate trench being deeper than the first trench; a first gate insulating film and a first gate conductor inside the first gate trench; and a second gate insulating film and a second gate conductor inside the second gate trench. The first gate conductor and the second gate conductor have the same potential. When a total number of first gate trenches is denoted by n, a total number of second gate trenches is at least 2 and at most n+1. In a second direction orthogonal to the first direction, the second gate trench is disposed at each of farthest ends of a region in which the first gate trenches and the second gate trenches are disposed.

Abstract: To reduce on-resistance while suppressing a characteristic variation increase of a vertical MOSFET with a Super Junction structure, the vertical MOSFET includes a semiconductor substrate having an n-type drift region, a p-type base region formed on the surface of the n-type drift region, a plurality of p-type column regions disposed in the n-type drift region at a lower portion of the p-type base region by a predetermined interval, a plurality of trenches whose bottom surface reaches a position deeper than the p-type base region and that is disposed between the adjacent p-type column regions, a plurality of gate electrodes formed in the plurality of trenches, and an n-type source region formed on the side of the gate electrode in the p-type base region.

Abstract: The present disclosure relates to a semiconductor memory device including a substrate, a plurality of buried word lines, a plurality of bit lines, and a plurality isolation fins. The substrate includes a plurality of active areas and a shallow trench isolation. The buried word lines are disposed in the substrate. The bit lines are disposed on the substrate. The isolation fins are disposed on the substrate, over each of the buried word lines respectively, wherein a portion of the isolation fins is disposed under the bit lines and overlapped with the bit lines.

Abstract: The disclosure relates to a semiconductor die with a transistor device, which has a channel region formed in a semiconductor body, a gate region aside the channel region, for controlling a channel formation, a drift region formed in the semiconductor body, and a field electrode in a field electrode trench, which extends from a frontside of the semiconductor body vertically into the drift region, wherein an insulating layer is formed on the frontside of the semiconductor body and a frontside metallization is formed on the insulating layer, and wherein a capacitor electrode is formed in the insulating layer, which is conductively connected to at least a portion of the field electrode.

Abstract: A SiC Schottky rectifier with surge current ruggedness is described. The Schottky rectifier includes one or more multi-layer bodies that provide multiple types of surge current protection.

Abstract: A semiconductor device having a gate-all-around structure includes a first fin pattern and a second fin pattern separated by a first trench and extending in a first direction, a first nanosheet on the first fin pattern, a second nanosheet on the second fin pattern, a first fin liner extending along at least a portion of a sidewall and a bottom surface of the first trench, a first field insulation layer disposed on the first fin liner and filling a portion of the first trench, and a first gate structure overlapping an end portion of the first fin pattern and including a first gate spacer. A height from the bottom surface of the first trench to a lower surface of the first gate spacer is greater than a height from the bottom surface of the first trench to an upper surface of the first field insulation layer.

Abstract: A semiconductor device manufacturing method according to the exemplary embodiments of the disclosure includes patterning a substrate, thereby forming an active pattern, forming a trench penetrating the active pattern, forming a support layer covering the trench, forming a first opening at the support layer, forming a gate electrode layer filling the trench through the first opening, and forming a bit line structure electrically connected to the active pattern. The support layer includes a base portion covering a top surface of the active pattern, and a support disposed in the trench.

Abstract: A semiconductor structure and a forming method thereof are disclosed in the embodiments of the present disclosure. The semiconductor structure includes: a base, wherein a gate dielectric layer defining a groove is provided in the base, a source region and a drain region are located on two opposite sides at a top of the groove, and the groove has an extension direction parallel to a surface of the base; a first gate, including a first work function layer and a first conductive layer, wherein the first work function layer covers a bottom surface and partial sidewall of the groove, and the first conductive layer covers a surface of the first work function layer; and a second gate, including a second work function layer and a second conductive layer, wherein the second gate is laminated on the first gate and has a top surface lower than the surface of the base.

Abstract: A semiconductor device includes a first fin-shaped pattern which extends lengthwise in a first direction, a second fin-shaped pattern which is spaced apart from the first fin-shaped pattern in a second direction and extends lengthwise in the first direction, a first gate electrode extending lengthwise in the second direction on the first fin-shaped pattern, a second gate electrode extending lengthwise in the second direction on the second fin-shaped pattern, a first gate separation structure which separates the first gate electrode and the second gate electrode and is at the same vertical level as the first gate electrode and the second gate electrode, and a first source/drain contact extending lengthwise in the second direction on the first fin-shaped pattern and the second fin-shaped pattern.

Abstract: Embodiments of the present application provide a semiconductor structure and its fabricating method, and a semiconductor memory. The method of fabricating a semiconductor structure comprises providing a substrate and performing ion implantation on the substrate to form an active area, forming a gate groove on surface of the substrate, measuring depth of the gate groove, and performing ion implantation compensation, if the depth of the gate groove meets a preset condition, on the substrate according to the depth of the gate groove, and forming an ion compensation region in the active area at one side of the gate groove.

Abstract: The present application discloses a vertical UMOSFET device with a high channel mobility and a preparation method thereof. The vertical UMOSFET device with a high channel mobility includes an epitaxial structure, and a source, a drain and a gate which match the epitaxial structure, where the epitaxial structure includes a first semiconductor, and a second semiconductor and a third semiconductor which are sequentially disposed on the first semiconductor, a groove structure matching the gate is also disposed in the epitaxial structure, and the groove structure continuously extends into the first semiconductor from a first surface of the epitaxial structure; a fourth semiconductor is also disposed at least between an inner wall of the groove structure and the second semiconductor, and the fourth semiconductor is a high resistivity semiconductor.

Abstract: A thin film transistor array substrate and an electronic device including the thin film transistor array are disclosed. The thin film transistor comprises a substrate, a first active layer on the substrate, a gate electrode on the first active layer, a second active layer on the gate electrode such that the gate electrode is between the first active layer and the second active layer. The gate electrode is configured to drive the first active layer and the second active layer. Thereby, it is possible to provide the thin film transistor array substrate including one or more thin film transistors having high current characteristics in a small area, and the electronic device including the thin film transistor array substrate.

Abstract: A semiconductor device includes a semiconductor layer having a main surface in which a trench is formed, a first-conductivity-type body region formed along a sidewall of the trench in a surface layer portion of the main surface of the semiconductor layer, a second-conductivity-type impurity region formed along the sidewall of the trench in a surface layer portion of the body region, a gate insulating layer formed on an inner wall of the trench, a gate electrode that is embedded in the trench and that faces the body region and the impurity region with the gate insulating layer placed between the gate electrode and the body region and between the gate electrode and the impurity region, a contact electrode that passes through the sidewall of the trench from inside the trench and is drawn out to the surface layer portion of the main surface of the semiconductor layer and is electrically connected to the body region and to the impurity region, and an embedded insulating layer that is interposed between the gate el

Abstract: A semiconductor device structure including a doped region under an isolation feature is provided. The semiconductor device structure includes a first substrate, a first well region, a first gate structure, a second gate structure, a first doped region, and a first conductive feature. The substrate has a first surface and a second surface opposite to the first surface. The first well region is in the first substrate. The first well region has a first conductive type. The first gate structure is disposed on the second surface. The second gate structure is disposed on the second surface. The first doped region includes a second conductive type different from the first conductive type. The first doped region is disposed between the first gate structure and the second gate structure. The first conductive feature extends between the first surface of the first substrate and the first doped region.

Abstract: A semiconductor device includes a vertical field-effect transistor including: a low-concentration impurity layer; a body region; a gate trench; a gate insulating film; and a gate conductor. The body region includes: a first body portion containing an active region and has a constant depth; and a second body portion adjacent to the first body portion and includes a zone that has a limited length in a second direction orthogonal to the first direction along the top surface of the low-concentration impurity layer, and has a constant depth at a position shallower than the constant depth of the first body portion. The second body portion includes a portion in which a region having relatively high concentration of an impurity and a region having relatively low concentration of an impurity are alternately and periodically present in the first direction in a cross-sectional view of a plane orthogonal to the second direction.

Abstract: A super junction structure includes a substrate, wherein the substrate has a first conductivity type. The super junction structure includes an epitaxial layer over the substrate, wherein the epitaxial layer has a second conductivity type opposite the first conductivity type. The super junction structure further includes a bury layer between the epitaxial layer and the substrate, wherein the bury layer has the second conductivity type. The super junction structure further includes a conductive pillar in the epitaxial layer, wherein the conductive pillar has the first conductivity type, sidewalls of the conductive pillar are angled with respect to a top-most surface of the epitaxial layer, a bottom surface of the conductive pillar is rounded, and a top-most surface of the conductive pillar is coplanar with the top-most surface of the epitaxial layer.

Abstract: The present disclosure provides a semiconductor structure comprising one or more fins formed on a substrate and extending along a first direction; one or more gates formed on the one or more fins and extending along a second direction substantially perpendicular to the first direction, the one or more gates including an first isolation gate and at least one functional gate; source/drain features formed on two sides of each of the one or more gates; an interlayer dielectric (ILD) layer formed on the source/drain features and forming a coplanar top surface with the first isolation gate. A first height of the first isolation gate is greater than a second height of each of the at least one functional gate.

Abstract: An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.

Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes a substrate; a gate electrode disposed within the substrate; a gate dielectric layer disposed within the substrate and surrounding the gate electrode; a plurality of first protection structures disposed over the gate electrode; a second protection structure disposed over the gate dielectric layer and contacting the gate dielectric layer; and a pair of source/drain regions on opposing sides of the gate dielectric layer.

Abstract: Some embodiments include an integrated assembly having a first deck which has first memory cells, and having a second deck which has second memory cells. The first memory cells have first control gate regions which include a first conductive material vertically between horizontally-extending bars of a second conductive material. The second memory cells have second control gate regions which include a fourth conductive material along an outer surface of a third conductive material. A pillar passes through the first and second decks. The pillar includes a dielectric-barrier material laterally surrounding a channel material. The first and fourth materials are directly against the dielectric-barrier material. Some embodiments include methods of forming integrated assemblies.

Abstract: A semiconductor device includes a semiconductor part; first and second electrodes respectively on back and front surfaces of the semiconductor part; and a control electrode between the semiconductor part and the second electrode. The control electrode is provided inside a trench of the semiconductor part. The control electrode is electrically insulated from the semiconductor part by a first insulating film and electrically insulated from the second electrode by a second insulating film. The control electrode includes an insulator at a position apart from the first insulating film and the second insulating film. The semiconductor part includes a first layer of a first conductivity type provided between the first and second electrodes, the second layer of a second conductivity type provided between the first layer and the second electrode and the third layer of the first conductivity type selectively provided between the second layer and the second electrode.

Abstract: A method includes forming an ion-implanted capping layer in a first epitaxial layer disposed on a silicon substrate. The ion-implanted capping layer is doped with a second dopant of a same conductivity type as a first dopant in the silicon substrate. The second dopant has a lower diffusivity than the diffusivity of the first dopant. The ion-implanted capping layer has a thickness configured to contain up-diffusion of the first dopant from the silicon wafer in the first epitaxial layer in thermal processes for fabricating a vertical MOSFET device in the substrate. The ion-implanted capping layer is configured to limit up-diffusion of the first dopant from the silicon wafer through the ion-implanted capping layer into a second epitaxial layer such that a concentration of the first dopant in the second epitaxial layer is lower than a concentration of the first dopant in the first epitaxial layer.

Abstract: An apparatus includes a semiconductor substrate; a line-shaped trench in the semiconductor substrate, an inner wall of the line-shaped trench being covered with an insulating film; a first conductive member including first and second line-shaped portions, the first line-shaped portion filling a lower portion of the line-shaped trench; and line-shaped second and third conductive members extending along the inner wall of the line-shaped trench and facing each other, the line-shaped second and third conductive members having a void therebetween; wherein the second line-shaped portion of the first conductive member protrudes from a central portion of the first line-shaped portion to fill the void.

Abstract: A semiconductor is disclosed that may include: a first drift region; a base region arranged on the first semiconductor layer; a source region arranged on the base region; a main electrode electrically connected to the source region; and a gate electrode structure that penetrates the source region and base region and reaches the first drift region, wherein the gate electrode structure comprises: a gate electrode; and an insulating material that insulates the gate electrode from the first drift region and the base region; and a field plate structure reaching the first drift region deeper than the gate electrode structure, wherein the field plate structure comprises: a field plate; a resistive part that electrically connects the main electrode to the field plate; and an insulating material that insulates the field plate and the resistive part section from the first drift region and the base region.

Abstract: A semiconductor device according to an embodiment includes first to third semiconductor regions, a structure body, a gate electrode, and a high resistance part. The structure body includes an insulating part and a conductive part. The insulating part is arranged with the third semiconductor region, the second semiconductor region, and a portion of the first semiconductor region. The conductive part is located in the insulating part. The conductive part includes a portion facing the first semiconductor region. The high resistance part is located in the first semiconductor region and has a higher electrical resistance than the first semiconductor region. A plurality of the structure bodies includes first to third structure bodies. The second and third structure bodies are next to the first structure body. The high resistance part overlaps a circle center of an imaginary circle passing through centers of the first to third structure bodies.

Abstract: A semiconductor device includes a semiconductor fin, a gate structure, and a dielectric isolation plug. The semiconductor fin extends along a first direction above a substrate and includes a silicon germanium layer and a silicon layer over the silicon germanium layer. The gate structure extends across the semiconductor fin along a second direction perpendicular to the first direction. The dielectric isolation plug extends downwardly from a top surface of the silicon layer into the silicon germanium layer when viewed in a cross section taken along the first direction.

Abstract: A semiconductor device includes a polycrystalline silicon part buried in a termination region of a silicon layer. The polycrystalline silicon part contacts the silicon layer, has a higher crystal grain density than the silicon layer, and includes a heavy metal. The silicon layer includes a drift layer located in a cell region and the termination region. The drift layer has a lower first-conductivity-type impurity concentration than a silicon substrate. The drift layer includes a same element of heavy metal as the heavy metal included in the polycrystalline silicon part.

Abstract: A semiconductor device includes: a silicon carbide semiconductor body having a source region of a first conductivity type and a body region of a second conductivity type; and a trench structure extending from a first surface into the silicon carbide semiconductor body along a vertical direction, the trench structure having a gate electrode and a gate dielectric. The trench structure is stripe-shaped and runs along a longitudinal direction that is perpendicular to the vertical direction. The source region includes a first source sub-region and a second source sub-region alternately arranged along the longitudinal direction. A doping concentration profile of the first source sub-region along the vertical direction differs from a doping concentration profile of the second source sub-region along the vertical direction. A corresponding method of manufacturing the semiconductor device is also described.

Abstract: Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof. According to embodiments of the present disclosure, a height of the work function layer, especially a height of the second portion of the work function layer, is significantly increased, and a height of the first gate material layer is significantly reduced, so that the height ratio of the second portion of the work function layer to the first gate material layer to the second gate material layer is maintained at 3 to 8:1 to 1.5:1; therefore, it can be ensured that the work function of the WL groove filling material layer of the recessed gate structure with a small WL width will be significantly increased, thereby greatly weakening the row hammer effect at the bottom of the WL groove and obviously reducing the GIDL effect at the upper part of the WL groove.

Abstract: A manufacturing method for a semiconductor device is provided. The method includes: forming a recess at a top surface of a substrate; forming a channel layer and a barrier layer in order, to conformally cover surfaces of the recess; filling up the recess with a conductive material; removing a top portion of the conductive material, such that a lower portion of the conductive material remained in the recess forms a gate electrode; and forming an insulating structure on the gate electrode. A hetero junction formed at an interface of the channel layer and the barrier layer is external to the substrate, and a two dimensional electron gas or a two dimensional hole gas is induced along the hetero junction external to the substrate.