Gate Electrode In Groove Patents (Class 257/330)
  • Patent number: 11462637
    Abstract: According to one embodiment, a semiconductor device includes first, second, and third conductive members, a semiconductor member, and a first insulating member. The semiconductor member includes a first semiconductor region provided on the first conductive member, a second semiconductor region provided on a portion of the first semiconductor region, and a third semiconductor region provided on the second semiconductor region. An impurity concentration in the third semiconductor region is greater than in the first semiconductor region. The second conductive member includes a first conductive portion electrically connected to the second and third semiconductor regions. The third conductive member is provided on an other portion of the first semiconductor region. At least a portion of the first insulating member is between the semiconductor member and the third conductive member.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: October 4, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Shotaro Baba, Yusuke Kobayashi, Hiroaki Katou, Toshifumi Nishiguchi
  • Patent number: 11456366
    Abstract: A semiconductor device includes a substrate including a first region and a second region, a first silicon-germanium film which is conformally formed inside a surface of the substrate of the first region and defines a first gate trench, a first gate insulating film which extends on the first silicon-germanium film along a profile of the first gate trench and is in physical contact with the first silicon-germanium film, a first metallic gate electrode on the first gate insulating film, a source/drain region formed inside the substrate on both sides of the first metallic gate electrode, a second gate insulating film in the second region and a second metallic gate electrode on the second gate insulating film.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: September 27, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho Kyun An, Su Min Cho
  • Patent number: 11444164
    Abstract: A SGT MOSFET having two stepped oxide (TSO) structure in gate trench is disclosed, wherein the TSO has thinner oxide thickness along upper sidewalls of the gate trench than along lower sidewalls of the gate trench. The BV can be enhanced as result of the electric filed reduction near channel region, on-resistance is thus reduced. The present invention further comprises a super junction region below the oxide charge balance region, making vertical electrical field more uniform, the BV is further enhanced and on-resistance is further reduced.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: September 13, 2022
    Assignee: NAMI MOS CO., LTD.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 11444188
    Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; an insulating material at least partially above the fin, wherein the insulating material includes a trench above the fin; and a gate metal on the insulating material and extending into the trench.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: September 13, 2022
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Nicole K. Thomas, Hubert C. George, Jeanette M. Roberts, Payam Amin, Zachary R. Yoscovits, Roman Caudillo, James S. Clarke
  • Patent number: 11430884
    Abstract: A semiconductor device includes a semiconductor part; first and second electrodes respectively on back and front surfaces of the semiconductor part; third and fourth electrodes inside a trench of the semiconductor part, the fourth electrode being provided between the first electrode and the third electrode; a first insulating portion electrically insulating the third electrode from the semiconductor part; a second insulating portion electrically insulating the third electrode from the second electrode; a third insulating portion electrically insulating the fourth electrode from the semiconductor part; a fourth insulating portion electrically insulating the fourth electrode from the third electrode; and a fifth insulating portion including a first portion and a second portion, the first portion being provided inside the fourth electrode, the second portion extending outward of the fourth electrode.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: August 30, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Toshifumi Nishiguchi
  • Patent number: 11430885
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, first and third semiconductor regions of a first conductivity type, second and fourth semiconductor regions of a second conductivity type, a gate electrode and a second electrode. The third semiconductor region is disposed on one portion of the second semiconductor region. The fourth semiconductor region is disposed on another portion of the second semiconductor region, is positioned below the third semiconductor region. The second electrode includes first and second portions separated from each other and allowing the fourth semiconductor region to be positioned therebetween, and the third portion disposed on the first and second portions and arranged with the third semiconductor region. The first, second, and third portions are in contact with the fourth semiconductor region.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: August 30, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Toshifumi Nishiguchi
  • Patent number: 11424344
    Abstract: A method of manufacturing a trench MOSFET can include: forming a trench extending from an upper surface of a semiconductor base layer to internal portion of the semiconductor base layer; forming a first insulating layer covering sidewall and bottom surfaces of the trench and the upper surface of the semiconductor base layer; forming a shield conductor filling a lower portion of the trench, where the first insulating layer separates the shield conductor from the semiconductor base layer; forming a second insulating layer covering a top surface of the shield conductor, where the first insulating layer separates the second insulating layer from the semiconductor base layer, and the first and second insulating layers conformally form a dielectric layer; and removing the dielectric layer located on the upper surface of the semiconductor base layer and located on the upper sidewall surface of the trench.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: August 23, 2022
    Assignee: HANGZHOU SILICON-MAGIC SEMICONDUCTOR TECHNOLOGY CO., LTD.
    Inventors: Jiakun Wang, Bing Wu
  • Patent number: 11424249
    Abstract: A method including forming an inter-layer insulation layer on a substrate, forming a plug material penetrating the inter-layer insulation layer and contacting a portion of the substrate, forming a contact plug by etching the plug material, forming a trench exposing a side wall of the contact plug by etching the substrate and the inter-layer insulation layer to be aligned with a side wall of the contact plug, forming a gate insulation layer on a surface of the trench and the exposed side wall of the contact plug, and forming a gate electrode partially filling the trench on the gate insulation layer. The method includes an inter-layer insulation layer formed on a substrate, a contact plug penetrating the inter-layer insulation layer and contacting a portion of the substrate, trenches extending in a line shape and aligned with side walls of the contact plug, and a plug spacer positioned between the trenches and surrounding the contact plug.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: August 23, 2022
    Assignee: SK hynix Inc.
    Inventor: Jae Houb Chun
  • Patent number: 11417736
    Abstract: A method (200) of fabricating a semiconductor device includes etching (205) a group of trenches in a semiconductor surface layer of a substrate. The group of trenches includes an outermost trench that has a first width and remaining trenches of the group of trenches have a second width that is less than the first width. The outermost trench is formed at an edge of the group of trenches. A dielectric liner is formed (210) in the group of trenches and the dielectric liner is etched (215) in an upper portion of the group of trenches to remove a partial thickness of the dielectric liner. A full thickness of the dielectric liner is maintained in a lower portion of the group of trenches. The group of trenches is filled (220) with a polysilicon layer.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: August 16, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Peng Li, Ya ping Chen, Yunlong Liu, Hong Yang, Shengpin Yang, Jing Hu, Chao Zhuang
  • Patent number: 11404422
    Abstract: A semiconductor device and a method for manufacturing the same are provided. The method includes forming a plurality of bit line structures on a semiconductor substrate, wherein there is a plurality of trenches between the bit line structures. The method also includes forming a first oxide layer conformally covering the bit line structures and the trenches, and forming a photoresist material layer in the trenches and on the first oxide layer, wherein the photoresist material layer has an etch selectivity that is higher than that of the first oxide layer. The method further includes removing the photoresist material layer to form a plurality of capacitor contact holes between the bit line structures, and forming a capacitor contact in the capacitor contact holes.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: August 2, 2022
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Wei-Che Chang, Tzu-Ming Ou Yang
  • Patent number: 11404547
    Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type, a first semiconductor portion of a second conductivity type provided in the semiconductor layer, first and second conductive members, each having an upper end reaching an upper surface of the semiconductor layer and a lower end connected to the first semiconductor portion, and first and second insulating films covering side surfaces of the first and second conductive members, respectively. A length from the upper end to the lower end of the first conductive member is greater than a total of a length of the first conductive member, a distance between the first conductive member and the second conductive member, and a length of the second conductive member in a direction from the first conductive member toward the second conductive member that is parallel to the upper surface of the semiconductor layer.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: August 2, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Shinji Kawahara, Nobuyuki Toda, Takeshi Yamamoto, Kazuaki Yamaura
  • Patent number: 11404567
    Abstract: A field effect transistor has a semiconductor layer with a top surface extending in a horizontal plane, and an active area defined in which are trench gate regions, which extend in depth with respect to the top surface and have an insulating coating layer and a conductive inner layer, and source regions, adjacent to the trench gate regions so as to form a conductive channel extending vertically. The trench gate regions have a plurality of first gate regions, which extend in length in the form of stripes through the active area along a first direction of the horizontal plane, and moreover a plurality of second gate regions, which extend in length in the form of stripes through the same active area along a second direction of the horizontal plane, orthogonal to, and crossing, the first gate regions. In particular, the first gate regions and second gate regions cross in the active area, joining with a non-zero curvature radius.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: August 2, 2022
    Assignee: STMicroelectronics S.R.L.
    Inventors: Salvatore Privitera, Davide Giuseppe Patti
  • Patent number: 11398561
    Abstract: A MOSFET is made by: forming a trench extending from an upper surface of a base layer to an internal portion of the base layer; forming a first insulating layer and a shield conductor occupying a lower portion of the trench; forming a gate dielectric layer and a gate conductor occupying an upper portion of the trench, where a top surface of the gate conductor is lower than the upper surface of the base layer; and before forming a body region, forming a blocking region on a region of the top surface of the gate conductor adjacent to sidewalls of the trench to prevent impurities from being implanted into the base layer from the sidewalls of the trench during subsequent ion implantation.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: July 26, 2022
    Assignee: HANGZHOU SILICON-MAGIC SEMICONDUCTOR TECHNOLOGY CO., LTD.
    Inventor: Jinyong Cai
  • Patent number: 11398481
    Abstract: Semiconductor cell structure and forming method thereof are provided. The semiconductor cell structure includes: a substrate including a first section and third regions on both sides of the first section in a first direction; and a first gate structure group including one or more first gate structures on the substrate. The first section includes a first region and a second region aligned along the first direction in the first section. The first region and the second region are configured to form transistors have a type opposite to a type of transistors configured to be formed in the third regions. The one or more first gate structures extend along the first direction across the first region, the second region, and the third regions on both sides of the first section.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: July 26, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Yan Fei Cai, Yuan Chai, Kai Hua Hou, Jian Chen, Jun Wang
  • Patent number: 11393750
    Abstract: A semiconductor device includes a substrate, a semiconductor fin, source region, a gate electrode, a source contact, and a source via. The semiconductor fin has a length extending above the substrate. The source region is on the semiconductor fin. The gate electrode has a length across the semiconductor fin. The source contact is above the source region. The source via lands on the source contact and has a first dimension along a lengthwise direction of the semiconductor fin and has a second dimension along a lengthwise direction of the gate electrode from a top view. A ratio of the second dimension to the first dimension of the source via is greater than about 2.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: July 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 11393908
    Abstract: A microelectronic device comprises a conductive structure, a metal nitride material, and a metal silicide material. The conductive structure comprises a first portion having a first width, and a second portion under the first portion and extending into a semiconductive material. The second portion has a tapered profile defining additional widths varying from the first width at an upper boundary of the second portion to a second width less than the first width at a lower boundary of the second portion. The metal nitride material substantially surrounds outer surfaces of the first portion and the second portion of the conductive structure. The metal silicide material substantially covers outer surfaces of the metal nitride material within vertical boundaries of the second portion of the conductive structure. Related methods, memory devices, and electronic systems are also described.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: July 19, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Sandeep Ramasamudra Suresha, Terrence B. McDaniel
  • Patent number: 11387318
    Abstract: A semiconductor device having an active region and a voltage withstand region comprises a first semiconductor layer of a first conductive type, a second semiconductor region of a second conductive type, disposed selectively on the front side of the first semiconductor layer, a plurality of first trench contact (TC) sections disposed at a peripheral section of the active region in the second semiconductor region, being apart from one another and extending in a first direction, a second trench contact (TC) disposed at the peripheral section of the active region in the second semiconductor region, extending in the first direction and being further from the voltage withstand region than the plurality of first trench contact sections, an electric conductor layer electrically connecting together the plurality of first TC sections, and a conductive connection region disposed between the first TC sections and second TC section, having a lower resistivity than the second semiconductor region, and electrically connecti
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: July 12, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Isamu Sugai
  • Patent number: 11380690
    Abstract: A semicondcutor device, and a method of fabricating the semiconductor device including forming on a substrate a device isolation layer defining a plurality of active regions; and forming a plurality of gate lines intersecting the active regions and buried in the substrate. The forming of the gate lines includes forming on the substrate a trench that intersects the active regions; forming a work-function control layer on a sidewall and a bottom surface of the trench; forming a conductive layer on the work-function control layer; sequentially forming a barrier layer and a source layer on the work-function control layer and the conductive layer, the source layer including a work-function control element; and diffusing the work-function control element from the source layer into an upper portion of the work-function control layer.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: July 5, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Jung Lee, Joon-Seok Moon, Dongsoo Woo
  • Patent number: 11380765
    Abstract: This invention provides a novel structure formed from GaN material using PEC etching. The structure comprises a member constituted by a single crystal of gallium nitride and the member includes a recess having an aspect ratio of 5 or more.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: July 5, 2022
    Assignees: SCIOCS COMPANY LIMITED, SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventor: Fumimasa Horikiri
  • Patent number: 11374011
    Abstract: A method for manufacturing a DRAM includes: forming a hard mask layer on a substrate with an opening therein; forming a dielectric layer on a sidewall of the opening; forming a first barrier layer and a first conductor layer in the opening; performing a first dry etching and a first wet etching processes to respectively partially remove the first barrier layer and the first conductor layer, to expose the dielectric layer on upper sidewall; forming a second barrier layer in the opening; forming a mask layer in the opening to cover the second barrier layer; removing a part of the second barrier layer and the mask layer to expose the dielectric layer on the upper sidewall of the opening; and forming a second conductor layer in the opening.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: June 28, 2022
    Assignee: Winbond Electronics Corp.
    Inventors: Akira Kuroda, Hsin-Ya Wang, Chang-Han Tsai, Ming-Ting Cai
  • Patent number: 11362202
    Abstract: There is provided a semiconductor device including: an anode electrode that is provided on a front surface side of a semiconductor substrate; a drift region of a first conductivity type that is provided in the semiconductor substrate; a first anode region of a first conductivity type that is in Schottky contact with the anode electrode; and a second anode region of a second conductivity type that is different from the first conductivity type, in which the first anode region has a doping concentration lower than or equal to a doping concentration of the second anode region, and is spaced from the drift region by the second anode region.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: June 14, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takahiro Tamura, Michio Nemoto
  • Patent number: 11355537
    Abstract: A pixel cell includes a photodiode buried beneath a first side of semiconductor material and coupled to photogenerate image charge in response to incident light. A transfer gate is disposed over the photodiode and includes a vertical transfer gate portion extending a first distance from the first side into the semiconductor material. A floating diffusion region is disposed in the semiconductor material proximate to the transfer gate and is coupled to transfer the image charge from the photodiode toward the first side of the semiconductor material and into the floating diffusion region in response to a transfer control signal. A first pixel transistor having a first gate is disposed over the photodiode proximate to the first side of the semiconductor material. The first gate has a ring structure laterally surrounding the floating diffusion region and the transfer gate at the first side of the semiconductor material.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: June 7, 2022
    Assignee: OmniVision Technologies, Inc.
    Inventors: Hui Zang, Gang Chen
  • Patent number: 11349024
    Abstract: A semiconductor device includes an active area structure, at least one gate and at least one isolation structure. The active area structure is arranged along a first direction. The at least one gate is arranged above the active area structure and along a second direction. The second direction is different from the first direction. The at least one isolation structure is arranged in the active area structure. A length of the at least one isolation structure is shorter than a width of the active area structure in the second direction.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: May 31, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chung-Yu Huang, Po-Ching Lin, Tay-Her Tsaur
  • Patent number: 11348957
    Abstract: Image sensors include a photodiode formed in a substrate material and a transistor coupled to the photodiode. The transistor has a trench structure formed in the substrate material, an isolation layer disposed on the substrate material, and a gate disposed on the isolation layer and extending into the trench structure. The trench structure has a polygonal cross section in a channel width plane, the polygonal cross section defining at least four sidewall portions of the substrate material, which contribute to an effective channel width measured in the channel width plane that is wider than a planar channel width of the transistor.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: May 31, 2022
    Assignee: OMNIVISION TECHNOLOGIES, INC.
    Inventors: Seong Yeol Mun, Young Woo Jung
  • Patent number: 11342452
    Abstract: A MOSFET includes: a semiconductor base substrate having an n-type column region and a p-type column region, the n-type column region and the p-type column region forming a super junction structure; and a gate electrode formed by way of a gate insulation film. Assuming a region of the semiconductor base substrate which provides a main operation of the MOSFET as an active region, a region of the semiconductor base substrate maintaining a withstand voltage of the MOSFET as an outer peripheral region, and a region of the semiconductor base substrate disposed between the active region and the outer peripheral region as an active connecting region, out of the active region, the active connecting region, and the outer peripheral region of the semiconductor base substrate, the crystal defects are formed only in the active region and the active connecting region.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: May 24, 2022
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Daisuke Arai, Mizue Kitada, Takeshi Asada, Noriaki Suzuki, Koichi Murakami
  • Patent number: 11342424
    Abstract: An electronic device can include a substrate, an active region of a transistor, and a shield electrode. The substrate can define a trench and include a mesa adjacent to the trench, and the shield electrode can be within the trench. In an embodiment, the electronic device can further include an active region of a transistor within the mesa and an insulating layer including a thicker section and a thinner section closer to a bottom of the trench. In another embodiment, the electronic device can include a body region and a doped region within the mesa and spaced apart from the body region by a semiconductor region. The doped region can have a dopant concentration that is higher than a dopant concentration of the semiconductor region and a portion of the substrate underlying the doped region.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: May 24, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Zia Hossain, Joseph Andrew Yedinak, Sauvik Chowdhury, Muh-Ling Ger
  • Patent number: 11342428
    Abstract: A semiconductor device including: a metal-insulator-semiconductor (MIS) structure that includes a nitride semiconductor layer, a gate insulator film, and a gate electrode stacked in stated order; and a source electrode and a drain electrode that are disposed to sandwich the gate electrode in a plan view and contact the nitride semiconductor layer. The gate insulator film includes a threshold value control layer that includes an oxynitride film.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: May 24, 2022
    Assignees: Panasonic Holdings Corporation, OSAKA UNIVERSITY
    Inventors: Hong-An Shih, Satoshi Nakazawa, Naohiro Tsurumi, Yoshiharu Anda, Heiji Watanabe, Takayoshi Shimura, Takuji Hosoi, Mikito Nozaki, Takahiro Yamada
  • Patent number: 11335789
    Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT) above a substrate. The transistor includes a gate electrode above the substrate, and a channel layer above the substrate, separated from the gate electrode by a gate dielectric layer. The transistor further includes a contact electrode above the channel layer and in contact with a contact area of the channel layer. The contact area has a thickness determined based on a Schottky barrier height of a Schottky barrier formed at an interface between the contact electrode and the contact area, a doping concentration of the contact area, and a contact resistance at the interface between the contact electrode and the contact area. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: May 17, 2022
    Assignee: Intel Corporation
    Inventors: Abhishek Sharma, Cory Weber, Van H. Le, Sean Ma
  • Patent number: 11335597
    Abstract: A method for forming a buried metal line in a substrate includes forming, at a position between a pair of semiconductor structures protruding from the substrate, a metal line trench in the substrate at a level below a base of each semiconductor structure of the pair. Forming the metal line trench includes etching an upper trench portion in the substrate, forming a spacer on sidewall surfaces of the upper trench portion that expose a bottom surface of the upper trench portion, and, while the spacer masks the sidewall surfaces, etching a lower trench portion by etching the substrate via the upper trench portion such that a width of the lower trench portion exceeds a width of the upper trench portion. The method further includes forming the metal line in the metal line trench.
    Type: Grant
    Filed: August 1, 2020
    Date of Patent: May 17, 2022
    Assignee: IMEC vzw
    Inventors: Eugenio Dentoni Litta, Anshul Gupta, Julien Ryckaert, Boon Teik Chan
  • Patent number: 11329156
    Abstract: A transistor device having a channel region including a portion located in a sidewall of semiconductor material of a trench and an extended drain region including a portion located in a lower portion of the semiconductor material of the trench. In one embodiment, a control terminal of the transistor device is formed by patterning a layer of control terminal material to form a sidewall in the trench and a field plate for the transistor device is formed by forming a conductive sidewall spacer structure along the sidewall of the control terminal material.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: May 10, 2022
    Assignee: NXP USA, INC.
    Inventors: Saumitra Raj Mehrotra, Ljubo Radic, Bernhard Grote
  • Patent number: 11322612
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type, a second electrode, a gate electrode, second semiconductor regions of a second conductivity type, third semiconductor regions of the first conductivity type, and a third electrode. The second electrode is provided in a plurality in second and third directions. Each second electrode opposes a portion of the first semiconductor region in the second and third directions with an insulating layer interposed. The gate electrode is provided around each second electrode. The first semiconductor region includes first regions provided respectively around the second electrodes and the second region provided around the first regions in the second and third directions. Impurity concentration of the first conductivity type in each of the first regions is higher than impurity concentration of the first conductivity type in the second region.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: May 3, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Kentaro Ichinoseki, Tatsuya Nishiwaki, Shingo Sato
  • Patent number: 11316045
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical field effect transistors (FETS) and methods of manufacture. The structure includes: a substrate material; at least one vertically oriented gate structure extending into the substrate material and composed of a gate dielectric material and conductive gate material; and vertically oriented source/drain regions extending into the substrate material and composed of conductive dopant material and a silicide on the source/drain regions.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: April 26, 2022
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Anthony K. Stamper, Aaron L. Vallett, Steven M. Shank, John J. Ellis-Monaghan
  • Patent number: 11315786
    Abstract: The present disclosure provides a semiconductor device structure with fine patterns at different levels and a method for forming the semiconductor device structure, which can prevent the collapse of the fine patterns and reduces the parasitic capacitance between fine patterns The semiconductor device structure includes a substrate; a first target structure disposed over the substrate, wherein the first target structure comprises a first portion, a second portion, and a third portion, a height of the first portion and a height of the second portion are greater than a height of the third portion; a second target structure disposed over the target layer, wherein the second target structure comprises a fourth portion, a fifth portion, and a sixth portion: a low-level conductive pattern positioned between the first target structure and the second target structure; and a high-level conductive pattern positioned in the first target structure.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: April 26, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Cheng-Hsiang Fan
  • Patent number: 11316026
    Abstract: An integrated circuit includes a SOI substrate comprising a base substrate, an insulator layer, and a semiconductor device layer. Source and drain regions in the semiconductor device layer are spaced apart by a channel region in the semiconductor device layer. A gate electrode is disposed over the channel region and has a bottom surface that extends below a top surface of the semiconductor device layer. A sidewall spacer structure extends along outer sidewalls of the gate electrode and has a bottom surface that rests on the top surface of the semiconductor device layer. A gate dielectric separates the channel region from the bottom surface of the gate electrode and contacts the bottom surface of the sidewall spacer structure. The channel region beneath the bottom surface of the gate electrode corresponds to the semiconductor device layer and has a thickness of less than 40 angstroms.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: April 26, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ming Chyi Liu
  • Patent number: 11309386
    Abstract: Each of a plurality of IGBT cells includes an n base layer formed in a semiconductor layer, a p base layer formed in a surface portion of the n base layer on a side of the first main surface, an n emitter layer formed in a surface portion of the p base layer, and a p collector layer formed in a surface portion of the semiconductor layer on a side of the second main surface. On a first main surface of the semiconductor layer, a gate electrode and an emitter electrode are formed. On a second main surface of the semiconductor layer, a collector electrode is formed. A pitch of the plurality of IGBT cells is 1/40 or more and 1/20 or less of a distance between the p base layer and the p collector layer.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: April 19, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventor: Katsumi Satoh
  • Patent number: 11302792
    Abstract: A device includes a nanowire, a gate dielectric layer, a gate electrode, a gate pickup metal layer, and a gate contact. The nanowire extends in a direction perpendicular to a top surface of a substrate. The gate dielectric layer laterally surrounds the nanowire. The gate electrode laterally surrounds the gate dielectric layer. The gate pickup metal layer is in contact with a bottom surface of the gate electrode and extends laterally past opposite sidewalls of the gate electrode. The gate contact is in contact with the gate pickup metal layer.
    Type: Grant
    Filed: August 29, 2020
    Date of Patent: April 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yung-Chih Wang, Yu-Chieh Liao, Tai-I Yang, Hsin-Ping Chen
  • Patent number: 11296219
    Abstract: In a deep trench DTC reaching a predetermined depth from a first main surface of a semiconductor substrate SUB, a plurality of columnar conductors CCB including plugs PUG and field plates FP are formed. A p type impurity layer PIL is formed along the side wall surface of the deep trench DTC. Between the bottom of the plug PUG and the bottom of the p type impurity layer PIL, the field plate FP and the p type impurity layer PIL are positioned to face each other via an insulating film FIF interposed therebetween. Between the bottom of the p type impurity layer PIL and the bottom of the field plate FP, the field plate FP and an n-type drift layer NDL of the semiconductor substrate SUB are positioned to face each other via the insulating film FIF interposed therebetween.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: April 5, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Senichirou Nagase, Tsuyoshi Kachi, Yoshinori Hoshino
  • Patent number: 11296091
    Abstract: Provided is a dynamic random access memory (DRAM) including a substrate, a plurality of word-line sets, a plurality of bit-line structures, a plurality of capacitors, a plurality of capacitor contacts, and a plurality of air gaps. The substrate has a plurality of active areas. The word-line sets extend along a Y direction and disposed in the substrate. The bit-line structures extend along a X direction, disposed on the substrate, and across the word-line sets. The capacitors are respectively disposed at two terminals of the active areas. The capacitor contacts are respectively disposed between the capacitors and the active regions. The air gaps are disposed in a plurality of spaces enclosed by the bit-line structures and the capacitor contacts. A method of forming a DRAM is also provided.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: April 5, 2022
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Li-Peng Chang, San-Jung Chang
  • Patent number: 11295955
    Abstract: A transistor is provided and includes a substrate; a first interlayer dielectric layer disposed on the substrate, the first interlayer dielectric layer including an opening there-through; a work function layer at least disposed over a bottom of the opening; a gate electrode layer disposed in the opening and over the work function layer; and a protection layer disposed on the work function layer and between the gate electrode layer and the first interlayer dielectric layer.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: April 5, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Yong Li
  • Patent number: 11282925
    Abstract: A silicon carbide semiconductor device has a gate insulating film, a first gate electrode, a first electrode, a second electrode, and a gate runner. A silicon carbide substrate has a first main surface and a second main surface. The silicon carbide substrate includes a first impurity region, a second impurity region, and a third impurity region. The first main surface is provided with a gate electrode trench and a gate runner trench. The gate electrode trench is defined by a side surface and a bottom surface continuous to the side surface. The gate insulating film is in contact with both the side surface and the bottom surface. The first gate electrode is provided on the gate insulating film. The second gate electrode is provided in the gate runner trench, and is electrically connected to the first gate electrode. The gate runner is provided on the second gate electrode.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: March 22, 2022
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Toru Hiyoshi, Takashi Tsuno
  • Patent number: 11282743
    Abstract: The present application discloses a semiconductor device with the multi-layered connecting structure and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a single-layered connecting structure positioned above the substrate, and a multi-layered connecting structure positioned above the substrate and including a plurality of first conductive layers and a plurality of second conductive layers alternatively stacked. A top surface of the multi-layered connecting structure is substantially coplanar with a top surface of the single-layered connecting structure and a width of the multi-layered connecting structure is less than a width of the single-layered connecting structure.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: March 22, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Cheng-Hsiang Fan
  • Patent number: 11282956
    Abstract: A transistor device having a channel region including a portion located in a sidewall of semiconductor material of a trench and an extended drain region including a portion located in a lower portion of the semiconductor material of the trench. In one embodiment, a control terminal of the transistor device is formed by patterning a layer of control terminal material to form a sidewall in the trench and a field plate for the transistor device is formed by forming a conductive sidewall spacer structure along the sidewall of the control terminal material.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: March 22, 2022
    Assignee: NXP USA, INC.
    Inventors: Saumitra Raj Mehrotra, Ljubo Radic, Bernhard Grote
  • Patent number: 11282833
    Abstract: A semiconductor device is provided. The semiconductor device includes a first substrate, an active region defined by an isolation film in the first substrate, an oxide semiconductor layer on the first substrate in the active region, and not comprising silicon, a recess inside the oxide semiconductor layer, and a gate structure filling the recess, comprising a gate electrode and a capping film on the gate electrode, and having an upper surface on a same plane as an upper surface of the active region.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: March 22, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong Jin Lee, Ji Young Kim, Bong Soo Kim, Hyeon Kyun Noh, Moon Young Jeong
  • Patent number: 11276776
    Abstract: A semiconductor device having a metal oxide semiconductor that includes a semiconductor substrate, a first semiconductor layer provided on a the semiconductor substrate, a plurality of second semiconductor layers selectively provided on the first semiconductor layer, a plurality of first semiconductor regions selectively provided in the second semiconductor layers at a surface thereof, a plurality of gate insulating films with a plurality of gate electrodes provided thereon, a plurality of first electrodes provided on the second semiconductor layers and the first semiconductor regions, and a second electrode provided on a back surface of the semiconductor substrate. The MOS structure configures an active region and a current detecting region of the semiconductor device. The semiconductor substrate and the first semiconductor layer are in both the active region and the current detecting region.
    Type: Grant
    Filed: November 27, 2020
    Date of Patent: March 15, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yasuyuki Hoshi
  • Patent number: 11271100
    Abstract: First and second trenches are provided in a semiconductor body. A mesa dividing structure is provided between the first and second trenches and comprises non-semiconductor material. A first semiconductor mesa is provided between the first trench and the non-semiconductor material of the mesa dividing structure. The first semiconductor mesa includes emitter, body and drift regions. The first and second trenches are formed by a masked etching technique with a minimum trench separation distance, and the first semiconductor mesa is provided to have a lateral width that is less than the minimum trench separation distance.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: March 8, 2022
    Assignee: Infineon Technologies Austria AG
    Inventor: Alim Karmous
  • Patent number: 11264288
    Abstract: A method of integrated circuit (IC) fabrication includes exposing a plurality of channel regions including a p-type channel region and an n-type channel region; forming a gate dielectric layer over the exposed channel regions; and forming a work function metal (WFM) structure over the gate dielectric layer. The WFM structure includes a p-type WFM portion formed over the p-type channel region and an n-type WFM portion formed over the n-type channel region, and the p-type WFM portion is thinner than the n-type WFM portion. The method further includes forming a fill metal layer over the WFM structure such that the fill metal layer is in direct contact with both the p-type and n-type WFM portions.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: March 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Lung-Kun Chu, Mao-Lin Huang, Wei-Hao Wu, Kuo-Cheng Chiang
  • Patent number: 11264494
    Abstract: A wide gap semiconductor device has: a drift layer 12 using wide gap semiconductor material being a first conductivity type; a plurality of well regions 20 being a second conductivity type and formed in the drift layer 12; a polysilicon layer 150 provided on the well regions 20 and on the drift layer 12 between the well regions 20; an interlayer insulating film 65 provided on the polysilicon layer 150; a gate pad 120 provided on the interlayer insulating film 65; and a source pad 110 electrically connected to the polysilicon layer 150.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: March 1, 2022
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventor: Shunichi Nakamura
  • Patent number: 11264479
    Abstract: A method of production of a field-effect transistor from a stack of layers forming a semiconductor-on-insulator type substrate, the stack including a superficial layer of an initial thickness, made of a crystalline semiconductor material and covered with a protective layer, the method including: defining, by photolithography, a gate pattern in the protective layer; etching the gate pattern into the superficial layer to leave a thickness of the layer of semiconductor material in place, the thickness defining a height of a conduction channel of the field-effect transistor; forming a gate in the gate pattern; forming, in the superficial layer and on either side of the gate, source and drain zones, while preserving, in the zones, the initial thickness of the superficial layer.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: March 1, 2022
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Laurent Grenouillet, Maud Vinet, Romain Wacquez
  • Patent number: 11264451
    Abstract: A semiconductor device includes a semiconductor layer having a first surface and a second surface, a first region of a first conductivity type formed on the first surface side of the semiconductor layer, a second region of a second conductivity type in contact with the first region, a third region of the first conductivity type that is in contact with the second region and exposed from the first surface side of the semiconductor layer, a gate electrode facing the second region through a gate insulating film, a first electrode that is physically separated from the gate electrode and faces the second region and the third region through an insulating film, a second electrode formed on the semiconductor layer and electrically connected to the first region, the second region, and the first electrode, and a third electrode electrically connected to the third region.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: March 1, 2022
    Assignee: ROHM CO., LTD.
    Inventor: Yusuke Kubo
  • Patent number: 11257945
    Abstract: A semiconductor device, including a first semiconductor layer of the first conductivity type formed on a semiconductor substrate, a first semiconductor region of the first conductivity type, a first base region of a second conductivity type and a first base region of a second conductivity type that are respectively selectively provided in the first semiconductor layer, a second semiconductor layer of the second conductivity type provided on the first semiconductor layer, a second semiconductor region of the first conductivity type selectively provided in the second semiconductor layer, a trench that penetrates the second semiconductor layer and the second semiconductor region, a gate electrode provided in the trench via a gate insulating film, an interlayer insulating film provided on the gate electrode, a first electrode in contact with the second semiconductor layer and the second semiconductor region, and a second electrode provided on a back surface of the semiconductor substrate.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: February 22, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji Okumura