Gate Electrode In Groove Patents (Class 257/330)
  • Patent number: 11031494
    Abstract: A semiconductor device includes a trench structure extending from a first surface into a semiconductor body composed of silicon carbide. The trench structure includes an electrode and between the electrode and the first surface a gate electrode. A shielding region adjoining the electrode forms a first pn junction with a drift structure formed in the semiconductor body. A Schottky contact is formed between the drift structure and a first contact structure.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: June 8, 2021
    Assignee: Infineon Technologies AG
    Inventor: Andreas Meiser
  • Patent number: 11031495
    Abstract: A method includes forming a first semiconductor layer over a substrate, forming a second semiconductor layer over the first semiconductor layer, forming a first trench and a second trench through in the first semiconductor layer and the second semiconductor layer, wherein a width of the second trench is different from a width of the first trench, forming a dielectric region in the first trench and forming a first gate region in the first trench and over the dielectric region, and a second gate region in the second trench.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: June 8, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wai Ng, Hsueh-Liang Chou, Po-Chih Su, Ruey-Hsin Liu
  • Patent number: 11024627
    Abstract: The present disclosure provides HKMG transistor structures and fabrication methods thereof. An exemplary method includes providing a base substrate having a first region and a second region; forming a dielectric layer having a first opening in the first region and a second opening in the second region over; forming a gate dielectric layer on a side surface of the first opening and a portion of the base substrate in the first opening and on a side surface of the second opening and a portion of the base substrate in the second opening; filling a sacrificial layer in the first opening; forming a second work function layer in the second opening and a second gate electrode layer on the second work function layer; removing the sacrificial layer; and forming a first work function layer in the first opening and a first gate electrode layer on the first work function layer.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: June 1, 2021
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Yong Li
  • Patent number: 11018127
    Abstract: A SGT MOSFET having ESD diode and a method of manufacturing the same are disclosed. The SGT trench MOSFET according to the present invention, has n+ doped shielded electrode in an N channel device and requires only two poly-silicon layers, making the device can be shrunk with reducing shielded gate width for Rds reduction without increasing switching loss and having dynamic switching instability.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: May 25, 2021
    Assignee: NAMI MOS CO, LTD.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 11018251
    Abstract: A semiconductor device includes a semiconductor body; first and second electrodes provided on back and front surfaces of the semiconductor body, respectively; a third electrode provided on the front surface; and a control electrode disposed inside a trench on the front surface side, and electrically connected to the third electrode. The third electrode is electrically insulated from the semiconductor body and the second electrode. The control electrode is placed between the semiconductor body and the second electrode, and is electrically insulated from the semiconductor body and the second electrode. The control electrode continuously extends inside the trench without branching. The control electrode includes first and second portions. The first portion extends in a first direction parallel to the front surface of the semiconductor body, and the second portion extends in a second direction parallel to the front surface of the semiconductor body and crossing the first direction.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: May 25, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Toshifumi Nishiguchi
  • Patent number: 11011607
    Abstract: The likelihood of formation of a corner resulting from a recess in a part of an n-type semiconductor layer is reduced at a deeper position than a p-type semiconductor layer. A method of manufacturing a semiconductor device comprises: forming a gallium nitride (GaN) based n-type semiconductor layer containing n-type impurities; forming a groove by forming a first mask on a part of a surface of the n-type semiconductor layer and then etching a part uncovered by the first mask; removing the first mask; forming a gallium nitride (GaN) based p-type semiconductor layer containing p-type impurities on the surface of the n-type semiconductor layer including the groove; etching the p-type semiconductor layer so as to expose the n-type semiconductor layer at least in a range differing from a range in the presence of the groove; and forming a metal electrode contacting the exposed n-type semiconductor layer and the p-type semiconductor layer.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: May 18, 2021
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Kota Yasunishi, Toru Oka, Kazuya Hasegawa
  • Patent number: 11004785
    Abstract: First and second wells are formed in a semiconductor substrate. First and second trenches in the first second wells, respectively, each extend vertically and include a central conductor insulated by a first insulating layer. A second insulating layer is formed on a top surface of the semiconductor substrate. The second insulating layer is selectively thinned over the second trench. A polysilicon layer is deposited on the second insulating layer and then lithographically patterned to form: a first polysilicon portion over the first well that is electrically connected to the central conductor of the first trench to form a first capacitor plate, a second capacitor plate formed by the first well; and a second polysilicon portion over the second well forming a floating gate electrode of a floating gate transistor of a memory cell having an access transistor whose control gate is formed by the central conductor of the second trench.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: May 11, 2021
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SAS
    Inventors: Abderrezak Marzaki, Arnaud Regnier, Stephan Niel
  • Patent number: 11004964
    Abstract: A semiconductor device includes: a second semiconductor layer in a surface layer of a first semiconductor layer; a third semiconductor layer in a surface layer of the second semiconductor layer; a first trench penetrating the second semiconductor layer and the third semiconductor layer to reach an inside of the first semiconductor layer; a second trench penetrating, from an upper surface of the first semiconductor layer, the third semiconductor layer to reach an inside of the second semiconductor layer; and a fourth semiconductor layer in contact with a bottom of the second trench.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: May 11, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventor: Tatsuo Harada
  • Patent number: 11004844
    Abstract: A method includes forming an isolation region extending into a semiconductor substrate, etching a top portion of the isolation region to form a recess in the isolation region, and forming a gate stack extending into the recess and overlapping a lower portion of the isolation region. A source region and a drain region are formed on opposite sides of the gate stack. The gate stack, the source region, and the drain region are parts of a Metal-Oxide-Semiconductor (MOS) device.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Huan Chen, Kong-Beng Thei, Fu-Jier Fan, Ker-Hsiao Huo, Kau-Chu Lin, Li-Hsuan Yeh, Szu-Hsien Liu, Yi-Sheng Chen
  • Patent number: 10998440
    Abstract: A device comprises a vertical transistor. The vertical transistor comprises a semiconductive pillar, at least one gate electrode, a gate dielectric material, and void spaces. The semiconductive pillar comprises a source region, a drain region, and a channel region extending vertically between the source region and the drain region, the channel region comprising a semiconductive material having a band gap greater than 1.65 electronvolts. The at least one gate electrode laterally neighbors the semiconductive pillar. The gate dielectric material is laterally between the semiconductive pillar and the at least one gate electrode. The void spaces are vertically adjacent the gate dielectric material and laterally intervening between the at least one gate electrode and each of the source region and the drain region of the semiconductive pillar. Related electronic systems and methods are also disclosed.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: May 4, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Ramanathan Gandhi, Hong Li, Haitao Liu, Durai Vishak Nirmal Ramaswamy, Sanh D. Tang, Scott E. Sills
  • Patent number: 10991702
    Abstract: The present disclosure provide a semiconductor device and a method for preparing the semiconductor device. The semiconductor device includes a substrate having a memory cell region and a peripheral region, wherein the memory cell region has at least one first shallow trench isolation and the peripheral region has at least one second shallow trench isolation; a plurality of gates in the first shallow trench isolation; a first semiconductor layer in the peripheral region; a first insulating layer covering the substrate in the memory cell region; a crystalline overlayer in the memory cell region and a doped portion of the substrate below the crystalline overlayer; and a second semiconductor layer on a portion of the first insulating layer, wherein a top surface of the first semiconductor layer and a top surface of the second semiconductor layer are coplanar.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: April 27, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Te-Yin Chen
  • Patent number: 10991637
    Abstract: A wafer-level chip-scale package includes: a power semiconductor comprising a first semiconductor device formed on a semiconductor substrate, and a second semiconductor device formed on the semiconductor substrate; a common drain electrode connected to the first semiconductor device and the second semiconductor device; a first source metal bump formed on a surface of the first semiconductor device; and a second source metal bump formed on the surface of the second semiconductor device; wherein the first source metal bump, the common drain electrode, and the second source metal bump form a current path in an order of the first source metal bump, the common drain electrode, and the second source metal bump.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: April 27, 2021
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Myung Ho Park, Beom Su Kim, Sun Hwan Kim
  • Patent number: 10991807
    Abstract: A semiconductor device includes gate trench, an upper gate insulating layer on an inner surface of an upper region of the gate trench, a lower gate insulating layer on an inner surface and a lower surface of a lower region of the gate trench and connected to the upper gate insulating layer, a first gate barrier layer on an inner side of the lower gate insulating layer, a gate electrode on an inner side of the first gate barrier layer and configured to fill the lower region of the gate trench, and a gate buried portion on the gate electrode. A diameter of an inner circumference of an upper end of the lower gate insulating layer is greater than a diameter of an inner circumference of a lower end of the upper gate insulating layer.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: April 27, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ki Hyung Nam
  • Patent number: 10991815
    Abstract: A semiconductor device includes: a semiconductor base; a trench insulating film which is provided on the inner wall surface of a trench formed from the upper surface of the semiconductor base in a film thickness direction of the semiconductor base and including a charged region which is charged positively; and a gate electrode provided on the trench insulating film within the trench. The positive charge density of the charged region at least in a side part of an outer region of the trench insulating film which is provided on the side surface of the trench is higher than that of an inner region of the trench insulating film which is opposite to the outer region, the outer region being in contact with the semiconductor base.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: April 27, 2021
    Assignee: SANKEN ELECTRIC CO., LTD.
    Inventors: Shunsuke Fukunaga, Taro Kondo
  • Patent number: 10985268
    Abstract: A semiconductor device includes a semiconductor substrate including first and second surfaces, and a first semiconductor layer of a first conductivity type, a first electrode on the first surface, a first control electrode that is inwardly from the first surface and electrically insulated from the semiconductor substrate and the first electrode, a second control electrode that is inwardly from the first surface, electrically insulated from the semiconductor substrate and the first electrode via a fourth insulating film, and biased independently from the first control electrode, a third control electrode on the second surface and electrically insulated from the semiconductor substrate, and a second electrode on the second surface and electrically connected to the semiconductor substrate.
    Type: Grant
    Filed: September 2, 2019
    Date of Patent: April 20, 2021
    Assignees: KABUSH1 KI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Tomoko Matsudai, Yoko Iwakaji
  • Patent number: 10985256
    Abstract: A semiconductor device includes a semiconductor substrate, a gate dielectric, a gate electrode, a pair of source/drain regions, a pair of first well regions, a second well region, a pair of contact regions and a pair of third well regions. The gate dielectric is disposed in the semiconductor substrate having a concave profile that defines an upper boundary lower than an upper surface of the semiconductor substrate. The gate electrode is disposed over the gate dielectric. The pair of source/drain regions are disposed on opposing sides of the gate dielectric. The pair of first well regions are disposed under the pair of source/drain regions. The second well region is disposed between the pair of first well regions. The pair of contact regions are disposed on opposing sides of the pair of source/drain regions. The pair of third well regions are disposed under the pair of contact regions.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: April 20, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ta-Yuan Kung, Ruey-Hsin Liu, Chen-Liang Chu, Chih-Wen Yao, Ming-Ta Lei
  • Patent number: 10985255
    Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a gate trench crossing an active region, and a gate structure in the gate trench. The gate structure includes a gate dielectric layer disposed on an inner wall of the gate trench, a gate electrode disposed on the gate electric layer and partially filling the gate trench, a gate capping insulating layer disposed on the gate electrode, and a gap-fill insulating layer disposed in the gate trench and disposed on the gate capping insulating layer. The gate capping insulating layer includes a material formed by oxidizing a portion of the gate electrode, nitriding the portion of the gate electrode, or oxidizing and nitriding the portion of the gate electrode.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: April 20, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junghwan Huh, Dongchan Kim, Dae Hyun Kim, Euiju Kim, Jisoo Lee
  • Patent number: 10978503
    Abstract: A light detection apparatus according to an embodiment includes a first semiconductor region having a first conductivity type, a second semiconductor region having a second conductivity type, a third semiconductor region having the first conductivity type, and a circuit unit configured to count the number of generation times of an avalanche current, wherein a reverse bias voltage for causing avalanche multiplication of the signal charge is applied to the second semiconductor region and the third semiconductor region, and the signal charge is accumulated in the first semiconductor region when the potential barrier is formed, wherein the control unit controls the height of the potential barrier.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: April 13, 2021
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Mahito Shinohara
  • Patent number: 10978356
    Abstract: A method of forming a semiconductor structure includes forming a recess within a semiconductor substrate, the recess is located between adjacent fins of a plurality of fins on the semiconductor substrate, forming a first liner above a perimeter including the recess, top surfaces of the semiconductor substrate, and top surfaces and sidewalls of the plurality of fins, the first liner includes a first oxide material, forming a second liner directly above the first liner, and forming a third liner directly above the second liner, the third liner includes a nitride material, the second liner includes a second oxide material capable of creating a dipole effect that neutralizes positive charges generated within the third liner and between the third liner and the first liner.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: April 13, 2021
    Assignee: International Business Machines Corporation
    Inventors: Choonghyun Lee, Xin Miao, Alexander Reznicek, Jingyun Zhang
  • Patent number: 10978588
    Abstract: A semiconductor device includes a semiconductor part between first and second electrodes, first and second control electrodes between the semiconductor part and the second electrode. The semiconductor part includes a first region and a second region around the first region. The semiconductor part includes first and third layers of a first conductivity type and second layers of a second conductivity type. The second layers are provided between the first layer and the second electrode. A second layer faces the first control electrode in the second region. Another second layer faces the second control electrode in the second region. A third layer is provided between the second layer and the second electrode. Another third layer is provided between another second layer and the second electrode. The second layer includes a second conductivity type impurity with a concentration lower than that of a second conductivity type impurity in another second layer.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: April 13, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Shunsuke Nitta, Takeru Matsuoka, Hiroshi Ohta
  • Patent number: 10978585
    Abstract: A semiconductor device formed on a semiconductor substrate includes: an epitaxial layer overlaying the semiconductor substrate; a drain formed on back of the semiconductor substrate; a drain region that extends into the epitaxial layer; an active region comprising: a body disposed in the epitaxial layer; a source embedded in the body; a gate trench extending into the epitaxial layer; a gate disposed in the gate trench; an active region contact trench extending through the source and the body; and an active region contact electrode disposed within the active region contact trench; and an island region under the active region contact trench and disconnected from the body, the island region having an opposite polarity as the epitaxial layer; wherein the active region contact trench has a non-uniform depth.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: April 13, 2021
    Inventors: Anup Bhalla, Xiaobin Wang, Ji Pan, Sung-Po Wei
  • Patent number: 10964704
    Abstract: A semicondcutor device, and a method of fabricating the semiconductor device including forming on a substrate a device isolation layer defining a plurality of active regions; and forming a plurality of gate lines intersecting the active regions and buried in the substrate. The forming of the gate lines includes forming on the substrate a trench that intersects the active regions; forming a work-function control layer on a sidewall and a bottom surface of the trench; forming a conductive layer on the work-function control layer; sequentially forming a barrier layer and a source layer on the work-function control layer and the conductive layer, the source layer including a work-function control element; and diffusing the work-function control element from the source layer into an upper portion of the work-function control layer.
    Type: Grant
    Filed: August 24, 2019
    Date of Patent: March 30, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Jung Lee, Joon-Seok Moon, Dongsoo Woo
  • Patent number: 10957759
    Abstract: A silicon carbide (SiC) charge balance (CB) device includes a CB layer, which includes a first epitaxial (epi) layer. An active area of the first epi layer includes a first doping concentration of a first conductivity type and a first plurality of CB regions of a second conductivity type. A termination area of the first epi layer includes a minimized epi doping concentration of the first conductivity type. The SiC—CB device also includes a device layer, which includes a second epi layer disposed on the CB layer. An active area of the second epi layer includes the first doping concentration of the first conductivity type. A termination area of the device layer includes the minimized epi doping concentration of the first conductivity type and a first plurality of floating regions of the second conductivity type that form a junction termination of the device.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: March 23, 2021
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Stephen Daley Arthur, Reza Ghandi, Alexander Viktorovich Bolotnikov, David Alan Lilienfeld, Peter Almern Losee
  • Patent number: 10957771
    Abstract: Disclosed is a transistor device which includes a semiconductor body having a first surface, a source region, a drift region, a body region being arranged between the source region and the drift region, a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric, and a field electrode adjacent the drift region and dielectrically insulated from the drift region by a field electrode dielectric. The field electrode includes a first layer and a second layer. The second layer includes a different conductive material as the first layer. A portion of the second layer is disposed above and directly contacts a portion of the first layer.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: March 23, 2021
    Assignee: Infineon Technologies Austria AG
    Inventor: Thomas Feil
  • Patent number: 10950699
    Abstract: A vertical trench shield device can include a plurality of gate structures and a termination structure surrounding the plurality of gate structures. The plurality of gate structures can include a plurality of gate regions and a corresponding plurality of gate shield regions. The plurality of gate structures can be disposed between the plurality of source regions, and extending through the plurality of body regions to the drift region. The plurality of gate structures can be separated from each other by a first predetermined spacing in a core area. A first set of the plurality of gate structures can extend fully to the termination structure. The ends of a second set of the plurality of gate structures can be separated from the termination structure by a second predetermined spacing. The first and second spacings can be configured to balance charge in the core area and the termination area in a reverse bias condition.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: March 16, 2021
    Assignee: Vishay-Siliconix, LLC
    Inventors: Jun Hu, M. Ayman Shibib, Misbah Azam, Kyle Terrill
  • Patent number: 10950605
    Abstract: A semiconductor device includes a first transistor. The first transistor includes a first terminal, a first contact, a second terminal, and a second contact. The first contact is electrically connected to the first terminal, and the shape of the first contact is circular. The second contact is electrically connected to the second terminal and a ground terminal, and the shape of the second contact is rectangular.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: March 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 10950691
    Abstract: A power converter circuit includes an inductor and rectifier circuit having an inductor connected in series with an electronic switch, and a rectifier circuit, and a controller for generating a drive signal for driving the electronic switch. The electronic switch has drain, source and gate nodes, drift and compensation cells each including a drift region of a first doping type and a compensation region of a second doping type, and a control structure connected between the drift region of each of the drift and compensation cells and the source node. Each drift region is coupled to the drain node and each compensation region cells is coupled to the source node. A first type doping concentration N1 of the drift region is higher than a first doping level L1, and a second type doping concentration N2 of the compensation region is higher than a second doping level L2.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: March 16, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Giulio Fragiacomo, Bjoern Fischer, Rene Mente, Armin Willmeroth
  • Patent number: 10950620
    Abstract: A vertical-type memory device a vertical-type memory device comprising a substrate including a first region and a second region, adjacent to the first region, a first conductive layer extending on the first region and the second region, and a second conductive layer extending on the first region and the second region, the second conductive layer stacked on the first conductive layer. An upper surface of the substrate has a step portion at a boundary between the first region and the second region, and the upper surface of the substrate in the first region is lower than in the second region.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: March 16, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwang Young Jung, Dong Won Kim
  • Patent number: 10943997
    Abstract: A semiconductor layer may be subjected to etching to form a trench therein. An epitaxial layer may be further formed in the trench. Here, the impurity concentration of the epitaxial layer is controlled to be lower than that of the semiconductor layer. In this manner, concentration of electrical fields in the trench is reduced. A first innovations herein provides a semiconductor device including a first semiconductor layer containing impurities of a first conductivity type, a trench provided in the first semiconductor layer on a front surface side thereof, and a second semiconductor layer provided on an inner wall of the trench, where the second semiconductor layer contains impurities of the first conductivity type at a lower concentration than the first semiconductor layer.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: March 9, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Takeyoshi Nishimura
  • Patent number: 10937701
    Abstract: A semiconductor device includes a first gate structure in a substrate and a second gate structure in the substrate and adjacent to the first gate structure. Preferably, a top surface of the first gate structure and a top surface of the second gate structure are lower than a top surface of the substrate and a number of work function metal layers in the first gate structure and the second gate structure are different.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: March 2, 2021
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Shih-Fang Tzou, Yu-Cheng Tung, Ming-Feng Kuo, Li-Chiang Chen
  • Patent number: 10937859
    Abstract: A method for manufacturing a power device is disclosed. The method for manufacturing the power device comprises: forming a first doped region on the semiconductor substrate; forming a plurality of second doped regions in a first region of the first doped region; and forming a plurality of third doped regions in a second region of the first doped region. A first charge compensation structure is formed by the first doped region and the plurality of second doped regions, the first charge compensation structure and the semiconductor substrate are located on current channel. A second charge compensation structure is formed by the first doped region and the plurality of third doped regions, the second charge compensation structure is configured to disperse continuous surface electric field of the power device. The power device manufactured by the method not only has a stable blocking voltage and an improved reliability, but also has a reduced on-resistance.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: March 2, 2021
    Assignee: HANGZHOU SILAN MICROELECTRONICS CO., LTD.
    Inventor: Shaohua Zhang
  • Patent number: 10930351
    Abstract: A non-volatile memory cell includes a selection transistor having an insulated selection gate embedded in a semiconducting substrate region. A semiconducting source region contacts a lower part of the insulated selection gate. A state transistor includes a floating gate having an insulated part embedded in the substrate region above an upper part of the insulated selection gate, a semiconducting drain region, and a control gate insulated from the floating gate and located partially above the floating gate. The source region, the drain region, the substrate region, and the control gate are individually polarizable.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: February 23, 2021
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Julien Delalleau
  • Patent number: 10930774
    Abstract: A trench MOSFET is disclosed having shielded trenched gates in active area, multiple floating trenched gates and at least one channel stop trenched gate in termination area. A semiconductor power device layout is disclosed consisting of at least two said trench MOSFETs connected together with multiple sawing trenched gates across a space between the two trench MOSFETs having a width same as scribe line, making the invented trench MOSFET be feasibly achieved without degraded performance.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: February 23, 2021
    Assignee: NAMI MOS CO., LTD.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 10930759
    Abstract: A method of forming a vertical fin field effect transistor (vertical finFET) with a strained channel, including forming one or more vertical fins on a substrate, forming a sacrificial stressor layer adjacent to the one or more vertical fins, wherein the sacrificial stressor layer imparts a strain in the adjacent vertical fins, forming a fin trench through one or more vertical fins and the sacrificial stressor layer to form a plurality of fin segments and a plurality of sacrificial stressor layer blocks, forming an anchor wall adjacent to and in contact with one or more fin segment endwalls, and removing at least one of the plurality of the sacrificial stressor layer blocks, wherein the anchor wall maintains the strain of the adjacent fin segments after removal of the sacrificial stressor layer blocks adjacent to the fin segment with the adjacent anchor wall.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: February 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li
  • Patent number: 10910486
    Abstract: The present invention provides a semiconductor device including (a) a drift region of a first-conductivity-type, (b) a base region of a second-conductivity-type, (c) a plurality of trench portions arranged next to each other in a predetermined arrangement direction on the upper surface of the semiconductor substrate, (d) an emitter region of a first-conductivity-type which has a higher doping concentration than the drift region, (e) an accumulation region of a first-conductivity-type which has a higher doping concentration than the drift region, and (f) a second-conductivity-type region of a second-conductivity-type which has a higher doping concentration than the base region, wherein the accumulation region and the second-conductivity-type region are provided between the base region and the drift region in a non-channel mesa portion that does not have the emitter region provided therein and that is of mesa portions between adjacent ones of the plurality of trench portions.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: February 2, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yoshihiro Ikura, Akio Nakagawa
  • Patent number: 10910224
    Abstract: A method for fabricating a semiconductor device includes: forming a gate trench in a semiconductor substrate; forming a gate dielectric layer over a bottom surface and sidewalls of the gate trench; forming a first work function layer over the gate dielectric layer; doping a work function adjustment element to form a second work function layer which overlaps with the sidewalls of the gate trench; forming a gate conductive layer that partially fills the gate trench; and forming doped regions inside the semiconductor substrate on both sides of the gate trench.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: February 2, 2021
    Assignee: SK hynix Inc.
    Inventors: Tae-Su Jang, Jin-Chul Park, Ji-Hwan Park, Il-Sik Jang, Seong-Wan Ryu, Se-In Kwon, Jung-Ho Shin, Dae-Jin Ham
  • Patent number: 10903203
    Abstract: A trench transistor structure includes a substrate structure, a transistor device, and an electrostatic discharge (ESD) protection device. A first region and a second region are defined in the substrate structure. The substrate structure has a first trench located in the first region and a second trench located in the second region. The transistor device is located in the first region and includes an electrode located in the first trench. The electrode and the substrate structure are isolated from each other. The ESD protection device is located in the second region and includes a main body layer located in the second trench. The main body layer has a planarized top surface. PN junctions are located in the main body layer. The main body layer and the substrate structure are isolated from each other.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: January 26, 2021
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Wei-Yu Lin, Shih-Hao Cheng
  • Patent number: 10903311
    Abstract: A diode includes upper and lower electrodes and first and second N-type doped semiconductor substrate portions connected to the lower electrode. A first vertical transistor and a second transistor are formed in the first portion and series-connected between the electrodes. The gate of the first transistor is N-type doped and coupled to the upper electrode. The second transistor has a P channel and has a P-type doped gate. First and second doped areas of the second conductivity type are located in the second portion and are separated by a substrate portion topped with another N-type doped gate. The first doped area is coupled to the gate of the second transistor. The second doped area and the other gate are coupled to the upper electrode.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: January 26, 2021
    Assignee: STMICROELECTRONICS (TOURS) SAS
    Inventors: Frédéric Lanois, Alexei Ankoudinov, Vladimir Rodov
  • Patent number: 10896968
    Abstract: This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: January 19, 2021
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Anup Bhalla, François Hébert, Sung-Shan Tai, Sik K. Lui
  • Patent number: 10896959
    Abstract: This invention discloses a semiconductor power device formed on an upper epitaxial layer of a first conductivity type supported on a semiconductor substrate. The semiconductor power device having a super junction structure with the epitaxial layer formed with a plurality of vertically extended doped columns of a second conductivity type. The semiconductor power device further comprises a plurality of transistor cells each of the transistor cells comprises a planar gate extending over a top surface and each of the planar gates further includes a middle trench gate extending vertically into the epitaxial layer from a middle portion of the planar gates. Each of the middle trench gates is surrounded by a source region of the first conductivity type encompassed in a body region of the second conductivity type extending substantially between two adjacent doped columns of the second conductivity type.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: January 19, 2021
    Assignee: HUNTECK Semiconductor (Shanghai) Co. Ltd.
    Inventor: Jun Hu
  • Patent number: 10892355
    Abstract: Presented is a lateral fin static induction transistor including a semi conductive substrate, source and drain regions extending from an optional buffer layer of same or varied thickness supported by the semi conductive substrate, a semi conductive channel electrically coupling the source region to the drain region of the transistor, a portion of the semi conductive channel being a fin and having a face covered by a gated structure, thereby defining a gated channel within the semi conductive channel, the semi conductive channel further including a drift region electrically coupling the gated channel to the drain region of the transistor.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: January 12, 2021
    Assignee: HRL Laboratories, LLC
    Inventor: Biqin Huang
  • Patent number: 10892188
    Abstract: Semiconductor devices made by forming hard mask pillars on a surface of a substrate, forming sacrificial spacers on a first side of each hard mask pillar and a second side of each hard mask pillar. The open gaps may be formed between adjacent sacrificial spacers. The semiconductor devices may also be formed by etching the hard mask pillars to form pillar gaps, etching gate trenches into the substrate through the open gaps and the pillar gaps, forming a gate electrode within the gate trenches, implanting channels and sources in the substrate below the sacrificial spacers, forming an insulator layer around the sacrificial spacers, etching the sacrificial spacers to form contact trenches within the substrate, and filling the contact trenches with a conductive material to form contacts.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: January 12, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Mitsuru Soma, Masahiro Shimbo, Masaki Kuramae, Kouhei Uchida
  • Patent number: 10886160
    Abstract: An electronic device, e.g. an integrated circuit, includes a semiconductor substrate having a top surface and an area of the semiconductor substrate surrounded by inner and outer trench rings. The inner trench ring includes a first dielectric liner that extends from the substrate surface to a bottom of the inner trench ring, the first dielectric liner electrically isolating an interior region of the inner trench ring from the semiconductor substrate. The outer trench ring surrounds the inner trench ring and includes a second dielectric liner that extends from the substrate surface to a bottom of the outer trench ring. The second dielectric liner includes an opening at a bottom of the outer trench ring, the opening providing a path between an interior region of the outer trench ring and the semiconductor substrate.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: January 5, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Binghua Hu, Alexei Sadovnikov, Scott Kelly Montgomery
  • Patent number: 10886277
    Abstract: A memory device includes cell transistors on active regions defined by a device isolation layer on a substrate such that each cell transistor has a buried cell gate and a junction portion adjacent to and at least partially distal to the substrate in relation to the buried cell gate, an insulation pattern on the substrate and covering the cell transistors and the device isolation layer, and a bit line structure on the insulation pattern and connected to the junction portion. The bit line structure includes a buffer pattern on the pattern and having a thermal oxide pattern, a conductive line on the buffer pattern, and a contact extending from the conductive line to the junction portion through the buffer pattern and the insulation pattern.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: January 5, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Augustin Jinwoo Hong, Young-Ju Lee, Joon-Yong Choe, Jung-Hyun Kim, Sang-Jun Lee, Hyeon-Kyu Lee, Yoon-Chul Cho, Je-Min Park, Hyo-Dong Ban
  • Patent number: 10879133
    Abstract: A complementary metal-oxide-semiconductor (CMOS) integrated circuit structure, and method of fabricating the same according to a replacement metal gate process. P-channel and n-channel MOS transistors are formed with high-k gate dielectric material that differ from one another in composition or thickness, and with interface dielectric material that differ from one another in composition or thickness. The described replacement gate process enables construction so that neither of the p-channel or n-channel transistor gate structures includes the metal gate material from the other transistor, thus facilitating reliable filling of the gate structures with fill metal.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: December 29, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hiroaki Niimi, Seung-Chul Song
  • Patent number: 10879110
    Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes first and second fins formed on a semiconductor substrate and laterally separated from each other by an isolation feature, the isolation feature formed of a dielectric material that physically contacts the semiconductor substrate; and a contact feature between the first and second fins and extending into the isolation feature thereby defining an air gap vertically between the isolation feature and the contact feature, the dielectric material of the isolation feature extending from the semiconductor substrate to the contact feature.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Che Tsai, Min-Yann Hsieh, Hua Feng Chen, Kuo-Hua Pan
  • Patent number: 10879363
    Abstract: A power semiconductor die has a semiconductor body coupled to a first load terminal and a second load terminal of the power semiconductor die and configured to conduct a load current between the load terminals. The die further comprises: a control trench structure for controlling the load current, the control trench structure extending into the semiconductor body along a vertical direction and arranged in accordance with a horizontal grid pattern having a plurality of grid openings; a plurality of power cells, each power cell being, in a horizontal cross-section, at least partially arranged in a respective one of the plurality of grid openings.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: December 29, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Oliver Blank, Marcel Rene Mueller, Cedric Ouvrard
  • Patent number: 10872975
    Abstract: According to an embodiment, a semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a gate electrode, and a second electrode. The gate electrode includes a first portion and a second portion. The first portion opposes the third semiconductor region, the second semiconductor region, and a portion of the first semiconductor region in a first direction perpendicular to a second direction from the first electrode toward the first semiconductor region. The second portion is arranged with the first portion in a third direction perpendicular to the first and first directions. The second portion opposes the second semiconductor region in the first direction. A lower end of the second portion is positioned higher than an interface between the first semiconductor region and the second semiconductor region.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: December 22, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Hiroaki Katou
  • Patent number: 10872826
    Abstract: A method of forming a semiconductor device includes forming a first dummy gate structure and a second dummy gate structure over a fin; forming a first dielectric layer around the first dummy gate structure and around the second dummy gate structure; removing the first dummy gate structure and the second dummy gate structure to form a first recess and a second recess in the first dielectric layer, respectively; forming a gate dielectric layer in the first recess and the second recess; forming a first work function layer over the gate dielectric layer in the first recess and in the second recess; removing the first work function layer from the first recess; converting a surface layer of the first work function layer in the second recess into an oxide; and forming a second work function layer in the first recess over the gate dielectric layer and in the second recess over the oxide.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: December 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shao-Jyun Wu, Sheng-Liang Pan
  • Patent number: 10868172
    Abstract: A semiconductor device includes: a gate trench extending into a Si substrate; a body region in the Si substrate, the body region including a vertical channel region adjacent a sidewall of the gate trench; a source region in the Si substrate above the body region; a contact trench extending into the Si substrate and separated from the gate trench by a portion of the source region and by a portion of the body region; an electrically conductive material in the contact trench; and a diffusion barrier structure interposed between a sidewall of the contact trench and the vertical channel region, the diffusion barrier structure including alternating layers of Si and oxygen-doped Si and configured to increase carrier mobility within the vertical channel region. Corresponding methods of manufacture are also described.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: December 15, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Oliver Blank, Thomas Feil, Maximilian Roesch, Martin Poelzl, Robert Haase, Sylvain Leomant, Bernhard Goller, Andreas Meiser