Gate Electrode In Groove Patents (Class 257/330)
  • Patent number: 10692858
    Abstract: A semiconductor device may include a substrate, a first doped region and a second doped region on the substrate, a base region on the first doped region, a channel region on the second doped region, and a third doped region and a fourth doped region on the base region and the channel region, respectively. The first doped region and the second doped region may be isolated from direct contact with each other in a first direction that is substantially parallel to a top surface of the substrate. A channel gate structure may be on a side surface of the channel region. A thickness of the base region, in a second direction that is substantially perpendicular to the top surface of the substrate, may be equal to or larger than a thickness of the channel region.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: June 23, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: YeonCheol Heo
  • Patent number: 10686065
    Abstract: A method includes forming a first semiconductor layer over a substrate, forming a second semiconductor layer over the first semiconductor layer, forming a first trench and a second trench through in the first semiconductor layer and the second semiconductor layer, wherein a width of the second trench is different from a width of the first trench, forming a dielectric region in the first trench and forming a first gate region in the first trench and over the dielectric region, and a second gate region in the second trench.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wai Ng, Hsueh-Liang Chou, Po-Chih Su, Ruey-Hsin Liu
  • Patent number: 10686047
    Abstract: A semiconductor device includes a semiconductor substrate, a gate dielectric, a gate electrode and a pair of source/drain regions. The gate dielectric is disposed in the semiconductor substrate having a concave profile that defines an upper boundary lower than an upper surface of the semiconductor substrate. The gate electrode is disposed over the gate dielectric. The pair of source/drain regions are disposed on opposing sides of the gate dielectric.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ta-Yuan Kung, Ruey-Hsin Liu, Chen-Liang Chu, Chih-Wen Yao, Ming-Ta Lei
  • Patent number: 10685865
    Abstract: A method of forming a semiconductor device may include providing a semiconductor device structure. The semiconductor device structure may include semiconductor fins pitched at a fin pitch on a substrate and a mask, disposed over the semiconductor fins, the mask defining a plurality of openings. The semiconductor device structure may further include an isolation oxide disposed on the substrate, between the semiconductor fins. The method may further include directing angled ions into the at least one of the plurality of openings. The angled ions may form at least one trench between at least one pair of the semiconductor fins, in the substrate below the isolation oxide between the at least one pair of the semiconductor fins. Furthermore, a width within the substrate of the at least one trench is greater than a minimum fin pitch and greater than a width of the at least one trench above the substrate.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: June 16, 2020
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Min Gyu Sung, Sony Varghese, Johannes Van Meer, John Hautala
  • Patent number: 10680095
    Abstract: A power semiconductor device includes a semiconductor layer having a first conductivity type. A trench is defined within the semiconductor layer, the trench having an opening, a sidewall and a base. A pillar is provided below the trench and has a second conductivity type that is different than the first conductivity type. A metal layer is provided over the sidewall of the trench, the metal layer contacting the semiconductor layer at the sidewall of the trench to form a Schottky interface of a Schottky diode. A first electrode is provided over a first side of the semiconductor layer. A second electrode is provided over a second side of the semiconductor layer.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: June 9, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Wonhwa Lee, Gary H. Loechelt
  • Patent number: 10680101
    Abstract: A semiconductor device includes: a first semiconductor region disposed over a second semiconductor region, wherein the first and second semiconductor regions have a first doping type and a second doping type, respectively; a first source/drain contact region and a second source/drain contact region having the second doping type and laterally spaced; and a gate electrode disposed laterally between the first and second source/drain contact regions, wherein the gate electrode comprises a first sidewall relatively closer to the first source/drain region and a second sidewall relatively closer to the second source/drain region, and wherein respective cross-sectional areas of the first and second sidewalls of the gate electrode are different from each other.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wan-Jyun Syue, Chin-Yi Huang, Kuo-Lung Tzeng, Zhuo-Cang Yang
  • Patent number: 10680097
    Abstract: A semiconductor device, comprising: a substrate; an active gate trench in the substrate; a source polysilicon pickup trench in the substrate; a polysilicon electrode disposed in the source polysilicon pickup trench; a gate pickup trench in the substrate; a first conductive region and a second conductive region disposed in the gate pickup trench, the first conductive region and the second conductive region being separated by oxide, wherein at least a portion of the oxide surrounding the first conductive region in the gate pickup trench is thicker than at least a portion of the oxide under the second conductive region; and a body region in the substrate.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: June 9, 2020
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: John Chen, Il Kwan Lee, Hong Chang, Wenjun Li, Anup Bhalla, Hamza Yilmaz
  • Patent number: 10679990
    Abstract: A multiple-fin device includes a substrate and a plurality of fins formed on the substrate. Source and drain regions are formed in the respective fins. A dielectric layer is formed on the substrate. The dielectric layer has a first thickness adjacent one side of a first fin and having a second thickness, different from the first thickness, adjacent an opposite side of the fin. A continuous gate structure is formed overlying the plurality of fins, the continuous gate structure being adjacent a top surface of each fin and at least one sidewall surface of at least one fin. By adjusting the dielectric layer thickness, channel width of the resulting device can be fine-tuned.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • Patent number: 10665706
    Abstract: A power semiconductor transistor includes: a semiconductor body coupled to a load terminal; a drift region in the semiconductor body and having dopants of a first conductivity type; a first trench extending into the semiconductor body along a vertical direction and including a control electrode electrically insulated from the semiconductor body by an insulator; a second trench extending into the semiconductor body along the vertical direction; a mesa region arranged between the trenches and including a source region electrically connected to the load terminal and a channel region separating the source and drift regions; and a portion of a contiguous plateau region of a second conductivity type arranged in the semiconductor drift region and extending below the trenches and below the channel and source regions, the contiguous plateau region having a plurality of openings aligned below the channel region in a widthwise direction of the channel region.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: May 26, 2020
    Assignee: Infineon Technologies AG
    Inventors: Anton Mauder, Franz-Josef Niedernostheide, Christian Philipp Sandow
  • Patent number: 10651165
    Abstract: A semiconductor device includes a semiconductor region having charge carriers of a first conductivity type, a transistor cell in the semiconductor region, and a semiconductor channel region in the transistor cell and having a first doping concentration of charge carriers of a second conductivity type. A semiconductor auxiliary region in the semiconductor region has a second doping concentration of charge carriers of the second conductivity type, which is at least 30% higher than the first doping concentration. A pn-junction between the semiconductor auxiliary region and the semiconductor region is positioned as deep or deeper in the semiconductor region as a pn-junction between the semiconductor channel region and the semiconductor region. The semiconductor auxiliary region is positioned closer to the semiconductor channel region than any other semiconductor region having charge carriers of the second conductivity type and that forms a further pn-junction with the semiconductor region.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: May 12, 2020
    Assignee: Infineon Technologies AG
    Inventors: Johannes Georg Laven, Roman Baburske, Thomas Basler, Philip Christoph Brandt, Maria Cotorogea
  • Patent number: 10643852
    Abstract: A process of forming electronic device can include providing a substrate having a first portion and a second portion; introducing a nitrogen-containing species into the second portion of the substrate; and exposing the substrate to an oxidizing ambient, wherein a thicker oxide is grown from the first portion as compared to the second portion. In an embodiment, the process can include removing the first portion while the second portion of the substrate that includes the nitrogen-containing species remains. In another embodiment, the process can be used to form different thicknesses of an oxide layer at different portions along a sidewall of a trench. The process may be used in other applications where different thicknesses of oxide layers are to be formed during the same oxidation cycle, such as forming a tunnel dielectric layer and a gate dielectric layer for a floating gate memory cell.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: May 5, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Peter A. Burke, James Kimball, Gordon M. Grivna
  • Patent number: 10644154
    Abstract: A method for manufacturing a semiconductor device includes forming a fin structure including a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer. An isolation insulating layer is formed so that the channel layer of the fin structure protrudes from the isolation insulating layer and a part of or an entirety of the oxide layer is embedded in the isolation insulating layer. A gate structure is formed over the fin structure. A recessed portion is formed by etching a part of the fin structure not covered by the gate structure such that the oxide layer is exposed. A recess is formed in the exposed oxide layer. An epitaxial seed layer in the recess in the oxide layer. An epitaxial layer is formed in and above the recessed portion. The epitaxial layer is in contact with the epitaxial seed layer.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: May 5, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Chih-Hao Wang, Wai-Yi Lien
  • Patent number: 10643851
    Abstract: A compound semiconductor device includes a semiconductor substrate having a ground layer of a first conductivity type made of a compound semiconductor, a first conductivity type region formed at a corner portion of a bottom of a deep trench formed to the ground layer, and a deep layer of a second conductivity type formed in the deep trench so as to cover the first conductivity type region. A cross section of the first conductivity type region is a triangular shape or a rounded triangular shape in which a portion of the first conductivity type region being in contact with the deep layer is recessed to have a curved surface.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: May 5, 2020
    Assignee: DENSO CORPORATION
    Inventors: Yuichi Takeuchi, Atsuya Akiba, Katsumi Suzuki, Sachiko Aoi
  • Patent number: 10644022
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device pertain to a semiconductor device having a channel pattern, wherein the channel pattern includes a pipe channel and vertical channels protruding in a first direction from the pipe channel. The semiconductor device also has interlayer insulating layers disposed over the pipe channel and gate electrodes disposed over the pipe channel, wherein the gate electrodes are alternately stacked with the interlayer insulating layers in the first direction, wherein the stacked interlayer insulating layers and gate electrodes surround the vertical channels, and wherein the gate electrodes include a first conductive pattern and second conductive patterns. The semiconductor device further has an etch stop pattern disposed over the first conductive pattern and under the second conductive patterns.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: May 5, 2020
    Assignee: SK hynix Inc.
    Inventor: Kang Sik Choi
  • Patent number: 10629676
    Abstract: First and second cell trench structures extend from a first surface into a semiconductor substrate. The first cell trench structure includes a first buried electrode and a first insulator layer between the first buried electrode and a semiconductor mesa separating the first and second cell trench structures. A capping layer covers the first surface. The capping layer is patterned to form an opening having a minimum width larger than a thickness of the first insulator layer. The opening exposes a first vertical section of the first insulator layer at the first surface. An exposed portion of the first insulator layer is removed to form a recess between the semiconductor mesa and the first buried electrode. A contact structure is in the opening and the recess. The contact structure electrically connects both a buried zone in the semiconductor mesa and the first buried electrode and allows for narrower semiconductor mesa width.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: April 21, 2020
    Assignee: Infineon Technologies AG
    Inventors: Johannes Georg Laven, Maria Cotorogea, Hans-Joachim Schulze, Haybat Itani, Erich Griebl, Andreas Haghofer
  • Patent number: 10630199
    Abstract: A switching device according to the present invention is a switching device for switching a load by on-off control of voltage, and includes an SiC semiconductor layer where a current path is formed by on-control of the voltage, a first electrode arranged to be in contact with the SiC semiconductor layer, and a second electrode arranged to be in contact with the SiC semiconductor layer for conducting with the first electrode due to the formation of the current path, while the first electrode has a variable resistance portion made of a material whose resistance value increases under a prescribed high-temperature condition for limiting current density of overcurrent to not more than a prescribed value when the overcurrent flows to the current path.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: April 21, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Yuki Nakano, Hiroyuki Sakairi
  • Patent number: 10622467
    Abstract: High-voltage, gallium-nitride HEMTs are described that are capable of withstanding reverse-bias voltages of at least 900 V and, in some cases, in excess of 2000 V with low reverse-bias leakage current. A HEMT may comprise a lateral geometry having a gate, a thin insulating layer formed beneath the gate, a gate-connected field plate, and a source-connected field plate.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: April 14, 2020
    Assignee: MACOM Technology Solutions Holdings, Inc.
    Inventors: Timothy E. Boles, Douglas Carlson, Anthony Kaleta
  • Patent number: 10622446
    Abstract: A semiconductor device includes in an active region in which current flows, an n+-type silicon carbide epitaxial layer of a low concentration and formed on an n+-type silicon carbide substrate; a p-type channel region constituting a channel region; a trench contacting the p-type channel region and having embedded therein an oxide film and a gate electrode; a p+-type base layer arranged beneath the trench; a third n-type CSL layer region contacting the p-type channel region; a second n-type CSL layer region having a maximum impurity concentration higher than that of the third n-type CSL layer region, the maximum impurity concentration being farther on a substrate front side than a top of the p+-type base layer arranged beneath the trench is; and a first n-type CSL layer region contacting the second n-type CSL layer region and having a maximum impurity concentration lower than that of the second n-type CSL layer region.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: April 14, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yusuke Kobayashi, Akimasa Kinoshita, Shinsuke Harada
  • Patent number: 10622378
    Abstract: A ferroelectric memory device may include a semiconductor substrate, a plurality of ferroelectric layers, a source, a drain and a gate. The semiconductor substrate may have a recess. The ferroelectric layers may be formed in the recess. The source may be arranged at a first side of the recess. The drain may be arranged at a second side of the recess opposite to the first side. The gate may be arranged on the ferroelectric layers. The ferroelectric layers may be polarized by different electric fields.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: April 14, 2020
    Assignee: SK hynix Inc.
    Inventors: Se Hun Kang, Deok Sin Kil
  • Patent number: 10615275
    Abstract: A semiconductor device includes a semiconductor layer. A first conductivity type region is formed on a base layer portion of the semiconductor layer. A body region of a second conductivity type is formed on the semiconductor layer to be in contact with the first conductivity type region. A trench in which a gate electrode is embedded through a gate insulating film is formed on the semiconductor layer. The trench penetrates through the body region, so that a deepest portion thereof reaches the first conductivity type region. A source region of the first conductivity type is formed on a surface layer portion of the semiconductor layer around the trench. The gate insulating film includes a thick-film portion having a relatively large thickness on a bottom surface of the trench.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: April 7, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Naoki Izumi
  • Patent number: 10615254
    Abstract: An embodiment of a semiconductor device includes a SiC semiconductor body region having a body region of a first conductivity type, a drift zone of a second conductivity type, and a compensation structure of the first conductivity type. The compensation structure and a drift zone section of the drift zone form a super junction structure. The compensation structure adjoins the body region and is positioned entirely below the body region in a vertical direction perpendicular to a surface of the SiC semiconductor body. The compensation structure includes a first compensation sub-structure and a second compensation sub-structure. The first compensation sub-structure and the second compensation sub-structure are arranged above one another in the vertical direction. A width of the compensation structure changes along the vertical direction.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: April 7, 2020
    Assignee: Infineon Technologies AG
    Inventors: Anton Mauder, Rudolf Elpelt, Dethard Peters
  • Patent number: 10608106
    Abstract: A power semiconductor device including a first conductivity type semiconductor substrate, a drain metal electrode, a first conductivity type semiconductor drift region, and a second conductivity type semiconductor body region. The second conductivity type semiconductor body region includes a first conductivity type semiconductor source region and anti-punch-through structure; the anti-punch-through structure is a second conductivity type semiconductor body contact region or metal structure; the lower surface of the anti-punch-through structure coincides with the upper surface of the first conductivity type semiconductor drift region or the distance between the two is less than 0.5 ?m, so that make the device avoid from punch-through. An anti-punch-through structure is introduced at the source end of the device to avoid punch-through breakdown caused by short channel and light-doped body region.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: March 31, 2020
    Assignee: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA
    Inventors: Ming Qiao, Zhengkang Wang, Ruidi Wang, Zhao Qi, Bo Zhang
  • Patent number: 10608118
    Abstract: An embodiment is a semiconductor device which includes a first oxide semiconductor layer over a substrate having an insulating surface and including a crystalline region formed by growth from a surface of the first oxide semiconductor layer toward an inside; a second oxide semiconductor layer over the first oxide semiconductor layer; a source electrode layer and a drain electrode layer which are in contact with the second oxide semiconductor layer; a gate insulating layer covering the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer; and a gate electrode layer over the gate insulating layer and in a region overlapping with the second oxide semiconductor layer. The second oxide semiconductor layer is a layer including a crystal formed by growth from the crystalline region.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: March 31, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10600777
    Abstract: A semiconductor device includes a semiconductor body, first to third electrodes provided on the semiconductor body, and a control electrode. The control electrode is provided between the semiconductor body and the first electrode. The semiconductor body includes first to sixth layers. The second layer of a second conductivity type is selectively provided between the first layer of a first conductivity type and the first electrode. The third layer of the first conductivity type is selectively provided between the second layer and the first electrode. The fourth layer of the second conductivity type is provided between the first layer and the second and third electrodes. The fifth layer of the first conductivity type is selectively provided in the fourth layer and electrically connected to the first electrode. The sixth layer of the first conductivity type is provided in the fourth layer, and electrically connected to the third electrode.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: March 24, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hisao Ichijo, Syotaro Ono, Hiroaki Yamashita
  • Patent number: 10600905
    Abstract: A device has an active area made of an array of first type of device cells and a gate or shield contact area made of an array of a second type of device cells that are laid out at a wider pitch than the array of first type of device cells. Each device cell in the active area includes a trench that contains a gate electrode and an adjoining mesa that contains the drain, source, body, and channel regions of the device. The second type of device cell includes a trench that is wider than the trench in the first device cell, but a mesa of the second type of device cell has about the same width as the mesa of the first type of device cell. Having about the same width, the mesa in the second type of device cell in the contact area has similar breakdown characteristics as a mesa in the first type of device cell in the active area of the device.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: March 24, 2020
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Prasad Venkatraman, Dean E. Probst
  • Patent number: 10600794
    Abstract: A twin bit memory cell includes first and second spaced apart floating gates formed in first and second trenches in the upper surface of a semiconductor substrate. An erase gate, or a pair of erase gates, are disposed over and insulated from the floating gates, respectively. A word line gate is disposed over and insulated from a portion of the upper surface that is between the first and second trenches. A first source region is formed in the substrate under the first trench, and a second source region formed in the substrate under the second trench. A continuous channel region of the substrate extends from the first source region, along a side wall of the first trench, along the portion of the upper surface that is between the first and second trenches, along a side wall of the second trench, and to the second source region.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: March 24, 2020
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Chunming Wang, Andy Liu, Xian Liu, Leo Xing, Melvin Diao, Nhan Do
  • Patent number: 10593769
    Abstract: A method of manufacturing a semiconductor device includes forming a base layer in an upper part of a substrate and a trench in the substrate. A gate insulating film is on an inner bottom surface and an inner side surface of the trench and a gate electrode is embedded into the trench. The gate electrode is etched so that an upper surface of the gate electrode is at a first height from the bottom of the trench. A source region is in contact with an outer side surface of the trench. A base contact region is in contact with part of the outer side surface of the trench, an upper part of the base layer, and an upper part of the source region. A source electrode is embedded in a remaining part of the trench and in contact with the source region and the base contact region.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: March 17, 2020
    Assignee: ABLIC INC.
    Inventors: Yuki Osuga, Hirofumi Harada
  • Patent number: 10593793
    Abstract: A semiconductor device according to an embodiment includes: a first semiconductor region of a first conductive type; a base region of a second conductive type; gate electrodes penetrating through the base region to reach the first semiconductor region; gate insulating films around the plurality of gate electrodes; a first region having a source region of the first conductive type, among a plurality of regions between the plurality of gate insulating films; a second region not having the source region among the plurality of regions, the second region being located in a terminal region of the first region; a first contact of a first width in the first region and electrically connecting the base region and a source electrode; and a second contact of a second width larger than the first width, the second contact being in the second region and electrically connecting the base region and the source electrode.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: March 17, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Tatsuya Nishiwaki, Kohei Oasa, Hiroshi Matsuba, Kikuo Aida, Hung Hung
  • Patent number: 10593758
    Abstract: A method for manufacturing a power semiconductor device includes forming a trench in a semiconductor substrate, forming a gate insulation film and a gate electrode in the trench, implanting a first conductivity type impurity into the semiconductor substrate to form a first conductivity type body region, implanting a second conductivity type impurity onto a surface of the semiconductor substrate to form a second conductivity type source region, forming an interlayer insulation film in the trench, implanting the first conductivity type impurity onto the surface of the semiconductor substrate to form a first conductivity type highly doped body contact region, exposing a portion of a side surface of the trench, and forming a source metal to be in contact with the exposed side surface of the trench.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: March 17, 2020
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Seong Jo Hong, Soo Chang Kang, Ha Yong Yang, Young Ho Seo
  • Patent number: 10586851
    Abstract: A semiconductor device includes a trench structure extending from a first surface into a silicon carbide semiconductor body. The trench structure includes an auxiliary electrode at a bottom of the trench structure and a gate electrode arranged between the auxiliary electrode and the first surface. A shielding region adjoins the auxiliary electrode at the bottom of the trench structure and forms a first pn junction with a drift structure. A corresponding method of manufacturing the semiconductor device is also described.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: March 10, 2020
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Caspar Leendertz, Anton Mauder, Roland Rupp
  • Patent number: 10586877
    Abstract: A semiconductor device may include: an n type of layer disposed on a first surface of a substrate; a p+ type of region disposed on the first surface of the substrate; a p? type of region disposed at a top portion of the n type of layer; a first electrode disposed on the p+ type of region and the p? type of region; and a second electrode disposed on a second surface of the substrate, wherein the side surface of the p+ type of region and the side surface of the n type of layer are in contact, and the thickness of the p+ type of region is the same as the thickness of the n type of layer and the thickness of the p? type of region.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: March 10, 2020
    Assignees: Hyundai Motor Company, Kia Motors Corporation
    Inventors: Dae Hwan Chun, NackYong Joo
  • Patent number: 10580878
    Abstract: A SiC device with a doped buried region is provided. The doped buried region may be formed by: forming a first trench which extends into a first side of a SiC epitaxial layer of a first conductivity type, the first trench terminating at a first depth in the SiC epitaxial layer; at least partly filling the first trench with an epitaxial material of a second conductivity type opposite the first conductivity type; forming a second trench which extends into the first side of the SiC epitaxial layer so that the second trench overlaps the first trench, the second trench terminates at a second depth in the SiC epitaxial layer which is less than the first depth, and the epitaxial material in the first trench laterally extends below a bottom of the second trench; and forming a gate electrode in the second trench and electrically insulated from the SiC epitaxial layer.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: March 3, 2020
    Assignee: Infineon Technologies AG
    Inventors: Ravi Keshav Joshi, Rudolf Elpelt, Romain Esteve
  • Patent number: 10580888
    Abstract: A semiconductor device includes a gate trench extending into a Si substrate, a body region in the Si substrate, the body region including a channel region which extends along a sidewall of the gate trench, a source region in the Si substrate above the body region, a contact trench extending into the Si substrate and separated from the gate trench by a portion of the source region and a portion of the body region, the contact trench being filled with an electrically conductive material which contacts the source region at a sidewall of the contact trench and a highly doped body contact region at a bottom of the contact trench, and a diffusion barrier structure formed along the sidewall of the contact trench and disposed between the highly doped body contact region and the channel region, the diffusion barrier structure including alternating layers of Si and oxygen-doped Si.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: March 3, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Oliver Blank, Thomas Feil, Maximilian Roesch, Martin Poelzl, Robert Haase, Sylvain Leomant, Bernhard Goller, Andreas Meiser
  • Patent number: 10573653
    Abstract: A semiconductor device can include a plurality of landing pads arranged according to a layout on a substrate, wherein a cross-sectional shape of each of the landing pads has a diamond shape so that opposing interior angles of the diamond shape are equal to one another and adjacent interior angles of the diamond shape are unequal to one another.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: February 25, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun-Kyum Kim, Jung-Woo Seo, Sung-Un Kwon
  • Patent number: 10573741
    Abstract: A semiconductor device in embodiments, may include a device region having: two active trenches, each having at least a gate electrode. Two insulated trenches each having an electrode may be formed between the two active trenches separated by a junction. First p-doped layers may be provided between a first active trench and a first insulated trench, and between a second active trenches and a second insulated trench. Second p-doped layers may be provided between a first insulated trench and a second insulated trench with the junction arranged therebetween. The second p-doped layers may be provided on an external surface of the respective first one and second one of the two insulated trenches at a depth and a thickness set to form a current path when the power semiconductor device is in an OFF state.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: February 25, 2020
    Assignee: SANKEN ELECTRIC CO., LTD.
    Inventors: Shunsuke Fukunaga, Taro Kondo, Shinji Kudo
  • Patent number: 10573634
    Abstract: A semiconductor device includes a substrate, first, second, third and fourth bottom contacts in the substrate, and first, second, third and fourth active fins on respective ones of the first, second, third and fourth bottom contacts, the second and third fins overlapping in a first direction. First, second and third gate electrodes extend longitudinally in the first direction, the first and second gate electrodes disposed on side surfaces of respective ones of the first and fourth active fins and the third gate electrode disposed on side surfaces of the second and third active fins. A first top contact is on the first and second active fins and a second top contact is on the third and fourth active fins.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: February 25, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin Woo Jeong, Kwan Young Chun
  • Patent number: 10566201
    Abstract: A method that includes forming a conductive source/drain structure that is conductively coupled to source/drain regions of first and second transistor devices, selectively forming a conductive source/drain metallization cap structure on and in contact with an upper surface of the conductive source/drain structure, forming a patterned etch mask that exposes a portion of the gate cap and a portion of the conductive source/drain metallization cap structure, and performing at least one etching process to remove the exposed portion of the gate cap and thereafter an exposed portion of the final gate structure so as to form a gate cut opening, wherein the conductive source/drain metallization cap structure protects the underlying conductive source/drain structure during the at least one etching process.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: February 18, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Chanro Park, Ruilong Xie, Hui Zang, Laertis Economikos, Andre LaBonte
  • Patent number: 10566464
    Abstract: A semiconductor device includes a semiconductor layer located between first and second electrodes. The contact location of the semiconductor layer with the first electrode forms a first contact plane. The semiconductor layer includes a first-conductivity-type first semiconductor region in contact with the first electrode, a second-conductivity-type second semiconductor region located between the first electrode and the first semiconductor region and contacting the first electrode, a second-conductivity-type third semiconductor region located between the first electrode and the second semiconductor region and contacting the first electrode and having a higher impurity concentration than that of the second semiconductor region, and a second-conductivity-type fourth semiconductor region located between the first electrode and the first semiconductor region and contacting the first electrode.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: February 18, 2020
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsuyoshi Oota, Yoichi Hori
  • Patent number: 10559466
    Abstract: A transistor comprises channel material having first and second opposing sides. A gate is on the first side of the channel material and a gate insulator is between the gate and the channel material. A first insulating material has first and second opposing sides, with the first side being adjacent the second side of the channel material. A second insulating material of different composition from that of the first insulating material is adjacent the second side of the first insulating material. The second insulating material has at least one of (a), (b), and (c), where, (a): lower oxygen diffusivity than the first material, (b): net positive charge, and (c): at least two times greater shear strength than the first material. In some embodiments, an array of elevationally-extending strings of memory cells comprises such transistors. Other embodiments, including method, are disclosed.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: February 11, 2020
    Assignee: Micron Technology, Inc.
    Inventors: David H. Wells, Anish A. Khandekar, Kunal Shrotri, Jie Li
  • Patent number: 10553685
    Abstract: A semiconductor device includes a trench extending from a first surface into a SiC semiconductor body. The trench has a first sidewall, a second sidewall opposite to the first sidewall, and a trench bottom. A gate electrode is arranged in the trench and is electrically insulated from the SiC semiconductor body by a trench dielectric. A body region of a first conductivity type adjoins the first sidewall. A shielding structure of the first conductivity type adjoins at least a portion of the second sidewall and the trench bottom. A first section of the trench bottom and a second section of the trench bottom are offset to one another by a vertical offset along a vertical direction extending from the first surface to a second surface of the SiC semiconductor body opposite to the first surface.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: February 4, 2020
    Assignee: Infineon Technologies AG
    Inventors: Ralf Siemieniec, Thomas Aichinger, Romain Esteve, Daniel Kueck
  • Patent number: 10546951
    Abstract: A trench MOS device with improved single event burnout endurance, applied in the field of semiconductor. The device is provided, in an epitaxial layer, with a conductive type semiconductor pillar connected to a source and a second conductive type current-directing region. Whereby, the trajectory of the electron-hole pairs induced by the single event effect is changed and thus avoids the single event burnout caused by the triggering of parasitic transistors, therefore improving the endurance of the single event burnout of the trench MOS device.
    Type: Grant
    Filed: September 17, 2016
    Date of Patent: January 28, 2020
    Assignees: University of Electronic Science and Technology of China, Institute of Electronic and Information Engineering of UESTC in Guangdong
    Inventors: Min Ren, Yuci Lin, Chi Xie, Zhiheng Su, Zehong Li, Jinping Zhang, Wei Gao, Bo Zhang
  • Patent number: 10546955
    Abstract: A method of forming a fin structure that includes forming a plurality of fin structures from a bulk semiconductor substrate and forming a dielectric spacer on a sidewall of each fin structure in the plurality of fin structure. A semiconductor spacer is formed on a sidewall of the dielectric spacer. A dielectric fill is formed in the space between the adjacent fin structures. The semiconductor spacer and a portion of the fin structures that is present below a lower surface of the dielectric spacer are oxidized. Oxidizing a base portion of the fin structures produces a first strain and oxidizing the semiconductor spacer produces a second strain that is opposite the first strain.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: January 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Bruce B. Doris, Darsen D. Lu, Ali Khakifirooz, Kern Rim
  • Patent number: 10541326
    Abstract: A semiconductor device contains a vertical MOS transistor having a trench gate in trenches extending through a vertical drift region to a drain region. The trenches have field plates under the gate; the field plates are adjacent to the drift region and have a plurality of segments. A dielectric liner in the trenches separating the field plates from the drift region has a thickness great than a gate dielectric layer between the gate and the body. The dielectric liner is thicker on a lower segment of the field plate, at a bottom of the trenches, than an upper segment, immediately under the gate. The trench gate may be electrically isolated from the field plates, or may be connected to the upper segment. The segments of the field plates may be electrically isolated from each other or may be connected to each other in the trenches.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: January 21, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hideaki Kawahara, Seetharaman Sridhar, Christopher Boguslaw Kocon, Simon John Molloy, Hong Yang
  • Patent number: 10541303
    Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device includes a substrate having a fin. A first nanowire is disposed on the fin and a second nanowire is disposed on the fin, the second nanowire being laterally separated from the first nanowire. A gate structure extends around the first nanowire and the second nanowire. The gate structure also extends over a top surface of the fin. The first nanowire, the second nanowire, and the fin form a channel of a transistor.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: January 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Aryan Afzalian, Blandine Duriez, Mark van Dal
  • Patent number: 10529814
    Abstract: Machining accuracy of an IGBT region is worsened due to a height difference caused by polysilicon. Therefore, there is a problem that characteristic variation of the IGBT increases. Provided is a semiconductor device including a semiconductor substrate; a gate wiring layer provided on a front surface side of the semiconductor substrate; and a gate structure that includes a gate electrode and is provided on the front surface of the semiconductor substrate. The gate wiring layer includes an outer periphery portion that is a metal wiring layer and is provided along an outer periphery of the semiconductor substrate; and an extending portion that is a metal wiring layer, is provided extending from the outer periphery portion toward a central portion of the semiconductor substrate, and is electrically connected to the gate electrode.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: January 7, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuya Naito
  • Patent number: 10529847
    Abstract: The present disclosure provides a trench power semiconductor component and a method of manufacturing the same. The trench gate structure of the trench power semiconductor component includes a shielding electrode, a gate electrode disposed above the shielding electrode, and an inter-electrode dielectric layer. Before the formation of the inter-electrode dielectric layer, the step of forming the trench gate structure includes: forming a laminated structure covering the inner wall surface of the cell trench, in which the laminated structure includes a semiconductor material layer and an initial inner dielectric layer covering the semiconductor material layer; forming a heavily-doped semiconductor material in the lower part of the cell trench; and removing a portion of the initial inner dielectric layer located at an upper part of the cell trench to expose an upper half portion of the semiconductor material layer and a top portion of the heavily doped semiconductor material.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: January 7, 2020
    Assignee: SUPER GROUP SEMICONDUCTOR CO., LTD.
    Inventor: Hsiu-Wen Hsu
  • Patent number: 10529846
    Abstract: A semiconductor device includes a semiconductor substrate, a gate electrode, and a first contact plug. The semiconductor substrate includes a first surface and a second surface. Over the semiconductor substrate, a source region, a drain region, a drift region, and a body region are formed. A first trench in which the gate electrode is buried is formed in the first surface. The first surface includes an effective region and a peripheral region. The first trench extends from the peripheral region over the effective region along a first direction. The gate electrode includes a portion opposed to and insulated from the body region sandwiched between the source region and the drift region. In the peripheral region, the first contact plug is electrically coupled to the gate electrode buried in the first trench such that its longer side is along the first direction when seen in a plan view.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: January 7, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Taro Moriya, Hiroyoshi Kudou, Hiroshi Yanagigawa
  • Patent number: 10522696
    Abstract: A semiconductor body of a first type of conductivity is formed including a base layer, a first further layer on the base layer and a second further layer on the first further layer. The base layer and the second further layer have an intrinsic doping or a doping concentration that is lower than the doping concentration of the first further layer. A doped region of an opposite second type of conductivity is arranged in the semiconductor body, penetrates the first further layer and extends into the base layer and into the second further layer. Anode and cathode terminals are electrically connected to the first further layer and the doped region, respectively. The doped region can be produced by filling a trench with doped polysilicon.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: December 31, 2019
    Assignee: ams AG
    Inventors: Jordi Teva, Frederic Roger
  • Patent number: 10522620
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a gate electrode, and a conductive portion. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The gate electrode opposes, in a second direction with a gate insulating layer interposed, the third semiconductor region, the second semiconductor region, and the first semiconductor region. The second direction is perpendicular to a first direction from the second semiconductor region toward the third semiconductor region. The conductive portion includes first and second portions. The first and second portions are respectively arranged with the second and third semiconductor regions. A length of the first portion is longer than a length of the second portion.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: December 31, 2019
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Toshifumi Nishiguchi
  • Patent number: 10510875
    Abstract: A method includes forming a fin structure on the substrate, wherein the fin structure includes a first fin active region; a second fin active region; and an isolation feature separating the first and second fin active regions; forming a first gate stack on the first fin active region and a second gate stack on the second fin active region; performing a first recessing process to a first source/drain region of the first fin active region by a first dry etch; performing a first epitaxial growth to form a first source/drain feature on the first source/drain region; performing a fin sidewall pull back (FSWPB) process to remove a dielectric layer on the second fin active region; and performing a second epitaxial growth to form a second source/drain feature on a second source/drain region of the second fin active region.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Teng Liao, Chih-Shan Chen, Yi-Wei Chiu, Chih Hsuan Cheng, Tzu-Chan Weng