With Charge Trapping Gate Insulator, E.g., Mnos Transistor (epo) Patents (Class 257/E21.423)
  • Patent number: 10381345
    Abstract: Provided is a semiconductor device having an enhanced characteristic and a resistor structure satisfying a desired target resistor value of a resistor device. A semiconductor device includes: a lower interlayer insulating layer disposed on a substrate comprising a resistor area; a resistor structure comprising a resistor layer and an etch stop pattern sequentially stacked on the lower interlayer insulating layer of the resistor area; an upper interlayer insulating layer configured to cover the resistor structure and disposed on the lower interlayer insulating layer; a resistor contact structure configured to pass through the upper interlayer insulating layer and the etch stop pattern and contact the resistor layer; and a resistor contact spacer disposed between the upper interlayer insulating layer, the etch stop pattern, and the resistor contact structure.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: August 13, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong-sik Shin, Do-hyoung Kim, Doo-young Lee, Hyon-wook Ra, Seo-bum Lee, Won-hyuk Lee
  • Patent number: 10366915
    Abstract: A semiconductor device includes a first gate structure disposed over a substrate. The first gate structure extends in a first direction. A second gate structure is disposed over the substrate. The second gate structure extends in the first direction. A dielectric material is disposed between the first gate structure and the second gate structure. An air gap is disposed within the dielectric material.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: July 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Patent number: 10134585
    Abstract: Surface pretreatment of SiGe or Ge surfaces prior to gate oxide deposition cleans the SiGe or Ge surface to provide a hydrogen terminated surface or a sulfur passivated (or S—H) surface. Atomic layer deposition (ALD) of a high-dielectric-constant oxide at a low temperature is conducted in the range of 25-200° C. to form an oxide layer. Annealing is conducted at an elevated temperature. A method for oxide deposition on a damage sensitive III-V semiconductor surface conducts in-situ cleaning of the surface with cyclic pulsing of hydrogen and TMA (trimethyl aluminum) at a low temperature in the range of 100-200° C. Atomic layer deposition (ALD) of a high-dielectric-constant oxide forms an oxide layer. Annealing is conducted at an elevated temperature. The annealing can create a silicon terminated interfaces.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: November 20, 2018
    Assignee: The Regents of the University of California
    Inventors: Kasra Sardashti, Tobin Kaufman-Osborn, Tyler Kent, Andrew Kummel, Shariq Siddiqui, Bhagawan Sahu, Adam Brand, Naomi Yoshida
  • Patent number: 9941300
    Abstract: A method for fabricating a fully depleted silicon on insulator (FDSOI) device is described. A charge trapping layer in a buried oxide layer is provided on a semiconductor substrate. A backgate well in the semiconductor substrate is provided under the charge trapping layer. A device structure including a gate structure, source and drain regions is disposed over the buried oxide layer. A charge is trapped in the charge trapping layer. The threshold voltage of the device is partially established by the charge trapped in the charge trapping layer. Different aspects of the invention include the structure of the FDSOI device and a method of tuning the charge trapped in the charge trapping layer of the FDSOI device.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: April 10, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John Joseph Ellis-Monaghan, Terence B Hook, Kirk David Peterson
  • Patent number: 9755050
    Abstract: The semiconductor device including: a semiconductor layer extending in a first direction, the semiconductor layer including a pair of source/drain regions and a channel region, a gate extending on the semiconductor layer to cover the channel region, and a gate dielectric layer interposed between the channel region and the gate, a corner insulating spacer having a first surface and a second surface, the first surface extending in the second direction along a side wall of the gate, the first surface covering from a side portion of the gate dielectric layer to at least a portion of the side wall of the gate, and the second surface covering a portion of the semiconductor layer, and an outer portion insulating spacer covering the side wall of the gate above the corner insulating spacer, the outer portion insulating spacer having a smaller dielectric constant than the corner insulating spacer, may be provided.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: September 5, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Je-min Park
  • Patent number: 9666585
    Abstract: Semiconductor devices are provided. The semiconductor device includes a bit line contact plug and a storage node contact plug electrically connected to an active region of a substrate. A bit line structure is disposed on the bit line contact plug to extend in a first direction. The bit line structure is disposed in a trench pattern that intrudes into a side of the storage node contact plug. Related methods and systems are also provided.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: May 30, 2017
    Assignee: SK HYNIX INC.
    Inventors: Jin Ki Jung, Myoung Soo Kim
  • Patent number: 9620384
    Abstract: A method of manufacturing a semiconductor structure, by depositing a dielectric layer is a dummy gate, or an existing gate structure, prior to the formation of gate spacers. Following the formation of spacers, and in some embodiments replacing a dummy gate with a final gate structure, oxygen is introduced to a gate dielectric through a diffusion process, using the deposited dielectric layer as a diffusion pathway.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: April 11, 2017
    Inventors: Takashi Ando, Claude Ortolland, Kai Zhao
  • Patent number: 9449984
    Abstract: A three dimensional memory device including a substrate and a semiconductor channel. At least one end portion of the semiconductor channel extends substantially perpendicular to a major surface of the substrate. The device also includes at least one charge storage region located adjacent to semiconductor channel and a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate. The plurality of control gate electrodes include at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level. Each of the plurality of control gate electrodes includes a first edge surface which is substantially free of silicide, the first edge surface facing the semiconductor channel and the at least one charge storage region and a silicide located on remaining surfaces of the control gate electrode.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: September 20, 2016
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Johann Alsmeier, Peter Rabkin
  • Patent number: 9041111
    Abstract: A flat panel detector includes a photoelectric conversion layer and a pixel detecting element disposed under the photoelectric conversion layer. The pixel detecting element includes: a pixel electrode for receiving charges, a storage capacitor for storing the received charges, and a thin film transistor for controlling outputting of the stored charges. The storage capacitor includes a first electrode and a second electrode. The first electrode includes an upper electrode and a bottom electrode that are disposed opposite to each other and electrically connected. A second electrode is sandwiched between the upper electrode and the bottom electrode. It is insulated between the upper electrode and the second electrode and between the second electrode and the bottom electrode.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: May 26, 2015
    Assignee: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Zhenyu Xie
  • Patent number: 9035374
    Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: May 19, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kidoh, Masaru Kito, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Hideaki Aochi
  • Patent number: 9013005
    Abstract: According to an embodiment, a semiconductor device includes a second semiconductor layer provided on a first semiconductor layer and including first pillars and second pillars. A first control electrode is provided in a trench of the second semiconductor layer and a second control electrode is provided on the second semiconductor layer and connected to the first control electrode. A first semiconductor region is provided on a surface of the second semiconductor layer except for a portion under the second control electrode. A second semiconductor region is provided on a surface of the first semiconductor region, the second semiconductor region being apart from the portion under the second control electrode and a third semiconductor region is provided on the first semiconductor region. A first major electrode is connected electrically to the first semiconductor layer and a second major electrode is connected electrically to the second and the third semiconductor region.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: April 21, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Syotaro Ono, Wataru Saito, Shunji Taniuchi, Miho Watanabe, Hiroaki Yamashita, Toshiyuki Naka
  • Patent number: 9000510
    Abstract: A nonvolatile memory device includes: a channel layer extending in a vertical direction from a substrate; a plurality of interlayer dielectric layers and word lines alternately stacked along the channel layer over the substrate; a bit line formed under plurality of interlayer dielectric layers and word lines, coupled to the channel layer, and extending in a direction crossing the word lines; and a common source layer coupled to the channel layer and formed over the plurality of interlayer dielectric layers and word lines.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: April 7, 2015
    Assignee: SK Hynix Inc.
    Inventor: Young-Ok Hong
  • Patent number: 8981452
    Abstract: Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices). Methods for protecting nanostructures from fusion during high temperature processing also are provided.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: March 17, 2015
    Assignee: SanDisk Corporation
    Inventors: Jian Chen, Xiangfeng Duan, Chao Liu, Madhuri Nallabolu, J. Wallace Parce, Srikanth Ranganathan
  • Patent number: 8969947
    Abstract: A memory device includes a substrate, a semiconductor column extending perpendicularly from the substrate and a plurality of spaced-apart charge storage cells disposed along a sidewall of the semiconductor column. Each of the storage cells includes a tunneling insulating layer disposed on the sidewall of the semiconductor column, a polymer layer disposed on the tunneling insulating layer, a plurality of quantum dots disposed on or in the polymer layer and a blocking insulating layer disposed on the polymer layer.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: March 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-goo Lee, Jung-dal Choi, Young-woo Park
  • Patent number: 8956943
    Abstract: A method for manufacturing a non-volatile memory is disclosed. A gate structure is formed on a substrate and includes a gate dielectric layer and a gate conductive layer. The gate dielectric layer is partly removed, thereby a symmetrical opening is formed among the gate conductive layer, the substrate and the gate dielectric layer, and a cavity is formed on end sides of the gate dielectric layer. A first oxide layer is formed on a sidewall and bottom of the gate conductive layer, and a second oxide layer is formed on a surface of the substrate. A nitride material layer is formed covering the gate structure, the first and second oxide layer and the substrate and filling the opening. An etching process is performed to partly remove the nitride material layer, thereby forming a nitride layer on a sidewall of the gate conductive layer and extending into the opening.
    Type: Grant
    Filed: May 27, 2013
    Date of Patent: February 17, 2015
    Assignee: United Microelectronics Corporation
    Inventors: Chien-Hung Chen, Tzu-Ping Chen, Yu-Jen Chang
  • Patent number: 8957471
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a conductive member, a semiconductor pillar, and a charge storage layer. The stacked body is provided above the substrate. The stacked body includes a plurality of insulating films stacked alternately with a plurality of electrode films. A plurality of terraces are formed in a stairstep configuration along only a first direction in an end portion of the stacked body on the first-direction side. The first direction is parallel to an upper face of the substrate. The plurality of terraces are configured with upper faces of the electrode films respectively. The conductive member is electrically connected to the terrace to connect electrically the electrode film to the substrate by leading out the electrode film in a second direction parallel to the upper face of the substrate and orthogonal to the first direction.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: February 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiaki Fukuzumi
  • Patent number: 8951864
    Abstract: A semiconductor device includes a substrate; a storage element disposed over the substrate in a first region; a control gate disposed over the storage element; a high-k dielectric layer disposed on the substrate in a second region adjacent the first region; and a metal select gate disposed over the high-k dielectric layer and adjacent to the storage element and the control gate.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: February 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hsiung Wang, Chih-Ren Hsieh, Tung-Sheng Hsiao
  • Patent number: 8946021
    Abstract: On a silicon substrate is formed a stacked body by alternately stacking a plurality of silicon oxide films and silicon films, a trench is formed in the stacked body, an alumina film, a silicon nitride film and a silicon oxide film are formed in this order on an inner surface of the trench, and a channel silicon crystalline film is formed on the silicon oxide film. Next, a silicon oxide layer is formed at an interface between the silicon oxide film and the channel silicon crystalline film by performing thermal treatment in an oxygen gas atmosphere.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: February 3, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshio Ozawa
  • Patent number: 8941171
    Abstract: Memory devices, methods for fabricating, and methods for adjusting flatband voltages are disclosed. In one such memory device, a pair of source/drain regions are formed in a semiconductor. A dielectric material is formed on the semiconductor between the pair of source/drain regions. A control gate is formed on the dielectric material. A charged species is introduced into the dielectric material. The charged species, e.g., mobile ions, has an energy barrier in a range of greater than about 0.5 eV to about 3.0 eV. A flatband voltage of the memory device can be adjusted by moving the charged species to different levels within the dielectric material, thus programming different states into the device.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: January 27, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Roy Meade
  • Patent number: 8928064
    Abstract: A method of forming a gate structure for a semiconductor device that includes forming a non-stoichiometric high-k gate dielectric layer on a semiconductor substrate, wherein an oxide containing interfacial layer can be present between the non-stoichiometric high-k gate dielectric layer and the semiconductor substrate. At least one gate conductor layer may be formed on the non-stoichiometric high-k gate dielectric layer. The at least one gate conductor layer comprises a boron semiconductor alloy layer. An anneal process is applied, wherein during the anneal process the non-stoichiometric high-k gate dielectric layer removes oxide material from the oxide containing interfacial layer. The oxide containing interfacial layer is thinned by removing the oxide material during the anneal process.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Martin M. Frank, Isaac Lauer, Jeffrey W. Sleight
  • Patent number: 8912089
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a stacked body on a substrate. The stacked body includes a plurality of first conductive layers including a metallic element as a main component and a plurality of second conductive layers including a metallic element as a main component provided respectively between the first conductive layers. The method includes making a hole to pierce the stacked body. The method includes making a slit to divide the stacked body. The method includes making a gap between the first conductive layers by removing the second conductive layers by etching via the slit or the hole. The method includes forming a memory film including a charge storage film at a side wall of the hole. The method includes forming a channel body on an inner side of the memory film inside the hole.
    Type: Grant
    Filed: March 21, 2013
    Date of Patent: December 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Seiichi Omoto, Yoshihiro Uozumi, Tadashi Iguchi, Osamu Yamane, Kazuyuki Masukawa, Yoshihiro Yanai
  • Patent number: 8900948
    Abstract: A method for fabricating a non-volatile memory device includes alternately stacking a plurality of inter-layer dielectric layers and a plurality of sacrificial layers over a substrate, forming at least a channel hole that exposes the substrate by selectively etching the inter-layer dielectric layers and the sacrificial layers, forming a protective layer on sidewalls of the sacrificial layers that are exposed through the channel hole, sequentially forming a memory layer and a channel layer on the sidewalls of the channel hole, forming slit holes that penetrate through the inter-layer dielectric layers and the sacrificial layers on both sides of the channel hole, removing the sacrificial layers that are exposed through the slit holes, removing the protective layer, and forming gate electrodes in space from which the sacrificial layers and the protective layer are removed.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: December 2, 2014
    Assignee: SK Hynix Inc.
    Inventors: Seok-Min Jeon, Sun-Kok Hwang
  • Patent number: 8901632
    Abstract: A method of making a semiconductor structure includes forming a select gate over a substrate in an NVM region and a first protection layer over a logic region. A control gate and a storage layer are formed over the substrate in the NVM region. The control gate has a top surface below a top surface of the select gate. The charge storage layer is under the control gate, along adjacent sidewalls of the select gate and control gate, and is partially over the top surface of the select gate. A second protection layer is formed over the NVM portion and the logic portion. The first and second protection layers are removed from the logic region. A portion of the second protection layer is left over the control gate and the select gate. A gate structure, formed over the logic region, has a high k dielectric and a metal gate.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: December 2, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Asanga H. Perera, Cheong Min Hong, Sung-Taeg Kang, Byoung W. Min, Jane A. Yater
  • Patent number: 8883624
    Abstract: Memory cells including embedded SONOS based non-volatile memory (NVM) and MOS transistors and methods of forming the same are described. Generally, the method includes: forming a gate stack of a NVM transistor in a NVM region of a substrate including the NVM region and a plurality of MOS regions; and depositing a high-k dielectric material over the gate stack of the NVM transistor and the plurality of MOS regions to concurrently form a blocking dielectric comprising the high-k dielectric material in the gate stack of the NVM transistor and high-k gate dielectrics in the plurality of MOS regions. In one embodiment, a first metal layer is deposited over the high-k dielectric material and patterned to concurrently form a metal gate over the gate stack of the NVM transistor, and a metal gate of a field effect transistor in one of the MOS regions.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: November 11, 2014
    Assignee: Cypress Semiconductor Corporation
    Inventor: Krishnaswamy Ramkumar
  • Patent number: 8877568
    Abstract: Methods of making a logic transistor in a logic region and an NVM cell in an NVM region of a substrate include forming a conductive layer on a gate dielectric, patterning the conductive layer over the NVM region, removing the conductive layer over the logic region, forming a dielectric layer over the NVM region, forming a protective layer over the dielectric layer, removing the dielectric layer and the protective layer from the logic region, forming a high-k dielectric layer over the logic region and a remaining portion of the protective layer, and forming a first metal layer over the high-k dielectric layer. The first metal layer, the high-k dielectric, and the remaining portion of the protective layer are removed over the NVM region. A conductive layer is deposited over the remaining portions of the dielectric layer and over the first metal layer, and the conductive layer is patterned.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: November 4, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mehul D. Shroff, Mark D. Hall
  • Patent number: 8877587
    Abstract: A method for fabricating a nonvolatile memory device includes forming a stacked structure over a substrate defining a cell area and a peripheral area and having a source region, the stacked structure including interlayer dielectric layers and sacrifice layers, forming channel layers connected to the substrate through the stacked structure of the cell area, forming a first slit in the stacked structure of the cell area, forming a second slit in the stacked structure, the second slit including a first portion and a second portion, removing the sacrifice layers exposed through the first and second slits, forming conductive layers to fill spaces from which the sacrifice layers are removed, forming an insulating layer in the second slit, and forming a source contact by burying a conductive material in the first portion of the second slit having the insulating layer formed therein.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: November 4, 2014
    Assignee: SK Hynix Inc.
    Inventor: Yoo-Hyun Noh
  • Patent number: 8871598
    Abstract: A method of making a semiconductor device includes forming a split gate memory gate structure on a memory region of a substrate, and protecting the split gate memory gate structure by depositing protective layers over the memory region including the memory gate structure and over a logic region of the substrate. The protective layers include a material that creates a barrier to diffusion of metal. The protective layers are retained over the memory region while forming a logic gate in the logic region. The logic gate includes a high-k dielectric layer and a metal layer. A spacer material is deposited over the logic gate. Spacers are formed on the memory gate structure and the logic gate. The spacer on the logic gate is formed of the spacer material and the spacer on the memory gate structure is formed with one of the protective layers.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: October 28, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Asanga H. Perera
  • Patent number: 8872255
    Abstract: A semiconductor device includes a region in a semiconductor substrate having a top surface with a first charge storage layer on the top surface. A first conductive line is on the first charge storage layer. A second charge storage layer is on the top surface. A second conductive line is on the second charge storage layer. A third charge storage layer is on the top surface. A third conductive line is on the third charge storage layer. A fourth charge storage layer has a first side adjoining a first sidewall of the first conductive line and a second side adjoining a first sidewall of the second conductive line. A fifth charge storage layer has a first side adjoining a second sidewall of the second conductive line and a second side adjoining a first sidewall of the third conductive line. Source and drain regions are formed in the substrate on either side of the semiconductor device.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: October 28, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mark D. Hall, Mehul D. Shroff
  • Patent number: 8859410
    Abstract: A method of forming a gate structure for a semiconductor device that includes forming a non-stoichiometric high-k gate dielectric layer on a semiconductor substrate, wherein an oxide containing interfacial layer can be present between the non-stoichiometric high-k gate dielectric layer and the semiconductor substrate. At least one gate conductor layer may be formed on the non-stoichiometric high-k gate dielectric layer. The at least one gate conductor layer comprises a boron semiconductor alloy layer. An anneal process is applied, wherein during the anneal process the non-stoichiometric high-k gate dielectric layer removes oxide material from the oxide containing interfacial layer. The oxide containing interfacial layer is thinned by removing the oxide material during the anneal process.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: October 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Martin M. Frank, Isaac Lauer, Jeffrey W. Sleight
  • Patent number: 8853769
    Abstract: Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion. Some embodiments include a method of forming a semiconductor construction. First semiconductor material and metal-containing material are formed over a NAND string. An opening is formed through the metal-containing material and the first semiconductor material, and is lined with gate dielectric. Second semiconductor material is provided within the opening to form a channel region of a transistor. The transistor is a select device electrically coupled to the NAND string.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: October 7, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Deepak Thimmegowda, Andrew R. Bicksler, Roland Awusie
  • Patent number: 8841183
    Abstract: On a silicon substrate is formed a stacked body by alternately stacking a plurality of silicon oxide films and silicon films, a trench is formed in the stacked body, an alumina film, a silicon nitride film and a silicon oxide film are formed in this order on an inner surface of the trench, and a channel silicon crystalline film is formed on the silicon oxide film. Next, a silicon oxide layer is formed at an interface between the silicon oxide film and the channel silicon crystalline film by performing thermal treatment in an oxygen gas atmosphere.
    Type: Grant
    Filed: March 10, 2011
    Date of Patent: September 23, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshio Ozawa
  • Patent number: 8835232
    Abstract: A disposable dielectric structure is formed on a semiconductor-on-insulator (SOI) substrate such that all physically exposed surfaces of the disposable dielectric structure are dielectric surfaces. A semiconductor material is selectively deposited on semiconductor surfaces, while deposition of any semiconductor material on dielectric surfaces is suppressed. After formation of at least one gate spacer and source and drain regions, a planarization dielectric layer is deposited and planarized to physically expose a top surface of the disposable dielectric structure. The disposable dielectric structure is replaced with a replacement gate stack including a gate dielectric and a gate conductor portion. Lower external resistance can be provided without impacting the short channel performance of a field effect transistor device.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Hemanth Jagannathan, Sivananda K. Kanakasabapathy
  • Patent number: 8809938
    Abstract: Three dimensional semiconductor memory devices are provided. The three dimensional semiconductor memory device includes a first stacked structure and a second stacked structure sequentially stacked on a substrate. The first stacked structure includes first insulating patterns and first gate patterns which are alternately and repeatedly stacked on a substrate, and the second stacked structure includes second insulating patterns and second gate patterns which are alternately and repeatedly stacked on the first stacked structure. A plurality of first vertical active patterns penetrate the first stacked structure, and a plurality of second vertical active patterns penetrate the second stacked structure. The number of the first vertical active patterns is greater than the number of the second vertical active patterns.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: August 19, 2014
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Sung-Min Hwang, Hansoo Kim, Changseok Kang, Wonseok Cho, Jae-Joo Shim
  • Patent number: 8809152
    Abstract: A semiconductor device including a germanium containing substrate including a gate structure on a channel region of the semiconductor substrate. The gate structure may include a silicon oxide layer that is in direct contact with an upper surface of the germanium containing substrate, at least one high-k gate dielectric layer in direct contact with the silicon oxide layer, and at least one gate conductor in direct contact with the high-k gate dielectric layer. The interface between the silicon oxide layer and the upper surface of the germanium containing substrate is substantially free of germanium oxide. A source region and a drain region may be present on opposing sides of the channel region.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: August 19, 2014
    Assignee: International Business Machines Corporation
    Inventors: MaryJane Brodsky, Murshed M. Chowdhury, Michael P. Chudzik, Min Dai, Siddarth A. Krishnan, Shreesh Narasimha, Shahab Siddiqui
  • Patent number: 8802526
    Abstract: Methods of forming non-volatile memory cell structures are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in reverse and normal mode floating node memory cells that allow for direct tunnel programming and erase, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The low voltage direct tunneling program and erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and enhancing device lifespan. The low voltage direct tunnel program and erase capability also enables size reduction through low voltage design and further device feature scaling. Such memory cells also allow multiple bit storage. These characteristics allow such memory cells to operate within the definition of a universal memory, capable of replacing both DRAM and ROM in a system.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: August 12, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Arup Bhattacharyya
  • Patent number: 8796756
    Abstract: A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be less than 40 nm. Therefore, in the write state, since the movement in the transverse direction of the electrons and the holes locally existing in the charge storage layer decreases, the variation of the threshold voltage when holding a high temperature can be reduced. In addition, the effective channel length is made to be 30 nm or less so as to reduce an apparent amount of holes so that coupling of the electrons with the holes in the charge storage layer decreases; therefore, the variation of the threshold voltage when holding at room temperature can be reduced.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: August 5, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Kenichi Akita, Daisuke Okada, Keisuke Kuwahara, Yasafumi Morimoto, Yasuhiro Shimamoto, Kan Yasui, Tsuyoshi Arigane, Tetsuya Ishimaru
  • Patent number: 8796754
    Abstract: A memory structure including a memory cell is provided, and the memory cell includes following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure and a second charge storage structure disposed in the second dielectric structure. At least one of the first charge storage structure and the second charge storage structure includes two charge storage units which are physically separated. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source and drain and a second source and drain are disposed on the first dielectric layer and located at two sides of the channel layer.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: August 5, 2014
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Cheng-Hsien Cheng, Wen-Jer Tsai, Shih-Guei Yan, Chih-Chieh Cheng, Jyun-Siang Huang
  • Patent number: 8791523
    Abstract: A nonvolatile semiconductor storage device includes: a structural body; semiconductor layers; a memory film; a connecting member; and a conductive member. The structural body is provided above a memory region of a substrate including the memory region and a non-memory region, and includes electrode films stacked along a first axis perpendicular to a major surface of the substrate. The semiconductor layers penetrate through the structural body along the first axis. The memory film is provided between the electrode films and the semiconductor layer. The connecting member is provided between the substrate and the structural body and connected to respective end portions of two adjacent ones of the semiconductor layers. The conductive member is provided between the substrate and the connecting member, extends from the memory region to the non-memory region, includes a recess provided above the non-memory region, and includes a first silicide portion provided in the recess.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: July 29, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiromitsu Iino, Tadashi Iguchi
  • Patent number: 8785334
    Abstract: A select transistor for use in a memory device including a plurality of memory transistors connected in series includes a tunnel insulating layer formed on a semiconductor substrate, a charge storage layer formed on the tunnel insulating layer, a blocking insulating layer formed on the charge storage layer and configured to be irradiated with a gas cluster ion beam containing argon as source gas, a gate electrode formed on the blocking insulating layer, and a source/drain region formed within the semiconductor substrate at both sides of the gate electrode.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: July 22, 2014
    Assignee: Tokyo Electron Limited
    Inventor: Yoshitsugu Tanaka
  • Patent number: 8779503
    Abstract: According to one embodiment, a nonvolatile semiconductor memory includes a semiconductor layer, a first insulating layer on the semiconductor layer, a charge storage layer on the first insulating layer, a second insulating layer on the charge storage layer, and a control gate electrode on the second insulating layer. The second insulating layer comprises a stacked structure provided in order of a first lanthanum aluminate layer, a lanthanum aluminum silicate layer and a second lanthanum aluminate layer from the charge storage layer side to the control gate electrode side.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: July 15, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Matsushita, Akira Takashima
  • Patent number: 8765538
    Abstract: Provided are three-dimensional semiconductor memory devices and methods of forming the same. The device includes a substrate, conductive patterns stacked on the substrate, and an active pattern penetrating the conductive patterns to be connected to the substrate. The active pattern may include a first doped region provided in an upper portion of the active pattern, and a diffusion-resistant doped region overlapped with at least a portion of the first doped region. The diffusion-resistant doped region may be a region doped with carbon.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: July 1, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bio Kim, Kihyun Hwang, Jaeyoung Ahn, SeungHyun Lim, Dongwoo Kim
  • Patent number: 8759896
    Abstract: There is provided a non-volatile semiconductor memory having a charge accumulation layer of a configuration where a metal oxide with a dielectric constant sufficiently higher than a silicon nitride, e.g., a Ti oxide, a Zr oxide, or a Hf oxide, is used as a base material and an appropriate amount of a high-valence substance whose valence is increased two levels or more (a VI-valence) is added to produce a trap level that enables entrance and exit of electrons with respect to the base material.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: June 24, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Koichi Muraoka
  • Patent number: 8748968
    Abstract: Provided are a method of forming nano dots, method of fabricating a memory device including the same, charge trap layer including the nano dots and memory device including the same. The method of forming the nano dots may include forming cores, coating surfaces of the cores with a polymer, and forming graphene layers covering the surfaces of the cores by thermally treating the cores coated with the polymer. Also, the cores may be removed after forming the graphene layers. In addition, the surfaces of the cores may be coated with a graphitization catalyst material before coating the cores with the polymer. Also, the cores may include metal particles that trap charges and may also function as a graphitization catalyst.
    Type: Grant
    Filed: April 15, 2008
    Date of Patent: June 10, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-young Choi, Hyeon-jin Shin, Seon-mi Yoon
  • Patent number: 8742489
    Abstract: According to one embodiment, a nonvolatile semiconductor memory including a first gate insulating film formed on a channel region of a semiconductor substrate, a first particle layer formed in the first gate insulating film, a charge storage part formed on the first gate insulating film, a second gate insulating film which is formed on the charge storage part, a second particle layer formed in the second gate insulating film, and a gate electrode formed on the second gate insulating film. The first particle layer includes first conductive particles that satisfy Coulomb blockade conditions. The second particle layer includes second conductive particles that satisfy Coulomb blockade conditions and differs from the first conductive particles in average particle diameter.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: June 3, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryuji Ohba, Daisuke Matsushita
  • Patent number: 8735965
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, an electrode layer provided above the substrate, a first insulating layer provided on the electrode layer, a stacked body provided on the insulating layer, a memory film, a channel body layer, a channel body connecting portion and a second insulating layer. The stacked body has a plurality of conductive layers and a plurality of insulating film alternately stacked on each other. The memory film is provided on a sidewall of each of a pair of holes penetrating the stacked body in a direction of stacking the stacked body. The channel body layer is provided on an inner side of the memory film in each of the pair of the holes.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: May 27, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hanae Ishihara, Mitsuru Sato, Toru Matsuda
  • Patent number: 8729624
    Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: May 20, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kidoh, Masaru Kito, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Hideaki Aochi
  • Publication number: 20140126290
    Abstract: The disclosure is related to memory arrays and methods. One such memory array has a substantially vertical pillar. A memory cell adjacent to the pillar where the pillar has a first size has a greater channel length than a memory cell adjacent to the pillar where the pillar has a second size larger than the first size.
    Type: Application
    Filed: November 2, 2012
    Publication date: May 8, 2014
    Applicant: MICRON TECEHNOLOGY, INC
    Inventors: Koji Sakui, Peter Feeley
  • Patent number: 8710579
    Abstract: A semiconductor device and method of manufacturing the same are provided. In one embodiment, semiconductor device comprises a split charge-trapping region comprising two nitride layers with charge traps distributed therein, the two nitride layers separated by one or more oxide layers. The two nitride layers include a first nitride layer closer to a substrate over which the split charge-trapping region is formed, and a second nitride layer on the other side of the one or more oxide layers. The second nitride layer comprises a majority of the charge traps. Other embodiments are also described.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: April 29, 2014
    Assignee: Cypress Semiconductor Corporation
    Inventors: Fredrick Jenne, Krishnaswamy Ramkumar
  • Patent number: 8710578
    Abstract: Embodiments of a non-planar memory device including a split charge-trapping region and methods of forming the same are described. Generally, the device comprises: a channel formed from a thin film of semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide overlying the channel; a split charge-trapping region overlying the tunnel oxide, the split charge-trapping region including a bottom charge-trapping layer comprising a nitride closer to the tunnel oxide, and a top charge-trapping layer, wherein the bottom charge-trapping layer is separated from the top charge-trapping layer by a thin anti-tunneling layer comprising an oxide. Other embodiments are also disclosed.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: April 29, 2014
    Assignee: Cypress Semiconductor Corporation
    Inventors: Fredrick Jenne, Krishnaswamy Ramkumar
  • Patent number: 8705274
    Abstract: The present disclosure relates to the field of microelectronics manufacture and memories. A three-dimensional multi-bit non-volatile memory and a method for manufacturing the same are disclosed. The memory comprises a plurality of memory cells constituting a memory array. The memory array may comprise: a gate stack structure; periodically and alternately arranged gate stack regions and channel region spaces; gate dielectric layers for discrete charge storage; periodically arranged channel regions; source doping regions and drain doping regions symmetrically arranged to each other; bit lines led from the source doping regions and the drain doping regions; and word lines led from the gate stack regions. The gate dielectric layers for discrete charge storage can provide physical storage spots to achieve single-bit or multi-bit operations, so as to achieve a high storage density.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: April 22, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Ming Liu, Chenxi Zhu, Zongliang Huo, Feng Yan, Qin Wang, Shibing Long