Abstract: Some embodiments include a memory cell having a conductive gate, and having a charge-blocking region adjacent the conductive gate. The charge-blocking region includes silicon oxynitride and silicon dioxide. A charge-storage region is adjacent the charge-blocking region. Tunneling material is adjacent the charge-storage region. Channel material is adjacent the tunneling material. The tunneling material is between the channel material and the charge-storage region. Some embodiments include memory arrays. Some embodiments include methods of forming assemblies (e.g., memory arrays).

Abstract: Semiconductor devices and methods of fabricating semiconductor devices are provided. The present disclosure provides a semiconductor device that includes a first fin structure and a second fin structure each extending from a substrate; a first gate segment over the first fin structure and a second gate segment over the second fin structure; a first isolation feature separating the first and second gate segments; a first source/drain (S/D) feature over the first fin structure and adjacent to the first gate segment; a second S/D feature over the second fin structure and adjacent to the second gate segment; and a second isolation feature also disposed in the trench. The first and second S/D features are separated by the second isolation feature, and a composition of the second isolation feature is different from a composition of the first isolation feature.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located within a respective one of the memory openings, and at least one drain-select-level isolation structure vertically extending through at least a topmost electrically conductive layer among the electrically conductive layers. The at least one drain-select-level isolation structure may include wiggles and cut through upper portions of at least some of the memory opening fill structures, or may include a vertically-extending dielectric material portion and laterally-protruding dielectric material portions adjoined to the vertically-extending dielectric material portion and laterally protruding into lateral recesses located adjacent to the at least the topmost electrically conductive layer.

Abstract: Some embodiments include apparatuses and methods having a source material, a dielectric material over the source material, a select gate material over the dielectric material, a memory cell stack over the select gate material, a conductive plug located in an opening of the dielectric material and contacting a portion of the source material, and a channel material extending through the memory cell stack and the select gate material and contacting the conductive plug.

Abstract: Embodiments are described herein to reshape spacer profiles to improve spacer uniformity and thereby improve etch uniformity during pattern transfer associated with self-aligned multiple-patterning (SAMP) processes. For disclosed embodiments, cores are formed on a material layer for a substrate of a microelectronic workpiece. A spacer material layer is then formed over the cores. Symmetric spacers are then formed adjacent the cores by reshaping the spacer material layer using one or more directional deposition processes to deposit additional spacer material and using one or more etch process steps. For one example embodiment, one or more oblique physical vapor deposition (PVD) processes are used to deposit the additional spacer material for the spacer profile reshaping. This reshaping of the spacer profiles allows for symmetric spacers to be formed thereby improving etch uniformity during subsequent pattern transfer processes.

Abstract: A solar cell is provided with: a semiconductor substrate having a light-receiving surface and a non-light-receiving surface; a PN junction section formed on the semiconductor substrate; a passivation layer formed on the light-receiving surface and/or the non-light-receiving surface; and power extraction electrodes formed on the light-receiving surface and the non-light-receiving surface. The solar cell is characterized in that the passivation layer includes an aluminum oxide film having a thickness of 40 nm or less. As a result of forming a aluminum oxide film having a predetermined thickness on the surface of the substrate, it is possible to achieve excellent passivation performance and excellent electrical contact between silicon and the electrode by merely firing the conductive paste, which is conventional technology. Furthermore, an annealing step, which has been necessary to achieve the passivation effects of the aluminum oxide film in the past, can be eliminated, thus dramatically reducing costs.

Abstract: A solar cell is provided with: a semiconductor substrate having a light-receiving surface and a non-light-receiving surface; a PN junction section formed on the semiconductor substrate; a passivation layer formed on the light-receiving surface and/or the non-light-receiving surface; and power extraction electrodes formed on the light-receiving surface and the non-light-receiving surface. The solar cell is characterized in that the passivation layer includes an aluminum oxide film having a thickness of 40 nm or less. As a result of forming a aluminum oxide film having a predetermined thickness on the surface of the substrate, it is possible to achieve excellent passivation performance and excellent electrical contact between silicon and the electrode by merely firing the conductive paste, which is conventional technology. Furthermore, an annealing step, which has been necessary to achieve the passivation effects of the aluminum oxide film in the past, can be eliminated, thus dramatically reducing costs.

Abstract: A method includes depositing a first work function tuning layer over a gate dielectric layer using an atomic layer deposition process. The atomic layer deposition process comprises depositing one or more first nitride monolayers; and depositing one or more carbide monolayers over the one or more first nitride monolayers. The method further includes depositing an adhesion layer of the first work function tuning layer; and depositing a conductive material over the adhesion layer.

Abstract: A semiconductor device of an embodiment includes: a first and second semiconductor regions of a first conductivity type; a third semiconductor region of a second conductivity type disposed between the first and second semiconductor regions; a fourth semiconductor region of the first conductivity type disposed below the first semiconductor region; a fifth semiconductor region of the first conductivity type disposed below the second semiconductor region; a first region containing carbon disposed between the first and fourth semiconductor regions; a second region containing carbon disposed between the second and fifth semiconductor regions; a third region disposed between the first and second regions; the first and second regions having a first and second carbon concentrations respectively, the third region not containing carbon or having a lower carbon concentration than the first and second carbon concentrations in a portion below an end of a lower face of a gate electrode.

Abstract: In one embodiment, a semiconductor storage device includes a substrate, a stacked film including a plurality of first insulating layers and a plurality of electrode layers that are alternately provided on the substrate, and a second insulating layer provided on the stacked film. The device further includes a plurality of pillar portions, each of which including a first insulator, a charge storage layer, a second insulator, a first semiconductor layer and a third insulator that are sequentially provided in the stacked film and the second insulating layer. Furthermore, a width of the second insulating layer sandwiched between the pillar portions is narrower than a width of the stacked film sandwiched between the pillar portions, in at least a portion of the second insulating layer.

Abstract: A semiconductor memory device includes: a semiconductor substrate; a memory cell array provided in a first region; a first transistor provided in a second region; a second transistor provided in a third region; and an insulative laminated film. The first and second transistors each include a semiconductor layer, a gate electrode, and a gate insulating film. A concentration of boron (B) in the gate electrode of the second transistor is higher than that of the first transistor. The insulative laminated film includes a first insulating film contacting the surface of the semiconductor substrate, and a second insulating film having a smaller diffusion coefficient of hydrogen (H) than that of the first insulating film. The second insulating film has a first portion contacting the semiconductor portion, and the first portion surrounds the third region.

Abstract: According to one embodiment, the semiconductor body of the first portion includes a first semiconductor part and a second semiconductor part. The first semiconductor part extends in the stacking direction. The second semiconductor part is provided between the first semiconductor part and the first electrode layer, and has an end located closer to the first electrode layer side than the first semiconductor part. The first insulating film of the second portion includes a first insulating part and a second insulating part. The first insulating part extends in the stacking direction. The second insulating part is provided between the first insulating part and the second electrode layer, and has an end located closer to the second electrode layer side than the first insulating part.

Abstract: Various examples are provided related to hydrogen plasma treatment of hafnium oxide. In one example, a method includes depositing a monolayer of a precursor on a first oxide monolayer; forming a second oxide monolayer by applying an oxygen (O2) plasma to the monolayer of the precursor; and creating oxygen vacancies in the second oxide monolayer by applying a hydrogen (H2) plasma to the second oxide monolayer. In another example, a device includes a hafnium oxide (HfO2) based ferroelectric thin film on a first side of a substrate and an electrode layer disposed on the HfO2 based ferroelectric thin film opposite the substrate. The HfO2 film includes a plurality of oxide monolayers including at least one HfO2 monolayer, each of the plurality of oxide monolayers having oxygen vacancies distributed throughout that oxide monolayer.

Abstract: A semiconductor device includes a base body, a stacked body on the base body and a first columnar part. The base body includes a substrate, a first insulating film on the substrate, a first conductive film on the first insulating film, and a first semiconductor part on the first conductive film. The stacked body includes conductive layers and insulating layers stacked alternately in a stacking direction. The first columnar part is provided inside the stacked body and the first semiconductor part. The first columnar part includes a semiconductor body and a memory film between the semiconductor body and conductive layers. The semiconductor body extends in the stacking direction. The first columnar part has a first diameter and a second diameter in a first direction crossing the stacking direction. The first diameter inside the first semiconductor part is larger than the second diameter inside the stacked body.

Abstract: A semiconductor device includes: a substrate; a fin structure and a gate structure formed on the substrate; and a source/drain trench formed in the fin structure on each side of the gate structure. The source/drain trench includes a bottom region and a top region located above the bottom region. Along an extension direction of the fin structure, a dimension of the top region is larger than a dimension of the bottom region. Along the extension direction of the fin structure, a shortest distance from a sidewall surface of the top region of the source/drain trench to a sidewall surface of the gate structure is smaller than a shortest distance from a sidewall surface of the bottom region of the source/drain trench to the sidewall surface of the gate structure. The semiconductor device further includes a source/drain doped layer formed in the source/drain trench.

Abstract: Integrated circuit devices having improved interlayer dielectric (ILD) layer topography and methods of fabrication thereof are disclosed herein. An exemplary integrated circuit device includes a first gate structure having a first height disposed over a substrate in a first region and a second gate structure having a second height disposed over the substrate in a second region. The second height is less than the first height. A first contact etch stop layer is disposed over the first gate structure. A second contact etch stop layer disposed over the second gate structure. The first contact etch stop layer has a first thickness, the second contact etch stop layer has a second thickness, and the second thickness is greater than the first thickness. An interlayer dielectric layer is disposed over the first contact etch stop layer and the second contact etch stop layer.

Abstract: The subject of the invention is the use, as catalyst support sublayer in a process for growing carbon nanotubes by chemical vapour deposition (CVD), of a multilayer stack formed of alternating layers of silica and of alumina, each of the layers having a thickness of less than or equal to 10 nm and consisting of one or more superposed atomic monolayer(s). It also relates to a multilayer structure comprising a substrate which has, on at least one of its faces, such a multilayer stack, and also to the use thereof for the growth of a mat of carbon nanotubes, which are in particular spinnable, by chemical vapour deposition, preferably hot-filament chemical vapour deposition.

Abstract: A fin field device structure and method for forming the same are provided. The FinFET device structure includes a protruding structure extending from a substrate and an anti-punch through implant (APT) region formed in the protruding structure. The FinFET device structure includes a barrier layer formed on the APT region, and the barrier layer has a width in a horizontal direction. The width gradually tapers from a bottom of the barrier layer to a top of the barrier layer.

Abstract: A semiconductor device with a large storage capacity per unit area is provided. A semiconductor device includes a memory cell. The memory cell includes a first conductor; a first insulator over the first conductor; a first oxide over the first insulator and including a first region, a second region, and a third region positioned between the first region and the second region; a second insulator over the first oxide; a second conductor over the second insulator; a third insulator positioned in contact with a side surface of the first region; and a second oxide positioned on the side surface of the first region, with the third insulator therebetween. The first region includes a region overlapping the first conductor. The third region includes a region overlapped by the second conductor. The first region and the second region have a lower resistance than the third region.

Abstract: A semiconductor device includes a substrate and first and second gate electrodes on the substrate. The first gate electrode includes a first gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion and away from the substrate defining a first trench having a first width and a first functional film filling the first trench. The second gate electrode includes a second gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion defining a second trench having a second width different from the first width, a second functional film conforming to the second gate insulation film in the second trench and defining a third trench, and a metal region in the third trench. The first width may be less than the second width.

Abstract: Disclosed is a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device comprises a first III-V compound semiconductor layer having a first material structure, a second semiconductor layer having a second material structure and a third semiconductor layer having a third material structure. An interface between the first semiconductor layer and the second semiconductor layer consists of at least one corresponding crystalline terminating oxide layer of the first semiconductor layer, and an interface between the second semiconductor layer and the third semiconductor layer comprises at least one corresponding crystalline terminating oxide layer of a III-V compound semiconductor layer.

Abstract: A vertical non-volatile memory device includes a lower insulating layer on a substrate, a multilayer structure including gate electrodes and interlayer insulating layers alternately stacked on the lower insulating layer, a gate dielectric layer and a channel structure, and has an opening extending through the multilayer structure and exposing the lower insulating layer. The opening includes a first open portion extending through at least one layer of the multilayer structure at a first width, and a second open portion extending through the multilayer structure at a second width less than the first width. The gate dielectric layer lines the opening, and the channel structure is disposed on the gate dielectric layer and is electrically connected to the substrate.

Abstract: A semiconductor device fabrication process includes forming gates on a substrate having a plurality of openings, each gate having a conducting layer a first metal and a gate dielectric layer of a first dielectric material, partially filling the openings with a second dielectric material, forming a first structure on the substrate in a processing system without breaking vacuum, depositing a third dielectric material over the first structure, and forming a planarized surface of the gates and a surface of the third dielectric material that is disposed over the first structure. The forming of the first structure includes forming trenches by removing second portions of the second dielectric material within each opening, forming recessed active regions in the trenches by partially filling the trenches with a second metal, forming a liner over each recessed active region, and forming a metal cap layer over each liner.

Abstract: The present description relates the formation of a first level interlayer dielectric material layer within a non-planar transistor, which may be formed by a spin-on coating technique followed by oxidation and annealing. The first level interlayer dielectric material layer may be substantially void free and may exert a tensile strain on the source/drain regions of the non-planar transistor.

Abstract: The present disclosure provides methods for performing an annealing process on a metal containing layer in TFT display applications, semiconductor or memory applications. In one example, a method of forming a metal containing layer on a substrate includes supplying an oxygen containing gas mixture on a substrate in a processing chamber, the substrate comprising a metal containing layer disposed on an optically transparent substrate, maintaining the oxygen containing gas mixture in the processing chamber at a process pressure between about 2 bar and about 50 bar, and thermally annealing the metal containing layer in the presence of the oxygen containing gas mixture.

Abstract: Embodiments of 3D memory devices having one or more high-? dielectric layers and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including a high-? dielectric layer above the substrate and a plurality of interleaved conductor and dielectric layers above the high-? dielectric layer, and a semiconductor plug disposed above the substrate and in an opening of the high-? dielectric layer.

Abstract: Embodiments of methods for forming channel holes in 3D memory devices using a nonconformal sacrificial layer are disclosed. In an example, a dielectric stack including interleaved first dielectric layers and second dielectric layers is formed on a substrate. An opening extending vertically through the dielectric stack is formed. A nonconformal sacrificial layer is formed along a sidewall of the opening, such that a variation of a diameter of the opening decreases. The nonconformal sacrificial layer and part of the dielectric stack abutting the nonconformal sacrificial layer are removed. A channel structure is formed in the opening after removing the nonconformal sacrificial layer and part of the dielectric stack.

Abstract: Provided is a method of selectively etching a substrate including at least one cycle of: depositing a chemical precursor on a surface of the substrate, the substrate including a first portion and a second portion, to selectively form a chemical precursor layer on a surface of the first portion of the substrate without forming or substantially without forming the chemical precursor layer on a surface of the second portion of the substrate, wherein the first portion of the substrate and the second portion of the substrate are of different composition; exposing the chemical precursor layer on the surface of the first portion of the substrate and the surface of the second portion of the substrate to a plasma environment subjected to a bias power; and selectively and in a self-limited fashion removing at least a part of the second portion of the substrate, and repeating the cycle until the second portion of the substrate is substantially or completely removed.

Abstract: A third type of metal gate stack is provided above an isolation structure and between a replacement metal gate n-type field effect transistor and a replacement metal gate p-type field effect transistor. The third type of metal gate stack includes at least three different components. Notably, the third type of metal gate stack includes, as a first component, an n-type workfunction metal layer, as a second component, a p-type workfunction metal layer, and as a third component, a low resistance metal layer. In some embodiments, the uppermost surface of the first, second and third components of the third type of metal gate stack are all substantially coplanar with each other. In other embodiments, an uppermost surface of the third component of the third type of metal gate stack is non-substantially coplanar with an uppermost surface of both the first and second components of the third type of metal gate stack.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a plurality vertical memory strings disposed through an alternating conductor/dielectric stack. Each of the memory strings includes a composite dielectric layers and a TFET semiconductor layer. The TFET semiconductor layer includes an n-type semiconductor layer and a p-type semiconductor layer.

Abstract: A transmission line impedance transformer including at least two different dielectric media having different dielectric properties, each of the dielectric media being configured to taper in thickness along the length of the impedance transformer in an inverse relationship with respect to each other so as to form a combined dielectric medium having an effective dielectric property that is graded along the transmission path. The two or more dielectric media may be disposed between two conductors to provide an impedance transformer in which a characteristic impedance of the transmission line varies along its length in response to the gradation of the effective dielectric property of the combined dielectric medium.

Abstract: A semiconductor device includes a substrate, a first conductive feature over a portion of the substrate, and an etch stop layer over the substrate and the first conductive feature. The etch stop layer includes a silicon-containing dielectric (SCD) layer and a metal-containing dielectric (MCD) layer over the SCD layer. The semiconductor device further includes a dielectric layer over the etch stop layer, and a second conductive feature in the dielectric layer. The second conductive feature penetrates the etch stop layer and electrically connects to the first conductive feature.

Abstract: The performances of a semiconductor device of a memory element are improved. Over a semiconductor substrate, a gate electrode for memory element is formed via overall insulation film of gate insulation film for memory element. The overall insulation film has first insulation film, second insulation film over first insulation film, third insulation film over second insulation film, fourth insulation film over third insulation film, and fifth insulation film over fourth insulation film. The second insulation film is an insulation film having charge accumulation function. Each band gap of first insulation film and third insulation film is larger than the band gap of second insulation film. The third insulation film is polycrystal film including high dielectric constant material containing metallic element and oxygen. Fifth insulation film is polycrystal film including the same material as that for third insulation film. Fourth insulation film includes different material from that for third insulation film.

Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a memory cell with a large operation window and a high erase speed. In some embodiments, the IC comprises a semiconductor substrate and a memory cell. The memory cell comprises a control gate electrode, a select gate electrode, a charge trapping layer, and a common source/drain region. The common source/drain is defined by the semiconductor substrate and is n-type. The control gate electrode and the select gate electrode overlie the semiconductor substrate and are respectively on opposite sides of the common source/drain. Further, the control gate electrode overlies the charge trapping layer and comprises a metal with a p-type work function. In some embodiments, the select gate electrode comprises a metal with an n-type work function.

Abstract: Embodiments of the present disclosure generally relate to methods for forming a high-k gate dielectric in a transistor. The high-k gate dielectric may be formed by introducing a fluorine containing gas into a processing chamber during the deposition of the high-k gate dielectric in the processing chamber. In one embodiment, the high-k gate dielectric is formed by an ALD process in a processing chamber, and a fluorine containing gas is introduced into the processing chamber during one or more stages of the ALD process. Fluorine ions, molecules or radicals from the fluorine containing gas (may be activated by a plasma) can fill the oxygen vacancies in the high-k dielectric.

Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, and an intermediate region. A position of the first electrode is between a position of the second electrode and a position of the third electrode. The first semiconductor region is separated from the first, second, and third electrodes. The second semiconductor region is provided between the second electrode and the first semiconductor region. The third semiconductor region is provided between the third electrode and the first semiconductor region. The intermediate region includes at least one of a first compound or a second compound. At least a portion of the first electrode is positioned between the second and third semiconductor regions. The intermediate region includes a first partial region, a second partial region, and a third partial region.

Abstract: A memory device comprises a reference conductor, and a stack of conductive strips separated by insulating strips, where the conductive strips in the stack extend in a first direction, and the stack is disposed on the reference conductor. The memory device comprises a plurality of hemi-cylindrical vertical channel structures extending through respective vias in the conductive strips in the stack, and comprising semiconductor films in electrical contact with the reference conductor having outside surfaces. Each of the hemi-cylindrical vertical channel structures has a divided elliptical cross section with a major axis tilted relative to the first direction. The memory device comprises data storage structures between the outside surfaces of the semiconductor films and sidewalls of the vias in the conductive strips.

Abstract: A semiconductor device includes a substrate, a semiconductor column vertically disposed on the substrate, a first contact material layer on the substrate and in contact with a lower portion of the semiconductor column, a first insulating material layer on the first contact material layer and having an upper surface lower than an upper surface of the semiconductor column, a gate dielectric material layer on the first insulating material layer and on a portion of sidewalls of the semiconductor column while exposing an upper portion of the semiconductor column, and a gate stack structure on the gate dielectric material layer and surrounding a portion of the gate dielectric material layer on the sidewalls of the semiconductor column. The gate stack structure includes from inside to outside a P-type work function layer, an N-type work function layer, and a gate.

Abstract: A TiON film forming method is provided. A cycle of forming a unit TiN film at a predetermined processing temperature by alternately supplying a Ti-containing gas and a nitriding gas into the processing chamber accommodating a target substrate and oxidizing the unit TiN film by supplying an oxidizing agent into the processing chamber is repeated multiple times. In an initial stage of the film formation, a cycle of repeating the alternate supply of the Ti-containing gas and the nitriding gas X1 times and supplying the oxidizing agent is repeated Y1 times. In a later stage of the film formation, a cycle of repeating the alternate supply of the Ti-containing gas and the nitriding gas X2 times and supplying the oxidizing agent is repeated Y2 times until a desired film thickness is obtained. The number of repetition X1 is set to be greater than the number of repetition X2.

Abstract: A semiconductor device may include a substrate, a gate electrode disposed on the substrate, a gate insulation layer disposed on the substrate to cover the gate electrode, an active layer including an oxide semiconductor disposed on the gate insulation layer, an insulating interlayer disposed on the gate insulation layer to cover the active layer, a protection structure including a plurality of metal oxide layers disposed on the insulating interlayer, and a source electrode and a drain electrode disposed on the protection structure.

Abstract: A semiconductor structure and a fabrication method are provided. The fabrication method includes providing a base substrate including a substrate and a plurality of discrete fins on the substrate; forming a support layer at least partially on sidewalls of the fins; ion implanting the fins through the support layer to form an ion doped region by an ion implantation process; removing the support layer to expose sidewalls of the fins.

Abstract: Methods are provided for selectively depositing a material on a first metal or metallic surface of a substrate relative to a second, dielectric surface of the substrate, or for selectively depositing metal oxides on a first metal oxide surface of a substrate relative to a second silicon oxide surface. The selectively deposited material can be, for example, a metal, metal oxide, metal nitride, metal silicide, metal carbide and/or dielectric material. In some embodiments a substrate comprising a first metal or metallic surface and a second dielectric surface is alternately and sequentially contacted with a first vapor-phase metal halide reactant and a second reactant. In some embodiments a substrate comprising a first metal oxide surface and a second silicon oxide surface is alternately and sequentially contacted with a first vapor phase metal fluoride or chloride reactant and water.

Abstract: An optoelectronic device and method of manufacturing an optoelectronic device are disclosed. The optoelectronic device includes a substrate; a semiconductor comprising an n-type layer disposed on the substrate, a p-type layer disposed on the n-type layer, and an active layer disposed between the n-type layer and the p-type layer; a transition layer disposed on the substrate and located between the n-type layer and the substrate, the transition layer including an oxygenated IIIA-transition metal nitride; and a p-contact layer disposed on the p-type layer of the semiconductor.

Abstract: According to one embodiment, the source layer includes a semiconductor layer including a dopant. The columnar portions are disposed in an area between the separation portions. The columnar portions extend in the stacking direction through the stacked body and through the semiconductor layer. The columnar portions include a plurality of semiconductor bodies including sidewall portions contacting the semiconductor layer. The dopant diffusion prevention film is provided inside the semiconductor layer and separated from the columnar portions in an area between the columnar portions. The dopant diffusion prevention film is not provided inside the semiconductor layer in an area between the separation portion and the columnar portions.

Abstract: The present invention provides a technology capable of removing impurities remaining in a thin film when the film is formed and modifying a characteristic of the thin film according to a change in impurity concentration. There is provided a method of manufacturing a semiconductor device including: (a) repetitively supplying a plurality of gases including elements constituting a film in temporally separated pulses (in non-simultaneous manner) to form the film on the substrate; and (b) exciting a modifying gas including a reducing gas and at least one of a nitriding gas and an oxidizing gas by plasma and supplying the modifying gas excited by plasma to modify the film.

Abstract: A third type of metal gate stack is provided above an isolation structure and between a replacement metal gate n-type field effect transistor and a replacement metal gate p-type field effect transistor. The third type of metal gate stack includes at least three different components. Notably, the third type of metal gate stack includes, as a first component, an n-type workfunction metal layer, as a second component, a p-type workfunction metal layer, and as a third component, a low resistance metal layer. In some embodiments, the uppermost surface of the first, second and third components of the third type of metal gate stack are all substantially coplanar with each other. In other embodiments, an uppermost surface of the third component of the third type of metal gate stack is non-substantially coplanar with an uppermost surface of both the first and second components of the third type of metal gate stack.

Abstract: Techniques for forming an electronic device having a ferroelectric film are described. The electronic device comprises a ferroelectric material having one or more crystalline structures. The one or more crystalline structures may comprise hafnium, oxygen, and one or more dopants. The one or more dopants are distributed in the ferroelectric material to form a first layer, a second layer, and a third layer. The second layer is positioned between the first layer and the third layer. Distribution of one or more dopants within the first layer, the second layer, and the third layer may promote a crystalline structure to have an orthorhombic phase.

Abstract: An integrated circuit structure includes a plurality of flash memory cells forming a memory array, wherein each of the plurality of flash memory cells includes a select gate and a memory gate. A select gate electrode includes a first portion including polysilicon, wherein the first portion forms select gates of a column of the memory array, and a second portion electrically connected to the first portion, wherein the second portion includes a metal. A memory gate electrode has a portion forming memory gates of the column of the memory array.

Abstract: Various embodiments provide a thin film transistor (TFT), a fabrication method thereof, and a display apparatus including the TFT. A carbon nanotube layer is formed over a substrate. The carbon nanotube layer includes a first plurality of carbon nanotubes. A plurality of gaps are formed through the carbon nanotube layer to provide a first patterned carbon nanotube layer. Carbon nanotube structures each including a second plurality of carbon nanotubes are formed in the plurality of gaps. The carbon nanotube structures have a carrier mobility different from the first patterned carbon nanotube layer, thereby forming an active layer for forming active structures of the thin-film transistor.

Abstract: Provided are P type MOSFETs and methods for manufacturing the same. The method may include forming source/drain regions in a semiconductor substrate; forming an interfacial oxide layer on the semiconductor substrate; forming a high K gate dielectric layer on the interfacial oxide layer; forming a first metal gate layer on the high K gate dielectric layer; implanting dopants into the first metal gate layer through conformal doping; and performing annealing to change an effective work function of a gate stack including the first metal gate layer, the high K gate dielectric, and the interfacial oxide layer.