Gate Insulator Structure Constructed Of Diverse Dielectrics (e.g., Mnos, Etc.) Or Of Nonsilicon Compound Patents (Class 438/287)
  • Patent number: 10790297
    Abstract: Embodiments of methods for forming channel holes in 3D memory devices using a nonconformal sacrificial layer are disclosed. In an example, a dielectric stack including interleaved first dielectric layers and second dielectric layers is formed on a substrate. An opening extending vertically through the dielectric stack is formed. A nonconformal sacrificial layer is formed along a sidewall of the opening, such that a variation of a diameter of the opening decreases. The nonconformal sacrificial layer and part of the dielectric stack abutting the nonconformal sacrificial layer are removed. A channel structure is formed in the opening after removing the nonconformal sacrificial layer and part of the dielectric stack.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: September 29, 2020
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Baoyou Chen, Weihua Cheng, Hai Hui Huang, Zhuqing Huang, Guanping Wu, Hongbin Zhu, Yu Qi Wang
  • Patent number: 10790157
    Abstract: Provided is a method of selectively etching a substrate including at least one cycle of: depositing a chemical precursor on a surface of the substrate, the substrate including a first portion and a second portion, to selectively form a chemical precursor layer on a surface of the first portion of the substrate without forming or substantially without forming the chemical precursor layer on a surface of the second portion of the substrate, wherein the first portion of the substrate and the second portion of the substrate are of different composition; exposing the chemical precursor layer on the surface of the first portion of the substrate and the surface of the second portion of the substrate to a plasma environment subjected to a bias power; and selectively and in a self-limited fashion removing at least a part of the second portion of the substrate, and repeating the cycle until the second portion of the substrate is substantially or completely removed.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: September 29, 2020
    Assignee: University of Maryland, College Park
    Inventors: Gottlieb S. Oehrlein, Kang-Yi Lin, Chen Li
  • Patent number: 10741554
    Abstract: A third type of metal gate stack is provided above an isolation structure and between a replacement metal gate n-type field effect transistor and a replacement metal gate p-type field effect transistor. The third type of metal gate stack includes at least three different components. Notably, the third type of metal gate stack includes, as a first component, an n-type workfunction metal layer, as a second component, a p-type workfunction metal layer, and as a third component, a low resistance metal layer. In some embodiments, the uppermost surface of the first, second and third components of the third type of metal gate stack are all substantially coplanar with each other. In other embodiments, an uppermost surface of the third component of the third type of metal gate stack is non-substantially coplanar with an uppermost surface of both the first and second components of the third type of metal gate stack.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: August 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ramachandra Divakaruni, Sameer H. Jain, Viraj Y. Sardesai, Keith H. Tabakman
  • Patent number: 10720442
    Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a plurality vertical memory strings disposed through an alternating conductor/dielectric stack. Each of the memory strings includes a composite dielectric layers and a TFET semiconductor layer. The TFET semiconductor layer includes an n-type semiconductor layer and a p-type semiconductor layer.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: July 21, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Xin Yun Huang, Qi Wang, Xiang Fu, Zhiliang Xia, Huang Peng Zhang, Hua Min Cao
  • Patent number: 10692641
    Abstract: A transmission line impedance transformer including at least two different dielectric media having different dielectric properties, each of the dielectric media being configured to taper in thickness along the length of the impedance transformer in an inverse relationship with respect to each other so as to form a combined dielectric medium having an effective dielectric property that is graded along the transmission path. The two or more dielectric media may be disposed between two conductors to provide an impedance transformer in which a characteristic impedance of the transmission line varies along its length in response to the gradation of the effective dielectric property of the combined dielectric medium.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: June 23, 2020
    Assignee: Raytheon Company
    Inventors: Daniel B. Schlieter, Patrick J. Kocurek, Christopher A. Loehrlein, Brandon W. Pillans
  • Patent number: 10685873
    Abstract: A semiconductor device includes a substrate, a first conductive feature over a portion of the substrate, and an etch stop layer over the substrate and the first conductive feature. The etch stop layer includes a silicon-containing dielectric (SCD) layer and a metal-containing dielectric (MCD) layer over the SCD layer. The semiconductor device further includes a dielectric layer over the etch stop layer, and a second conductive feature in the dielectric layer. The second conductive feature penetrates the etch stop layer and electrically connects to the first conductive feature.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Szu-Ping Tung, Jen Hung Wang, Shing-Chyang Pan
  • Patent number: 10672916
    Abstract: The performances of a semiconductor device of a memory element are improved. Over a semiconductor substrate, a gate electrode for memory element is formed via overall insulation film of gate insulation film for memory element. The overall insulation film has first insulation film, second insulation film over first insulation film, third insulation film over second insulation film, fourth insulation film over third insulation film, and fifth insulation film over fourth insulation film. The second insulation film is an insulation film having charge accumulation function. Each band gap of first insulation film and third insulation film is larger than the band gap of second insulation film. The third insulation film is polycrystal film including high dielectric constant material containing metallic element and oxygen. Fifth insulation film is polycrystal film including the same material as that for third insulation film. Fourth insulation film includes different material from that for third insulation film.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: June 2, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Masao Inoue
  • Patent number: 10672783
    Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a memory cell with a large operation window and a high erase speed. In some embodiments, the IC comprises a semiconductor substrate and a memory cell. The memory cell comprises a control gate electrode, a select gate electrode, a charge trapping layer, and a common source/drain region. The common source/drain is defined by the semiconductor substrate and is n-type. The control gate electrode and the select gate electrode overlie the semiconductor substrate and are respectively on opposite sides of the common source/drain. Further, the control gate electrode overlies the charge trapping layer and comprises a metal with a p-type work function. In some embodiments, the select gate electrode comprises a metal with an n-type work function.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun-Chi Wu, Cheng-Bo Shu, Chien Hung Liu
  • Patent number: 10580643
    Abstract: Embodiments of the present disclosure generally relate to methods for forming a high-k gate dielectric in a transistor. The high-k gate dielectric may be formed by introducing a fluorine containing gas into a processing chamber during the deposition of the high-k gate dielectric in the processing chamber. In one embodiment, the high-k gate dielectric is formed by an ALD process in a processing chamber, and a fluorine containing gas is introduced into the processing chamber during one or more stages of the ALD process. Fluorine ions, molecules or radicals from the fluorine containing gas (may be activated by a plasma) can fill the oxygen vacancies in the high-k dielectric.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: March 3, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Johanes S. Swenberg, Linlin Wang, Wei Liu
  • Patent number: 10573735
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, and an intermediate region. A position of the first electrode is between a position of the second electrode and a position of the third electrode. The first semiconductor region is separated from the first, second, and third electrodes. The second semiconductor region is provided between the second electrode and the first semiconductor region. The third semiconductor region is provided between the third electrode and the first semiconductor region. The intermediate region includes at least one of a first compound or a second compound. At least a portion of the first electrode is positioned between the second and third semiconductor regions. The intermediate region includes a first partial region, a second partial region, and a third partial region.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: February 25, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiro Koyama, Tatsuo Shimizu, Shinya Nunoue
  • Patent number: 10566348
    Abstract: A memory device comprises a reference conductor, and a stack of conductive strips separated by insulating strips, where the conductive strips in the stack extend in a first direction, and the stack is disposed on the reference conductor. The memory device comprises a plurality of hemi-cylindrical vertical channel structures extending through respective vias in the conductive strips in the stack, and comprising semiconductor films in electrical contact with the reference conductor having outside surfaces. Each of the hemi-cylindrical vertical channel structures has a divided elliptical cross section with a major axis tilted relative to the first direction. The memory device comprises data storage structures between the outside surfaces of the semiconductor films and sidewalls of the vias in the conductive strips.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: February 18, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Teng-Hao Yeh, Hang-Ting Lue
  • Patent number: 10559684
    Abstract: A semiconductor device includes a substrate, a semiconductor column vertically disposed on the substrate, a first contact material layer on the substrate and in contact with a lower portion of the semiconductor column, a first insulating material layer on the first contact material layer and having an upper surface lower than an upper surface of the semiconductor column, a gate dielectric material layer on the first insulating material layer and on a portion of sidewalls of the semiconductor column while exposing an upper portion of the semiconductor column, and a gate stack structure on the gate dielectric material layer and surrounding a portion of the gate dielectric material layer on the sidewalls of the semiconductor column. The gate stack structure includes from inside to outside a P-type work function layer, an N-type work function layer, and a gate.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: February 11, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Zhaoxu Shen, Duohui Bei
  • Patent number: 10483100
    Abstract: A TiON film forming method is provided. A cycle of forming a unit TiN film at a predetermined processing temperature by alternately supplying a Ti-containing gas and a nitriding gas into the processing chamber accommodating a target substrate and oxidizing the unit TiN film by supplying an oxidizing agent into the processing chamber is repeated multiple times. In an initial stage of the film formation, a cycle of repeating the alternate supply of the Ti-containing gas and the nitriding gas X1 times and supplying the oxidizing agent is repeated Y1 times. In a later stage of the film formation, a cycle of repeating the alternate supply of the Ti-containing gas and the nitriding gas X2 times and supplying the oxidizing agent is repeated Y2 times until a desired film thickness is obtained. The number of repetition X1 is set to be greater than the number of repetition X2.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: November 19, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Tadahiro Ishizaka, Masaki Koizumi, Masaki Sano, Seokhyoung Hong
  • Patent number: 10461192
    Abstract: A semiconductor device may include a substrate, a gate electrode disposed on the substrate, a gate insulation layer disposed on the substrate to cover the gate electrode, an active layer including an oxide semiconductor disposed on the gate insulation layer, an insulating interlayer disposed on the gate insulation layer to cover the active layer, a protection structure including a plurality of metal oxide layers disposed on the insulating interlayer, and a source electrode and a drain electrode disposed on the protection structure.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: October 29, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Je-Hun Lee, Eun-Hyun Kim, Sang-Won Shin, Eun-Young Lee
  • Patent number: 10453690
    Abstract: A semiconductor structure and a fabrication method are provided. The fabrication method includes providing a base substrate including a substrate and a plurality of discrete fins on the substrate; forming a support layer at least partially on sidewalls of the fins; ion implanting the fins through the support layer to form an ion doped region by an ion implantation process; removing the support layer to expose sidewalls of the fins.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: October 22, 2019
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Guo Bin Yu, Xiao Ping Xu
  • Patent number: 10428421
    Abstract: Methods are provided for selectively depositing a material on a first metal or metallic surface of a substrate relative to a second, dielectric surface of the substrate, or for selectively depositing metal oxides on a first metal oxide surface of a substrate relative to a second silicon oxide surface. The selectively deposited material can be, for example, a metal, metal oxide, metal nitride, metal silicide, metal carbide and/or dielectric material. In some embodiments a substrate comprising a first metal or metallic surface and a second dielectric surface is alternately and sequentially contacted with a first vapor-phase metal halide reactant and a second reactant. In some embodiments a substrate comprising a first metal oxide surface and a second silicon oxide surface is alternately and sequentially contacted with a first vapor phase metal fluoride or chloride reactant and water.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: October 1, 2019
    Assignee: ASM IP Holding B.V.
    Inventors: Suvi P. Haukka, Raija H. Matero, Elina Färm, Tom E. Blomberg
  • Patent number: 10418522
    Abstract: An optoelectronic device and method of manufacturing an optoelectronic device are disclosed. The optoelectronic device includes a substrate; a semiconductor comprising an n-type layer disposed on the substrate, a p-type layer disposed on the n-type layer, and an active layer disposed between the n-type layer and the p-type layer; a transition layer disposed on the substrate and located between the n-type layer and the substrate, the transition layer including an oxygenated IIIA-transition metal nitride; and a p-contact layer disposed on the p-type layer of the semiconductor.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: September 17, 2019
    Assignee: GOFORWARD TECHNOLOGY INC.
    Inventors: Yangang Xi, Jiguang Li
  • Patent number: 10411028
    Abstract: According to one embodiment, the source layer includes a semiconductor layer including a dopant. The columnar portions are disposed in an area between the separation portions. The columnar portions extend in the stacking direction through the stacked body and through the semiconductor layer. The columnar portions include a plurality of semiconductor bodies including sidewall portions contacting the semiconductor layer. The dopant diffusion prevention film is provided inside the semiconductor layer and separated from the columnar portions in an area between the columnar portions. The dopant diffusion prevention film is not provided inside the semiconductor layer in an area between the separation portion and the columnar portions.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: September 10, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Osamu Arisumi, Yusuke Kawano
  • Patent number: 10355098
    Abstract: The present invention provides a technology capable of removing impurities remaining in a thin film when the film is formed and modifying a characteristic of the thin film according to a change in impurity concentration. There is provided a method of manufacturing a semiconductor device including: (a) repetitively supplying a plurality of gases including elements constituting a film in temporally separated pulses (in non-simultaneous manner) to form the film on the substrate; and (b) exciting a modifying gas including a reducing gas and at least one of a nitriding gas and an oxidizing gas by plasma and supplying the modifying gas excited by plasma to modify the film.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: July 16, 2019
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Motomu Degai, Masanori Nakayama, Kazuhiro Harada, Masahito Kitamura
  • Patent number: 10262996
    Abstract: A third type of metal gate stack is provided above an isolation structure and between a replacement metal gate n-type field effect transistor and a replacement metal gate p-type field effect transistor. The third type of metal gate stack includes at least three different components. Notably, the third type of metal gate stack includes, as a first component, an n-type workfunction metal layer, as a second component, a p-type workfunction metal layer, and as a third component, a low resistance metal layer. In some embodiments, the uppermost surface of the first, second and third components of the third type of metal gate stack are all substantially coplanar with each other. In other embodiments, an uppermost surface of the third component of the third type of metal gate stack is non-substantially coplanar with an uppermost surface of both the first and second components of the third type of metal gate stack.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: April 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: Ramachandra Divakaruni, Sameer H. Jain, Viraj Y. Sardesai, Keith H. Tabakman
  • Patent number: 10153155
    Abstract: Techniques for forming an electronic device having a ferroelectric film are described. The electronic device comprises a ferroelectric material having one or more crystalline structures. The one or more crystalline structures may comprise hafnium, oxygen, and one or more dopants. The one or more dopants are distributed in the ferroelectric material to form a first layer, a second layer, and a third layer. The second layer is positioned between the first layer and the third layer. Distribution of one or more dopants within the first layer, the second layer, and the third layer may promote a crystalline structure to have an orthorhombic phase.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: December 11, 2018
    Assignee: UNIVERSITY OF FLORIDA RESEARCH FOUNDATION, INCORPORATED
    Inventors: Toshikazu Nishida, Mohammad Takmeel, Saeed Moghaddam, Patrick Lomenzo
  • Patent number: 10068773
    Abstract: An integrated circuit structure includes a plurality of flash memory cells forming a memory array, wherein each of the plurality of flash memory cells includes a select gate and a memory gate. A select gate electrode includes a first portion including polysilicon, wherein the first portion forms select gates of a column of the memory array, and a second portion electrically connected to the first portion, wherein the second portion includes a metal. A memory gate electrode has a portion forming memory gates of the column of the memory array.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: September 4, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Wei-Cheng Wu, Ya-Chen Kao, Chin-Yi Huang
  • Patent number: 10061173
    Abstract: Various embodiments provide a thin film transistor (TFT), a fabrication method thereof, and a display apparatus including the TFT. A carbon nanotube layer is formed over a substrate. The carbon nanotube layer includes a first plurality of carbon nanotubes. A plurality of gaps are formed through the carbon nanotube layer to provide a first patterned carbon nanotube layer. Carbon nanotube structures each including a second plurality of carbon nanotubes are formed in the plurality of gaps. The carbon nanotube structures have a carrier mobility different from the first patterned carbon nanotube layer, thereby forming an active layer for forming active structures of the thin-film transistor.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: August 28, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Shuai Zhang, Yu Cheng Chan
  • Patent number: 10056261
    Abstract: Provided are P type MOSFETs and methods for manufacturing the same. The method may include forming source/drain regions in a semiconductor substrate; forming an interfacial oxide layer on the semiconductor substrate; forming a high K gate dielectric layer on the interfacial oxide layer; forming a first metal gate layer on the high K gate dielectric layer; implanting dopants into the first metal gate layer through conformal doping; and performing annealing to change an effective work function of a gate stack including the first metal gate layer, the high K gate dielectric, and the interfacial oxide layer.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: August 21, 2018
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Qiuxia Xu, Yanbo Zhang, Hong Yang
  • Patent number: 10026887
    Abstract: In some aspects, the present disclosure provides methods of depositing a metal onto a nanomaterial which has been passivized with a self-assembled monolayer at a weakened point in the topography of the nanomaterial. In some embodiments, the weakened point is caused by the curvature of the topography. This method may be used to prepare electronic devices such as memory modules.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: July 17, 2018
    Assignee: BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM
    Inventors: John G. Ekerdt, Sonali N. Chopra
  • Patent number: 9984882
    Abstract: A method for fabricating a semiconductor structure includes providing a substrate, forming an interface layer on the substrate, and then performing a first annealing process on the interface layer under a nitrogen-containing environment to form a nitrogen-containing layer from a top portion of the interface layer. The first annealing process also deactivates non-bonded silicon ions and oxygen ions in the interface layer. The method further includes forming a high-k dielectric layer on the nitrogen-containing layer, and performing a second annealing process on the high-k dielectric layer to allow nitrogen ions in the nitrogen-containing layer to diffuse into the high-k dielectric layer to reduce a density of active oxygen vacancies in the high-k dielectric layer. Finally, the method includes forming a gate electrode layer on the high-k dielectric layer.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: May 29, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Yong Li, Zhongshan Hong
  • Patent number: 9972695
    Abstract: A method of forming a gate stack that includes treating a semiconductor substrate with a wet etch chemistry to clean a surface of the semiconductor substrate and form an oxide containing interfacial layer, and converting the oxide containing interfacial layer to a binary alloy oxide based interlayer using a plasma deposition sequence including alternating a metal gas precursor and a nitrogen and/or hydrogen containing plasma. The method of forming the gate stack may further include forming a high-k dielectric layer atop the binary alloy oxide based interlayer.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: May 15, 2018
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, ULVAC, INC.
    Inventors: Vijay Narayanan, Yohei Ogawa, John Rozen
  • Patent number: 9905703
    Abstract: To improve electric characteristics of a semiconductor device including an oxide semiconductor. Alternatively, to improve reliability of a semiconductor device including an oxide semiconductor. In a transistor including a first oxide film, an oxide semiconductor film, a pair of electrodes in contact with the oxide semiconductor film, and a second oxide film in contact with the oxide semiconductor film and the pair of electrodes, oxygen is added to the first oxide film and the second oxide film in contact with the oxide semiconductor film and the pair of electrodes, so that oxygen vacancies are reduced. The oxygen is diffused to the oxide semiconductor film by heat treatment or the like; thus, oxygen vacancies in the oxide semiconductor film are reduced.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: February 27, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9899270
    Abstract: There is disclosed a method for manufacturing a semiconductor device comprising two opposite types of MOSFETs formed on one semiconductor substrate, the method comprising: forming a portion of the MOSFET on the semiconductor substrate, said portion of said MOSFET comprising source/drains regions located in the semiconductor substrate, a dummy gate stack located between the source/drain region and above the semiconductor substrate and a gate spacer surrounding the dummy gate stack; removing the dummy gate stack of said MOSFET to form a gate opening which exposes the surface of the semiconductor substrate; forming an interfacial oxide layer on the exposed surface of the semiconductor structure; forming a high-K gate dielectric on the interfacial oxide layer within the gate opening; forming a first metal gate layer on the high-K gate dielectric; implanting doping ions in the first metal gate layer; forming a second metal gate layer on the first metal gate layer to fill up the gate opening; and annealing to diffu
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: February 20, 2018
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Qiuxia Xu, Huilong Zhu, Gaobo Xu, Huajie Zhou, Qingqing Liang, Dapeng Chen, Chao Zhao
  • Patent number: 9892922
    Abstract: A method of fabricating an integrated circuit includes forming a plurality of polysilicon gate electrode structures over a plurality of fin-shaped channel structures. A portion of the plurality of polysilicon gate electrode structures may then be removed to expose a surface region of a fin-shaped channel structure in the plurality of fin-shaped channel structures. The remaining portion of the polysilicon gate electrode structures may form a plurality of polysilicon transistors. A layer of high-k dielectric material is deposited on the exposed surface region of the fin-shaped channel structure. A metal layer may be deposited over the high-k dielectric material to form at least one high-k metal gate transistor over the fin-shaped channel structure.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: February 13, 2018
    Assignee: Altera Corporation
    Inventors: Ning Cheng, Peter Smeys
  • Patent number: 9876083
    Abstract: Semiconductor devices, FinFET devices and methods of forming the same are disclosed. One of the semiconductor devices includes a substrate, a gate over the substrate and a gate dielectric layer between the gate and the substrate. The gate dielectric layer includes an oxide-inhibiting layer having a dielectric constant greater than about 8 and being in an amorphous state.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: January 23, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Liang-Chen Chi, Chia-Ming Tsai, Chin-Kun Wang, Wei-Cheng Wang, Miin-Jang Chen
  • Patent number: 9853030
    Abstract: Various embodiments provide semiconductor devices and methods for forming the same. A first fin and a second fin are formed on a semiconductor substrate. A first dielectric layer is formed on the semiconductor substrate and has a top surface lower than a top surface of both of the first fin and the second fin. A gate structure is formed on the first dielectric layer and covering across a first portion of each of the first fin and the second fin. A second portion of the first fin on both sides of the gate structure is removed, forming a first recess. A first semiconductor layer is formed in the first recess. A second dielectric layer is formed on the first dielectric layer and the first semiconductor layer, and exposes a top surface of the second fin. A second semiconductor layer is formed on the exposed top surface of the second fin.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: December 26, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Mieno Fumitake, Jianhua Ju
  • Patent number: 9812533
    Abstract: One object of one embodiment of the present invention is to provide a highly reliable semiconductor device including an oxide semiconductor, which has stable electrical characteristics. In a method for manufacturing a semiconductor device, a first insulating film is formed; source and drain electrodes and an oxide semiconductor film electrically connected to the source and drain electrodes are formed over the first insulating film; heat treatment is performed on the oxide semiconductor film so that a hydrogen atom in the oxide semiconductor film is removed; oxygen doping treatment is performed on the oxide semiconductor film, so that an oxygen atom is supplied into the oxide semiconductor film; a second insulating film is formed over the oxide semiconductor film; and a gate electrode is formed over the second insulating film so as to overlap with the oxide semiconductor film.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: November 7, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9698021
    Abstract: In a method of forming a layer, a substrate is loaded into a chamber and placed at a home position that is a first relative angular position. A process cycle is performed a number of times while the substrate is at the home position. The cycle includes directing source gas onto the substrate at a first location adjacent the periphery of the substrate, purging the chamber, directing reaction gas onto the substrate from the first location, and purging the chamber. The cycle is performed another number of times while the substrate is at another relative angular position, i.e., at a position rotated about its general center relative from the home position.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: July 4, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-Joo Lee, Weon-Hong Kim, Moon-Kyun Song, Dong-Su Yoo, Soo-Jung Choi
  • Patent number: 9691620
    Abstract: A semiconductor structure includes: a germanium layer 30; and an insulating film that has a film 32 that includes a germanium oxide and is formed on the germanium layer and a high dielectric oxide film 34 that is formed on the film including the germanium oxide and has a dielectric constant higher than that of a silicon oxide, wherein: an EOT of the insulating film is 2 nm or less; and on a presumption that an Au acting as a metal film is formed on the insulating film, a leak current density is 10?5×EOT+4 A/cm2 or less in a case where a voltage of the metal film with respect to the germanium layer is applied from a flat band voltage to an accumulation region side by 1 V.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: June 27, 2017
    Assignee: Japan Science and Technology Agency
    Inventors: Akira Toriumi, Choong-hyun Lee
  • Patent number: 9666449
    Abstract: An embodiment of a method of forming a control gate includes forming a conductor having a concentration of germanium that varies with a thickness of the conductor, and removing portions of the conductor at a variable rate that is governed, at least in part, by the concentration of the germanium.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: May 30, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Randy J. Koval
  • Patent number: 9660055
    Abstract: A method of manufacturing a semiconductor device includes providing dielectric stripe structures extending from a first surface into a semiconductor substrate between semiconductor fins. A first mask is provided that covers a first area including first stripe sections of the dielectric stripe structures and first fin sections of the semiconductor fins. The first mask exposes a second area including second stripe and second fin sections. A channel/body zone is formed in the second fin sections by introducing impurities, wherein the first mask is used as an implant mask. Using an etch mask that is based on the first mask, recess grooves are formed at least in the second stripe sections.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: May 23, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Martin Poelzl, Till Schloesser, Andreas Meiser
  • Patent number: 9589977
    Abstract: The invention provides a non-volatile memory and a fabricating method thereof. The non-volatile memory includes a substrate, an embedded-type charge storage transistor, and a selection transistor. The substrate has an opening. The embedded-type charge storage transistor is disposed in the substrate. The embedded-type charge storage transistor includes a charge storage structure and a conductive layer. The charge storage structure is disposed on the substrate in the opening. The conductive layer is disposed on the charge storage structure and fills the opening. The selection transistor is disposed on the substrate at one side of the embedded-type charge storage transistor, wherein the selection transistor includes a metal gate structure. The non-volatile memory has excellent charge storage capacity.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: March 7, 2017
    Assignee: United Microelectronics Corp.
    Inventors: Ko-Chi Chen, Shen-De Wang
  • Patent number: 9577112
    Abstract: To improve electric characteristics of a semiconductor device including an oxide semiconductor. Alternatively, to improve reliability of a semiconductor device including an oxide semiconductor. In a transistor including a first oxide film, an oxide semiconductor film, a pair of electrodes in contact with the oxide semiconductor film, and a second oxide film in contact with the oxide semiconductor film and the pair of electrodes, oxygen is added to the first oxide film and the second oxide film in contact with the oxide semiconductor film and the pair of electrodes, so that oxygen vacancies are reduced. The oxygen is diffused to the oxide semiconductor film by heat treatment or the like; thus, oxygen vacancies in the oxide semiconductor film are reduced.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: February 21, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9570569
    Abstract: A complementary metal-oxide semiconductor (CMOS) device and a method of fabricating a CMOS device are described. The method includes forming an interfacial layer in a trench on a substrate in both a p-channel field effect transistor (pFET) area of the CMOS device and an n-channel FET (nFET) area of the CMOS device, depositing a high-k dielectric on the interfacial layer in both the pFET area and the nFET area, selectively forming a first metal layer on the high-k dielectric in only the pFET area, and depositing a second metal layer on the first metal layer in the pFET area and on the high-k dielectric in the nFET area. The method also includes performing an anneal that increases a thickness of the interfacial layer in only the pFET area.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: February 14, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Hemanth Jagannathan, Barry P. Linder
  • Patent number: 9536733
    Abstract: Embodiments of the present invention provide hydrogen-free dielectric films and methods of fabrication. A hydrogen-free precursor, such as tetraisocyanatosilane, and hydrogen-free reactants, such as nitrogen, oxygen (O2/O3) and nitrous oxide are used with chemical vapor deposition processes (PECVD, thermal CVD, SACVD, HDP CVD, and PE and Thermal ALD) to create hydrogen-free dielectric films. In some embodiments, there are multilayer dielectric films with sublayers of various materials such as silicon oxide, silicon nitride, and silicon oxynitride. In embodiments, the hydrogen-free reactants may include Tetra Isocyanato Silane, along with a hydrogen-free gas including, but not limited to, N2, O2, O3, N2O, CO2, CO and a combination thereof of these H-Free gases. Plasma may be used to enhance the reaction between the TICS and the other H-free gasses. The plasma may be controlled during film deposition to achieve variable density within each sublayer of the films.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: January 3, 2017
    Assignee: International Business Machines Corporation
    Inventors: Donald Francis Canaperi, Alfred Grill, Sanjay C. Mehta, Son Van Nguyen, Deepika Priyadarshini, Hosadurga Shobha, Matthew T. Shoudy
  • Patent number: 9530654
    Abstract: Fin height control techniques for FINFET fabrication are disclosed. The technique includes a method for controlling the height of plurality of fin structures to achieve uniform height thereof relative to a top surface of isolation material located between fin structures on a semiconductor substrate. The isolation material located between fin structures may be selectively removed after treatment to increase its mechanical strength such as by, for example, annealing and curing. A sacrificial material may be deposited over the isolation material between the fin structures in a substantially uniform thickness. The top portion of the fin structures may be selectively removed to achieve a uniform planar surface over the fin structures and sacrificial material. The sacrificial material may then be selectively removed to achieve a uniform fin height relative to the isolation material.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: December 27, 2016
    Assignee: GLOBALFOUNDARIES INC.
    Inventor: Nicholas V. Licausi
  • Patent number: 9530683
    Abstract: An embodiment includes forming an isolation region between first and second active regions in a semiconductor, forming an opening between the first and second active regions by removing a portion of the isolation region, and forming a dielectric plug within the opening so that the dielectric plug is between the first and second active regions and so that a portion of the dielectric plug extends below upper surfaces of the first and second active regions. The dielectric plug may be formed of a dielectric material having a lower removal rate than a dielectric material of the isolation region for a particular isotropic removal chemistry.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: December 27, 2016
    Assignee: Micron Technology, Inc.
    Inventors: John Hopkins, James Matthew, Jie Sun, Gordon Haller
  • Patent number: 9524982
    Abstract: According to one embodiment, the semiconductor body of the first portion includes a first semiconductor part and a second semiconductor part. The first semiconductor part extends in the stacking direction. The second semiconductor part is provided between the first semiconductor part and the first electrode layer, and has an end located closer to the first electrode layer side than the first semiconductor part. The first insulating film of the second portion includes a first insulating part and a second insulating part. The first insulating part extends in the stacking direction. The second insulating part is provided between the first insulating part and the second electrode layer, and has an end located closer to the second electrode layer side than the first insulating part.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: December 20, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takeshi Kamigaichi
  • Patent number: 9520403
    Abstract: A semiconductor memory device includes: a plurality of first channel columns including a plurality of first channel layers that are arranged in a direction and offset by their centers; a plurality of second channel columns alternately arranged with the plurality of first channel columns and having a plurality of second channel layers that are arranged in the direction and offset by their centers; first insulating layers and first conductive layers alternately stacked to surround the first channel layers; second insulating layers and second conductive layers stacked to surround the second channel layers; and spacers placed between the first channel columns and the second channel columns and interposed between the first conductive layers and the second conductive layers.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: December 13, 2016
    Assignee: SK HYNIX INC.
    Inventors: Jung Ryul Ahn, Yun Kyoung Lee
  • Patent number: 9508736
    Abstract: A three-dimensional charge trap semiconductor device is constructed with alternating insulating and gate layers stacked over a substrate. During the manufacturing process, a channel hole is formed in the stack and the gate layers are recessed from the channel hole. Using the recessed topography of the gate layers, a charge trap layer can be deposited on the sidewalls of the channel hole and etched, leaving individual discrete charge trap layer sections in each recess. Filling the channel hole with channel material effectively provides a three-dimensional semiconductor device having individual charge trap layer sections for each memory cell.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: November 29, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventors: Chun Chen, Kuo-Tung Chang, Shenqing Fang
  • Patent number: 9496413
    Abstract: Reducing hydrogen concentration in a channel formation region of an oxide semiconductor is important in stabilizing threshold voltage of a transistor including an oxide semiconductor and improving reliability. Hence, hydrogen is attracted from the oxide semiconductor and trapped in a region of an insulating film which overlaps with a source region and a drain region of the oxide semiconductor. Impurities such as argon, nitrogen, carbon, phosphorus, or boron are added to the region of the insulating film which overlaps with the source region and the drain region of the oxide semiconductor, thereby generating a defect. Hydrogen in the oxide semiconductor is attracted to the defect in the insulating film. The defect in the insulating film is stabilized by the presence of hydrogen.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: November 15, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masashi Tsubuku, Yusuke Nonaka, Noritaka Ishihara, Masashi Oota, Hideyuki Kishida
  • Patent number: 9472773
    Abstract: A device structure including a gate structure containing a first layer of carbon nanotubes and a second layer of carbon nanotubes. The first and the second layers are stacked vertically. The first and the second layers have carbon nanotubes which have substantially homogeneous electric characteristics within each layer. The carbon nanotubes in the first layer have different electric characteristics than the carbon nanotubes in the second layer, so that the device structure exhibits a multiple threshold behavior when coupled to a voltage source. The disclosure also includes a method for fabricating a multithreshold device structure.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: October 18, 2016
    Assignee: International Business Machines Corporation
    Inventors: Sami Rosenblatt, Rasit Onur Topaloglu
  • Patent number: 9466609
    Abstract: The device includes plural control gates stacked on a substrate, plural first channels, configured to penetrate the control gates, and plural memory layer patterns, each located between the control gate and the first channel, configured to respectively surround the first channel, wherein the memory layer patterns are isolated from one another.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: October 11, 2016
    Assignee: SK Hynix Inc.
    Inventors: Min Soo Kim, Dong Sun Sheen, Young Jin Lee, Jin Hae Choi, Joo Hee Han, Sung Jin Whang
  • Patent number: 9455203
    Abstract: A replacement metal gate process in which a high-k dielectric is applied. The high-k dielectric may be doped with lanthanum in an NMOS region or aluminum in a PMOS region. A dummy gate structure may be formed over the high-k dielectric and etched to form an opening over the NMOS region and an opening over the PMOS region. Thereafter, first work function metals are deposited in the NMOS opening and second work function metals are applied in the PMOS openings. A suitable gate electrode material may then fill the remainder of the NMOS and PMOS openings.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: September 27, 2016
    Assignees: International Business Machines Corporation, Global Foundries Inc.
    Inventors: Takashi Ando, Changhwan Choi, Kisik Choi, Vijay Narayanan