Gate Insulator Structure Constructed Of Diverse Dielectrics (e.g., Mnos, Etc.) Or Of Nonsilicon Compound Patents (Class 438/287)
  • Patent number: 10428421
    Abstract: Methods are provided for selectively depositing a material on a first metal or metallic surface of a substrate relative to a second, dielectric surface of the substrate, or for selectively depositing metal oxides on a first metal oxide surface of a substrate relative to a second silicon oxide surface. The selectively deposited material can be, for example, a metal, metal oxide, metal nitride, metal silicide, metal carbide and/or dielectric material. In some embodiments a substrate comprising a first metal or metallic surface and a second dielectric surface is alternately and sequentially contacted with a first vapor-phase metal halide reactant and a second reactant. In some embodiments a substrate comprising a first metal oxide surface and a second silicon oxide surface is alternately and sequentially contacted with a first vapor phase metal fluoride or chloride reactant and water.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: October 1, 2019
    Assignee: ASM IP Holding B.V.
    Inventors: Suvi P. Haukka, Raija H. Matero, Elina Färm, Tom E. Blomberg
  • Patent number: 10418522
    Abstract: An optoelectronic device and method of manufacturing an optoelectronic device are disclosed. The optoelectronic device includes a substrate; a semiconductor comprising an n-type layer disposed on the substrate, a p-type layer disposed on the n-type layer, and an active layer disposed between the n-type layer and the p-type layer; a transition layer disposed on the substrate and located between the n-type layer and the substrate, the transition layer including an oxygenated IIIA-transition metal nitride; and a p-contact layer disposed on the p-type layer of the semiconductor.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: September 17, 2019
    Assignee: GOFORWARD TECHNOLOGY INC.
    Inventors: Yangang Xi, Jiguang Li
  • Patent number: 10411028
    Abstract: According to one embodiment, the source layer includes a semiconductor layer including a dopant. The columnar portions are disposed in an area between the separation portions. The columnar portions extend in the stacking direction through the stacked body and through the semiconductor layer. The columnar portions include a plurality of semiconductor bodies including sidewall portions contacting the semiconductor layer. The dopant diffusion prevention film is provided inside the semiconductor layer and separated from the columnar portions in an area between the columnar portions. The dopant diffusion prevention film is not provided inside the semiconductor layer in an area between the separation portion and the columnar portions.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: September 10, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Osamu Arisumi, Yusuke Kawano
  • Patent number: 10355098
    Abstract: The present invention provides a technology capable of removing impurities remaining in a thin film when the film is formed and modifying a characteristic of the thin film according to a change in impurity concentration. There is provided a method of manufacturing a semiconductor device including: (a) repetitively supplying a plurality of gases including elements constituting a film in temporally separated pulses (in non-simultaneous manner) to form the film on the substrate; and (b) exciting a modifying gas including a reducing gas and at least one of a nitriding gas and an oxidizing gas by plasma and supplying the modifying gas excited by plasma to modify the film.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: July 16, 2019
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Motomu Degai, Masanori Nakayama, Kazuhiro Harada, Masahito Kitamura
  • Patent number: 10262996
    Abstract: A third type of metal gate stack is provided above an isolation structure and between a replacement metal gate n-type field effect transistor and a replacement metal gate p-type field effect transistor. The third type of metal gate stack includes at least three different components. Notably, the third type of metal gate stack includes, as a first component, an n-type workfunction metal layer, as a second component, a p-type workfunction metal layer, and as a third component, a low resistance metal layer. In some embodiments, the uppermost surface of the first, second and third components of the third type of metal gate stack are all substantially coplanar with each other. In other embodiments, an uppermost surface of the third component of the third type of metal gate stack is non-substantially coplanar with an uppermost surface of both the first and second components of the third type of metal gate stack.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: April 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: Ramachandra Divakaruni, Sameer H. Jain, Viraj Y. Sardesai, Keith H. Tabakman
  • Patent number: 10153155
    Abstract: Techniques for forming an electronic device having a ferroelectric film are described. The electronic device comprises a ferroelectric material having one or more crystalline structures. The one or more crystalline structures may comprise hafnium, oxygen, and one or more dopants. The one or more dopants are distributed in the ferroelectric material to form a first layer, a second layer, and a third layer. The second layer is positioned between the first layer and the third layer. Distribution of one or more dopants within the first layer, the second layer, and the third layer may promote a crystalline structure to have an orthorhombic phase.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: December 11, 2018
    Assignee: UNIVERSITY OF FLORIDA RESEARCH FOUNDATION, INCORPORATED
    Inventors: Toshikazu Nishida, Mohammad Takmeel, Saeed Moghaddam, Patrick Lomenzo
  • Patent number: 10068773
    Abstract: An integrated circuit structure includes a plurality of flash memory cells forming a memory array, wherein each of the plurality of flash memory cells includes a select gate and a memory gate. A select gate electrode includes a first portion including polysilicon, wherein the first portion forms select gates of a column of the memory array, and a second portion electrically connected to the first portion, wherein the second portion includes a metal. A memory gate electrode has a portion forming memory gates of the column of the memory array.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: September 4, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Wei-Cheng Wu, Ya-Chen Kao, Chin-Yi Huang
  • Patent number: 10061173
    Abstract: Various embodiments provide a thin film transistor (TFT), a fabrication method thereof, and a display apparatus including the TFT. A carbon nanotube layer is formed over a substrate. The carbon nanotube layer includes a first plurality of carbon nanotubes. A plurality of gaps are formed through the carbon nanotube layer to provide a first patterned carbon nanotube layer. Carbon nanotube structures each including a second plurality of carbon nanotubes are formed in the plurality of gaps. The carbon nanotube structures have a carrier mobility different from the first patterned carbon nanotube layer, thereby forming an active layer for forming active structures of the thin-film transistor.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: August 28, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Shuai Zhang, Yu Cheng Chan
  • Patent number: 10056261
    Abstract: Provided are P type MOSFETs and methods for manufacturing the same. The method may include forming source/drain regions in a semiconductor substrate; forming an interfacial oxide layer on the semiconductor substrate; forming a high K gate dielectric layer on the interfacial oxide layer; forming a first metal gate layer on the high K gate dielectric layer; implanting dopants into the first metal gate layer through conformal doping; and performing annealing to change an effective work function of a gate stack including the first metal gate layer, the high K gate dielectric, and the interfacial oxide layer.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: August 21, 2018
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Qiuxia Xu, Yanbo Zhang, Hong Yang
  • Patent number: 10026887
    Abstract: In some aspects, the present disclosure provides methods of depositing a metal onto a nanomaterial which has been passivized with a self-assembled monolayer at a weakened point in the topography of the nanomaterial. In some embodiments, the weakened point is caused by the curvature of the topography. This method may be used to prepare electronic devices such as memory modules.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: July 17, 2018
    Assignee: BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM
    Inventors: John G. Ekerdt, Sonali N. Chopra
  • Patent number: 9984882
    Abstract: A method for fabricating a semiconductor structure includes providing a substrate, forming an interface layer on the substrate, and then performing a first annealing process on the interface layer under a nitrogen-containing environment to form a nitrogen-containing layer from a top portion of the interface layer. The first annealing process also deactivates non-bonded silicon ions and oxygen ions in the interface layer. The method further includes forming a high-k dielectric layer on the nitrogen-containing layer, and performing a second annealing process on the high-k dielectric layer to allow nitrogen ions in the nitrogen-containing layer to diffuse into the high-k dielectric layer to reduce a density of active oxygen vacancies in the high-k dielectric layer. Finally, the method includes forming a gate electrode layer on the high-k dielectric layer.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: May 29, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Yong Li, Zhongshan Hong
  • Patent number: 9972695
    Abstract: A method of forming a gate stack that includes treating a semiconductor substrate with a wet etch chemistry to clean a surface of the semiconductor substrate and form an oxide containing interfacial layer, and converting the oxide containing interfacial layer to a binary alloy oxide based interlayer using a plasma deposition sequence including alternating a metal gas precursor and a nitrogen and/or hydrogen containing plasma. The method of forming the gate stack may further include forming a high-k dielectric layer atop the binary alloy oxide based interlayer.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: May 15, 2018
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, ULVAC, INC.
    Inventors: Vijay Narayanan, Yohei Ogawa, John Rozen
  • Patent number: 9905703
    Abstract: To improve electric characteristics of a semiconductor device including an oxide semiconductor. Alternatively, to improve reliability of a semiconductor device including an oxide semiconductor. In a transistor including a first oxide film, an oxide semiconductor film, a pair of electrodes in contact with the oxide semiconductor film, and a second oxide film in contact with the oxide semiconductor film and the pair of electrodes, oxygen is added to the first oxide film and the second oxide film in contact with the oxide semiconductor film and the pair of electrodes, so that oxygen vacancies are reduced. The oxygen is diffused to the oxide semiconductor film by heat treatment or the like; thus, oxygen vacancies in the oxide semiconductor film are reduced.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: February 27, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9899270
    Abstract: There is disclosed a method for manufacturing a semiconductor device comprising two opposite types of MOSFETs formed on one semiconductor substrate, the method comprising: forming a portion of the MOSFET on the semiconductor substrate, said portion of said MOSFET comprising source/drains regions located in the semiconductor substrate, a dummy gate stack located between the source/drain region and above the semiconductor substrate and a gate spacer surrounding the dummy gate stack; removing the dummy gate stack of said MOSFET to form a gate opening which exposes the surface of the semiconductor substrate; forming an interfacial oxide layer on the exposed surface of the semiconductor structure; forming a high-K gate dielectric on the interfacial oxide layer within the gate opening; forming a first metal gate layer on the high-K gate dielectric; implanting doping ions in the first metal gate layer; forming a second metal gate layer on the first metal gate layer to fill up the gate opening; and annealing to diffu
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: February 20, 2018
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Qiuxia Xu, Huilong Zhu, Gaobo Xu, Huajie Zhou, Qingqing Liang, Dapeng Chen, Chao Zhao
  • Patent number: 9892922
    Abstract: A method of fabricating an integrated circuit includes forming a plurality of polysilicon gate electrode structures over a plurality of fin-shaped channel structures. A portion of the plurality of polysilicon gate electrode structures may then be removed to expose a surface region of a fin-shaped channel structure in the plurality of fin-shaped channel structures. The remaining portion of the polysilicon gate electrode structures may form a plurality of polysilicon transistors. A layer of high-k dielectric material is deposited on the exposed surface region of the fin-shaped channel structure. A metal layer may be deposited over the high-k dielectric material to form at least one high-k metal gate transistor over the fin-shaped channel structure.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: February 13, 2018
    Assignee: Altera Corporation
    Inventors: Ning Cheng, Peter Smeys
  • Patent number: 9876083
    Abstract: Semiconductor devices, FinFET devices and methods of forming the same are disclosed. One of the semiconductor devices includes a substrate, a gate over the substrate and a gate dielectric layer between the gate and the substrate. The gate dielectric layer includes an oxide-inhibiting layer having a dielectric constant greater than about 8 and being in an amorphous state.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: January 23, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Liang-Chen Chi, Chia-Ming Tsai, Chin-Kun Wang, Wei-Cheng Wang, Miin-Jang Chen
  • Patent number: 9853030
    Abstract: Various embodiments provide semiconductor devices and methods for forming the same. A first fin and a second fin are formed on a semiconductor substrate. A first dielectric layer is formed on the semiconductor substrate and has a top surface lower than a top surface of both of the first fin and the second fin. A gate structure is formed on the first dielectric layer and covering across a first portion of each of the first fin and the second fin. A second portion of the first fin on both sides of the gate structure is removed, forming a first recess. A first semiconductor layer is formed in the first recess. A second dielectric layer is formed on the first dielectric layer and the first semiconductor layer, and exposes a top surface of the second fin. A second semiconductor layer is formed on the exposed top surface of the second fin.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: December 26, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Mieno Fumitake, Jianhua Ju
  • Patent number: 9812533
    Abstract: One object of one embodiment of the present invention is to provide a highly reliable semiconductor device including an oxide semiconductor, which has stable electrical characteristics. In a method for manufacturing a semiconductor device, a first insulating film is formed; source and drain electrodes and an oxide semiconductor film electrically connected to the source and drain electrodes are formed over the first insulating film; heat treatment is performed on the oxide semiconductor film so that a hydrogen atom in the oxide semiconductor film is removed; oxygen doping treatment is performed on the oxide semiconductor film, so that an oxygen atom is supplied into the oxide semiconductor film; a second insulating film is formed over the oxide semiconductor film; and a gate electrode is formed over the second insulating film so as to overlap with the oxide semiconductor film.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: November 7, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9698021
    Abstract: In a method of forming a layer, a substrate is loaded into a chamber and placed at a home position that is a first relative angular position. A process cycle is performed a number of times while the substrate is at the home position. The cycle includes directing source gas onto the substrate at a first location adjacent the periphery of the substrate, purging the chamber, directing reaction gas onto the substrate from the first location, and purging the chamber. The cycle is performed another number of times while the substrate is at another relative angular position, i.e., at a position rotated about its general center relative from the home position.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: July 4, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-Joo Lee, Weon-Hong Kim, Moon-Kyun Song, Dong-Su Yoo, Soo-Jung Choi
  • Patent number: 9691620
    Abstract: A semiconductor structure includes: a germanium layer 30; and an insulating film that has a film 32 that includes a germanium oxide and is formed on the germanium layer and a high dielectric oxide film 34 that is formed on the film including the germanium oxide and has a dielectric constant higher than that of a silicon oxide, wherein: an EOT of the insulating film is 2 nm or less; and on a presumption that an Au acting as a metal film is formed on the insulating film, a leak current density is 10?5×EOT+4 A/cm2 or less in a case where a voltage of the metal film with respect to the germanium layer is applied from a flat band voltage to an accumulation region side by 1 V.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: June 27, 2017
    Assignee: Japan Science and Technology Agency
    Inventors: Akira Toriumi, Choong-hyun Lee
  • Patent number: 9666449
    Abstract: An embodiment of a method of forming a control gate includes forming a conductor having a concentration of germanium that varies with a thickness of the conductor, and removing portions of the conductor at a variable rate that is governed, at least in part, by the concentration of the germanium.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: May 30, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Randy J. Koval
  • Patent number: 9660055
    Abstract: A method of manufacturing a semiconductor device includes providing dielectric stripe structures extending from a first surface into a semiconductor substrate between semiconductor fins. A first mask is provided that covers a first area including first stripe sections of the dielectric stripe structures and first fin sections of the semiconductor fins. The first mask exposes a second area including second stripe and second fin sections. A channel/body zone is formed in the second fin sections by introducing impurities, wherein the first mask is used as an implant mask. Using an etch mask that is based on the first mask, recess grooves are formed at least in the second stripe sections.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: May 23, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Martin Poelzl, Till Schloesser, Andreas Meiser
  • Patent number: 9589977
    Abstract: The invention provides a non-volatile memory and a fabricating method thereof. The non-volatile memory includes a substrate, an embedded-type charge storage transistor, and a selection transistor. The substrate has an opening. The embedded-type charge storage transistor is disposed in the substrate. The embedded-type charge storage transistor includes a charge storage structure and a conductive layer. The charge storage structure is disposed on the substrate in the opening. The conductive layer is disposed on the charge storage structure and fills the opening. The selection transistor is disposed on the substrate at one side of the embedded-type charge storage transistor, wherein the selection transistor includes a metal gate structure. The non-volatile memory has excellent charge storage capacity.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: March 7, 2017
    Assignee: United Microelectronics Corp.
    Inventors: Ko-Chi Chen, Shen-De Wang
  • Patent number: 9577112
    Abstract: To improve electric characteristics of a semiconductor device including an oxide semiconductor. Alternatively, to improve reliability of a semiconductor device including an oxide semiconductor. In a transistor including a first oxide film, an oxide semiconductor film, a pair of electrodes in contact with the oxide semiconductor film, and a second oxide film in contact with the oxide semiconductor film and the pair of electrodes, oxygen is added to the first oxide film and the second oxide film in contact with the oxide semiconductor film and the pair of electrodes, so that oxygen vacancies are reduced. The oxygen is diffused to the oxide semiconductor film by heat treatment or the like; thus, oxygen vacancies in the oxide semiconductor film are reduced.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: February 21, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9570569
    Abstract: A complementary metal-oxide semiconductor (CMOS) device and a method of fabricating a CMOS device are described. The method includes forming an interfacial layer in a trench on a substrate in both a p-channel field effect transistor (pFET) area of the CMOS device and an n-channel FET (nFET) area of the CMOS device, depositing a high-k dielectric on the interfacial layer in both the pFET area and the nFET area, selectively forming a first metal layer on the high-k dielectric in only the pFET area, and depositing a second metal layer on the first metal layer in the pFET area and on the high-k dielectric in the nFET area. The method also includes performing an anneal that increases a thickness of the interfacial layer in only the pFET area.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: February 14, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Hemanth Jagannathan, Barry P. Linder
  • Patent number: 9536733
    Abstract: Embodiments of the present invention provide hydrogen-free dielectric films and methods of fabrication. A hydrogen-free precursor, such as tetraisocyanatosilane, and hydrogen-free reactants, such as nitrogen, oxygen (O2/O3) and nitrous oxide are used with chemical vapor deposition processes (PECVD, thermal CVD, SACVD, HDP CVD, and PE and Thermal ALD) to create hydrogen-free dielectric films. In some embodiments, there are multilayer dielectric films with sublayers of various materials such as silicon oxide, silicon nitride, and silicon oxynitride. In embodiments, the hydrogen-free reactants may include Tetra Isocyanato Silane, along with a hydrogen-free gas including, but not limited to, N2, O2, O3, N2O, CO2, CO and a combination thereof of these H-Free gases. Plasma may be used to enhance the reaction between the TICS and the other H-free gasses. The plasma may be controlled during film deposition to achieve variable density within each sublayer of the films.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: January 3, 2017
    Assignee: International Business Machines Corporation
    Inventors: Donald Francis Canaperi, Alfred Grill, Sanjay C. Mehta, Son Van Nguyen, Deepika Priyadarshini, Hosadurga Shobha, Matthew T. Shoudy
  • Patent number: 9530683
    Abstract: An embodiment includes forming an isolation region between first and second active regions in a semiconductor, forming an opening between the first and second active regions by removing a portion of the isolation region, and forming a dielectric plug within the opening so that the dielectric plug is between the first and second active regions and so that a portion of the dielectric plug extends below upper surfaces of the first and second active regions. The dielectric plug may be formed of a dielectric material having a lower removal rate than a dielectric material of the isolation region for a particular isotropic removal chemistry.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: December 27, 2016
    Assignee: Micron Technology, Inc.
    Inventors: John Hopkins, James Matthew, Jie Sun, Gordon Haller
  • Patent number: 9530654
    Abstract: Fin height control techniques for FINFET fabrication are disclosed. The technique includes a method for controlling the height of plurality of fin structures to achieve uniform height thereof relative to a top surface of isolation material located between fin structures on a semiconductor substrate. The isolation material located between fin structures may be selectively removed after treatment to increase its mechanical strength such as by, for example, annealing and curing. A sacrificial material may be deposited over the isolation material between the fin structures in a substantially uniform thickness. The top portion of the fin structures may be selectively removed to achieve a uniform planar surface over the fin structures and sacrificial material. The sacrificial material may then be selectively removed to achieve a uniform fin height relative to the isolation material.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: December 27, 2016
    Assignee: GLOBALFOUNDARIES INC.
    Inventor: Nicholas V. Licausi
  • Patent number: 9524982
    Abstract: According to one embodiment, the semiconductor body of the first portion includes a first semiconductor part and a second semiconductor part. The first semiconductor part extends in the stacking direction. The second semiconductor part is provided between the first semiconductor part and the first electrode layer, and has an end located closer to the first electrode layer side than the first semiconductor part. The first insulating film of the second portion includes a first insulating part and a second insulating part. The first insulating part extends in the stacking direction. The second insulating part is provided between the first insulating part and the second electrode layer, and has an end located closer to the second electrode layer side than the first insulating part.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: December 20, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takeshi Kamigaichi
  • Patent number: 9520403
    Abstract: A semiconductor memory device includes: a plurality of first channel columns including a plurality of first channel layers that are arranged in a direction and offset by their centers; a plurality of second channel columns alternately arranged with the plurality of first channel columns and having a plurality of second channel layers that are arranged in the direction and offset by their centers; first insulating layers and first conductive layers alternately stacked to surround the first channel layers; second insulating layers and second conductive layers stacked to surround the second channel layers; and spacers placed between the first channel columns and the second channel columns and interposed between the first conductive layers and the second conductive layers.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: December 13, 2016
    Assignee: SK HYNIX INC.
    Inventors: Jung Ryul Ahn, Yun Kyoung Lee
  • Patent number: 9508736
    Abstract: A three-dimensional charge trap semiconductor device is constructed with alternating insulating and gate layers stacked over a substrate. During the manufacturing process, a channel hole is formed in the stack and the gate layers are recessed from the channel hole. Using the recessed topography of the gate layers, a charge trap layer can be deposited on the sidewalls of the channel hole and etched, leaving individual discrete charge trap layer sections in each recess. Filling the channel hole with channel material effectively provides a three-dimensional semiconductor device having individual charge trap layer sections for each memory cell.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: November 29, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventors: Chun Chen, Kuo-Tung Chang, Shenqing Fang
  • Patent number: 9496413
    Abstract: Reducing hydrogen concentration in a channel formation region of an oxide semiconductor is important in stabilizing threshold voltage of a transistor including an oxide semiconductor and improving reliability. Hence, hydrogen is attracted from the oxide semiconductor and trapped in a region of an insulating film which overlaps with a source region and a drain region of the oxide semiconductor. Impurities such as argon, nitrogen, carbon, phosphorus, or boron are added to the region of the insulating film which overlaps with the source region and the drain region of the oxide semiconductor, thereby generating a defect. Hydrogen in the oxide semiconductor is attracted to the defect in the insulating film. The defect in the insulating film is stabilized by the presence of hydrogen.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: November 15, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masashi Tsubuku, Yusuke Nonaka, Noritaka Ishihara, Masashi Oota, Hideyuki Kishida
  • Patent number: 9472773
    Abstract: A device structure including a gate structure containing a first layer of carbon nanotubes and a second layer of carbon nanotubes. The first and the second layers are stacked vertically. The first and the second layers have carbon nanotubes which have substantially homogeneous electric characteristics within each layer. The carbon nanotubes in the first layer have different electric characteristics than the carbon nanotubes in the second layer, so that the device structure exhibits a multiple threshold behavior when coupled to a voltage source. The disclosure also includes a method for fabricating a multithreshold device structure.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: October 18, 2016
    Assignee: International Business Machines Corporation
    Inventors: Sami Rosenblatt, Rasit Onur Topaloglu
  • Patent number: 9466609
    Abstract: The device includes plural control gates stacked on a substrate, plural first channels, configured to penetrate the control gates, and plural memory layer patterns, each located between the control gate and the first channel, configured to respectively surround the first channel, wherein the memory layer patterns are isolated from one another.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: October 11, 2016
    Assignee: SK Hynix Inc.
    Inventors: Min Soo Kim, Dong Sun Sheen, Young Jin Lee, Jin Hae Choi, Joo Hee Han, Sung Jin Whang
  • Patent number: 9455203
    Abstract: A replacement metal gate process in which a high-k dielectric is applied. The high-k dielectric may be doped with lanthanum in an NMOS region or aluminum in a PMOS region. A dummy gate structure may be formed over the high-k dielectric and etched to form an opening over the NMOS region and an opening over the PMOS region. Thereafter, first work function metals are deposited in the NMOS opening and second work function metals are applied in the PMOS openings. A suitable gate electrode material may then fill the remainder of the NMOS and PMOS openings.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: September 27, 2016
    Assignees: International Business Machines Corporation, Global Foundries Inc.
    Inventors: Takashi Ando, Changhwan Choi, Kisik Choi, Vijay Narayanan
  • Patent number: 9449981
    Abstract: A method includes forming an amorphous or polycrystalline semiconductor material over at least a portion of a sidewall of a front side opening and within front side recesses in a stack of alternating first and second material layers, forming a layer of a metal material over at least a portion of the sidewall of the front side opening and adjacent to the semiconductor material within the front side recesses; annealing the metal material and the semiconductor material within the front side recesses to form a large grain polycrystalline or single crystal semiconductor material charge storage region within each of the front side recesses by a metal induced crystallization process, and forming a tunnel dielectric layer and semiconductor channel in the front side opening. Following the metal induced crystallization process, at least a portion of the metal material is located between the charge storage regions and the second material layers.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: September 20, 2016
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Jayavel Pachamuthu, Johann Alsmeier, Henry Chien
  • Patent number: 9397107
    Abstract: A method of making a three dimensional NAND string includes providing a stack of alternating first material layers and second material layers over a substrate. The method further includes forming a front side opening in the stack, forming a tunnel dielectric in the front side opening, forming a semiconductor channel in the front side opening over the tunnel dielectric and forming a back side opening in the stack. The method also includes selectively removing the second material layers through the back side opening to form back side recesses between adjacent first material layers, forming a metal charge storage layer in the back side opening and in the back side recesses and forming discrete charge storage regions in the back side recesses by removing the metal charge storage layer from the back side opening and selectively recessing the metal charge storage layer in the back side recesses.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: July 19, 2016
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Raghuveer S. Makala, Yao-Sheng Lee, Senaka Krishna Kanakamedala, Yanli Zhang, George Matamis, Johann Alsmeier
  • Patent number: 9397114
    Abstract: Methods of fabricating three-dimensional semiconductor memory devices including forming a plate stack structure with insulating layers and sacrificial layers stacked alternatingly on a substrate, forming first and second trenches separating the plate stack structure into a plurality of mold structures, the first trench being between the second trenches, forming first vertical insulating separators in the first and second trenches, forming semiconductor patterns penetrating the mold structure and being spaced apart from the first and second trenches, removing the first vertical insulating separator from the second trench to expose the sacrificial layers, removing the sacrificial layers exposed by the second trench to form recess regions partially exposing the semiconductor patterns and the first vertical insulating separator, and forming conductive patterns in the recess regions.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: July 19, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jumi Yun, Kwangmin Park, Dongchul Yoo, Byong-hyun Jang
  • Patent number: 9390930
    Abstract: A method for incorporating radicals of a plasma into a substrate or a material on a semiconductor substrate using a remote plasma source. In one embodiment, a method for processing doped materials on a substrate surface is provided and includes forming a doped layer on a substrate and optionally cleaning the doped layer, such as by a wet clean process. The method also includes generating an ionized nitrogen plasma in a remote plasma source, wherein the ionized nitrogen plasma has an ion concentration within a range from about 0.001% to about 0.1%, de-ionizing the ionized nitrogen plasma while forming non-ionized nitrogen plasma. The method further includes flowing the non-ionized nitrogen plasma into a processing region within a processing chamber, forming a nitrided capping layer from an upper portion of the doped layer by exposing the doped layer within the processing region to the non-ionized nitrogen plasma during a stabilization process.
    Type: Grant
    Filed: September 20, 2012
    Date of Patent: July 12, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Matthew S. Rogers, Martin A. Hilkene
  • Patent number: 9384989
    Abstract: An improved semiconductor device is provided whereby the semiconductor device is defined by a layered structure comprising a first dielectric layer, a data storage material disposed on the first dielectric layer, and a second dielectric layer disposed on the data storage material, the layered structured substantially forming the outer layer of the semiconductor device. For example, the semiconductor device may be a SONOS structure having an oxide-nitride-oxide (ONO) film that substantially surrounds the SONOS structure. The invention also provides methods for fabricating the semiconductor device and the SONOS structure of the invention.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: July 5, 2016
    Assignee: Macronix International Co., Ltd.
    Inventors: Ching-Chang Lin, Kai-Hsiang Chang, Chih-Yuan Wu, Kuang-Wen Liu
  • Patent number: 9356112
    Abstract: A dielectric structure may be arranged having a thin nitrided surface of an insulator with a charge blocking insulator over the nitrided surface. The insulator may be formed of a number of different insulating materials such as a metal oxide, a metal oxycarbide, a semiconductor oxide, or oxycarbide. In an embodiment, the dielectric structure may be formed by nitridation of a surface of an insulator using ammonia and deposition of a blocking insulator having a larger band gap than the insulator. The dielectric structure may form part of a memory device, as well as other devices and systems.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: May 31, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Leonard Forbes, Kie Y. Ahn
  • Patent number: 9315896
    Abstract: Atomic layer deposition (ALD) processes for forming Group VA element containing thin films, such as Sb, Sb—Te, Ge—Sb and Ge—Sb—Te thin films are provided, along with related compositions and structures. Sb precursors of the formula Sb(SiR1R2R3)3 are preferably used, wherein R1, R2, and R3 are alkyl groups. As, Bi and P precursors are also described. Methods are also provided for synthesizing these Sb precursors. Methods are also provided for using the Sb thin films in phase change memory devices.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: April 19, 2016
    Assignee: ASM IP HOLDING B.V.
    Inventors: Viljami Pore, Timo Hatanpää, Mikko Ritala, Markku Leskelä
  • Patent number: 9306024
    Abstract: A semiconductor device and methods of formation are provided. A semiconductor device includes a dielectric film over a dielectric layer. The dielectric film includes a crystalline structure having a substantially uniform composition of zirconium, nitrogen and oxygen. The dielectric film is formed through in situ nitrogen plasma doping of a zirconium layer. The dielectric film functions as a gate dielectric. The dielectric film has a high dielectric constant between about 28-29 and has a low leakage current density of about 4.79×10?5 A/cm2. The substantially uniform distribution of nitrogen throughout the zirconium oxide of the dielectric film increases the k value of the dielectric film by between about 15% to about 17% as compared to a dielectric film that has a non-uniform distribution of nitrogen through a zirconium oxide layer.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: April 5, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Liang-Chen Chi, Chia-Ming Tsai, Chin-Kun Wang, Jhih-Jie Huang, Miin-Jang Chen
  • Patent number: 9305928
    Abstract: Semiconductor devices having a silicon-germanium channel layer and methods of forming the semiconductor devices are provided. The methods may include forming a silicon-germanium channel layer on a substrate in a peripheral circuit region and sequentially forming a first insulating layer and a second insulating layer on the silicon-germanium channel layer. The methods may also include forming a conductive layer on the substrate, which includes a cell array region and the peripheral circuit region, and patterning the conductive layer to form a conductive line in the cell array region and a gate electrode in the peripheral circuit region. The first insulating layer may be formed at a first temperature and the second insulating layer may be formed at a second temperature higher than the first temperature.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: April 5, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youngkuk Kim, Ho-Kyun An, Jaehyun Yeo, Badro Im, HanJin Lim, Sungho Jang, Insang Jeon
  • Patent number: 9305932
    Abstract: A method of making a monolithic three dimensional NAND string includes providing a first stack of alternating first material layers and second material layers over a major surface of a substrate. The first material layers include first silicon oxide layers, the second material layers include second silicon oxide layers, and the first silicon oxide layers have a different etch rate from the second silicon oxide when exposed to the same etching medium. The first stack includes a back side opening, a front side opening, and at least a portion of a floating gate layer, a tunnel dielectric and a semiconductor channel located in the front side opening. The method also includes selectively removing the first material layers through the back side opening to form back side control gate recesses between adjacent second material layers.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: April 5, 2016
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Senaka Krishna Kanakamedala, Yanli Zhang, Raghuveer S. Makala, Yao-Sheng Lee, Johann Alsmeier, George Matamis
  • Patent number: 9293461
    Abstract: A stack of a barrier metal layer and a first-type work function metal layer is deposited in replacement metal gate schemes. The barrier metal layer can be deposited directly on the gate dielectric layer. The first-type work function metal layer is patterned to be present only in regions of a first type field effect transistor. A second-type work function metal layer is deposited directly on the barrier metal layer in the regions of a second type field effect transistor. Alternately, the first-type work function layer can be deposited directly on the gate dielectric layer. The barrier metal layer is patterned to be present only in regions of a first type field effect transistor. A second-type work function metal layer is deposited directly on the gate dielectric layer in the regions of the second type field effect transistor. A conductive material fill and planarization form dual work function replacement gate structures.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: March 22, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Unoh Kwon, Michael P. Chudzik, Ravikumar Ramachandran
  • Patent number: 9269636
    Abstract: A replacement metal gate transistor is formed with high quality gate dielectric under the high-k dielectric. The high quality gate dielectric is formed on the substrate at a temperature of at least 850° C. A sacrificial gate dielectric is formed on the high quality gate dielectric and a polysilicon replacement gate is formed on the sacrificial gate dielectric. The polysilicon replacement gate is removed leaving a gate trench. The sacrificial gate dielectric is removed from a bottom of the gate. A high-k dielectric is deposited into the gate trench. Metal gate material is deposited on the high-k dielectric.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: February 23, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mahalingam Nandakumar, Hiroaki Niimi
  • Patent number: 9263344
    Abstract: A replacement metal gate process in which a high-k dielectric is applied. The high-k dielectric may be doped with lanthanum in an NMOS region or aluminum in a PMOS region. Alternatively, after a dummy gate is removed in the NMOS and PMOS regions to leave openings in the NMOS and PMOS regions, lanthanum oxide may be deposited in the NMOS opening or aluminum oxide deposited in the PMOS opening. Thereafter, first work function metals are deposited in the NMOS opening and second work function metals are applied in the PMOS openings. A suitable gate electrode material may then fill the remainder of the NMOS and PMOS openings.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: February 16, 2016
    Assignees: International Business Machines Corporation, Global Foundries Inc.
    Inventors: Takashi Ando, Changhwan Choi, Kisik Choi, Vijay Narayanan
  • Patent number: 9263589
    Abstract: An object of the present invention is to manufacture a semiconductor device where fluctuation in electrical characteristics is small and reliability is high in a transistor in which an oxide semiconductor is used. An insulating layer from which oxygen is released by heating is used as a base insulating layer of an oxide semiconductor layer which forms a channel. Oxygen is released from the base insulating layer, whereby oxygen deficiency in the oxide semiconductor layer and an interface state between the base insulating layer and the oxide semiconductor layer can be reduced. Thus, a semiconductor device where fluctuation in electrical characteristics is small and reliability is high can be manufactured.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: February 16, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuta Endo, Toshinari Sasaki, Kosei Noda, Mizuho Sato
  • Patent number: 9257314
    Abstract: Novel methods, systems, and apparatuses for reclaiming annealing gases from a high pressure annealing processing system are disclosed. According to an embodiment, the exhaust gasses from the high pressure annealing processing system are directed into a gas reclaiming system only when a precious gas, e.g., deuterium is used. The annealing gas is the separated from other gasses used in the high pressure annealing processing system and is then pressurized, filtered, and purified prior to transferring the gas to a bulk storage distribution unit. In one embodiment, the reclaimed gas is then again provided to the high pressure annealing processing system to anneal the wafers.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: February 9, 2016
    Assignee: Poongsan Corporation
    Inventors: Manuel Rivera, Biao Wu