Electroplating Solutions and Methods For Deposition of Group IIIA-VIA Films

- SOLOPOWER, INC.

The embodiment described herein relate to pulse electroplating methods and solutions.

Skip to: Description  ·  Claims  · Patent History  ·  Patent History
Description
CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation-in-part of U.S. patent application Ser. No. 13/347,540 filed Jan. 10, 2012, which is a continuation of U.S. patent application Ser. No. 12/143,609 filed Jun. 20, 2008 (now U.S. Pat. No. 8,092,667), and is a continuation-in-part of U.S. patent application Ser. No. 13/306,863 filed Nov. 29, 2011, which is a continuation of U.S. patent application Ser. No. 12/123,372 filed May 19, 2008 (now U.S. Pat. No. 8,066,865), and is a continuation-in-part of U.S. patent application Ser. No. 12/121,687 filed May 15, 2008, and the entire contents of these applications are incorporated herein by reference.

BACKGROUND

1. Field of the Art

This application relates to electroplating methods and solutions and, more particularly, to methods and electroplating solution chemistries for electrodeposition of Group IIIA-VIA layers on a conductive surface for solar cell applications.

2. Description of the Related Art

Solar cells are photovoltaic devices that convert sunlight directly into electrical power. The most common solar cell material is silicon, which is in the form of single or polycrystalline wafers. However, the cost of electricity generated using silicon-based solar cells is higher than the cost of electricity generated by the more traditional methods. Therefore, since early 1970's there has been an effort to reduce cost of solar cells for terrestrial use. One way of reducing the cost of solar cells is to develop low-cost thin film growth techniques that can deposit solar-cell-quality absorber materials on large area substrates and to fabricate these devices using high-throughput, low-cost methods.

Group IBIIIAVIA compound semiconductors comprising some of the Group IB (Cu, Ag, Au), Group IIIA (B, Al, Ga, In, Tl) and Group VIA (O, S, Se, Te, Po) materials or elements of the periodic table are excellent absorber materials for thin film solar cell structures. Especially, compounds of Cu, In, Ga, Se and S which are generally referred to as CIGS(S), or Cu(In,Ga)(S,Se)2 or CuIn1-xGax(SySe1-y)k, where 0≦x≦1, 0≦y≦1 and k is approximately 2, have already been employed in solar cell structures that yielded conversion efficiencies approaching 20%. Absorbers containing Group IIIA element Al and/or Group VIA element Te also showed promise. Therefore, in summary, compounds containing: i) Cu from Group IB, ii) at least one of In, Ga, and Al from Group IIIA, and iii) at least one of S, Se, and Te from Group VIA, are of great interest for solar cell applications.

The structure of a conventional Group IBIIIAVIA compound photovoltaic cell such as a Cu(In,Ga,Al)(S,Se,Te)2 thin film solar cell is shown in FIG. 1. The device 10 is fabricated on a substrate 11, such as a sheet of glass, a sheet of metal, an insulating foil or web, or a conductive foil or web. The absorber film 12, which includes a material in the family of Cu(In,Ga,Al)(S,Se,Te)2 is grown over a conductive layer 13, which is previously deposited on the substrate 11 and which acts as the electrical contact to the device. Various conductive layers comprising Mo, Ta, W, Ti, and stainless steel etc. have been used in the solar cell structure of FIG. 1. If the substrate itself is a properly selected conductive material, it is possible not to use a conductive layer 13, since the substrate 11 may then be used as the ohmic contact to the device. After the absorber film 12 is grown, a transparent layer 14 such as a CdS, ZnO or CdS/ZnO stack is formed on the absorber film. Radiation 15 enters the device through the transparent layer 14. Metallic grids (not shown) may also be deposited over the transparent layer 14 to reduce the effective series resistance of the device. A variety of materials, deposited by a variety of methods, can be used to provide the various layers of the device shown in FIG. 1. It should be noted that although the chemical formula for a CIGS(S) layer is often written as Cu(In,Ga)(S,Se)2, a more accurate formula for the compound is Cu(In,Ga)(S,Se)k, where k is typically close to 2 but may not be exactly 2. For simplicity we will continue to use the value of k as 2. It should be further noted that the notation “Cu(X,Y)” in the chemical formula means all chemical compositions of X and Y from (X=0% and Y=100%) to (X=100% and Y=0%). For example, Cu(In,Ga) means all compositions from CuIn to CuGa. Similarly, Cu(In,Ga)(S,Se)2 means the whole family of compounds with Ga/(Ga+In) molar ratio varying from 0 to 1, and Se/(Se+S) molar ratio varying from 0 to 1.

One technique employed for growing Cu(In,Ga)(S,Se)2 type compound thin films for solar cell applications is a two-stage process where at least two ingredients or elements or components of the Cu(In,Ga)(S,Se)2 material are first deposited onto a substrate, and then reacted with S and/or Se in a high temperature annealing process. For example, for CuInSe2 or CIS film growth, thin layers of Cu and In are first deposited on a substrate and then this stacked precursor layer is reacted with Se at elevated temperature to form CIS. If the reaction atmosphere also contains sulfur, then a CuIn(S,Se)2 or CIS(S) layer can be grown. Addition of Ga in the precursor layer, i.e. use of a Cu/In/Ga stacked film precursor, allows the growth of a Cu(In,Ga)(S,Se)2 or CIGS(S) absorber.

Sputtering and evaporation techniques have been used in prior art approaches to deposit the layers containing the Group IB and Group IIIA components of the precursor stacks. In the case of CulnSe2 growth, for example, Cu and In layers were sequentially sputter-deposited on a substrate and then the stacked film was heated in the presence of gas containing Se at elevated temperature for times typically longer than about 30 minutes, as described in U.S. Pat. No. 4,798,660. More recently U.S. Pat. No. 6,048,442 disclosed a method comprising sputter-depositing a stacked precursor film comprising a Cu—Ga alloy layer and an In layer to form a Cu—Ga/In stack on a metallic back electrode layer and then reacting this precursor stack film with one of Se and S to form the absorber layer. Such techniques may yield good quality absorber layers and efficient solar cells, however, they suffer from the high cost of capital equipment, and relatively slow rate of production.

One prior art method described in U.S. Pat. No. 4,581,108 utilizes a low cost electrodeposition approach for metallic precursor preparation. In this method a Cu layer is first electrodeposited on a substrate. This is then followed by electrodeposition of an In layer and heating of the deposited Cu/In stack in a reactive atmosphere containing Se. Various other researchers have reported In electroplating approaches for the purpose of obtaining In-containing precursor layers later to be converted into CIS absorber films through reaction with Se (see for example, Lokhande and Hodes, Solar Cells 21 (1987) 215; Fritz and Chatziagorastou, Thin Solid Films, 247 (1994) 129; Kim et al Proceedings of the 1st World Conf. on Photovoltaic Energy Conversion, 1994, p. 202; Calixto and Sebastian, J. Materials Science, 33 (1998) 339; Abedin et al., Electrochemica Acta, 52 (2007) 2746, and, Valderrama et al., Electrochemica Acta, 53 (2008) 3714).

A number of In electroplating baths used for depositing In layers on various conductive substrates have been disclosed in several references. For example, In plating baths containing sulfamate (U.S. Pat. No. 2,458,839), cyanide (U.S. Pat. No. 2,497,988), alkali hydroxides (U.S. Pat. No. 2,287,948), tartaric acid (U.S. Pat. No. 2,423,624), and fluoborate (U.S. Pat. No. 3,812,020, U.S. Pat. No. 2,409,983) have been developed. Some details on such chemistries may be found in the review paper of Walsh and Gabe (Surface Technology, 8 (1979) 87). Although it is possible to deposit In layers using various electroplating chemistries employing standard plating practices, unless these layers have sub-micron thickness and smooth morphology, they cannot be effectively used in thin film Group IBIIIAVIA compound solar cell fabrication.

As described above, one recent application of electroplated In films involves the formation of Cu(In,Ga)(Se,S)2 or CIGS(S) films, which are the most advanced compound absorbers for polycrystalline thin film solar cells. An exemplary plating process includes first electroplating a thin In layer on a Cu layer, and then reacting this Cu/In precursor stack with Se to form a CuInSe2, or a CIS absorber. Furthermore, to form a CIGS or CIGS(S) type of compound absorber, Ga can also be included in the precursor stack by plating it on the In layer or by including it in the In layer. Zank et al. (Thin Solid Films, 286 (1996) 259), for example, electrodeposited an In—Ga alloy layer on a Cu film forming a Cu/In—Ga precursor stack and then obtained a CIGS absorber layer by reacting the precursor stack with Se vapor. The CIGS absorber was then used to fabricate a thin film solar cell having a structure similar to the one shown in FIG. 1.

In a thin film solar cell employing a Group IBIIIAVIA compound absorber such as CIS or CIGS, the solar cell efficiency is a strong function of the molar ratio of the IB element(s) to IIIA element(s), i.e. the IB/IIIA molar ratio. If there are more than one Group IIIA materials in the composition, the relative amounts or molar ratios of these IIIA elements also affect the solar cell efficiency and other properties. For a Cu(In,Ga)(S,Se)2 absorber layer, for example, the efficiency of the device is a function of the molar ratio of Cu/(In+Ga). Furthermore, some of the important parameters of the cell, such as its open circuit voltage, short circuit current and fill factor vary with the molar ratio of the IIIA elements, i.e. the Ga/(Ga+In) molar ratio. In general, for good device performance Cu/(In+Ga) molar ratio is kept at or below 1.0. For ratios higher than 1.0, a low resistance copper selenide phase, which may introduce electrical shorts within the solar cells may form. Increasing the Ga/(Ga+In) molar ratio, on the other hand, widens the optical bandgap of the absorber layer, resulting in increased open circuit voltage and decreased short circuit current. A CIGS material with a Ga/(Ga+In) molar ratio higher than about 0.3 is electronically poor. It is for this reason that the sunlight-to-electricity conversion efficiency of a CIGS type solar cell first increases as the Ga/(Ga+In) molar ratio in the absorber is increased from 0 to 0.3, and then the efficiency starts to decrease as the molar ratio is further increased towards 1.

In light of the above discussion, it should be appreciated that if the electrodeposition process is used to introduce In into the composition of a CIGS(S) precursor material, it is essential that the electroplated In films have smooth morphology and uniform thickness, in micro-scale. If micro-structure of an In film or a In—Ga film electroplated on a Cu and optionally Ga containing precursor layer is rough and includes protrusions and valleys or discontinuities, the localized micro-scale Ga/(In+Ga) ratio at the protrusions would be lower than the Ga/(In+Ga) ratio at the valleys. Even the Cu/(In+Ga) molar ratio would be different at these two locations. As will be described next, this kind of micro-scale non-uniformity would yield a CIGS(S) absorber with non-uniform electrical and optical properties after reaction of the precursor stack with Se and/or S. The same argument also holds for the other thin film layers (such as Cu and Ga) within the precursor stack. However, electroplating a smooth Cu layer is relatively easy and the problem usually lies with Ga and In electrodeposition due to the tendency of these low melting, high surface tension elements forming droplets rather than continuous layers when deposited in thin film form.

Thin film CIGS(S) solar cell absorbers typically have a thickness range of 1000-3000 nm. The amount of In that needs to be included in such a thin absorber is equivalent to an In layer thickness which is in the range of about 200-700 nm. For example, for the formation of about 2000 nm thick CIGS absorber with a final Cu/(In+Ga) ratio of 0.85-0.9 and a Ga/(Ga+In) ratio of about 0.3, one needs to deposit about 250-300 nm thick Cu film, about 150 nm thick Ga layer and about 450-500 nm thick In film to form a precursor which may then be reacted with Se. Since cost lowering in CIGS solar cell fabrication as well as the need to reduce stress in the CIGS layer grown by the two-stage processes dictate the use of an absorber thickness which is in the range of 1000-1500 nm, the thickness of the In film in the above example gets reduced to about 200-300 nm level. The Ga layer thickness goes down even lower to the 75-100 nm range. Therefore, in a two stage CIGS(S) absorber formation approach employing an electroplated In layer, the electroplated In film thickness will have to be much less than 1000 nm, preferably less than 700 nm, most preferably less 500 nm. This requirement presents many challenges for prior art In electroplating methods and chemistries. Although these issues will be discussed with respect to In electrodeposition, it should be understood that they are also applicable to Ga and In—Ga alloy electrodeposition.

Low melting Group IIIA materials such as In and Ga have high surface tension and they grow in the form of islands or droplets when deposited on a substrate surface in thin film form. This behavior has been observed in prior work carried out on electroplated In films (see for example, Chen et al., Solar Cells, 30 (1991) 451; Kim et al, Proceedings of the 1st World Conf. on Photovoltaic Energy Conversion, 1994, p. 202; Calixto and Sebastian, J. Materials Science, 33 (1998) 339; Abedin et al., Electrochemica Acta, 52 (2007) 2746, and, Valderrama et al., Electrochemica Acta, 53 (2008) 3714), and in work carried out on In—Ga alloy films (see for example Zank et al., Thin Solid Films, 286 (1996) 259). As stated before, lack of planarity in sub-micron thick In and/or Ga-rich layers presents problems for application of such non-uniform layers to thin film solar cell manufacturing.

FIGS. 2A-2B schematically show a prior art structure in perspective and side views, respectively. The structure includes a typical prior art In layer 37, with sub-micron thickness which may be electrodeposited on a surface 36 of an under-layer 33. The under-layer 33 is formed over a base 30 having a substrate 31 and a contact layer 32. The under-layer 33 may, for example, include Cu and Ga and be formed on the contact layer 32. As can be seen from FIGS. 2A and 2B, the sub-micron thick In layer 37 is discontinuous and it includes islands 34 of In, separated by valleys 35 through which the surface 36 of the under-layer 33 is exposed. The width of the islands may be in the range of 500-5000 nm. If the structure of FIGS. 2A and 2B is reacted with a Group VIA material such as Se, a CIGS solar cell absorber 40 may be formed on the base 30 as shown in FIG. 3. The CIGS solar cell absorber 40 has compositional non-uniformities caused by the morphological non-uniformity of the sub-micron thick In layer 37. Accordingly, the CIGS solar cell absorber 40 has a first region 41 and a second region 42. The first region 41 corresponds to the islands 34 of In of the structure of FIG. 2A, and is an In-rich, Ga-poor region. The second region 42 corresponds to the valleys 35 of the structure of FIG. 2A, and is an In-poor, Ga-rich region. Furthermore, the Cu(In+Ga) molar ratio in the first region 41 is lower than the Cu(In+Ga) molar ratio in the second region 42. It should be appreciated that when a solar cell is fabricated on the CIGS solar cell absorber 40, the efficiency of the solar cell would be determined by both the first region 41 and the second region 42. The solar cell would act like two separate solar cells, one made on the first region 41 and the other made on the second region 42 and then interconnected in parallel. Since the Ga/(Ga+In) as well as the Cu/(In+Ga) molar ratios in the two regions are widely different the quality of the separate solar cells on these regions would also be different. The quality of the overall solar cell would then suffer from the poor I-V characteristics of the separate solar cells formed on either one of the first and second regions.

It should be noted that such non-uniformity problems may not be important in applications where the electroplated In layer is not used for the fabrication of an active electronic device such as a solar cell. It should also be noted that the In films when electrodeposited to thicknesses larger than about 1000 nm they may start forming continuous layers. In such cases the islands 34 in FIG. 2A grow horizontally as well as vertically and eventually merge, eliminating the valleys 35. However, such thick electroplated In layers are not useful for thin film solar cell fabrication since they yield CIGS absorbers that are too thick (thicker than about 3000 nm). Thick absorber layers cause excessive stress and delamination from the base. They also add to the cost of processing, which is not in line with the cost-lowering targets of thin film photovoltaics. Highly efficient CIGS solar cells can be fabricated on 1000 nm thick CIGS absorbers. Using a 3000 nm thick CIGS absorber in a solar cell structure increases materials usage three time and wastes effectively 67% of the materials used in forming the CIGS absorber structure.

As can be seen from the foregoing discussion it is necessary to develop new Group IIIA material electroplating approaches that can yield continuous layers at thicknesses less than about 700 nm, preferably less than about 500 nm. Such thin layers can be used in electronic and semiconductor applications such as in processing thin film CIGS type solar cells.

SUMMARY

The embodiment described herein relate to electroplating methods and plating electrolyte solutions.

In one embodiment is described a method of forming an absorber layer over a surface of a base, the method comprising: forming a metal layer over the surface of the base, wherein the metal layer comprises a Group IIIA material; co-depositing Group IIIIA and Group VA materials to form a Group IIIA-VIA layer on the metal layer using pulse electroplating that varies an electroplating pulse between a first higher value and a second lower value, wherein at the first higher value electroplating of at least one of Ga and In predominates, and wherein at the second lower value electroplating of one of Se, Te and S predominates, wherein the step of co-depositing the Group IIIA-VIA layer uses a roll-to-roll electroplating process wherein the base having the metal layer is continuously advanced within an electroplating solution held in a deposition chamber as at least one electric field is formed between at least one anode to deposit the Group IIIA-VIA layer onto the metal layer; and reacting the metal layer and the Group IIIA-VIA layer to form the absorber layer.

In another embodiment is described an electroplating solution for deposition of a Group IIIA-Group VIA thin film on a Group IIIA material surface, the electroplating solution comprising: a solvent; a Group IIIA material source that provides Ga in ionic form in the solvent; a Group VIA material source that dissolves in the solvent and provides Se in ionic form; an anti-oxidant; an anti-flocculant; a pH adjuster including at least one of an organic acid, an inorganic acid, an organic base and an inorganic base; additives including at least one of a surface-active compound, a complexing agent and an ionic conductivity enhancer; wherein the pH of the solution is in the range of 0.5-13.

Other embodiments and aspects are described herein.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other aspects and features will become apparent to those of ordinary skill in the art upon review of the following description of specific embodiments in conjunction with the accompanying figures, wherein:

FIG. 1 is a schematic view of a prior art solar cell structure.

FIG. 2A is a perspective top view of a prior art precursor structure formed by electroplating a sub-micron thick In layer on a sub-layer.

FIG. 2B is a cross-sectional view of the structure of FIG. 2A taken along the line AA.

FIG. 3 is a CIGS layer formed after reaction of the structure of FIG. 2B with Se.

FIGS. 4A-4C schematically shows electrodeposition of a uniform In-rich layer over a continuous interlayer thus forming a uniform stack.

FIG. 5 shows a Group IBIIIAVIA compound layer formed on a base using the stack of FIG. 4.

FIG. 6A is a schematic view of a precursor stack including a Group IB-IIIA meta layer on a base, a Group IIIA-VIA alloy layer on the metal layer and a Group VIA layer on the alloy layer;

FIG. 6B is a schematic view of a precursor layer formed after reacting the precursor stack shown in FIG. 6A;

FIG. 7A is an electroplating voltage-time graph;

FIG. 7B is an electroplating current density-time graph;

FIG. 8A is a pulsed electroplating voltage-time graph;

FIG. 8B is a pulsed electroplating current density-time graph;

FIGS. 9A-9B various electroplating voltage-time and electroplating current density-time graphs;

FIG. 10 is a pulsed electroplating voltage-time graph;

FIG. 11 is a pulsed electroplating current density-time graph;

FIG. 12A is a schematic view of an embodiment of a first electroplating system;

FIG. 12B is a process graph showing voltage or current density variation along the length of an electroplating chamber of the first system shown in FIG. 12A;

FIG. 13A is a schematic view of an embodiment of a second electroplating system;

FIG. 13B is a process graph showing voltage or current density variation along the length of an electroplating chamber of the second system shown in FIG. 13A;

FIG. 14A is a schematic view of an embodiment of a third electroplating system; and

FIG. 14B is a process graph showing voltage or current density variation along the length of an electroplating chamber of the third system shown in FIG. 14A.

 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Described are methods for forming a Group IIIA material thin film on a conductive layer which is coated by an interlayer to facilitate a uniform Group IIIA material thin film growth with thickness less than about 700 nm. The Group IIIA material film, the interlayer and the conductive layer may be a part of a precursor stack that will eventually be reacted and transformed into a Group IBIIIAVIA solar cell absorber. The Group IIIA material thin film may comprise any one of a substantially pure In material, a substantially pure Ga material, or an In—Ga binary alloy. The Group IIIA material thin film is a continuous film having a thickness less than about 700 nm. In one embodiment, the Group IIIA material thin film may be formed by an electrodeposition process on the surface of the interlayer. Accordingly, the interlayer is formed on a conductive surface which may be the top surface of a base or a precursor stack. The group IIIA material thin film may then be formed by electrodeposition on the exposed surface of the interlayer. The interlayer comprises 20-90 molar percent, preferably 40-80 molar percent of at least one of In and Ga. The balance of the interlayer composition comprises an additive material. The additive material of the interlayer includes at least one of Cu, Se, Te, Ag and S, preferably at least one of Cu and Te. Other materials or impurities may also be present in the additive material as long as their molar content does not exceed about 10 molar percent of the total additive material composition. The process used to form the Group IIIA material thin film on the interlayer is electrodeposition; however, in the following description the words electroplating, plating and deposition may be used to refer to the electrodeposition process of the In and/or Ga layer.

An electrodeposition process which forms a Group IIIA material layer, or thin film, for the manufacture of a Group IBIIIAVIA solar cell precursor structure will be described using FIGS. 4A-4C. FIG. 5 shows the structure with the Group IBIIIAVIA solar cell absorber, which is formed from the precursor stack of FIG. 4C.

FIG. 4A exemplifies a first structure 100 including a first layer 102 formed on a base 104 to initiate the precursor stack forming process. The first layer 102 may preferably be formed using an electrodeposition process; however, other deposition processes such as evaporation, sputtering and the like may also be used to form the first layer 102. The base 104 may be a conductive base including a substrate 106 and a contact layer 108, which will eventually form an electrical contact to the CIGS(S) absorber after the reaction step. The substrate 106 may be a continuous conductive material such as a metal or alloy foil, preferably a stainless steel foil. The contact layer 108 may comprise conductive materials such as Mo, W, metal nitrides, Ru, Os, and Ir, which make ohmic contact to CIGS(S) type absorber films. The first layer 102 is a conductive layer comprising Cu. The first layer 102 may be a pure Cu layer or it may comprise In and/or Ga. The first layer 102 may be homogeneous or it may be in the form of a stack. Exemplary stacks forming the first layer 102 include, but are not limited to, Cu/Ga, Cu/Ga/Cu, Cu—Ga/Cu, and the like, stacks.

FIG. 4B shows a second structure 200 formed as the process proceeds. In the second structure 200, a second layer 112 or an interlayer is formed on the top surface 110 of the first layer 102, using preferably an electrodeposition process. The interlayer 112 is a conditioned conductive layer so that it establishes a conditioned surface for the following Group IIIA thin film deposition. In the context of this application, the word conditioned refers to establishing a mate composition that not only helps forming a thin and continuous Group IIIA layer on the interlayer but also includes constituents that do not affect negatively the overall composition of the resulting precursor stack and do not deteriorate the quality of the CIGS(S) absorber to be formed. The interlayer 112 is a continuous layer with a substantially uniform thickness which is less than 100 nm, preferably less than 50 nm. Surface 114 of the interlayer 112 functions as an active deposition site to allow a Group IIIA material to continuously and uniformly deposit onto the surface 114 in the subsequent step, thereby eliminating the discontinuity problems of the prior art described above.

The interlayer 112 comprises 20-90 molar percent, preferably 40-80 molar percent of at least one of In and Ga. Presence of In and/or Ga in the interlayer composition is important for the interlayer to provide effective nucleation to the In and/or Ga rich layer that will be electroplated on top of it. However, the In and/or Ga content of the interlayer cannot be more than 90% because the interlayer needs to be continuous to be able to provide the effective nucleation sites. If the interlayer becomes near pure In and/or Ga layer then it would be in the form of islands or droplets as discussed before.

Besides In and/or Ga, the balance of the interlayer composition is an additive material. The additive material in the interlayer includes at least one of Cu, Se, Te, Ag and S. The most preferred additives are Cu and Te. These additives assist in making the interlayer a continuous film, and at the same time the In and/or Ga in the interlayer provide high density of nucleation sites for the In and/or Ga layer that would be electroplated on the interlayer. Since the Group IBIIIAVIA absorber layer (compound layer) fabrication is specifically targeted, the additive materials are the materials that will not damage the electronic quality of the CIGS(S) absorber. Other materials or impurities may also be present in the additive material without exceeding about 10 molar percent of the total additive material composition. Examples of such impurities include Sb and As. The composition of the interlayer is largely determined by the chemical composition of the Group IIIA material layer (layer 116 in FIG. 4C) that will be electrodeposited onto the interlayer 112 and any other layer that may be present in the resulting precursor stack.

In one embodiment, the interlayer 112 may be electrodeposited out of plating electrolytes comprising at least one of In and Ga as well as at least one additive such as Cu and Te. By co-depositing these additives and including them into the interlayer 112, a continuous interlayer may be obtained even at a thickness as low as 10 nm. Although the thickness of the interlayer 112 depends on the thickness of the Group IIIA material layer that will be electrodeposited onto the interlayer, a preferable thickness of it may be for example less than about 50 nm so that the amount In, Ga and other materials that it may contain do not become a determining factor in the overall composition, i.e. the Cu/(In+Ga) molar ratio or Ga/(Ga+In) molar ratio, of the resulting structure after the Group IIIA material deposition. In one embodiment, the thickness of the interlayer is less than or equal to about 20%, preferably less than about 10% of the thickness of the Group IIIA material-rich layer that is deposited over the interlayer, so that the effect of the interlayer on determining the overall composition of the resulting precursor stack is limited. This is important for manufacturability and repeatability of the process.

FIG. 4C shows a third structure 300 formed after electrodepositing a third layer 116 which is a substantially pure Group IIIA material layer onto the interlayer 112. As opposed to the discontinuity problems of the prior art In and/or Ga films, the third layer 116 is a continuous thin film. By employing an electrodeposition process that uses the interlayer 112 as a cathode, very thin Group IIIA material layers having uniform thickness may be formed on the interlayer 112. The thickness of the third layer 116 may be less than about 700 nm, preferably less than about 500 nm, whereas the thickness of the interlayer is less than about 20% of these values, i.e. less than about 140 nm, preferably less than about 100 nm. Most preferably the thickness of the interlayer is less than about 10% of the thickness of the third layer 166, i.e. less than about 70 nm. In one embodiment, the Group IIIA material deposited on the interlayer may be a substantially pure In—Ga binary alloy electrodeposited from an electrolyte comprising In and Ga ions. During the electrodeposition process, in an electrodeposition chamber containing the electrodeposition electrolyte, the interlayer 112 is cathodically polarized with respect to an anode so that the third layer comprising In and Ga deposits onto the surface 114 of the interlayer in a uniform manner. The chemical composition of the third layer 116 may preferably comprise at least 90 molar percent In and/or Ga, preferably at least 95 molar percent In and/or Ga.

Referring back to FIG. 4C, as will be appreciated, in the third structure 300, the stack of the first layer 102, the second layer 112 or interlayer and the third layer 116 forms a precursor stack containing Group IB and Group IIIA elements on the base 104.

As shown in FIG. 5, in the following process step, the precursor stack 118 is reacted with at least one Group VIA material such as Se, Te or S to form an absorber layer 120 on the base 104. As mentioned above the precursor stack 118 comprises Cu, In, and Ga, and therefore reacting them with a Group VIA material forms the absorber 120 which is a compositionally uniform Group IBIIIAVIA compound layer.

Described also are methods for forming a Group IIIA-Group VIA (IIIA-VIA) material layers or films on a conductive layer. The IIIA-VIA layer may be a part of a precursor stack that is reacted to form a Group IBIIIAVIA compound semiconductor absorber layer (CIGS layer). The IIIA-VIA layer may comprise any one of a Ga—Se binary alloy, an In—Se binary alloy or an In—Ga—Se ternary alloy. Alternatively, the IIIA-VIA layer may comprise any one of a Ga—Te binary alloy, an In—Te binary alloy or an In—Ga—Te ternary alloy. The IIIA-VIA layer may be formed, using a PVD process, such as sputter deposition, evaporation deposition, or an electrodeposition process, on an In film or a Ga film of a precursor stack including Cu, Ga and In films.

An electroplating process which forms a IIIA-VIA layer or thin film to manufacture a Group IBIIIAVIA solar cell precursor structure will be described using FIG. 6A. The electroplating process includes an electroplating solution coupled with galvanic (constant current), potentiostatic (constant voltage) or pulsed galvanic or potentiostatic electroplating techniques to provide more control over the electroplated film morphology and quality. Electroplating process may be performed in a roll-to-roll electroplating system including an electroplating tank containing an electroplating solution and at least one electrode (anode). As shown in FIG. 6A, a first layer 302 or metal layer may be formed on a base 304 to initiate the precursor stack forming process. The metal layer 302 may preferably be formed using an electroplating process; however, other deposition processes such as evaporation, sputtering and the like may also be used to form the metal layer 302. The base 304 may be a conductive base including a substrate 306 and a contact layer 308, which will eventually form an electrical contact to the CIGS(S) absorber after the reaction step. The substrate 306 may be a continuous conductive material such as a metal or alloy foil, preferably a stainless-steel foil. The contact layer 308 may comprise conductive materials such as Mo, W, metal nitrides, Ru, Os and Ir, which make ohmic contact to CIGS(S) type absorber films. The metal layer 302 is a conductive layer comprising Cu, In and Ga. The metal layer 302 may preferably be in the form of a stack including multiple films of Cu and at least one of In and Ga. Exemplary stacks forming the metal layer 302 include, but are not limited to, Cu/Ga, Cu/In, Cu/In/Ga, Cu/Ga/In, and the like, stacks. In the preferred embodiment, the metal layer is a stack with an In-film, i.e., the top surface of the metal layer 302 is In metal.

As shown in FIG. 6A, a second layer 312 or a IIIA-VIA layer is formed on a top surface 310 of the metal layer 302, using preferably an electroplating process. The IIIA-VIA layer 312 may be electrodeposited from a IIIA-VIA electroplating solution or electrolyte onto the metal layer 302. The IIIA-VIA layer may be an alloy with the predetermined compositions of non-alloyed 111A and VIA materials, a mixture of alloys of IIIA and VIA materials or a mixture of alloyed and non-alloyed IIIA and VIA materials. In the preferred embodiment IIIA and VIA materials are co-electrodeposited to form the IIIA-VIA layer. In the preferred exemplary embodiment the IIIA-VIA layer 312 is a Ga—Se binary alloy layer or a layer of mixed Ga and Se materials co-electrodeposited from a Ga—Se electroplating solution on the top surface 310 of the metal layer 302. In one embodiment, the metal layer 302 and the IIIA-VIA layer 312 form a CIGS precursor stack 314. Before the reaction step, a cap layer 316 that preferably includes a Group VIA layer including at least one of Se, Te and S and a dopant layer including at least one of Na, K and L is deposited onto the CIGS precursor stack 314 and the stack is reacted to form an absorber layer 320 on the base 304, as shown in FIG. 6B. Between the cap layer 316 and the IIIA-VIA layer 312, there may be one or more films of Cu, In and Ga. As also mentioned above the CIGS precursor stack 314 comprises Cu, In, Ga and Se and therefore reacting the precursor stack 314 with Group VIA material forms the absorber layer 320 which is a compositionally uniform Group IBIIIAVIA compound semiconductor layer.

The electroplating process of the IIIA-VIA layer 312 utilizes precise chemistry control coupled with a waveform deposition profile in either a galvanic mode or a potentiostatic mode to precisely control the co-deposition of Group IIIA and Group VIA materials, i.e. Ga and Se. A stable multi-composition electroplating solution with an increased lifetime was formulated. The electrolyte solution includes several distinctive additives such as anti-oxidants, anti-flocculants, surface-active compounds, organic-water solvent pairs (non-aqueous solvents) to facilitate defect-free, continuous and device-quality layers containing IIIA and VIA elements. The waveform deposition profile provides a flexible platform for the deposition of IIIA-VIA layers with different electroplating redox potentials such that alloys, intermetallics, or mix-metal films can be electrodeposited.

The composition of the IIIA-VIA layer 312 of the Group IIIA and Group VIA material can also be controlled by the ratio of Group IIIA/Group VIA,.e, Ga/Se ratio, in the electroplating solution. A waveform deposition profile, e.g., pulsing either the deposition voltage or current density, provides a flexible platform for the deposition of IIIA-VIA alloys. In its simplest form, the waveform might be a constant current or a constant voltage that is applied for the required duration to electroplate the desired thickness and composition of IIIA-VIA alloys as illustrated in FIGS. 7A-7B. FIG. 7A shows a constant voltage V1 for duration T1 while FIG. 7B shows a constant current density J1 for duration T1. In addition, intentional grading can be employed in the electrodeposition of IIIA-VIA layers to distribute the elemental species throughout the layer thicknesses to obtain desirable precursor structures. For example, in the preparation of the precursor first a Cu—In—Ga layer can be deposited, preferably with the use of plating. Precursor formation can be completed by plating a graded In—Se or Ga—Se layer on the top of this layer with an In/Ga-rich bottom region and a Se-rich top region. If the potentiostatic (voltage) mode is used, a high plating voltage followed by a low plating voltage can be used to obtain a layer grading. FIG. 8A shows a constant voltage V1 for duration T1 followed by V2 for duration T2, where V2>V1.

The film grading can also be accomplished in a galvanostatic (current) mode by applying a high current density initially to obtain an In/Ga-rich layer and then lowering the current density to incorporate more selenium into the growing layer, these approach is shown in FIG. 8B where a constant current density J1 for duration T1 is followed by J2 for duration T2, where J2>J1. Yet another way to achieve such type of graded structure in either a potentiostatic and galvanostatic modes is by application of a waveform (pulse). FIGS. 9A-9B illustrate one of many types of waveforms for gradual grading in potentiodynamic and galvanodynamic modes. FIG. 9A shows a constant voltage increasing from V1 to V2 for duration from T1 to T2 and FIG. 9B shows a current density increasing from J1 to J2 for duration from T1 to T2 in linear or parabolic fashions.

The IIIA-VIA electroplating solutions are prepared by dissolving a IIIA source material and a VIA source material in a solvent. In these solutions the amount of IIIA source can be in the range of 0-100%. In other words, the solution composition can be in any range from a pure VIA solution to a mixture of IIIA and VIA source at any ratio, to a pure IIIA solution. Similarly, the amount of VIA source can be in the range of 0-100%. In other words, the solution composition can be in any range from a pure IIIA solution to a mixture of VIA and IIIA source at any ratio, to a pure VIA solution. In an exemplary pure Se solution to deposit to a IIIA-VIA layer with 0% IIIA material may contain a selenium source, inorganic and organic acids and bases, complexing agents, additive groups such as anti-oxidants, anti-flocculants, surface-active compounds ionic conductivity enhancers and organic-water solvent pairs or non-aqueous solvents. Selenium oxide may provide Se source. In addition, compounds of Se such as acids of Se as well as oxides, chlorides, sulfates, nitrates, perchlorides, and phosphates of Se can be used.

Exemplary Ga—Se electroplating solutions to deposit the IIIA-VIA layer 312 may include a gallium source, a selenium source, inorganic and organic acids and bases, complexing agents, additive groups such as anti-oxidants, anti-flocculants, surface-active compounds ionic conductivity enhancers and organic-water solvent pairs or non-aqueous solvents. Ga source in this plating bath composition may comprise stock solutions prepared by dissolving Ga metals into their ionic forms as well as by dissolving soluble Ga salts, such as sulfates, chlorides, acetates, sulfamates, carbonates, nitrates, phosphates, oxides, perchlorates, hydroxides. Examples of a gallium source may include one of GaCl3, Ga(NO3)3, Ga2(SO4)3, Ga-Oxides, gallium (III) acetylacetonate, gallium bromide, gallium iodine, gallium (III) trifluoromethane sulfonate, gallium trichloride-phosphorus oxychloride, or gallium oxychloride. Selenium oxide may provide Se source. In addition, compounds of Se such as acids of Se as well as oxides, chlorides, sulfates, nitrates, perchlorides, and phosphates of Se can be used. Examples of a selenium source may include one of a selenus acid, selenic acid, selenium oxide, selenium (IV) bromide, selenium chloride (I, IV), selenium (IV) sulfide selenourea, N,N-dimethylselenourea, selenosemicabazide, sodium selenite, silver selenite or selenium disulfide.

The electroplating solution may also be prepared to electroplate other IIIA-VIA layers including other materials such as indium and tellurium to form an In—Te alloy layer or a layer of mixed In and Te. Further, indium salts may be dissolved in an above described Ga—Se solution to formulate an In—Ga—Se electroplating solution to deposit an In—Ga—Se alloy layer or a layer of mixed In, Ga and Se materials. In and Ga source in this plating bath composition may comprise stock solutions prepared by dissolving In and Ga metals into their ionic forms as well as by dissolving soluble In and Ga salts. Indium salts may include indium-chloride, indium-sulfate, indium-sulfamate, indium-acetate, indium-carbonate, indium-nitrate, indium-phosphate, indium-oxide, indium-perchlorate, and indium-hydroxide. Te sources such as telluric acid (H6TeO6), tellurium dioxide (TeO2) may be included in the above described Ga—Se solutions to formulate a Ga—Se—Te electroplating solution to deposit a Ga—Se—Te alloy layer or a layer of mixed Ga, Se and Te materials. Both In and Te salts may also be added to prepare an In—Ga—Se—Te solution to deposit an In—Ga—Se Te alloy or a layer of mixed In, Ga, Se and Te materials. In addition to Te, another group VIA element sulfur may also be incorporated into the electrodeposited IIIA-VIA layer if S sources are added into the electroplating solution specified above. Exemplary sulfur sources include selenium sulfides (Se4S4, SeS2, Se2S6), thiourea (CSN2H4), and sodium thiosulfate (Na2S2O3).

An exemplary In—Ga—Se—Te—S electroplating solution to deposit the IIIA-VIA layer 312 may include a gallium source, an indium source, a selenium source, a tellurium source, a sulfur source, inorganic and organic acids and bases, complexing agents, additive groups such as anti-oxidants, anti-flocculants, surface-active compounds ionic conductivity enhancers and organic-water solvent pairs or non-aqueous solvents. Group IIIA material source in this plating bath composition may comprise stock solutions prepared by dissolving In and Ga metals into their ionic forms as well as by dissolving soluble In and Ga salts, such as sulfates, chlorides, acetates, sulfamates, carbonates, nitrates, phosphates, oxides, perchlorates, and hydroxides. Selenium oxide and Te oxide may provide the Group VIA source. In addition, Group VIA compounds of Se and Te such as acids of Se and Te as well as oxides, chlorides, sulfates, nitrates, perchlorides, and phosphates of Se and Te can be used. Sulfur can be provided from source including selenium sulfides (Se4S4, SeS2, Se2S6), thiourea (CSN2H4), and sodium thiosulfate (Na2S2O3).

Antioxidants are compounds which can be used to regulate the oxidation potential of the solution to control the oxidation state, and thus the relative amounts of dissolved selenium ions from +4 to +6. For example, inclusions of appropriate anti-oxidants can provide the ability to regulate the ratio of selenite (SeO32-) ion, where Se has an oxidation state of +4, to selenate (SeO42-) ion, where Se has an oxidation state of +6. The oxidation states of ionic selenium ions for +4 and +6 will be designated as Se(+4) and Se(+6) from here on. In the absence of any anti-oxidants, the oxidation of Se (+4) to Se (+6) ions is mainly controlled by the dissolved oxygen in the electroplating baths. Several categories of anti-oxidants operating under different mechanisms can be considered to prevent the oxidation of Se(+4) to Se(+6). For example, in one category, additives that reduce the oxygen solubility in the electroplating bath can be used. These will reduce the rate of oxidation of selenium. In another category, additives that sequester the dissolved oxygen can be used to reduce the dissolved oxygen and to decrease the oxidation rate. In another category, that reduce the selenium (+4) to Selenium (+6) by oxidizing themselves can be considered. Controlling the Se (+4)/Se (+6) ratio can provide an increase and stable faradaic plating efficiency. An increase in the faradaic efficiency might be possible as the reduction of Se (+4) to elemental Se will require four electrons as compared to 6 electrons needed for Se(+6). Having a constant Se (+4)/Se(+6) ratio can provide a constant faradic efficiency which will yield films with a better Se thickness control in the film over time. As a result, the ratio of Ga/Se in the Ga—Se films can be controlled more precisely since the faradaic efficiency for selenium plating, will be constant. Any anti-oxidant that can assist to provide a better control over the Ga/Se ratio in the resulting Ga—Se film can be included in the Ga Se electrolytes. Some of the anti-oxidant that can be used to control the selenium oxidation state includes, but not limited to, one of organic anti-oxidants such as hydroquinone, pyrocatechol, gallic acid; cycloamines such as 4-amino-4H-1,2,4-triazole, 4,5-imidazoledicarboxylic acid; sugars such as dextrose, saccharin, fructose; organic-sulfonates such as hydroquinone sulfonic; alcohols such as ethanol, methanol, glycerol, ethyleneglycol and phenolic compounds such as 1,1-Diphenyl-2-picryl hydrazyl, dihydric phenols, catechol, resorcinol, 4-(N-alkylated) aminophenols, etc.

Anti-flocculants are compounds used to reduce the interaction between metal metal-oxides or other metal based particulates such that they do not aggregate and precipitate. Anti-flocculants can be used to increment the lifetime of the solution and reduce defect formation by reducing flocculation which could cause shadowing effects during electroplating due to particle formation on the working electrode/electrolyte interface; this effect would impact the integrity of the film and reduce the overall performance efficiency of the particular spot where flocculation has created a plating defect. Anti-flocculants may include phosphates including one of simple phosphates including dipotassium phosphate, ammonium dihydrogen phosphate, ammonium hexafluorophosphate, calcium phosphate, potassium metaphosphate, potassium phosphate, potassium triphosphate, potassium hexafluorophosphate, potassium hydrogen phosphate and sodium hydrogen phosphate; phosphate-thiols such as diethyl dithiophosphate; phosphate-ammonium such as diethyl dithiophosphate, ammonium salt; organic phosphates such as tetrabutylammonium hexafluorophosphate. Anti-flocculants may also include one of: glycols such as polyethylene glycol; organic compounds including acids and esters, such as tannic acid as an acid and ether as an ester; phosphonic acids such as organo-phosphates for example, 1-hydroxyethylidenebis(phosphonic acid) or methylenediphosphonic acid; and amines such as diethylenediamine or amino-phosphonic-organic acid, for example, (aminomethyl)phosphonic acid.

Surface active compounds are compounds that will bind to the surface of the working electrode (e.g., the surface 310 of the metal layer 302 in FIG. 6A) and will modify the growth by either binding to the surface and preventing growth or binding to the surface and aiding in the growth. Furthermore the surface active components can be non-ionic such that they will only change the surface tension of the solid-liquid interface and this effect will change the hydrodynamics at the surface which will in turn change the growth rate and diffusion limitations. Exemplary surface active compounds may include one of: amine such as melamine; amine-hydroxide such as dopamine hydrochloride; sulfonic such as (HEPES) 4-(2-hydroxyethyl)piperazine-1-ethanesulfonic acid; triazine-thiol such as 1,3,5-triazine-2,4,6-trithiol trisodium; anioninc surfactants such as SDS; cationic surfactants such as n-dodecylamine or sodium n-octyl sulfate; tri-block-polymers such as ethylene oxide(EO)-propylene oxide-EO, for example, pluronic P123, pluronic F127 (pluronic is a trade name from BASF but this should include similar type of polymers that are not a trademark, but a similar family of compounds); polyglycol the polymers such as Brij 35 or other Brij Polymers (Trademark of Croda).

Ionic conductivity enhancers are any family compounds that will form ionic compounds when dissolved in the electroplating bath medium (water or organic-water solvent pairs) that can increase the conductivity of the plating bath. Such compounds can range from inorganic salts such as NaCl or Na2SO4.

Organic-solvent pairs can be used to improve the solubility of the metal precursor or additive, decrease the temperature at which the plating can be performed to prevent the melting of Ga and/or In in the precursor stack, decrease the H2 evolution and increase the plating faradaic efficiency. The following solvents may be considered as water-solvent pairs: alcohols such as ethanol, methanol, iso-propanol, butanol, 2-butanol or tert-butanol, amongst other soluble alcohols; dimethysulfoxide; acetone; and other organic solvents in which water constitutes less than 5% of the total volume, for example, acetonitrile, dichloromethane, pyrrolidimome or tetrahydrofuran.

The pH of the electroplating solutions can be either in the acidic, neutral or alkaline regime, but pH's above 13 are not preferred as electrochemical reduction of Se becomes very difficult in this highly alkaline pH regime. In the acidic regime, the preferred pH regime is 0.5 to 4. A more preferred pH range is 0.8-2.5. Plating solutions can be prepared at a pH range between 4 to 13, and more preferably at a pH range between 7 to 12. Complexing agents such as such as tartaric acid, citric acid, acetic acid, malonic acid, malic acid, succinic acid, ethylenediamine, ethylenediaminetetraacetic acid, nitrilotriacetic acid, and hydroxyethylethylenediaminetriacetic acid, etc. may be employed in the plating solution in the entire pH regime. However, they might be most effective in the In the neutral and alkaline pH regimes to solubilize group III metal ions in the form of complexed species and to prevent them forming oxide and hydroxide species. The pH of the solution can be adjusted by incorporation of acids such as sulfuric acid, hydrochloric acid, phosphoric acid, ethylenediaminetetraacetic acid, malonic acid, malic acid, nitrilotriacetic acid, succinic acid, maleic acid, oxalic acid, tartaric acid, citric acid, sulfamic acid, hydroxyethylethylenediaminetriacetic acid etc. In addition to acids, inorganic and organic bases such as NaOH, KOH, NH4OH, organic amines such as methylamine and trimethylamine etc., organic hydroxides such as tetramethylammonium hydroxide and tetrabutylammonium hydroxide, other organic bases such as pyridine, imidazole, benzimidazole, histidine and phosphazene bases can also be used to adjust the pH of the plating solutions.

The electroplating solution may be employed by various electroplating processes to electroplate the above described Ga—Se layer on metal layers. In one embodiment of an electroplating process, a potential between the metal layer 302, which becomes the working electrode or cathode, and an anode, which is the counter electrode, is applied and controlled by either monitoring the voltage between the electroplated metal layer 302 and the anode or monitoring the voltage between the metal layer and a reference electrode such as a SHE (standard hydrogen electrode) or a Ag/AgCl saturated electrode.

In addition to waveforms described above, modulated or pulsed voltage and current (or current density) waveforms might be used in order to achieve a desired IIIA-VIA layer composition and morphology. For example FIG. 10 is a voltage-time graph showing a potential mode electrodeposition to deposit the IIIA-VIA layers. In this embodiment, the applied potential between the anode and the metal layer 302 is modulated, i.e., pulsed, between a first voltage V1 for a T1 time or first voltage application period (pulse 1) and a second voltage V2 for a T2 time or second voltage application period (pulse 2). TT is a total deposition time of the IIIA-VIA layer 312 onto the metal layer 302, based upon a cumulative amount of pulses. In some cases, more than two pulses might be advantageous. For example, a third Voltage V3 and T3 can be applied such that the 3 pulses are repeated until TT the total deposition time is reached.

Applications of a third pulse can be used when dissolution of the Ga—Se compound is preferred such that the first pulse would be a nucleation pulse, the second pulse would correspond to a growth regime and the third pulse would partially dissolve the alloy layer portion that was previously deposited during the second pulse. The voltage range for any of the pulses used in the waveform can be between 0 V and 20 V but more preferably between 0 and 10 V, and most preferably between 0 and 4 V. The duration of any of the pulses (pulse width in time) can be between 1E-7 sec to 360 sec but more preferably in the range of 1E-5 sec to 10 sec, and most preferably in the range of 1E-3 to 5 sec. The total electroplating time TT can be in the range of seconds to hours; this TT time can also be terminated once a total charge (Coulomb [A/cm2]) has been applied to the electroplated layer such that a desired thickness range can be obtained.

In FIG. 10, the voltage-time graph is a potentiostatic wave form in the form of a step function; however any other functional waveforms (sine, cosines, ramped profile, etc.) can also be used. By applying a pulsed potential, Ga will predominantly be deposited at a higher deposition potential while Se will be deposited at a lower deposition potential to form the Ga—Se layer. The Selenium distribution in the Ga—Se layer as a function of thickness can be controlled by simply changing the time that the voltage is maintained at V1; therefore the Ga profile can be controlled independently of the overall Ga/Se atomic overall layer composition. Furthermore by potential or galvanic modulation, the conductivity of the deposition receiving cathode layer may be better controlled. For example, a Ga film may first be pulse electroplated on a Se film, which is a semiconductor, and then the deposition may continue with Ga—Se layer pulse electroplating to form thicker Ga—Se layers. Ga—Se layers electrodeposited with the potential modulation may have a more uniform Ga—Se distribution than the Ga—Se layers electrodeposited with a galvanic modulation.

FIG. 11 is a current density-time graph showing a galvanic mode electrodeposition to form the IIIA-VIA layer. In this embodiment, a defined amount of current density [mA/cm2] is passed between the metal layer 302 (cathode) and an anode to deposit a Ga—Se layer onto the metal layer 302. The applied current density between the anode and the metal layer 302 is modulated, i.e., pulsed, between a first current density J1 for a T1 time or first current density application period and a second current density J2 for a T2 time or second current density application period. The current density range for J1 and J2 is from 0 to 200 mA/cm2, but more preferably from 0 to 50 mA/cm2 most preferably between 0.0 mA/cm2 and 20 mA/cm2. In some cases, more than two pulses might be advantageous. For example, a third pulse J3 with a duration of T3 can also be included. The current density range for any of the pulses used in the waveform can be from 0 mA/cm2 to 80 mA/cm2 but most preferably between 0 and 40 mA/cm2. The duration of any of the pulses (pulse width in time) can be between 1E-7 sec to 60 sec but more preferably in the range of 1E-5 sec to 10 sec, and most preferably in the range of 1E-3 to 5 sec.

The application of a constant current density permits a more precise control of the thickness of the deposited Ga—Se layer since the current density will be proportional to a deposition thickness; therefore a quasi-constant rate of Ga—Se can be deposited at each pulse of J1 and J2. The low current density pulse can serve as a nucleation pulse while the second pulse allows the Ga—Se layer to grow, however, one of the pulses may also be used as a dissolution pulse where a portion of the deposited Ga—Se layer is etched (anodic current) and some material is deposited on the cathodic pulse. The Ga distribution on the Ga—Se layer will be less controllable on a galvanostatic method since the resulting voltage between the working and counter electrode will vary due to the change in conductivity of the deposited layers. The conductivity of the Ga—Se layer will be a function of the Ga and Se distribution as well as the Ga/Se ratio in the layer.

In another embodiment of an electroplating process, a complex waveform in which the applied potential is varied as a function of time is used to deposit the Ga—Se compound. The waveform can be in any functional form such as a sine or cosine waveform, a linear ramp (known in electrochemistry as: Linear Sweep voltammetry), cyclic voltammetry and/or staircase voltammetry.

As described above, electroplating under a constant current or constant voltage for a predetermined amount of time is the most straightforward way of depositing the IIIA-VIA layers using the electrodeposition electrolytes. However, when the constant current density or constant voltage electroplating is compared to pulse electroplating described above, pulse electroplating might be preferable due to several advantages pulse plating provides. First the morphology of the electroplated layer might be controlled more closely with pulse plating which is advantageous for photovoltaic applications. Second the ratio of Ga/Se (on any other metal in solution) might also be controlled by the pulse deposition parameters. Finally, better intermixing of the deposited metals might be achieved since diffusion control deposition of the metal species with the highest deposition rate can be controlled (coupled with the concentration in solution of such species).

FIGS. 12A, 13A and 14A illustrate exemplary electroplating systems 400A-400C to achieve a high throughput continuous fashion electrodeposition at constant voltage or constant current mode to electroplate a IIIA-VIA layer onto a metal layer, including a Cu film and at least one of an In film and Ga film, on a continuous base. The roll-to roll systems 400 electroplate a compound film or IIIA-VIA layer 412 onto a continuous metal layer 402, formed on a continuous base 404 or substrate in a continuous fashion. The IIIA-VIA layer and metal layer have described above. As the metal layer 402 is advanced in a process direction P, it passes through the electroplating chamber 430 including a group IIIA-VIA electroplating solution, such as a Ga—Se electroplating solution 432 and at least one anode 434 immersed into the electroplating solution 432. In the following embodiments, the continuous base 404 including the continuous metal layer will be referred as a web 405. In the following embodiments, the web 405 will be unwrapped from a web supply roll SR; continuously advanced in the process direction ‘P’ and through the electroplating chamber 430 to form the IIIA-VIA layer 412 on a top surface 406 of the web 405, and the web 405 with the IIIA-VIA layer 412 is wound around as take-up roll TR. A DC power supply 440 anodically polarizes the at least one anode 434 and cathodically polarize the web 405 through a conductive brush touching the web during the electroplating process.

FIG. 12A shows a roll-to-roll electroplating system 400A which may be used in either constant voltage or constant current density mode. As shown in FIG. 12A, the web 405 may be electroplated at a constant voltage V1 as it is advanced for a total distance TD which is the length of the electroplating chamber 430. The residence time of the web will be TD/web velocity. In FIG. 12B, a first process graph 450A shows the voltage (V)-distance (D) variation or the voltage profile along the cell length TD. Alternatively, the system 400A may be used to electroplate in the current density mode by replacing the constant voltage V1 with a constant current (J1). In the current mode the first process graph 450A shown in FIG. 12B will become the current density (J) distance (D) variation or the current density profile along the cell length TD.

The systems 400B and 400C, shown FIGS. 13A and 14A, exemplary pulsed voltage or pulsed current density electroplating in a high throughput continuous fashion. FIG. 13A shows a roll-to-roll electroplating system 400B which may be used in either pulsed voltage or current density mode. The system 400B may have a plurality of anodes preferably isolated from one another. In the exemplary system 400B, there are four dividers 442 to confine three anodes 434 as in the manner shown in FIG. 13A. A distance D1 of a first region between the dividers 442A and 442B, and a distance D2 of a second region between the dividers 442C and 442D along the length of the electroplating chamber 430 are not exposed to the anodes 434 and hence the electric field in their confined sections. As shown in FIG. 13A, a second process graph 450B shows the voltage (V)-distance (D) variation or the voltage profile along the length TD of the chamber 430. As shown in the graph 450B, the anodes 434A-434C are held at a constant voltage V1 creating a constant voltage pulsed profile with the first and second regions with no applied potential. The applied electric field from the anodes is limited by the dividers 442 that delimit the applied potential in the first and second regions resulting in no applied potential. Multiple anodes 434 may be placed along the electroplating chamber 430, which are kept at the same voltage; however the spacing between the anodes, i.e. D1, D2 distances, can be changed such that the extend of the region where the electroplating is performed is varied. The dividers 442 delimit the region where the applied potential is reflected over the moving web delimiting the area where the constant potential will be applied. The constant potential at the edges of the anodes 434 will decay very fast and the applied potential will be stopped by the dividers 442. In FIG. 13B, a second process graph 450B shows the voltage (V)-distance (D) variation or the voltage profile along the length TD of the chamber 430. As shown in the graph 450B, the anodes 434A-434C are held at a constant voltage V1 creating a constant voltage pulsed profile with the first and second regions with no applied potential. Alternatively, the system 400B may be used to electroplate in the current density mode by replacing the constant voltage V1 with a constant current J1. In the current mode, the second process graph 450B shown in FIG. 13B will become the current density (J)-distance (D) variation or the current density profile along the length TD of the chamber 430. In the current mode, since the anodes 434A-434C are held at a constant current density, a constant current density pulsed profile with the first and second regions having no applied current will be formed. The implementation of constant voltage or constant current density along a distance over the web will mimic the pulsed electroplating modes such as those shown in FIGS. 10 and 11. Since the time domain is transferred into a distance, the pulse width T1, T2, etc will now be related to the length of the electric field (length of the anode) divided by the speed of the moving web. For example an anode with a length of 0.1 meter with a web speed of 1 meter/sec will be equivalent to a pulse time of a residence time of 0.1 sec. By employing an adequate number of anodes in the electroplating chamber, the total electroplating time will be equal to the number of anodes times the residence time.

FIG. 14A shows another roll-to-roll electroplating system 400C which may be used in either pulsed voltage or current density mode. The system 400C may have a plurality of anodes preferably isolated from one another. Each anode may be kept in a unique potential that is different from the potential of the rest of the anodes if the voltage mode is used, or each anode may be kept in a unique current density that is different from the current density of the rest of the anodes if the current mode is used. In the exemplary system 400C, there are five dividers 442 to confine six anodes 434 as in the manner shown in FIG. 14A. To generate the voltage pulse over the web during the electroplating, first anodes 434A, 434C and 434E may be held at a first potential V1, and second anodes 434B, 434D and 434F may be held at a second potential V2. The first potential V1 applied to the first anodes is different from the second potential V2 applied to the second anodes.

The dividers 442 delimit the region where the applied potential is reflected over the moving web delimiting the regions where the constant potentials V1 and V2 will be applied. In this configuration, first regions with the length D1 include the first anodes 434A, 434C and 434E and the second regions with the length D2 includes the second anodes 434B, 434D and 434F. The lengths D1 and D2 may be the lengths of the first and second anodes respectively. As the web 405 advances in the solution in the process direction ‘P’, it will encounter alternating V1 and V2 constant potentials from the first and second anodes. The lengths D1 and D2 determine the residence time that the moving web will spend on each of the potentials. In this embodiment, for clarity there are only two constant voltages V1 and V2; however a plurality of constant voltages may be used and it is within the scope intended herein.

In FIG. 14B, a third process graph 450C shows the voltage (V)-distance (D) variation or the voltage profile along the length TD of the chamber 430. As shown in the graph 450C, the anodes 434A-434F are held at the constant voltages V1 and V2 as described above to from a constant voltage pulsed profile. As shown in the graph 450C, the voltage is constant at the center position of each anode 434; however, there is a voltage drop near edges of the anodes adjacent the dividers 442. The dividers 442 utilized in this embodiment confine the voltage to a specific region and decrease the possibility of anode cross talk which may create a region where electrochemical reactions between the neighboring anodes may arise. As the web 405 passes through a deposition voltage range between V1 and that of the V2, the web 405 will experience a voltage modulation; which would mimic a pulsed waveform as shown in FIG. 10. A total deposition time can be determined by the web travel speed/TD.

Alternatively, the system 400C may be used to electroplate in the current density mode by replacing the constant voltages V1 and V2 with constant currents densities J1 and J2, where J1 is different from J2. In the current mode, the third process graph 450C shown in FIG. 14B will become the current density (J)-distance (D) variation or the current density profile along the cell length TD. In the current mode, since the anodes 434A-434F are held at the constant current densities J1 and J2 from a constant current density pulsed profile. The current density is constant at the center position of each anode 434; however, there is a current density drop near edges of the anodes adjacent the dividers 442.

Example 1

The Ga—Se solution used was comprised of GaCl3 and H2SeO3 with a pH between 1 and 2.5. The solution also included at least one of the following additive groups of (a): anti-oxidants, (b) anti-floculants, (c) surface-active compounds (d) ionic conductivity enhancers. Electroplating of the Ga—Se layer was conducted on a stainless steel substrate having an Indium terminated top metal layer. The electroplating was done in a batch mode and the cathode was titanium covered with IrO2. The deposition profile consisted of an applied constant voltage of 3.4 V between the anode and the cathode. The total deposition time was 60 sec. The Ga/Se ratio of the resulting film was 1.48. The deposited Ga—Se layers had a smooth and continuous surface with good adhesion properties. The values coefficient of variation (CV=STDEV/Mean Value) were 1.89% and 5.69% of Ga and Se respectively.

Example 2

The Ga—Se solution used was comprised of GaCl3 and H2SeO3 with a pH between 1 and 2.5. The solution also included at least one of the following additive groups of (a): anti-oxidants, (b) anti-flocculants, (c) surface-active compounds (d) ionic conductivity enhancers. Electroplating of the Ga—Se layer was conducted on a stainless steel substrate having an Indium terminated top metal layer. The electroplating was done in a batch mode and the cathode was titanium covered with IrO2. This time a pulsed voltage was applied during plating. The applied potential was modulated between 3.4 V for 500 milliseconds and 2.2 V for 50 milliseconds for a total deposition time of 54 sec. The deposited Ga—Se layers had a smooth and continuous surface with good adhesion properties. The Ga/Se ratio deposited in this case is 1.6. The coefficient of variation (CV=STDEV/Mean Value) are 1.71% and 3.78% of Ga and Se respectively.

Although the embodiments have been particularly described, it should be readily apparent to those of ordinary skill in the art that various changes, modifications and substitutes are intended within the form and details thereof, without departing from their spirit and scope. Accordingly, it will be appreciated that in numerous instances some features will be employed without a corresponding use of other features. Further, those skilled in the art will understand that variations can be made in the number and arrangement of components illustrated in the above figures.

Claims

1. A method of forming an absorber layer over a surface of a base, the method comprising:

forming a metal layer over the surface of the base, wherein the metal layer comprises a Group IIIA material;
co-depositing Group IIIIA and Group VA materials to form a Group IIIA-VIA layer on the metal layer using pulse electroplating that varies an electroplating pulse between a first higher value and a second lower value, wherein at the first higher value electroplating of at least one of Ga and In predominates, and wherein at the second lower value electroplating of one of Se, Te and S predominates, wherein the step of co-depositing the Group IIIA-VIA layer uses a roll-to-roll electroplating process wherein the base having the metal layer is continuously advanced within an electroplating solution held in a deposition chamber as at least one electric field is formed between at least one anode to deposit the Group IIIA-VIA layer onto the metal layer; and
reacting the metal layer and the Group IIIA-VIA layer to form the absorber layer.

2. The method of claim 1 wherein the Group IIIA-VIA layer is one of a Ga—Se alloy, In—Se and In—Ga—Se alloy.

3. The method of claim 1 wherein the Group IIIA-VIA layer is one of a Ga—Te alloy, In—Te and In—Ga—Te alloy.

4. The method of claim 1 wherein the Group IIIA-VIA layer is one of a Ga—S alloy, In—S and In—Ga—S alloy.

5. The method of claim 1 wherein the Group IIIA-VIA layer is one of a Ga—Se—Te alloy, In—Se—Te and In—Ga—Se—Te alloy.

6. The method of claim 1 wherein the Group IIIA-VIA layer is one of a Ga—Se—S, In—Se—S and In—Ga—Se—S alloy.

7. The method of claim 1 wherein the Group IIIA-VIA layer is one of a Ga—Te—S, In—Te—S and In—Ga—Te—S alloy.

8. The method of claim 1 wherein the Group IIIA-VIA layer is one of a Ga—Se—Te—S, In—Se—Te—S and In—Ga—Se—Te—S alloy.

9. The method of claim 1, wherein the step of forming the metal layer comprises forming an In-layer.

10. The method of claim 9, wherein the absorber layer is a CIS absorber.

11. The method of claim 1, wherein the step of forming the metal layer comprises forming a film stack comprising: a Cu film formed on the base, a Ga film formed on the Cu film and an In film formed on the Ga film.

12. The method of claim 11, wherein the absorber layer is a CIGS absorber.

13. The method of claim 1, wherein the pulse electroplating technique'includes varying an electroplating voltage between a first voltage value as the first higher value and a second voltage value as the second lower value.

14. The method of claim 13 wherein a voltage range between the first voltage value and the second voltage value is in the range of 0 and 20 volts.

15. The method of claim 13 wherein each pulse of the pulse electroplating has a duration that is in the range of 1E-7-360 sec.

16. The method of claim 1, wherein the pulse electroplating technique includes varying an electroplating current density between a first current density value as the first higher value and a second current density value as the second lower value.

17. The method of claim 16 wherein a current density range between the first current density value and the second current density value is between 0 and 200 mA/cm2.

18. The method of claim 1, wherein the at least one anode includes a plurality of anodes positioned along the deposition chamber so as to apply a plurality of electric fields during the electroplating as the base having the metal layer advanced in process direction across from the plurality of anodes;

19. The method of claim 18, wherein each anode is isolated from adjacent anodes by anode separators so as to isolate the electric field of each anode from the electric fields of the adjacent anodes.

20. The method of claim 1, wherein the electroplating solution comprises:

a solvent, a Group IIIA material source that provides Ga in ionic form in the solvent, a Group VIA material source that dissolves in the solvent and provides Se in ionic form, an anti-oxidant, an anti-flocculant, a pH adjuster including at least one of an organic acid, an inorganic acid, an organic base and an inorganic base, additives including at least one of an anti-oxidant, an anti-flocculant, a surface-active compound and an ionic conductivity enhancer and wherein the pH of the solution is in the range of 0.5-13.

21. The method of claim 1, wherein the Group IIIA-VIA layer includes at least one of a mixture of the Group IIIA and Group VIA materials and an alloy of the Group IIIA and Group VIA materials.

22. An electroplating solution for deposition of a Group IIIA-Group VIA thin film on a Group IIIA material surface, the electroplating solution comprising:

a solvent;
a Group IIIA material source that provides Ga in ionic form in the solvent;
a Group VIA material source that dissolves in the solvent and provides Se in ionic form;
an anti-oxidant;
an anti-flocculant;
a pH adjuster including at least one of an organic acid, an inorganic acid, an organic base and an inorganic base;
additives including at least one of a surface-active compound, a complexing agent and an ionic conductivity enhancer;
wherein the pH of the solution is in the range of 0.5-13.

23. The electroplating solution of claim 22, wherein the pH is in the range of 0.0.5-4.

24. The electroplating solution of claim 22, wherein the pH is in the range of 0.0.8-2.5.

25. The electroplating solution of claim 22, wherein the anti-oxidant includes at least one of hydroquinone, pyrocatechol, gallic acid; 4-Amino-4H-1,2,4-triazole, 4,5-Imidazoledicarboxylic acid; dextrose, saccharin, fructose; hydroquinone sulfonic; ethanol, methanol, glycerol and ethylenglycol.

26. The electroplating solution of claim 22, wherein the anti-flocculant includes at least one of dipotassium phosphate, ammonium dihydrogen phosphate, ammonium hexafluorophosphate, calcium phosphate, potassium metaphosphate, potassium phosphate, potassium triphosphate, potassium hexafluorophosphate, potassium hydrogen phosphate and sodium hydrogen phosphate, diethyl dithiophosphate, diethyl dithiophosphate, ammonium salt, Tetrabutylammonium hexafluorophosphate, polyethylene glycol, 1-Hydroxyethylidenebis(phosphonic acid), methylenediphosphonic acid and diethylenediamine.

27. The electroplating solution of claim 22, wherein the surface-active compound includes at least one of melamine, dopamine hydrochloride; (HEPES) 4-(2-Hydroxyethyl)piperazine-1-ethanesulfonic acid; 1,3,5-Triazine-2,4,6-trithiol trisodium Sodium Dodecyl Sulfate, n-Dodecylamine, Sodium n-octyl sulfate, Pluronic P123, Pluronic F127, Brij 35.

28. The electroplating solution of claim 22, wherein the ionic conductivity enhancer includes at least one of NaCl, Na2SO4, KCl, K2SO4, H4ClN, and (NH4)2SO4.

29. The electroplating solution of claim 22, wherein a molar ratio of Group IIIA/Group IIIA+VIA is in the range of 0 to 1.

30. The electroplating solution of claim 22, wherein the pH adjuster is selected from the group including sulfuric acid, hydrochloric acid, phosphoric acid, ethylenediaminetetraacetic acid, malonic acid, malic acid, nitrilotriacetic acid, succinic acid, maleic acid, oxalic acid, tartaric acid, citric acid, sulfamic acid, hydroxyethylethylenediaminetriacetic acid, NaOH, KOH, NH4OH, organic amines such as methylamine and trimethylamine, tetramethylammonium hydroxide and tetrabutylammonium hydroxide, pyridine, imidazole, benzimidazole, histidine and phosphazene.

31. The electroplating solution of claim 22, wherein the complexing agent is selected from the group including tartaric acid, citric acid, acetic acid, malonic acid, malic acid, succinic acid, ethylenediamine, ethylenediaminetetraacetic acid, nitrilotriacetic acid, and hydroxyethylethylenediaminetriacetic acid.

Patent History
Publication number: 20130112564
Type: Application
Filed: Oct 4, 2012
Publication Date: May 9, 2013
Applicant: SOLOPOWER, INC. (San Jose, CA)
Inventor: SOLOPOWER, INC. (San Jose, CA)
Application Number: 13/645,459
Classifications
Current U.S. Class: Nonreversing Pulsed Current Or Voltage (205/104); Depositing Predominantly Alloy Coating (205/238)
International Classification: C25D 3/56 (20060101); C25D 5/18 (20060101);