Utilizing Compound Semiconductor Patents (Class 438/285)
  • Patent number: 10679900
    Abstract: A method includes forming Shallow Trench Isolation (STI) regions in a semiconductor substrate and a semiconductor strip between the STI regions. The method also include replacing a top portion of the semiconductor strip with a first semiconductor layer and a second semiconductor layer over the first semiconductor layer. The first semiconductor layer has a first germanium percentage higher than a second germanium percentage of the second semiconductor layer. The method also includes recessing the STI regions to form semiconductor fins, forming a gate stack over a middle portion of the semiconductor fin, and forming gate spacers on sidewalls of the gate stack. The method further includes forming fin spacers on sidewalls of an end portion of the semiconductor fin, recessing the end portion of the semiconductor fin, and growing an epitaxial region over the end portion of the semiconductor fin.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Chiang, Ting-Hung Hsu, Chao-Hsiung Wang, Chi-Wen Liu
  • Patent number: 10658489
    Abstract: A semiconductor device and a fabrication method are provided. The fabrication method includes providing a gate structure on a substrate and a first protective layers on the gate structure; forming an initial sidewall spacer on a sidewall of each of the gate structure and the first protective layer; forming a first sidewall spacer on a sidewall of the initial sidewall spacer, the first and initial sidewall spacers being made of different materials; forming a second sidewall spacer by removing a portion of the initial sidewall spacer, leaving a trench formed above the second sidewall spacer and between the first sidewall spacer and the first protective layer; and forming a second protective layer in the trench, the second protective layer and the first sidewall spacer being made of a same material. The second sidewall spacer has a top surface higher than or level with a top surface of the gate structure.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: May 19, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Er Hu Zheng, Lu Jun Zou
  • Patent number: 10651287
    Abstract: A semiconductor structure includes a substrate, a semiconductor fin connected to the substrate, an epitaxial layer disposed over the semiconductor fin, and a silicide feature over and in contact with the epitaxial layer. The epitaxial layer including silicon germanium (SiGe) and further includes gallium (Ga) in an upper portion of the epitaxial layer that is in contact with the silicide feature.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: May 12, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shahaji B. More, Chun Hsiung Tsai, Shih-Chieh Chang, Kuo-Feng Yu, Cheng-Yi Peng
  • Patent number: 10593672
    Abstract: A method for manufacturing a semiconductor device includes growing a first strained semiconductor layer on a substrate, the first strained semiconductor layer having a first type of strain, wherein the substrate comprises a first crystalline orientation at a top surface of the substrate, forming at least one trench in the substrate, wherein exposed sidewalls of the at least one trench have a second crystalline orientation different from the first crystalline orientation, growing a buffer layer in the at least one trench from the exposed sidewalls of the trench, and growing a second strained semiconductor layer on the buffer layer, the second strained semiconductor layer having a second type of strain, wherein the first type of strain is different from the second type of strain.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: March 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Juntao Li, Kangguo Cheng, John G. Gaudiello
  • Patent number: 10573737
    Abstract: A transistor structure includes a substrate. A gate structure is disposed on the substrate. A hexagonal-shaped trench is disposed in the substrate at one side of the gate structure. A first epitaxial layer including first-type dopants is disposed in the hexagonal-shaped trench and contacts the hexagonal-shaped trench. A second epitaxial layer including second-type dopants is disposed in the hexagon-shaped trench. The first epitaxial layer is outside of the second epitaxial layer. The second epitaxial layer serves as a source/drain doped region of the transistor structure. The first-type dopants and the second-type dopants are of different conductive types.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: February 25, 2020
    Assignee: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: Sheng-Hsu Liu, Shih-Hsien Huang, Wen Yi Tan
  • Patent number: 10504771
    Abstract: A method for manufacturing a semiconductor device includes: forming a sacrificial layer on a first substrate, the sacrificial layer being made of a material whose lattice constant is different from that of germanium (Ge) by a preset threshold or below; forming a germanium (Ge) layer on the sacrificial layer; forming an insulation layer on a second substrate; bonding the germanium (Ge) layer onto the insulation layer; and removing the sacrificial layer and the first substrate by etching the sacrificial layer in a state where the germanium (Ge) layer is bonded to the insulation layer. In this method, a germanium-on-insulator (GeOI) structure having various surface orientations may be formed by means of epitaxial lift-off (ELO), and a strain may be applied to the germanium (Ge) layer using a lattice constant of the sacrificial layer.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: December 10, 2019
    Assignee: Korea Institute of Science and Technology
    Inventors: Hyung-Jun Kim, Sanghyeon Kim, Jae-Phil Shim, Yeon-Su Kim, Heejeong Lim
  • Patent number: 10439039
    Abstract: An integrated circuit includes a FinFET and a nanostructure FET. The integrated circuit includes a bulk substrate. The integrated circuit also includes a fin field effect transistor (FinFET) coupled to the bulk substrate. The FinFET includes a first source region, a first drain region, and a fin extending between the first source region and the first drain region. The integrated circuit also includes a nanostructure FET coupled to the bulk substrate. The nanostructure FET includes a second source region, a second drain region, and a stack of at least two nanostructures extending between the second source region and the second drain region.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: October 8, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Stanley Seungchul Song, Jeffrey Junhao Xu, Kern Rim, Choh Fei Yeap
  • Patent number: 10411007
    Abstract: Monolithic FETs including a channel region in a first semiconductor material disposed over a substrate. While a mask, such as a gate stack or sacrificial gate stack, is covering a channel region, a semiconductor spacer of a semiconductor material with a band offset relative to the channel material is grown, for example on at least a drain end of the channel region to introduce at least one charge carrier-blocking band offset between the channel semiconductor and a drain region of a third III-V semiconductor material. In some N-type transistor embodiments, the carrier-blocking band offset is a conduction band offset of at least 0.1 eV. A wider band gap and/or a blocking conduction band offset may contribute to reduced gate induced drain leakage (GIDL). Source/drain regions couple electrically to the channel region through the semiconductor spacer, which may be substantially undoped (i.e. intrinsic) or doped.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: September 10, 2019
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Willy Rachmady, Matthew V. Metz, Chandra S. Mohapatra, Sean T. Ma, Jack T. Kavalieros, Anand S. Murthy, Tahir Ghani
  • Patent number: 10366891
    Abstract: A vertical semiconductor apparatus includes: a gallium nitride substrate; a gallium nitride semiconductor layer on the gallium nitride substrate; a p-type impurity region in the gallium nitride semiconductor layer and having an element to function as an acceptor for gallium nitride; an n-type impurity region in the p-type impurity region and having an element to function as a donor for gallium nitride; and an electrode provided contacting a rear surface of the gallium nitride substrate. The element to function as the donor in the n-type impurity region includes: a first impurity element to enter sites of gallium atoms in the gallium nitride semiconductor layer; and a second impurity element different from the first impurity element and to enter sites of nitrogen atoms in the gallium nitride semiconductor layer. In the n-type impurity region, a concentration of the first impurity element is higher than that of the second impurity element.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: July 30, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Shinya Takashima, Katsunori Ueno, Masaharu Edo
  • Patent number: 10355102
    Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes semiconductor wires disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires, a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region, and dielectric spacers disposed in recesses formed toward the source/drain epitaxial layer.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: July 16, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, Yu-Lin Yang, Wei-Sheng Yun, Chen-Feng Hsu, Tzu-Chiang Chen
  • Patent number: 10249739
    Abstract: A method is presented for forming a nanosheet metal oxide semiconductor field effect transistor (MOSFET) structure. The method includes forming a heteroepitaxial film stack including at least one sacrificial layer and at least one channel layer, patterning the heteroepitaxial film stack, forming a dummy gate stack with sidewall spacers, and forming a cladded or embedded epitaxial source/drain material along the patterned heteroepitaxial film stack sidewalls. The method further includes removing the dummy gate stack, partially removing the at least one sacrificial layer, and forming a replacement gate stack.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael A. Guillorn, Terence B. Hook, Nicolas J. Loubet, Robert R. Robison, Reinaldo A. Vega
  • Patent number: 10249722
    Abstract: A FET device fabricated by providing a first conductor on a substrate, the first conductor having a first top surface with a first height above the substrate. A second conductor is provided adjacent the first conductor, the second conductor having a second top surface with a second height above the substrate. A portion of the second conductor is removed to provide a slot, wherein the slot is defined by opposing interior sidewalls and a bottom portion, such that the bottom portion of the slot is below the first height of the first conductor. An insulating material is deposited in the slot, the insulating material having a third top surface with a third height above the substrate, the third height being below the second height of the second conductor to provide space within the slot for a third conductor. The space within the slot is then filled with the third conductor.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10204990
    Abstract: A semiconductor device includes an N-type silicon carbide substrate, an N-type silicon carbide layer formed on the N-type silicon carbide substrate, a P-type region selectively formed in a surface layer of the N-type silicon carbide layer, an N-type source region formed in the P-type region, a P contact region formed in the P-type region, a gate insulating film formed on a portion of a region from the N-type source region, through the P-type region, to the N-type silicon carbide layer, a gate electrode formed on the gate insulating film, an interlayer insulating film covering the gate electrode, and a first source electrode electrically connected to a surface of the P contact region and the N-type source region. An end of the interlayer insulating film covering the gate electrode has a slope of a predetermined angle.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: February 12, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yuichi Harada, Yasuyuki Hoshi, Akimasa Kinoshita, Yasuhiko Oonishi
  • Patent number: 10199501
    Abstract: A method for manufacturing a semiconductor structure includes the following steps. First, a semiconductor substrate including a first semiconductor material is provided. The semiconductor substrate includes a dielectric structure formed thereon, and the dielectric structure includes at least a recess formed therein. A first epitaxial layer is then formed in the recess. The first epitaxial layer includes at least a second semiconductor material that a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. Subsequently, a thermal oxidation process is performed to the first epitaxial layer thereby forming a semiconductor layer at a bottom of the recess and a silicon oxide layer on the semiconductor layer. After removing the silicon oxide layer, a second epitaxial layer is formed on the semiconductor layer in the recess.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: February 5, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Chung-Yi Chiu
  • Patent number: 10181527
    Abstract: A field effect transistor (FET) structure includes: a gate; a first spacer having a first dielectric constant at a first region adjacent to the gate; and a second spacer having a second dielectric constant that is greater than the first dielectric constant at a second region adjacent to the gate.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: January 15, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dharmendar Reddy Palle, Borna Obradovic, Joon Goo Hong, Mark Rodder
  • Patent number: 10170549
    Abstract: Exemplary embodiments provide for fabricating a nanosheet stack structure having one or more sub-stacks.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: January 1, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jorge A. Kittl, Borna J. Obradovic, Robert C. Bowen, Mark S. Rodder
  • Patent number: 10164015
    Abstract: Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Matthew T. Currie, Anthony J. Lochtefeld, Richard Hammond, Eugene A. Fitzgerald
  • Patent number: 10164038
    Abstract: A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopant and a second dopant, and the second dopant comprises a group V material.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Han-Chin Chiu, Chen-Hao Chiang, Chi-Ming Chen, Chung-Yi Yu
  • Patent number: 10158004
    Abstract: Some embodiments of the present disclosure relates to a method of forming a semiconductor device having a strained channel and an associated device. In some embodiments, the method includes performing a first etching process by selectively exposing a substrate to a first etchant to produce a recess defined by sidewalls and a bottom surface of the substrate. An implantation process is performed to form an etch stop layer along the bottom surface. A second etching process is performed by exposing the sidewalls and the bottom surface defining the recess to a second etchant to form a source/drain recess. The source/drain recess laterally extends past the etch stop layer in opposing directions. A semiconductor material is formed within the source/drain recess.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Hsuing Chen, Ling-Sung Wang, Chi-Yen Lin
  • Patent number: 10141406
    Abstract: A tensile strained silicon layer and a compressively strained silicon germanium layer are formed on a strain relaxed silicon germanium buffer layer substrate. A relaxed silicon layer is formed on the substrate and the compressively strained silicon germanium layer is formed on the relaxed silicon layer. The compressively strained silicon germanium layer can accordingly have approximately the same concentration of germanium as the underlying strain relaxed buffer layer substrate, which facilitates gate integration. The tensile strained silicon layer and the compressively strained silicon germanium layer can be configured as fins used in the fabrication of FinFET devices. The relaxed silicon layer and a silicon germanium layer underlying the tensile silicon layer can be doped in situ to provide punch through stop regions adjoining the fins.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: November 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Keith E. Fogel, Pouya Hashemi, Alexander Reznicek
  • Patent number: 10083965
    Abstract: The semiconductor device includes a substrate comprising first and second regions, in the first region, first and second gate electrodes formed parallel to each other on the substrate, and being spaced apart from each other by a first distance, in the second region, third and fourth gate electrodes formed parallel to each other on the substrate, and being spaced apart from each other by a second distance which is greater than the first distance, in the first region, a first recess formed on the substrate between the first and second gate electrodes, in the second region, a second recess formed on the substrate between the third and fourth gate electrodes, a first epitaxial source/drain filling the first recess and a second epitaxial source/drain filling the second recess, wherein an uppermost portion of an upper surface of the first epitaxial source/drain is higher than an uppermost portion of an upper surface of the second epitaxial source/drain.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: September 25, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki Hwan Kim, Gi Gwan Park, Jung Gun You, Dong Suk Shin, Hyun Yul Choi
  • Patent number: 10079181
    Abstract: A method of forming a semiconductor structure includes forming a dummy gate above a semiconductor substrate. The dummy gate defines a source-drain region adjacent to the dummy gate and a channel region below the dummy gate. A silicon-germanium layer is epitaxially grown above the source-drain region with a target concentration of germanium atoms. The semiconductor structure is annealed to diffuse the germanium atoms from the silicon-germanium layer into the channel region to form a silicon-germanium channel region.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: September 18, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Ghavam G. Shahidi
  • Patent number: 9978843
    Abstract: An embodiment of a silicon carbide semiconductor device includes one or more inner cells each having a MOSFET and one or more outer peripheral cells that does not have a MOSFET structure, and the area (surface area) of the p+ contact region of each of the outermost peripheral cells is less than the surface area of an p+ contact region of each of the inner cells, for example, so that a unit total resistance of p+ contact regions of the outermost peripheral cells, as measured in a depth direction of the semiconductor substrate with respect to a unit area in a surface of the semiconductor substrate, is greater than a unit total resistance of the p+ contact regions of the inner cells, as measured in the depth direction of the semiconductor substrate with respect to the unit area in the surface of the semiconductor substrate.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: May 22, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Ryohei Takayanagi, Hiroki Wakimoto
  • Patent number: 9947788
    Abstract: A method includes forming a gate electrode structure above a channel region defined in a semiconductor material. The semiconductor material is recessed in a source/drain region. A first material is epitaxially grown in the source/drain region. The first material includes a dopant species having a first concentration. A diffusion blocking layer is formed in the source/drain region above the first material. A second material is epitaxially grown in the source/drain region above the diffusion blocking layer. The second material comprises the dopant species having a second concentration greater than the first concentration.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: April 17, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Shesh Mani Pandey, Pei Zhao, Baofu Zhu, Francis L. Benistant
  • Patent number: 9917191
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming a gate dielectric over the semiconductor wafer, and forming a gate over the gate dielectric. At least one recess is formed in the semiconductor wafer proximate the gate and the gate dielectric, at least a portion of the at least one recess extending beneath the gate. The at least one recess in the semiconductor wafer is filled with a semiconductive material.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: March 13, 2018
    Assignee: Infineon Technologies AG
    Inventors: Manfred Eller, Jin-Ping Han
  • Patent number: 9881821
    Abstract: A control wafer making device, a method of measuring an epitaxy thickness in a control wafer, and a method for monitoring a control wafer are provided. In various embodiments, the control wafer making device includes a wafer substrate removing element and an epitaxy forming element. In various embodiments, a control wafer includes a substrate, a recess, a blocking layer, and an epitaxy. The substrate has a surface, and the recess is in the surface of the substrate. The blocking layer is over the surface of the substrate other than the recess. The epitaxy is in the recess. In various embodiments, the thickness of the epitaxy of the control wafer is measured by a polarized light.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: January 30, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Wei Hung, Chia-Chiung Lo, Chien-Feng Lin
  • Patent number: 9853153
    Abstract: The present invention provides a method of manufacturing a fin field effect transistor, comprising: providing an SOI substrate comprising a substrate layer (100), a BOX layer (120) and an SOI layer (130); forming a basic fin structure from an SOI layer; forming source/drain regions (110) on both sides of the basic fin structure; forming a fin structure between the source/drain regions (110) from a basic fin structure; and forming a gate stack across the fin structure. The method of manufacturing a fin field effect transistor provided in the present invention can integrate a high-k gate dielectric layer, a metal gate, and stressed source/drain regions into the fin field effect transistor to enhance the performance of the semiconductor device.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: December 26, 2017
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Huilong Zhu, Zhijiong Luo, Haizhou Yin, Qingqing Liang
  • Patent number: 9799508
    Abstract: A process of forming a nitride semiconductor device is disclosed. The process includes steps of (a) implanting impurities into a portion of nitride semiconductor layers epitaxially grown on a substrate; (b) forming a silicon nitride (SiN) film on the nitride semiconductor layers; and (c) annealing the nitride semiconductor layers for activating the implanted impurities as covering the nitride semiconductor layers by the SiN film. The process has a feature that the SiN film shows, in a Fourier Transformation Infrared (FT-IR) spectroscopy measured before the step of annealing, absorbance peaks attributed to translational motions of a Si—H bond and an N—H bond at most 1/30 of an absorbance peak attributed to a SiN bond.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: October 24, 2017
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Masatoshi Koyama
  • Patent number: 9728534
    Abstract: A method of forming a fin-based field-effect transistor device includes forming one or more first fins comprising silicon on a substrate, forming epitaxial layers on sides of the one or more first fins, and removing the one or more first fins to form a plurality of second fins.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: August 8, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hong He, Chiahsun Tseng, Chun-Chen Yeh, Yunpeng Yin
  • Patent number: 9728671
    Abstract: An optoelectronic light emission device is provided that includes a gain region of at least one type III-V semiconductor layer that is present on a lattice mismatched semiconductor substrate. The gain region of the type III-V semiconductor layer has a nanoscale area using nano-cavities. The optoelectronic light emission device is free of defects.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: August 8, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Effendi Leobandung, Ning Li, Tak H. Ning, Jean-Oliver Plouchart, Devendra K. Sadana
  • Patent number: 9679990
    Abstract: Semiconductor structures and methods of fabrication are provided, with one or both of an extended source-to-channel interface or an extended drain-to-channel interface. The fabrication method includes, for instance, recessing a semiconductor material to form a cavity adjacent to a channel region of a semiconductor structure being fabricated, the recessing forming a first cavity surface and a second cavity surface within the cavity; and implanting one or more dopants into the semiconductor material through the first cavity surface to define an implanted region within the semiconductor material, and form an extended channel interface, the extended channel interface including, in part, an interface of the implanted region within the semiconductor material to the channel region of the semiconductor structure. In one embodiment, the semiconductor structure with the extended channel interface is a FinFET.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: June 13, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Edmund Kenneth Banghart, Mitsuhiro Togo, Shesh Mani Pandey
  • Patent number: 9666583
    Abstract: An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: May 30, 2017
    Assignee: Intel Corporation
    Inventors: Niti Goel, Ravi Pillarisetty, Niloy Mukherjee, Robert S. Chau, Willy Rachmady, Matthew V. Metz, Van H. Le, Jack T. Kavalieros, Marko Radosavljevic, Benjamin Chu-Kung, Gilbert Dewey, Seung Hoon Sung
  • Patent number: 9647166
    Abstract: According to example embodiments, an electronic device includes a substrate, an insulating layer on the substrate, and a diode layer on the insulating layer. The diode layer includes a two dimensional (2D) material layer. The 2D material layer includes an N-type region and a P-type region. According to example embodiments, a method of manufacturing an electronic device includes forming an insulating film on a substrate, forming a 2D material layer on the insulating film, and dividing the 2D material layer into an N-type region and a P-type region.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: May 9, 2017
    Assignees: Samsung Electronics Co., Ltd., Research & Business Foundation Sungyunkwan University
    Inventors: Minsup Choi, Wonjong Yoo, Deshun Qu, Changho Ra, Xiaochi Liu, Seunghwan Lee, Jia Lee
  • Patent number: 9590037
    Abstract: A method of forming a semiconductor structure includes forming a dummy gate above a semiconductor substrate. The dummy gate defines a source-drain region adjacent to the dummy gate and a channel region below the dummy gate. A silicon-germanium layer is epitaxially grown above the source-drain region with a target concentration of germanium atoms. The semiconductor structure is annealed to diffuse the germanium atoms from the silicon-germanium layer into the channel region to form a silicon-germanium channel region.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: March 7, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Ghavam G. Shahidi
  • Patent number: 9583378
    Abstract: A structure including a first semiconductor material portion and a second semiconductor material portion is provided. An oxygen impermeable hard mask is then formed directly on a surface of the first semiconductor material portion. Next, a silicon germanium layer is epitaxially formed on the second semiconductor material portion, but not the first semiconductor material portion. An oxygen permeable hard mask is then formed over the first and second semiconductor material portions. A thermal condensation process is then performed which converts the second semiconductor material portion into a germanium-containing semiconductor material portion. The oxygen permeable hard mask and the oxygen impermeable hard mask are then removed. A functional gate structure can be formed atop the remaining first semiconductor material portion and the thus formed germanium-containing semiconductor material portion.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: February 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Ghavam G. Shahidi
  • Patent number: 9525027
    Abstract: A lateral bipolar junction transistor is fabricated using a semiconductor-on-insulator substrate. The transistor includes a germanium gradient within a doped silicon base region, there being an increasing germanium content in the direction of the collector region of the transistor. The use of a substrate including parallel silicon fins to fabricate lateral bipolar junction transistors facilitates the inclusion of both CMOS FinFET devices and lateral bipolar junction transistors having graded silicon germanium base regions on the same chip.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: December 20, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Pouya Hashemi, Ali Khakifirooz, Darsen D. Lu, Alexander Reznicek, Dominic J. Schepis
  • Patent number: 9525054
    Abstract: A High Electron Mobility Transistor (HEMT) includes a first III-V compound layer having a first band gap, and a second III-V compound layer having a second band gap over the first III-V compound layer. The second band gap is smaller than the first band gap. The HEMT further includes a third III-V compound layer having a third band gap over the second III-V compound layer, wherein the third band gap is greater than the first band gap. A gate electrode is formed over the third III-V compound layer. A source region and a drain region are over the third III-V compound layer and on opposite sides of the gate electrode.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: December 20, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hao Chiang, Po-Chun Liu, Han-Chin Chiu, Chi-Ming Chen, Chung-Yi Yu
  • Patent number: 9514990
    Abstract: Methods for manufacturing a semiconductor device including a field effect transistor include forming first fins protruding from a substrate including a first region and a second region, the first fins including silicon-germanium (SiGe), forming a first mask pattern to expose the first fins disposed in the second region, the first mask pattern covering the first fins disposed in the first region, oxidizing the first fins in the second region to form second fins in the second region, and forming germanium (Ge)-rich layers each disposed on a surface of a respective one of the second fins.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: December 6, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bin Liu, Sungmin Kim
  • Patent number: 9502415
    Abstract: The disclosed technology generally relates to complementary metal-oxide-silicon (CMOS) devices, and more particularly to an n-channel metal-oxide-silicon (nMOS) device and a p-channel metal-oxide-silicon (pMOS) device that are under different types of strains. In one aspect, a method comprises providing trenches in a dielectric layer on a semiconductor substrate, where at least a first trench defines an nMOS region and a second trench defines a pMOS region, and where the trenches extend through the dielectric layer and abut a surface of the substrate. The method additionally includes growing a first seed layer in the first trench on the surface and growing a common strain-relaxed buffer layer in the first trench and the second trench, where the common strain-relaxed buffer layer comprises silicon germanium (SiGe). The method further includes growing a common channel layer comprising germanium (Ge) in the first and second trenches and on the common strain-relaxed buffer layer.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: November 22, 2016
    Assignee: IMEC VZW
    Inventors: Roger Loo, Jerome Mitard, Liesbeth Witters
  • Patent number: 9461043
    Abstract: A semiconductor device includes a substrate, a first gate, a second gate, and an insulating structure. The substrate includes a first fin and a second fin. The first gate is disposed over the first fin. The second gate is disposed over the second fin. A gap is formed between the first gate and the second gate, and the gap gets wider toward the substrate. The insulating structure is disposed in the gap. The insulating structure has a top surface and a bottom surface opposite to each other. The bottom surface faces the substrate. An edge of the top surface facing the first gate is curved inward the top surface.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: October 4, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Wei-Ting Chen
  • Patent number: 9373705
    Abstract: The present invention provides a manufacturing method of a fin-shaped field effect transistor (FinFET), comprises the following steps. Firstly, providing a substrate having a fin structure; forming a gate structure on the fin structure perpendicular to a extending direction of the fin structure; performing an amorphous implantation to form an amorphous layer on a exposed portion of the fin structure exposed by the gate structure and a light-doping implantation; forming a sacrificial spacer on sides of the gate structure covering a portion of the amorphous layer on the fin structure; forming a trench on the fin structure adjacent to the sacrificial spacer; growing an alloy in the trench; and then removing the sacrificial spacer. The invention also provides a FinFET device thereof.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: June 21, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Chun-Yu Chen, Chung-Ting Huang, Ming-Hua Chang, Tien-Chen Chan, Yen-Hsing Chen, Hsin-Chang Wu
  • Patent number: 9362387
    Abstract: A method for producing a multi-gate fin field-effect transistor (FinFET) is provided. The method includes forming a channel layer and a gate medium layer on a substrate; forming an amorphous silicon layer on the substrate, and etching the amorphous silicon layer, to form at least one fin; forming, by using an epitaxial growth process, a first protective layer from both sides to the middle of the substrate along a length direction of the at least one fin until a groove is formed in a middle location along the length direction of the at least one fin; forming a gate electrode layer on the substrate, performing planarization processing on the gate electrode layer to expose the first protective layer, and etching away the first protective layer by using an etching process, so as to form a gate electrode; and forming a source electrode and a drain electrode on the substrate.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: June 7, 2016
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Jing Zhao
  • Patent number: 9349831
    Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: May 24, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Huan Tsai, Chun-Fai Cheng, Hui Ouyang, Yuan-Hung Chiu, Yen-Ming Chen
  • Patent number: 9343563
    Abstract: Methods for forming a HEMT device are provided. The method includes forming an ultra-thin barrier layer on the plurality of thin film layers. A dielectric thin film layer is formed over a portion of the ultra-thin barrier layer to leave exposed areas of the ultra-thin barrier layer. A SAG S-D thin film layer is formed over the exposed areas of the ultra-thin barrier layer while leaving the dielectric thin film layer exposed. The dielectric thin film layer is then removed to expose the underlying ultra-thin barrier layer. The underlying ultra-thin barrier layer is treating with fluorine to form a treated area. A source and drain is added on the SAG S-D thin film layer, and a dielectric coating is deposited over the ultra-thin barrier layer treated with fluorine such that the dielectric coating is positioned between the source and the drain.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: May 17, 2016
    Assignee: University of South Carolina
    Inventors: Asif Khan, Qhalid Fareed, Vinod Adivarahan
  • Patent number: 9293554
    Abstract: Metal semiconductor alloy contacts are provided on each of a source region and a drain region which are present in a semiconductor substrate. A transition metal is then deposited on each of the metal semiconductor alloy contacts, and during the deposition of the transition metal, the deposited transition metal reacts preferably, but not necessarily always, in-situ with a portion of each the metal semiconductor alloy contacts forming a transition metal-metal semiconductor alloy liner atop each metal semiconductor alloy contact. Each transition metal-metal semiconductor alloy liner that is provided has outer edges that are vertically coincident with outer edges of each metal semiconductor alloy contact. The transition metal-metal semiconductor alloy liner is more etch resistant as compared to the underlying metal semiconductor alloy. As such, the transition metal-metal semiconductor alloy liner can serve as an effective etch stop layer during any subsequently performed etch process.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: March 22, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Nicolas Breil, Christian Lavoie, Ahmet S. Ozcan, Kathryn T. Schonenberg, Jian Yu
  • Patent number: 9293327
    Abstract: The invention relates to a method by means of which the average single crystal size, in particular the diameter of the single crystals, in a semiconductor thin film applied to a foreign substrate can be increased by an order of magnitude with respect to prior methods. The method is characterized in that a thin semiconductor film is applied to the foreign substrate in a first step. Then the foreign substrate is heated to such an extent that the semiconductor thin film melts. Then the temperature is slowly decreased to below the melting temperature of the semiconductor material. During the cooling process, the foreign substrate is heated in such a way that, proceeding from the surface of the foreign substrate, the temperature continuously decreases in a vertical direction perpendicular through the semiconductor thin film to the surface of the thin film.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: March 22, 2016
    Assignee: Solar Carbide S.à.r.l.
    Inventor: Jean-Paul Theis
  • Patent number: 9263342
    Abstract: The present disclosure provides devices and methods which provide for strained epitaxial regions. A method of semiconductor fabrication is provided that includes forming a gate structure over a fin of a semiconductor substrate and forming a recess in the fin adjacent the gate structure. A sidewall of the recess is then altered. Exemplary alterations include having an altered profile, treating the sidewall, and forming a layer on the sidewall. An epitaxial region is then grown in the recess. The epitaxial region interfaces the altered sidewall of the recess and is a strained epitaxial region.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: February 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Lin Lee, Feng Yuan, Hung-Li Chiang, Chih Chieh Yeh
  • Patent number: 9236259
    Abstract: A method of manufacturing a semiconductor device having a doped layer may be provided. The method includes providing a substrate having a first region and a second region, forming a gate dielectric layer on the substrate, forming a first gate electrode layer on the gate dielectric layer, forming a first doped layer on the first gate electrode layer, forming a first capping layer on the first doped layer, forming a mask pattern on the first capping layer in the first region, the mask pattern exposing the first capping layer in the second region, removing the first capping layer and the first doped layer in the second region, removing the mask pattern, and forming a second doped layer on the first capping layer in the first region and the first gate electrode layer in the second region.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: January 12, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun-Young Jo, Jong-Hoon Kang, Tae-Gon Kim, Han-Mei Choi
  • Patent number: 9209290
    Abstract: III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the source/drain layer and a III-N channel layer. An etch process, e.g., utilizing photochemical oxidation, selectively etches the source/drain layer over the etch stop layer. A gate electrode is disposed over the etch stop layer to form a recessed-gate III-N HEMT. At least a portion of the etch stop layer may be oxidized with a gate electrode over the oxidized etch stop layer for a recessed gate III-N MOS-HEMT including a III-N oxide. A high-k dielectric may be formed over the oxidized etch stop layer with a gate electrode over the high-k dielectric to form a recessed gate III-N MOS-HEMT having a composite gate dielectric stack.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: December 8, 2015
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Marko Radosavljevic, Uday Shah, Niloy Mukherjee, Ravi Pillarisetty, Benjamin Chu-Kung, Jack T. Kavalieros, Robert S. Chau
  • Patent number: 9136266
    Abstract: In various aspects, methods of forming a semiconductor device and semiconductor devices are provided. In some illustrative embodiments herein, a silicon/germanium layer is provided on a semiconductor substrate. On the silicon/germanium layer, at least one insulating material layer is formed. After having performed a thermal annealing process, the at least one insulating material layer is removed in subsequent process sequences such that the silicon/germanium layer is at least partially exposed. In further processing sequences which are to be subsequently applied, a gate electrode is formed on the exposed silicon/germanium layer.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: September 15, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ran Yan, Nicolas Sassiat, Jan Hoentschel, Torben Balzer