Utilizing Compound Semiconductor Patents (Class 438/285)
  • Patent number: 11355611
    Abstract: A semiconductor device includes a source/drain feature disposed over a substrate. The source/drain feature includes a first nanowire, a second nanowire disposed over the first nanowire, a cladding layer disposed over the first nanowire and the second nanowire and a spacer layer extending from the first nanowire to the second nanowire. The device also includes a conductive feature disposed directly on the source/drain feature such that the conductive feature physically contacts the cladding layer and the spacer layer.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: June 7, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Ching, Ching-Fang Huang, Wen-Hsing Hsieh, Ying-Keung Leung, Chih-Hao Wang, Carlos H. Diaz
  • Patent number: 11335815
    Abstract: A semiconductor device includes a semiconductor die, an N-doped region, an N-contact metal, a PN junction mesa, a P-contact metal, a first passivation layer, an anode feed metal, and a cathode feed metal. The semiconductor die may include a plurality of semiconductor layers disposed on an insulating substrate. The N-doped region may define an active area of the device. The N-contact metal may be disposed on a first portion of the N-doped region. The PN junction mesa may be disposed on a second portion of the N-doped region. The PN junction mesa may comprise a hyperabrupt N-doping layer disposed on the first portion of the N-doped region and a P-doped layer disposed on the hyperabrupt N-doping layer. The P-contact metal may be disposed on the P-doped layer of the PN junction mesa. The first passivation layer may cover the semiconductor layers of the semiconductor device and have openings for the N-contact metal and the P-contact metal. The anode feed metal may connect the P-contact metal to a first bond pad.
    Type: Grant
    Filed: February 20, 2021
    Date of Patent: May 17, 2022
    Assignee: Global Communication Semiconductors, LLC
    Inventors: Yuefei Yang, Shing-Kuo Wang, Wing Yau
  • Patent number: 11335552
    Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes an oxide semiconductor nanostructure suspended over a substrate. The semiconductor device structure also includes a source/drain structure adjacent to the oxide semiconductor nanostructure. The source/drain structure contains oxygen, and the oxide semiconductor nanostructure has a greater atomic concentration of oxygen than that of the source/drain structure. The semiconductor device structure further includes a gate stack wrapping around the oxide semiconductor nanostructure.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: May 17, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Yu Chang, Sai-Hooi Yeong, Yu-Ming Lin
  • Patent number: 11295951
    Abstract: A method for forming a wide band gap semiconductor device is provided. The method includes forming a gate insulation layer on a wide band gap semiconductor substrate and annealing the gate insulation layer using at least a first reactive gas species and a second reactive gas species, wherein the first reactive gas species differs from the second reactive gas species. The method can include forming a gate electrode on the gate insulation layer after annealing the gate insulation layer.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: April 5, 2022
    Assignee: Infineon Technologies AG
    Inventors: Thomas Aichinger, Gerald Rescher, Michael Stadtmueller
  • Patent number: 11264500
    Abstract: Disclosed herein are structures and techniques for device isolation in integrated circuit (IC) assemblies. In some embodiments, an IC assembly may include multiple transistors spaced apart by an isolation region. The isolation region may include a doped semiconductor body whose dopant concentration is greatest at one or more surfaces, or may include a material that is lattice-mismatched with material of the transistors, for example.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: March 1, 2022
    Assignee: Intel Corporation
    Inventors: Rishabh Mehandru, Stephen M. Cea, Tahir Ghani
  • Patent number: 11257951
    Abstract: A method of manufacturing a semiconductor device includes forming a first gate stack over a substrate. The method further includes etching the substrate to define a cavity. The method further includes growing a first epitaxial (epi) material in the cavity, wherein the first epi material includes a first upper surface having a first crystal plane. The method further includes growing a second epi material on the first epi material, wherein the second epi material includes a second upper surface having the first crystal plane. The method further includes treating the second epi material, wherein treating the second epi material comprises causing the second upper surface to transform to a second crystal plane different from the first crystal plane.
    Type: Grant
    Filed: November 4, 2020
    Date of Patent: February 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Lilly Su, Chii-Horng Li, Ming-Hua Yu, Pang-Yen Tsai, Tze-Liang Lee, Yen-Ru Lee
  • Patent number: 11257712
    Abstract: A method includes providing a structure that includes a semiconductor substrate, an epitaxial source/drain feature over the semiconductor substrate, and one or more dielectric layers over the epitaxial source/drain feature; etching a hole into the one or more dielectric layer to expose a portion of the epitaxial source/drain feature; forming a silicide layer over the portion of the epitaxial source/drain feature; forming a conductive barrier layer over the silicide layer; and applying a plasma cleaning process to at least the conductive barrier layer, wherein the plasma cleaning process uses a gas mixture including N2 gas and H2 gas and is performed at a temperature that is at least 300° C.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: February 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Wei Chang, Yu-Ming Huang, Ethan Tseng, Ken-Yu Chang, Yi-Ying Liu
  • Patent number: 11190152
    Abstract: A radio frequency (RF) power amplifier (PA) for amplifying an RF signal between a source node and an output node, the RF PA including a silicon substrate with a complementary metal oxide semiconductor (CMOS) N-type transistor with a source region and a drain region fabricated therein. The source region includes the source node of the RF PA and the drain region includes the output node of the RF PA. The RF PA includes a planar resistor fabricated on the surface of the silicon substrate proximal to the drain region of the N-type transistor, wherein the resistor provides a thermal source for heating the RF PA; and a control circuit providing thermal heating to the RF PA by providing power to the planar resistor during RF signal bursts wherein the added thermal heating compensates transient heating within the transistor and results in a linear power amplification operation.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: November 30, 2021
    Assignee: BeRex, Inc.
    Inventor: Oleksandr Gorbachov
  • Patent number: 11184003
    Abstract: A silicon carbide power device is controlled by a driver and comprises a gate-to-source voltage and a source voltage, wherein the source voltage decreases according to an increase of the gate-to-source voltage, or the source voltage increases according to a decrease of the gate-to-source voltage. Thus, a spike caused by a change of the gate-to-source voltage is suppressed, thereby suppressing the crosstalk phenomenon of the silicon carbide power device.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: November 23, 2021
    Assignee: SHANGHAI HESTIA POWER INC.
    Inventors: Fu-Jen Hsu, Chien-Chung Hung, Kuo-Ting Chu, Chwan-Ying Lee
  • Patent number: 11101143
    Abstract: A semiconductor device includes an isolation insulating layer disposed over a substrate, a fin structure disposed over the substrate, and extending in a first direction in plan view, an upper portion of the fin structure being exposed from the isolation insulating layer, a gate structure disposed over a part of the fin structure, the gate structure extending in a second direction crossing the first direction, and a source/drain structure formed on the upper portion of the fin structure, which is not covered by the gate structure and exposed from the isolation insulating layer. The source/drain structure includes a SiP layer, and an upper portion of the source/drain structure includes an alloy layer of Si, Ge and Ti.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: August 24, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Yuan-Shun Chao, Chih-Wei Kuo
  • Patent number: 11081356
    Abstract: A method includes providing a structure having a substrate, first and second semiconductor fins extending from the substrate, and a dielectric fin between the first and second semiconductor fins; forming a temporary gate on top and sidewalls of the first and second semiconductor fins and the dielectric fin; forming gate spacers on sidewalls of the temporary gate; removing the temporary gate and a first portion of the dielectric fin between the gate spacers; forming a gate between the gate spacers and on top and sidewalls of the first and second semiconductor fins, wherein the dielectric fin is in physical contact with sidewalls of the gate; removing a second portion of the dielectric fin, thereby exposing the sidewalls of the gate; and performing an etching process to the gate through the exposed sidewalls of the gate, thereby separating the gate into a first gate segment and a second gate segment.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: August 3, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pei-Yu Wang, Zhi-Chang Lin, Ching-Wei Tsai, Kuan-Lun Cheng
  • Patent number: 11062951
    Abstract: A process for fabricating a field-effect transistor includes providing a structure including a first silicon layer and a second layer, made of SiGe alloy, covering the first silicon layer. The method further includes forming a sacrificial gate covered with a hardmask on top of the second layer made of SiGe alloy and etching the second layer made of SiGe alloy, following the pattern of the hardmask in order to delimit an element made of SiGe alloy in the second layer. The method also includes forming spacers on top of the first silicon layer on either side of the sacrificial gate and of the element, removing the sacrificial gate, and enriching the first layer arranged beneath the element in germanium using a germanium condensation process.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: July 13, 2021
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventor: Shay Reboh
  • Patent number: 11056574
    Abstract: This disclosed technology generally relates to a semiconductor device. One aspect relates to a method of fabricating a stacked semiconductor including forming a semiconductor structure protruding above the substrate and a gate structure extending across the semiconductor structure. The semiconductor structure includes a lower channel layer formed of a first material, an intermediate layer formed of a second material and an upper channel layer formed of a third material. The method additionally includes forming oxidized end portions defining second spacers on end surfaces of an upper layer. And forming the oxidized end portions comprises oxidizing end portions of the upper channel layer at opposite sides of the gate structure using an oxidization process adapted to cause a rate of oxidation of the third material which is greater than a rate of oxidation of the first material, while first spacers cover intermediate end surfaces.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: July 6, 2021
    Assignee: IMEC vzw
    Inventor: Kurt Wostyn
  • Patent number: 11031499
    Abstract: An apparatus including a transistor device including a channel disposed on a substrate between a source and a drain, a gate electrode disposed on the channel, wherein the channel includes a length dimension between source and drain that is greater than a length dimension of the gate electrode such that there is a passivated underlap between an edge of the gate electrode and an edge of the channel relative to each of the source and the drain. A method including forming a channel of a transistor device on a substrate; forming first and second passivation layers on a surface of substrate on opposite sides of the channel; forming a gate stack on the channel between first and second passivation layers; and forming a source on the substrate between the channel and the first passivation layer and a drain on the substrate between the channel and the second passivation layer.
    Type: Grant
    Filed: July 2, 2016
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Van H. Le, Matthew V. Metz, Benjamin Chu-Kung, Ashish Agrawal, Jack T. Kavalieros
  • Patent number: 10957784
    Abstract: A method of manufacturing a semiconductor device includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers on a substrate. The first and second semiconductor layers include first end portions on either side of a second portion along a length of the first and second semiconductor layers. The first and second semiconductor layers are formed of different materials. The second portion of the first semiconductor layers is removed to form spaces. A mask layer is formed over the second portion of an uppermost second semiconductor layer above the spaces. The first portions of first and second semiconductor layers are irradiated with radiation from a radiation source to cause material from the first portions of the first and second semiconductor layers to combine with each other.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: March 23, 2021
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: I-Hsieh Wong, Samuel C. Pan, Chee-Wee Liu, Huang-Siang Lan, Chung-En Tsai, Fang-Liang Lu
  • Patent number: 10892365
    Abstract: A semiconductor structure includes a semiconductor substrate, at least a silicon germanium (SiGe) epitaxial region disposed in the semiconductor substrate, and a contact structure disposed on the SiGe epitaxial region. The contact structure includes a titanium nitride (TiN) barrier layer and a metal layer surrounded by the TiN barrier layer. A crystalline titanium germanosilicide stressor layer is disposed in the SiGe epitaxial region and between the TiN barrier layer and the SiGe epitaxial region.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: January 12, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Cheng-Yeh Huang, Te-Chang Hsu, Chun-Jen Huang, Che-Hsien Lin, Yao-Jhan Wang
  • Patent number: 10833107
    Abstract: Provided are a thin film transistor and manufacturing method therefor, and an array substrate, and a display device. The method includes: forming a source electrode and a drain electrode on a substrate; forming a photoresist layer at the side of the source electrode and the drain electrode away from the substrate; performing exposure and developing treatment on the photoresist layer so as to obtain a photoresist pattern; successively forming a semiconductor layer, a first insulation layer and a conducting layer in sequence on at the side of the photoresist pattern away from the substrate; and removing the photoresist pattern so as to obtain an active layer a gate insulation layer and a gate electrode.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: November 10, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Fengjuan Liu, Youngsuk Song, Hongda Sun
  • Patent number: 10818792
    Abstract: Structures for a field-effect transistor and methods of forming structures for a field-effect transistor. A layer stack includes nanosheet channel layers arranged to alternate with sacrificial layers. First and second gate structures are formed that extend across the layer stack and that are separated by a first gap. First and second sidewall spacers are formed over the layer stack and within the first gap respectively adjacent to the first and second gate structures, and the layer stack is subsequently etched to form first and second body features that are separated by a second gap. The sacrificial layers are recessed relative to the nanosheet channel layers to define indents in the first and second body features, and the first and second sidewall spacers are subsequently removed. After removing the first and second sidewall spacers, a conformal layer is deposited in the second gap that fills the indents to define inner spacers.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: October 27, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Julien Frougier, Ruilong Xie, Daniel Chanemougame
  • Patent number: 10790302
    Abstract: Provided herein is a semiconductor device and a method of manufacturing the same. The semiconductor device has improved erase characteristics by using a select gate enclosing a portion a first semiconductor region overlapping a second semiconductor region. The first semiconductor region and the second semiconductor region are formed of different semiconductor materials.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: September 29, 2020
    Assignee: SK hynix Inc.
    Inventor: Jin Ha Kim
  • Patent number: 10679900
    Abstract: A method includes forming Shallow Trench Isolation (STI) regions in a semiconductor substrate and a semiconductor strip between the STI regions. The method also include replacing a top portion of the semiconductor strip with a first semiconductor layer and a second semiconductor layer over the first semiconductor layer. The first semiconductor layer has a first germanium percentage higher than a second germanium percentage of the second semiconductor layer. The method also includes recessing the STI regions to form semiconductor fins, forming a gate stack over a middle portion of the semiconductor fin, and forming gate spacers on sidewalls of the gate stack. The method further includes forming fin spacers on sidewalls of an end portion of the semiconductor fin, recessing the end portion of the semiconductor fin, and growing an epitaxial region over the end portion of the semiconductor fin.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Chiang, Ting-Hung Hsu, Chao-Hsiung Wang, Chi-Wen Liu
  • Patent number: 10658489
    Abstract: A semiconductor device and a fabrication method are provided. The fabrication method includes providing a gate structure on a substrate and a first protective layers on the gate structure; forming an initial sidewall spacer on a sidewall of each of the gate structure and the first protective layer; forming a first sidewall spacer on a sidewall of the initial sidewall spacer, the first and initial sidewall spacers being made of different materials; forming a second sidewall spacer by removing a portion of the initial sidewall spacer, leaving a trench formed above the second sidewall spacer and between the first sidewall spacer and the first protective layer; and forming a second protective layer in the trench, the second protective layer and the first sidewall spacer being made of a same material. The second sidewall spacer has a top surface higher than or level with a top surface of the gate structure.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: May 19, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Er Hu Zheng, Lu Jun Zou
  • Patent number: 10651287
    Abstract: A semiconductor structure includes a substrate, a semiconductor fin connected to the substrate, an epitaxial layer disposed over the semiconductor fin, and a silicide feature over and in contact with the epitaxial layer. The epitaxial layer including silicon germanium (SiGe) and further includes gallium (Ga) in an upper portion of the epitaxial layer that is in contact with the silicide feature.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: May 12, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shahaji B. More, Chun Hsiung Tsai, Shih-Chieh Chang, Kuo-Feng Yu, Cheng-Yi Peng
  • Patent number: 10593672
    Abstract: A method for manufacturing a semiconductor device includes growing a first strained semiconductor layer on a substrate, the first strained semiconductor layer having a first type of strain, wherein the substrate comprises a first crystalline orientation at a top surface of the substrate, forming at least one trench in the substrate, wherein exposed sidewalls of the at least one trench have a second crystalline orientation different from the first crystalline orientation, growing a buffer layer in the at least one trench from the exposed sidewalls of the trench, and growing a second strained semiconductor layer on the buffer layer, the second strained semiconductor layer having a second type of strain, wherein the first type of strain is different from the second type of strain.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: March 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Juntao Li, Kangguo Cheng, John G. Gaudiello
  • Patent number: 10573737
    Abstract: A transistor structure includes a substrate. A gate structure is disposed on the substrate. A hexagonal-shaped trench is disposed in the substrate at one side of the gate structure. A first epitaxial layer including first-type dopants is disposed in the hexagonal-shaped trench and contacts the hexagonal-shaped trench. A second epitaxial layer including second-type dopants is disposed in the hexagon-shaped trench. The first epitaxial layer is outside of the second epitaxial layer. The second epitaxial layer serves as a source/drain doped region of the transistor structure. The first-type dopants and the second-type dopants are of different conductive types.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: February 25, 2020
    Assignee: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: Sheng-Hsu Liu, Shih-Hsien Huang, Wen Yi Tan
  • Patent number: 10504771
    Abstract: A method for manufacturing a semiconductor device includes: forming a sacrificial layer on a first substrate, the sacrificial layer being made of a material whose lattice constant is different from that of germanium (Ge) by a preset threshold or below; forming a germanium (Ge) layer on the sacrificial layer; forming an insulation layer on a second substrate; bonding the germanium (Ge) layer onto the insulation layer; and removing the sacrificial layer and the first substrate by etching the sacrificial layer in a state where the germanium (Ge) layer is bonded to the insulation layer. In this method, a germanium-on-insulator (GeOI) structure having various surface orientations may be formed by means of epitaxial lift-off (ELO), and a strain may be applied to the germanium (Ge) layer using a lattice constant of the sacrificial layer.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: December 10, 2019
    Assignee: Korea Institute of Science and Technology
    Inventors: Hyung-Jun Kim, Sanghyeon Kim, Jae-Phil Shim, Yeon-Su Kim, Heejeong Lim
  • Patent number: 10439039
    Abstract: An integrated circuit includes a FinFET and a nanostructure FET. The integrated circuit includes a bulk substrate. The integrated circuit also includes a fin field effect transistor (FinFET) coupled to the bulk substrate. The FinFET includes a first source region, a first drain region, and a fin extending between the first source region and the first drain region. The integrated circuit also includes a nanostructure FET coupled to the bulk substrate. The nanostructure FET includes a second source region, a second drain region, and a stack of at least two nanostructures extending between the second source region and the second drain region.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: October 8, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Stanley Seungchul Song, Jeffrey Junhao Xu, Kern Rim, Choh Fei Yeap
  • Patent number: 10411007
    Abstract: Monolithic FETs including a channel region in a first semiconductor material disposed over a substrate. While a mask, such as a gate stack or sacrificial gate stack, is covering a channel region, a semiconductor spacer of a semiconductor material with a band offset relative to the channel material is grown, for example on at least a drain end of the channel region to introduce at least one charge carrier-blocking band offset between the channel semiconductor and a drain region of a third III-V semiconductor material. In some N-type transistor embodiments, the carrier-blocking band offset is a conduction band offset of at least 0.1 eV. A wider band gap and/or a blocking conduction band offset may contribute to reduced gate induced drain leakage (GIDL). Source/drain regions couple electrically to the channel region through the semiconductor spacer, which may be substantially undoped (i.e. intrinsic) or doped.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: September 10, 2019
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Willy Rachmady, Matthew V. Metz, Chandra S. Mohapatra, Sean T. Ma, Jack T. Kavalieros, Anand S. Murthy, Tahir Ghani
  • Patent number: 10366891
    Abstract: A vertical semiconductor apparatus includes: a gallium nitride substrate; a gallium nitride semiconductor layer on the gallium nitride substrate; a p-type impurity region in the gallium nitride semiconductor layer and having an element to function as an acceptor for gallium nitride; an n-type impurity region in the p-type impurity region and having an element to function as a donor for gallium nitride; and an electrode provided contacting a rear surface of the gallium nitride substrate. The element to function as the donor in the n-type impurity region includes: a first impurity element to enter sites of gallium atoms in the gallium nitride semiconductor layer; and a second impurity element different from the first impurity element and to enter sites of nitrogen atoms in the gallium nitride semiconductor layer. In the n-type impurity region, a concentration of the first impurity element is higher than that of the second impurity element.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: July 30, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Shinya Takashima, Katsunori Ueno, Masaharu Edo
  • Patent number: 10355102
    Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes semiconductor wires disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires, a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region, and dielectric spacers disposed in recesses formed toward the source/drain epitaxial layer.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: July 16, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, Yu-Lin Yang, Wei-Sheng Yun, Chen-Feng Hsu, Tzu-Chiang Chen
  • Patent number: 10249722
    Abstract: A FET device fabricated by providing a first conductor on a substrate, the first conductor having a first top surface with a first height above the substrate. A second conductor is provided adjacent the first conductor, the second conductor having a second top surface with a second height above the substrate. A portion of the second conductor is removed to provide a slot, wherein the slot is defined by opposing interior sidewalls and a bottom portion, such that the bottom portion of the slot is below the first height of the first conductor. An insulating material is deposited in the slot, the insulating material having a third top surface with a third height above the substrate, the third height being below the second height of the second conductor to provide space within the slot for a third conductor. The space within the slot is then filled with the third conductor.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10249739
    Abstract: A method is presented for forming a nanosheet metal oxide semiconductor field effect transistor (MOSFET) structure. The method includes forming a heteroepitaxial film stack including at least one sacrificial layer and at least one channel layer, patterning the heteroepitaxial film stack, forming a dummy gate stack with sidewall spacers, and forming a cladded or embedded epitaxial source/drain material along the patterned heteroepitaxial film stack sidewalls. The method further includes removing the dummy gate stack, partially removing the at least one sacrificial layer, and forming a replacement gate stack.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael A. Guillorn, Terence B. Hook, Nicolas J. Loubet, Robert R. Robison, Reinaldo A. Vega
  • Patent number: 10204990
    Abstract: A semiconductor device includes an N-type silicon carbide substrate, an N-type silicon carbide layer formed on the N-type silicon carbide substrate, a P-type region selectively formed in a surface layer of the N-type silicon carbide layer, an N-type source region formed in the P-type region, a P contact region formed in the P-type region, a gate insulating film formed on a portion of a region from the N-type source region, through the P-type region, to the N-type silicon carbide layer, a gate electrode formed on the gate insulating film, an interlayer insulating film covering the gate electrode, and a first source electrode electrically connected to a surface of the P contact region and the N-type source region. An end of the interlayer insulating film covering the gate electrode has a slope of a predetermined angle.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: February 12, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yuichi Harada, Yasuyuki Hoshi, Akimasa Kinoshita, Yasuhiko Oonishi
  • Patent number: 10199501
    Abstract: A method for manufacturing a semiconductor structure includes the following steps. First, a semiconductor substrate including a first semiconductor material is provided. The semiconductor substrate includes a dielectric structure formed thereon, and the dielectric structure includes at least a recess formed therein. A first epitaxial layer is then formed in the recess. The first epitaxial layer includes at least a second semiconductor material that a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. Subsequently, a thermal oxidation process is performed to the first epitaxial layer thereby forming a semiconductor layer at a bottom of the recess and a silicon oxide layer on the semiconductor layer. After removing the silicon oxide layer, a second epitaxial layer is formed on the semiconductor layer in the recess.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: February 5, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Chung-Yi Chiu
  • Patent number: 10181527
    Abstract: A field effect transistor (FET) structure includes: a gate; a first spacer having a first dielectric constant at a first region adjacent to the gate; and a second spacer having a second dielectric constant that is greater than the first dielectric constant at a second region adjacent to the gate.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: January 15, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dharmendar Reddy Palle, Borna Obradovic, Joon Goo Hong, Mark Rodder
  • Patent number: 10170549
    Abstract: Exemplary embodiments provide for fabricating a nanosheet stack structure having one or more sub-stacks.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: January 1, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jorge A. Kittl, Borna J. Obradovic, Robert C. Bowen, Mark S. Rodder
  • Patent number: 10164015
    Abstract: Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Matthew T. Currie, Anthony J. Lochtefeld, Richard Hammond, Eugene A. Fitzgerald
  • Patent number: 10164038
    Abstract: A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopant and a second dopant, and the second dopant comprises a group V material.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Han-Chin Chiu, Chen-Hao Chiang, Chi-Ming Chen, Chung-Yi Yu
  • Patent number: 10158004
    Abstract: Some embodiments of the present disclosure relates to a method of forming a semiconductor device having a strained channel and an associated device. In some embodiments, the method includes performing a first etching process by selectively exposing a substrate to a first etchant to produce a recess defined by sidewalls and a bottom surface of the substrate. An implantation process is performed to form an etch stop layer along the bottom surface. A second etching process is performed by exposing the sidewalls and the bottom surface defining the recess to a second etchant to form a source/drain recess. The source/drain recess laterally extends past the etch stop layer in opposing directions. A semiconductor material is formed within the source/drain recess.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Hsuing Chen, Ling-Sung Wang, Chi-Yen Lin
  • Patent number: 10141406
    Abstract: A tensile strained silicon layer and a compressively strained silicon germanium layer are formed on a strain relaxed silicon germanium buffer layer substrate. A relaxed silicon layer is formed on the substrate and the compressively strained silicon germanium layer is formed on the relaxed silicon layer. The compressively strained silicon germanium layer can accordingly have approximately the same concentration of germanium as the underlying strain relaxed buffer layer substrate, which facilitates gate integration. The tensile strained silicon layer and the compressively strained silicon germanium layer can be configured as fins used in the fabrication of FinFET devices. The relaxed silicon layer and a silicon germanium layer underlying the tensile silicon layer can be doped in situ to provide punch through stop regions adjoining the fins.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: November 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Keith E. Fogel, Pouya Hashemi, Alexander Reznicek
  • Patent number: 10083965
    Abstract: The semiconductor device includes a substrate comprising first and second regions, in the first region, first and second gate electrodes formed parallel to each other on the substrate, and being spaced apart from each other by a first distance, in the second region, third and fourth gate electrodes formed parallel to each other on the substrate, and being spaced apart from each other by a second distance which is greater than the first distance, in the first region, a first recess formed on the substrate between the first and second gate electrodes, in the second region, a second recess formed on the substrate between the third and fourth gate electrodes, a first epitaxial source/drain filling the first recess and a second epitaxial source/drain filling the second recess, wherein an uppermost portion of an upper surface of the first epitaxial source/drain is higher than an uppermost portion of an upper surface of the second epitaxial source/drain.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: September 25, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki Hwan Kim, Gi Gwan Park, Jung Gun You, Dong Suk Shin, Hyun Yul Choi
  • Patent number: 10079181
    Abstract: A method of forming a semiconductor structure includes forming a dummy gate above a semiconductor substrate. The dummy gate defines a source-drain region adjacent to the dummy gate and a channel region below the dummy gate. A silicon-germanium layer is epitaxially grown above the source-drain region with a target concentration of germanium atoms. The semiconductor structure is annealed to diffuse the germanium atoms from the silicon-germanium layer into the channel region to form a silicon-germanium channel region.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: September 18, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Ghavam G. Shahidi
  • Patent number: 9978843
    Abstract: An embodiment of a silicon carbide semiconductor device includes one or more inner cells each having a MOSFET and one or more outer peripheral cells that does not have a MOSFET structure, and the area (surface area) of the p+ contact region of each of the outermost peripheral cells is less than the surface area of an p+ contact region of each of the inner cells, for example, so that a unit total resistance of p+ contact regions of the outermost peripheral cells, as measured in a depth direction of the semiconductor substrate with respect to a unit area in a surface of the semiconductor substrate, is greater than a unit total resistance of the p+ contact regions of the inner cells, as measured in the depth direction of the semiconductor substrate with respect to the unit area in the surface of the semiconductor substrate.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: May 22, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Ryohei Takayanagi, Hiroki Wakimoto
  • Patent number: 9947788
    Abstract: A method includes forming a gate electrode structure above a channel region defined in a semiconductor material. The semiconductor material is recessed in a source/drain region. A first material is epitaxially grown in the source/drain region. The first material includes a dopant species having a first concentration. A diffusion blocking layer is formed in the source/drain region above the first material. A second material is epitaxially grown in the source/drain region above the diffusion blocking layer. The second material comprises the dopant species having a second concentration greater than the first concentration.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: April 17, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Shesh Mani Pandey, Pei Zhao, Baofu Zhu, Francis L. Benistant
  • Patent number: 9917191
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming a gate dielectric over the semiconductor wafer, and forming a gate over the gate dielectric. At least one recess is formed in the semiconductor wafer proximate the gate and the gate dielectric, at least a portion of the at least one recess extending beneath the gate. The at least one recess in the semiconductor wafer is filled with a semiconductive material.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: March 13, 2018
    Assignee: Infineon Technologies AG
    Inventors: Manfred Eller, Jin-Ping Han
  • Patent number: 9881821
    Abstract: A control wafer making device, a method of measuring an epitaxy thickness in a control wafer, and a method for monitoring a control wafer are provided. In various embodiments, the control wafer making device includes a wafer substrate removing element and an epitaxy forming element. In various embodiments, a control wafer includes a substrate, a recess, a blocking layer, and an epitaxy. The substrate has a surface, and the recess is in the surface of the substrate. The blocking layer is over the surface of the substrate other than the recess. The epitaxy is in the recess. In various embodiments, the thickness of the epitaxy of the control wafer is measured by a polarized light.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: January 30, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Wei Hung, Chia-Chiung Lo, Chien-Feng Lin
  • Patent number: 9853153
    Abstract: The present invention provides a method of manufacturing a fin field effect transistor, comprising: providing an SOI substrate comprising a substrate layer (100), a BOX layer (120) and an SOI layer (130); forming a basic fin structure from an SOI layer; forming source/drain regions (110) on both sides of the basic fin structure; forming a fin structure between the source/drain regions (110) from a basic fin structure; and forming a gate stack across the fin structure. The method of manufacturing a fin field effect transistor provided in the present invention can integrate a high-k gate dielectric layer, a metal gate, and stressed source/drain regions into the fin field effect transistor to enhance the performance of the semiconductor device.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: December 26, 2017
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Huilong Zhu, Zhijiong Luo, Haizhou Yin, Qingqing Liang
  • Patent number: 9799508
    Abstract: A process of forming a nitride semiconductor device is disclosed. The process includes steps of (a) implanting impurities into a portion of nitride semiconductor layers epitaxially grown on a substrate; (b) forming a silicon nitride (SiN) film on the nitride semiconductor layers; and (c) annealing the nitride semiconductor layers for activating the implanted impurities as covering the nitride semiconductor layers by the SiN film. The process has a feature that the SiN film shows, in a Fourier Transformation Infrared (FT-IR) spectroscopy measured before the step of annealing, absorbance peaks attributed to translational motions of a Si—H bond and an N—H bond at most 1/30 of an absorbance peak attributed to a SiN bond.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: October 24, 2017
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Masatoshi Koyama
  • Patent number: 9728671
    Abstract: An optoelectronic light emission device is provided that includes a gain region of at least one type III-V semiconductor layer that is present on a lattice mismatched semiconductor substrate. The gain region of the type III-V semiconductor layer has a nanoscale area using nano-cavities. The optoelectronic light emission device is free of defects.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: August 8, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Effendi Leobandung, Ning Li, Tak H. Ning, Jean-Oliver Plouchart, Devendra K. Sadana
  • Patent number: 9728534
    Abstract: A method of forming a fin-based field-effect transistor device includes forming one or more first fins comprising silicon on a substrate, forming epitaxial layers on sides of the one or more first fins, and removing the one or more first fins to form a plurality of second fins.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: August 8, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hong He, Chiahsun Tseng, Chun-Chen Yeh, Yunpeng Yin
  • Patent number: 9679990
    Abstract: Semiconductor structures and methods of fabrication are provided, with one or both of an extended source-to-channel interface or an extended drain-to-channel interface. The fabrication method includes, for instance, recessing a semiconductor material to form a cavity adjacent to a channel region of a semiconductor structure being fabricated, the recessing forming a first cavity surface and a second cavity surface within the cavity; and implanting one or more dopants into the semiconductor material through the first cavity surface to define an implanted region within the semiconductor material, and form an extended channel interface, the extended channel interface including, in part, an interface of the implanted region within the semiconductor material to the channel region of the semiconductor structure. In one embodiment, the semiconductor structure with the extended channel interface is a FinFET.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: June 13, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Edmund Kenneth Banghart, Mitsuhiro Togo, Shesh Mani Pandey