Utilizing Compound Semiconductor Patents (Class 438/285)
  • Patent number: 12166079
    Abstract: The present disclosure describes a 2D channel FET with low contact resistance and a method for forming such a structure. The method includes depositing a dielectric layer on a semiconductor substrate, depositing a metal layer on the dielectric layer, and depositing a hard mask layer on the metal layer. The method further includes forming a gate opening by removing a portion of the hard mask layer and a portion of the metal layer. The method further includes depositing a spacer material layer on sidewalls of the gate opening and forming a channel, the channel including a TMC layer, at a bottom of the gate opening. The method further includes forming a gate structure on the channel and in the gate opening and removing the hard mask layer.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: December 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mrunal Abhijith Khaderbad, Dhanyakumar Mahaveer Sathaiya, Wei-Yen Woon
  • Patent number: 12142663
    Abstract: A semiconductor structure includes a substrate, a semiconductor fin extending from the substrate, and a silicon germanium (SiGe) epitaxial feature disposed over the semiconductor fin. A gallium-implanted layer is disposed over a top surface of the SiGe epitaxial feature, and a silicide feature is disposed over and in contact with the gallium-implanted layer.
    Type: Grant
    Filed: July 24, 2023
    Date of Patent: November 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shahaji B. More, Chun Hsiung Tsai, Shih-Chieh Chang, Kuo-Feng Yu, Cheng-Yi Peng
  • Patent number: 12119393
    Abstract: A method of forming a semiconductor device that includes forming a fin structure from a bulk semiconductor substrate and forming an isolation region contacting a lower portion of a sidewall of the fin structure, wherein an upper portion of the sidewall of the fin structure is exposed. A sacrificial spacer is formed on the upper portion of the sidewall of the fin structure. The isolation regions are recessed to provide an exposed section of the sidewall of the fin structure. A doped semiconductor material is formed on the exposed section of the lower portion of the sidewall of the fin structure. Dopant is diffused from the doped semiconductor material to a base portion of the fin structure.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: October 15, 2024
    Assignee: Adeia Semiconductor Solutions LLC
    Inventors: Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 12119035
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a lower electrode disposed within a dielectric structure over a substrate. A ferroelectric data storage structure is disposed over the lower electrode and an upper electrode is disposed over the ferroelectric data storage structure. One or more stressed sidewall spacers are arranged on opposing sides of the upper electrode. The ferroelectric data storage structure has an orthorhombic phase concentration that varies from directly below the one or more stressed sidewall spacers to laterally outside of the one or more stressed sidewall spacers.
    Type: Grant
    Filed: January 5, 2023
    Date of Patent: October 15, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Yu Lin, Yao-Wen Chang
  • Patent number: 12087766
    Abstract: An integrated circuit (IC) device includes a fin-type active region extending longitudinally in a first lateral direction on a substrate. A nanosheet is apart from a fin top surface of the fin-type active region in a vertical direction. An inner insulating spacer is between the substrate and the nanosheet. A gate line includes a main gate portion and a sub-gate portion. The main gate portion extends longitudinally in a second lateral direction on the nanosheet. The sub-gate portion is integrally connected to the main gate portion and between the substrate and the nanosheet. A source/drain region is in contact with the inner insulating spacer and the nanosheet. The source/drain region includes a single crystalline semiconductor body and at least one lower stacking fault surface linearly extending from the inner insulating spacer through the single crystalline semiconductor body.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: September 10, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sujin Jung, Kihwan Kim, Sunguk Jang, Youngdae Cho
  • Patent number: 12062720
    Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a gate stack over an active region and a source/drain region in the active region adjacent the gate stack. The source/drain region includes a first semiconductor layer having a first germanium concentration and a second semiconductor layer over the first semiconductor layer. The second semiconductor layer has a second germanium concentration greater than the first germanium concentration. The source/drain region further includes a third semiconductor layer over the second semiconductor layer and a fourth semiconductor layer over the third semiconductor layer. The third semiconductor layer has a third germanium concentration greater than the second germanium concentration. The fourth semiconductor layer has a fourth germanium concentration less than the third germanium concentration.
    Type: Grant
    Filed: March 20, 2023
    Date of Patent: August 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kun-Mu Li, Hsueh-Chang Sung
  • Patent number: 12051756
    Abstract: A flash memory device includes a substrate, a semiconductor quantum well layer, a semiconductor spacer, a semiconductor channel layer, a gate structure, and source/drain regions. The semiconductor quantum well layer is formed of a first semiconductor material and is disposed over the substrate. The semiconductor spacer is formed of a second semiconductor material and is disposed over the first semiconductor channel layer. The semiconductor channel layer is formed of the first semiconductor material and is disposed over the semiconductor spacer. Thea gate structure is over the second semiconductor channel layer. The source/drain regions are over the substrate and are on opposite sides of the gate structure.
    Type: Grant
    Filed: January 13, 2022
    Date of Patent: July 30, 2024
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Jiun-Yun Li, Nai-Wen Hsu, Wei-Chih Hou, Yu-Jui Wu, Yen Chuang, Chia-Yu Liu
  • Patent number: 12021117
    Abstract: A method of forming a semiconductor structure includes following operations. A substrate including a silicon (Si) layer is received. An amorphous germanium (Ge) layer is formed on the Si layer. A barrier layer is formed over the amorphous Ge layer. The substrate is annealed to transform the Si layer and the Ge layer to form a single crystalline SiGe layer. A Ge concentration is in a positive correlation with a ratio of a thickness of the Ge layer and a thickness of the Si layer.
    Type: Grant
    Filed: January 13, 2022
    Date of Patent: June 25, 2024
    Inventors: Te-Ming Kung, Ying-Lang Wang, Kei-Wei Chen, Wen-Hsi Lee, Shu Wei Chang
  • Patent number: 12020988
    Abstract: A fin field effect transistor (FinFET) device structure with dummy fin structures and method for forming the same are provided. The FinFET device structure includes an isolation structure over a substrate, and a first fin structure extended above the isolation structure. The fin field effect transistor (FinFET) device structure includes a second fin structure adjacent to the first fin structure, and a material layer formed over the fin structure. The material layer and the isolation structure are made of different materials, the material layer has a top surface with a top width and a bottom surface with a bottom width, and the bottom width is greater than the top width.
    Type: Grant
    Filed: January 19, 2023
    Date of Patent: June 25, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzung-Yi Tsai, Yen-Ming Chen, Tsung-Lin Lee, Chih-Chieh Yeh
  • Patent number: 12021152
    Abstract: Embodiments described herein provide thin film transistors (TFTs) and processes to reduce plasma induced damage in TFTs. In one embodiment, a buffer layer is disposed over a substrate and a semiconductor layer is disposed over the buffer layer. A gate dielectric layer is disposed over the semiconductor layer. The gate dielectric layer contacts the semiconductor layer at an interface. The gate electrode 204 is disposed over the gate dielectric layer. The gate dielectric layer has a Dit of about 5e10 cm?2 eV?1 to about 5e11 cm?2 eV?1 and a hysteresis of about 0.10 V to about 0.30 V improve performance capability of the TFT while having a breakdown field between about 6 MV/cm and about 10 MV/cm.
    Type: Grant
    Filed: April 27, 2023
    Date of Patent: June 25, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Jianheng Li, Lai Zhao, Yujia Zhai, Soo Young Choi
  • Patent number: 12020925
    Abstract: A method for preparing an AlN based template having a Si substrate and a method for preparing a GaN based epitaxial structure having a Si substrate are provided. The method for preparing the AlN based template having the Si substrate, which includes: providing the Si substrate; growing an AlN nucleation layer on the Si substrate; and introducing an ion passing through the AlN nucleation layer and into the Si substrate. After the AlN nucleation layer is prepared on the Si substrate, the ions are introduced into the Si substrate and the AlN nucleation layer through the AlN nucleation layer. In this way, types of the introduced ions can be expanded. In addition, a carrier concentration at an interface between the Si substrate and the AlN nucleation layer and a carrier concentration in the AlN nucleation layer can also be reduced.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: June 25, 2024
    Assignee: Xidian University
    Inventors: Zhihong Liu, Junwei Liu, Jincheng Zhang, Lu Hao, Kunlu Song, Hong Zhou, Shenglei Zhao, Yachao Zhang, Weihang Zhang, Yue Hao
  • Patent number: 12015076
    Abstract: A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer is different from that of the second III-V compound layer. A trench is disposed within the first III-V compound layer and the second III-V compound layer. The trench has a first corner and a second corner. The first corner and the second corner are disposed in the first III-V compound layer. A first dielectric layer contacts a sidewall of the first corner. A second dielectric layer contacts a sidewall of the second corner. The first dielectric layer and the second dielectric layer are outside of the trench. A gate is disposed in the trench. A source electrode and a drain electrode are respectively disposed at two sides of the gate. A gate electrode is disposed on the gate.
    Type: Grant
    Filed: January 3, 2023
    Date of Patent: June 18, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Wei Chang, Yao-Hsien Chung, Shih-Wei Su, Hao-Hsuan Chang, Da-Jun Lin, Ting-An Chien, Bin-Siang Tsai
  • Patent number: 12002854
    Abstract: A semiconductor device having an improved source/drain region profile and a method for forming the same are disclosed. In an embodiment, a method includes etching one or more semiconductor fins to form one or more recesses; and forming a source/drain region in the one ore more recesses, the forming the source/drain region including epitaxially growing a first semiconductor material in the one or more recesses at a temperature of 600° C. to 800° C., the first semiconductor material including doped silicon germanium; and conformally depositing a second semiconductor material over the first semiconductor material at a temperature of 300° C. to 600° C., the second semiconductor material including doped silicon germanium and having a different composition than the first semiconductor material.
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: June 4, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Heng-Wen Ting, Kei-Wei Chen, Chii-Horng Li, Pei-Ren Jeng, Hsueh-Chang Sung, Yen-Ru Lee, Chun-An Lin
  • Patent number: 11978791
    Abstract: A semiconductor structure, comprising: a semiconductor substrate, a heterojunction, an in-situ insulating layer and a transition layer, which are arranged in sequence from bottom to top; a groove, passing through the in-situ insulating layer and the transition layer; and a P-type semiconductor layer, disposed in the groove and in a gate region on the transition layer, wherein the P-type semiconductor layer does not fully fill the groove. A method of manufacturing semiconductor structure is further disclosed.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: May 7, 2024
    Assignee: ENKRIS SEMICONDUCTOR, INC.
    Inventor: Kai Cheng
  • Patent number: 11973143
    Abstract: Integrated circuit structures having source or drain structures and germanium N-channels are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion, the upper fin portion including germanium. A gate stack is over the upper fin portion of the fin. A first source or drain structure includes an epitaxial structure embedded in the fin at a first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at a second side of the gate stack. Each epitaxial structure includes a first semiconductor layer in contact with the upper fin portion, and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer comprises silicon, germanium and phosphorous, and the second semiconductor layer comprises silicon and phosphorous.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: April 30, 2024
    Assignee: Intel Corporation
    Inventors: Ryan Keech, Benjamin Chu-Kung, Subrina Rafique, Devin Merrill, Ashish Agrawal, Harold Kennel, Yang Cao, Dipanjan Basu, Jessica Torres, Anand Murthy
  • Patent number: 11899373
    Abstract: A method of generating a layout pattern includes determining a first energy density indirectly exposed to a first feature of one or more features of a layout pattern on an energy-sensitive material when the one or more features of the layout pattern on the energy-sensitive material are directly exposed by a charged particle beam. The method also includes adjusting a second energy density exposed the first feature when the first feature is directly exposed by the charged particle beam. A total energy density of the first feature that comprises a sum of the first energy density from the indirect exposure and the second energy density from the direct exposure is maintained at about a threshold energy level to fully expose the first feature in the energy-sensitive material.
    Type: Grant
    Filed: January 13, 2023
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen Lo, Shih-Ming Chang
  • Patent number: 11894379
    Abstract: A semiconductor device includes a first transistor in a first region of a substrate and a second transistor in a second region of the substrate. The first transistor includes multiple first semiconductor patterns; a first gate electrode; a first gate dielectric layer; a first source/drain region; and an inner-insulating spacer. The second transistor includes multiple second semiconductor patterns; a second gate electrode; a second gate dielectric layer; and a second source/drain region. The second gate dielectric layer extends between the second gate electrode and the second source/drain region and is in contact with the second source/drain region. The first source/drain region is not in contact with the first gate dielectric layer.
    Type: Grant
    Filed: June 20, 2022
    Date of Patent: February 6, 2024
    Inventors: Jung-Gil Yang, Geum-Jong Bae, Dong-Il Bae, Seung-Min Song, Woo-Seok Park
  • Patent number: 11682674
    Abstract: Stacked nanosheet complementary metal-oxide-semiconductor field effect transistor devices include a lower semiconductor channel sheet on a substrate. An upper semiconductor channel sheet is on the substrate above the lower semiconductor channel sheet. The upper semiconductor channel sheet is a different semiconductor material than the lower semiconductor channel sheet. A dielectric substitute partition sheet is on the substrate between the upper semiconductor channel sheet and the lower semiconductor channel sheet.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: June 20, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li
  • Patent number: 11662660
    Abstract: A method for manufacturing a semiconductor includes: receiving a photomask substrate including a shielding layer; defining a chip region and a peripheral region adjacent to the chip region; forming a design pattern in the chip region; forming a reference pattern by emitting one first radiation shot and a beta pattern by emitting a plurality of second radiation shots in the peripheral region, wherein a pixel size of the first radiation shot is greater than a pixel size of the second radiation shot; comparing a reference roughness of a boundary of the reference pattern and a beta roughness of a boundary of the beta pattern; transferring the design pattern to the shielding layer if a difference between the reference roughness and the beta roughness is within a tolerance; and transferring the design pattern of the photomask to a semiconductor substrate.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: May 30, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Cheng-Ming Lin, Hao-Ming Chang, Chih-Ming Chen, Chung-Yang Huang
  • Patent number: 11624978
    Abstract: A method for manufacturing a semiconductor includes: receiving a photomask substrate including a shielding layer; defining a chip region and a peripheral region adjacent to the chip region; forming a design pattern in the chip region; forming a reference pattern by emitting one first radiation shot and a beta pattern by emitting a plurality of second radiation shots in the peripheral region, wherein a pixel size of the first radiation shot is greater than a pixel size of the second radiation shot; comparing a reference roughness of a boundary of the reference pattern and a beta roughness of a boundary of the beta pattern; transferring the design pattern to the shielding layer if a difference between the reference roughness and the beta roughness is within a tolerance; and transferring the design pattern of the photomask to a semiconductor substrate.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: April 11, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Cheng-Ming Lin, Hao-Ming Chang, Chih-Ming Chen, Chung-Yang Huang
  • Patent number: 11616164
    Abstract: A method for producing a nitride compound semiconductor component is disclosed. In an embodiment the method includes providing a growth substrate, growing a nucleation layer of an aluminum-containing nitride compound semiconductor onto the growth substrate, growing a tension layer structure for generating a compressive stress, wherein the tension layer structure comprises at least a first GaN semiconductor layer and a second GaN semiconductor layer, and wherein an Al(Ga)N interlayer for generating the compressive stress is disposed between the first GaN semiconductor layer and the second GaN semiconductor layer and growing a functional semiconductor layer sequence of the nitride compound semiconductor component onto the tension layer structure, wherein a growth of the second GaN semiconductor layer is preceded by a growth of a first 3D AlGaN layer on the Al(Ga)N interlayer in such a way that it has nonplanar structures.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: March 28, 2023
    Assignee: OSRAM OLED GMBH
    Inventors: Philipp Drechsel, Werner Bergbauer, Thomas Lehnhardt, Jürgen Off, Joachim Hertkorn
  • Patent number: 11610994
    Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a gate stack over an active region and a source/drain region in the active region adjacent the gate stack. The source/drain region includes a first semiconductor layer having a first germanium concentration and a second semiconductor layer over the first semiconductor layer. The second semiconductor layer has a second germanium concentration greater than the first germanium concentration. The source/drain region further includes a third semiconductor layer over the second semiconductor layer and a fourth semiconductor layer over the third semiconductor layer. The third semiconductor layer has a third germanium concentration greater than the second germanium concentration. The fourth semiconductor layer has a fourth germanium concentration less than the third germanium concentration.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: March 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Kun-Mu Li, Hsueh-Chang Sung
  • Patent number: 11574841
    Abstract: The present application relates to a semiconductor device with an intervening layer and a method for fabricating the semiconductor device with the intervening layer. The semiconductor device includes a substrate, a bottom conductive plug positioned on the substrate, an intervening conductive layer positioned on the bottom conductive plug, and a top conductive plug positioned on the intervening conductive layer. A top surface of the intervening conductive layer is non-planar.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: February 7, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Ping Hsu
  • Patent number: 11522059
    Abstract: Disclosed herein are transistor electrode-channel arrangements, and related methods and devices. For example, in some embodiments, a transistor electrode-channel arrangement may include a channel material, source/drain electrodes provided over the channel material, and a sealant at least partially enclosing one or more of the source/drain electrodes, wherein the sealant includes one or more metallic conductive materials.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: December 6, 2022
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Tahir Ghani, Jack T. Kavalieros, Gilbert W. Dewey, Van H. Le, Lawrence D. Wong, Christopher J. Jezewski
  • Patent number: 11476338
    Abstract: Embodiments related to transistors and integrated circuits having aluminum indium phosphide subfins and germanium channels, systems incorporating such transistors, and methods for forming them are discussed.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: October 18, 2022
    Assignee: Intel Corporation
    Inventors: Matthew V. Metz, Willy Rachmady, Harold W. Kennel, Van H. Le, Benjamin Chu-Kung, Jack T. Kavalieros, Gilbert Dewey
  • Patent number: 11469229
    Abstract: In an embodiment, a method includes: forming a first fin and a second fin extending from a semiconductor substrate; depositing a liner layer along a first sidewall of the first fin, a second sidewall of the second fin, and a top surface of the semiconductor substrate, the liner layer formed of silicon oxynitride having a nitrogen concentration in a range of 5% to 30%; depositing a fill material on the liner layer, the fill material formed of silicon; annealing the liner layer and the fill material, the annealing converting the fill material to silicon oxide, the annealing decreasing the nitrogen concentration of the liner layer to a range of 1% to 5%; and recessing the liner layer and the fill material to form an isolation region between the first fin and the second fin.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: October 11, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wan-Yi Kao, Szu-Ping Lee, Che-Hao Chang, Chun-Heng Chen, Yung-Cheng Lu, Chi On Chui
  • Patent number: 11444196
    Abstract: A method of forming a semiconductor structure includes: providing a substrate including an upper surface, a gate structure disposed on the upper surface, a spacer disposed on a sidewall of the gate structure, a first region in the substrate, and a second region in the substrate; masking the second region and amorphizing the first region, such that an amorphous layer is formed in the first region; depositing a stress layer on the substrate, wherein the stress layer conformally covers the gate structure, the spacer, the first region and the second region; and recrystallizing the amorphous layer, thereby forming a dislocation in the first region.
    Type: Grant
    Filed: December 13, 2020
    Date of Patent: September 13, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Po-Yu Yang
  • Patent number: 11411106
    Abstract: A semiconductor device includes a substrate including an active pattern, a gate electrode crossing the active pattern in a plan view, and a ferroelectric pattern interposed between the active pattern and the gate electrode. The gate electrode includes a work function metal pattern disposed on the ferroelectric pattern, and an electrode pattern filling a recess formed in an upper portion of the work function metal pattern. A top surface of a topmost portion of the ferroelectric pattern is lower than a bottom surface of the recess.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: August 9, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Weonhong Kim, Wandon Kim, Hyeonjun Baek, Sangjin Hyun
  • Patent number: 11387357
    Abstract: A compound semiconductor device includes: a semiconductor laminate structure including an electron transit layer and an electron supply layer that are formed from a compound semiconductor; a gate electrode, a source electrode, and a drain electrode that are provided above the electron supply layer; and an insulating layer that is provided between the source electrode and the drain electrode, over the semiconductor laminate structure, and with a gate recess formed therein, wherein the gate electrode includes: a first portion in the gate recess; and a second portion that is coupled to the first portion and is provided over the insulating layer at a position further on the drain electrode side than the gate recess, wherein the insulating layer includes an aluminum oxide film in direct contact with the semiconductor laminate structure.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: July 12, 2022
    Assignee: FUJITSU LIMITED
    Inventors: Shirou Ozaki, Toshihiro Ohki
  • Patent number: 11355611
    Abstract: A semiconductor device includes a source/drain feature disposed over a substrate. The source/drain feature includes a first nanowire, a second nanowire disposed over the first nanowire, a cladding layer disposed over the first nanowire and the second nanowire and a spacer layer extending from the first nanowire to the second nanowire. The device also includes a conductive feature disposed directly on the source/drain feature such that the conductive feature physically contacts the cladding layer and the spacer layer.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: June 7, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Ching, Ching-Fang Huang, Wen-Hsing Hsieh, Ying-Keung Leung, Chih-Hao Wang, Carlos H. Diaz
  • Patent number: 11335552
    Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes an oxide semiconductor nanostructure suspended over a substrate. The semiconductor device structure also includes a source/drain structure adjacent to the oxide semiconductor nanostructure. The source/drain structure contains oxygen, and the oxide semiconductor nanostructure has a greater atomic concentration of oxygen than that of the source/drain structure. The semiconductor device structure further includes a gate stack wrapping around the oxide semiconductor nanostructure.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: May 17, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Yu Chang, Sai-Hooi Yeong, Yu-Ming Lin
  • Patent number: 11335815
    Abstract: A semiconductor device includes a semiconductor die, an N-doped region, an N-contact metal, a PN junction mesa, a P-contact metal, a first passivation layer, an anode feed metal, and a cathode feed metal. The semiconductor die may include a plurality of semiconductor layers disposed on an insulating substrate. The N-doped region may define an active area of the device. The N-contact metal may be disposed on a first portion of the N-doped region. The PN junction mesa may be disposed on a second portion of the N-doped region. The PN junction mesa may comprise a hyperabrupt N-doping layer disposed on the first portion of the N-doped region and a P-doped layer disposed on the hyperabrupt N-doping layer. The P-contact metal may be disposed on the P-doped layer of the PN junction mesa. The first passivation layer may cover the semiconductor layers of the semiconductor device and have openings for the N-contact metal and the P-contact metal. The anode feed metal may connect the P-contact metal to a first bond pad.
    Type: Grant
    Filed: February 20, 2021
    Date of Patent: May 17, 2022
    Assignee: Global Communication Semiconductors, LLC
    Inventors: Yuefei Yang, Shing-Kuo Wang, Wing Yau
  • Patent number: 11295951
    Abstract: A method for forming a wide band gap semiconductor device is provided. The method includes forming a gate insulation layer on a wide band gap semiconductor substrate and annealing the gate insulation layer using at least a first reactive gas species and a second reactive gas species, wherein the first reactive gas species differs from the second reactive gas species. The method can include forming a gate electrode on the gate insulation layer after annealing the gate insulation layer.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: April 5, 2022
    Assignee: Infineon Technologies AG
    Inventors: Thomas Aichinger, Gerald Rescher, Michael Stadtmueller
  • Patent number: 11264500
    Abstract: Disclosed herein are structures and techniques for device isolation in integrated circuit (IC) assemblies. In some embodiments, an IC assembly may include multiple transistors spaced apart by an isolation region. The isolation region may include a doped semiconductor body whose dopant concentration is greatest at one or more surfaces, or may include a material that is lattice-mismatched with material of the transistors, for example.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: March 1, 2022
    Assignee: Intel Corporation
    Inventors: Rishabh Mehandru, Stephen M. Cea, Tahir Ghani
  • Patent number: 11257951
    Abstract: A method of manufacturing a semiconductor device includes forming a first gate stack over a substrate. The method further includes etching the substrate to define a cavity. The method further includes growing a first epitaxial (epi) material in the cavity, wherein the first epi material includes a first upper surface having a first crystal plane. The method further includes growing a second epi material on the first epi material, wherein the second epi material includes a second upper surface having the first crystal plane. The method further includes treating the second epi material, wherein treating the second epi material comprises causing the second upper surface to transform to a second crystal plane different from the first crystal plane.
    Type: Grant
    Filed: November 4, 2020
    Date of Patent: February 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Lilly Su, Chii-Horng Li, Ming-Hua Yu, Pang-Yen Tsai, Tze-Liang Lee, Yen-Ru Lee
  • Patent number: 11257712
    Abstract: A method includes providing a structure that includes a semiconductor substrate, an epitaxial source/drain feature over the semiconductor substrate, and one or more dielectric layers over the epitaxial source/drain feature; etching a hole into the one or more dielectric layer to expose a portion of the epitaxial source/drain feature; forming a silicide layer over the portion of the epitaxial source/drain feature; forming a conductive barrier layer over the silicide layer; and applying a plasma cleaning process to at least the conductive barrier layer, wherein the plasma cleaning process uses a gas mixture including N2 gas and H2 gas and is performed at a temperature that is at least 300° C.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: February 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Wei Chang, Yu-Ming Huang, Ethan Tseng, Ken-Yu Chang, Yi-Ying Liu
  • Patent number: 11190152
    Abstract: A radio frequency (RF) power amplifier (PA) for amplifying an RF signal between a source node and an output node, the RF PA including a silicon substrate with a complementary metal oxide semiconductor (CMOS) N-type transistor with a source region and a drain region fabricated therein. The source region includes the source node of the RF PA and the drain region includes the output node of the RF PA. The RF PA includes a planar resistor fabricated on the surface of the silicon substrate proximal to the drain region of the N-type transistor, wherein the resistor provides a thermal source for heating the RF PA; and a control circuit providing thermal heating to the RF PA by providing power to the planar resistor during RF signal bursts wherein the added thermal heating compensates transient heating within the transistor and results in a linear power amplification operation.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: November 30, 2021
    Assignee: BeRex, Inc.
    Inventor: Oleksandr Gorbachov
  • Patent number: 11184003
    Abstract: A silicon carbide power device is controlled by a driver and comprises a gate-to-source voltage and a source voltage, wherein the source voltage decreases according to an increase of the gate-to-source voltage, or the source voltage increases according to a decrease of the gate-to-source voltage. Thus, a spike caused by a change of the gate-to-source voltage is suppressed, thereby suppressing the crosstalk phenomenon of the silicon carbide power device.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: November 23, 2021
    Assignee: SHANGHAI HESTIA POWER INC.
    Inventors: Fu-Jen Hsu, Chien-Chung Hung, Kuo-Ting Chu, Chwan-Ying Lee
  • Patent number: 11101143
    Abstract: A semiconductor device includes an isolation insulating layer disposed over a substrate, a fin structure disposed over the substrate, and extending in a first direction in plan view, an upper portion of the fin structure being exposed from the isolation insulating layer, a gate structure disposed over a part of the fin structure, the gate structure extending in a second direction crossing the first direction, and a source/drain structure formed on the upper portion of the fin structure, which is not covered by the gate structure and exposed from the isolation insulating layer. The source/drain structure includes a SiP layer, and an upper portion of the source/drain structure includes an alloy layer of Si, Ge and Ti.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: August 24, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Yuan-Shun Chao, Chih-Wei Kuo
  • Patent number: 11081356
    Abstract: A method includes providing a structure having a substrate, first and second semiconductor fins extending from the substrate, and a dielectric fin between the first and second semiconductor fins; forming a temporary gate on top and sidewalls of the first and second semiconductor fins and the dielectric fin; forming gate spacers on sidewalls of the temporary gate; removing the temporary gate and a first portion of the dielectric fin between the gate spacers; forming a gate between the gate spacers and on top and sidewalls of the first and second semiconductor fins, wherein the dielectric fin is in physical contact with sidewalls of the gate; removing a second portion of the dielectric fin, thereby exposing the sidewalls of the gate; and performing an etching process to the gate through the exposed sidewalls of the gate, thereby separating the gate into a first gate segment and a second gate segment.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: August 3, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pei-Yu Wang, Zhi-Chang Lin, Ching-Wei Tsai, Kuan-Lun Cheng
  • Patent number: 11062951
    Abstract: A process for fabricating a field-effect transistor includes providing a structure including a first silicon layer and a second layer, made of SiGe alloy, covering the first silicon layer. The method further includes forming a sacrificial gate covered with a hardmask on top of the second layer made of SiGe alloy and etching the second layer made of SiGe alloy, following the pattern of the hardmask in order to delimit an element made of SiGe alloy in the second layer. The method also includes forming spacers on top of the first silicon layer on either side of the sacrificial gate and of the element, removing the sacrificial gate, and enriching the first layer arranged beneath the element in germanium using a germanium condensation process.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: July 13, 2021
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventor: Shay Reboh
  • Patent number: 11056574
    Abstract: This disclosed technology generally relates to a semiconductor device. One aspect relates to a method of fabricating a stacked semiconductor including forming a semiconductor structure protruding above the substrate and a gate structure extending across the semiconductor structure. The semiconductor structure includes a lower channel layer formed of a first material, an intermediate layer formed of a second material and an upper channel layer formed of a third material. The method additionally includes forming oxidized end portions defining second spacers on end surfaces of an upper layer. And forming the oxidized end portions comprises oxidizing end portions of the upper channel layer at opposite sides of the gate structure using an oxidization process adapted to cause a rate of oxidation of the third material which is greater than a rate of oxidation of the first material, while first spacers cover intermediate end surfaces.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: July 6, 2021
    Assignee: IMEC vzw
    Inventor: Kurt Wostyn
  • Patent number: 11031499
    Abstract: An apparatus including a transistor device including a channel disposed on a substrate between a source and a drain, a gate electrode disposed on the channel, wherein the channel includes a length dimension between source and drain that is greater than a length dimension of the gate electrode such that there is a passivated underlap between an edge of the gate electrode and an edge of the channel relative to each of the source and the drain. A method including forming a channel of a transistor device on a substrate; forming first and second passivation layers on a surface of substrate on opposite sides of the channel; forming a gate stack on the channel between first and second passivation layers; and forming a source on the substrate between the channel and the first passivation layer and a drain on the substrate between the channel and the second passivation layer.
    Type: Grant
    Filed: July 2, 2016
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Van H. Le, Matthew V. Metz, Benjamin Chu-Kung, Ashish Agrawal, Jack T. Kavalieros
  • Patent number: 10957784
    Abstract: A method of manufacturing a semiconductor device includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers on a substrate. The first and second semiconductor layers include first end portions on either side of a second portion along a length of the first and second semiconductor layers. The first and second semiconductor layers are formed of different materials. The second portion of the first semiconductor layers is removed to form spaces. A mask layer is formed over the second portion of an uppermost second semiconductor layer above the spaces. The first portions of first and second semiconductor layers are irradiated with radiation from a radiation source to cause material from the first portions of the first and second semiconductor layers to combine with each other.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: March 23, 2021
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: I-Hsieh Wong, Samuel C. Pan, Chee-Wee Liu, Huang-Siang Lan, Chung-En Tsai, Fang-Liang Lu
  • Patent number: 10892365
    Abstract: A semiconductor structure includes a semiconductor substrate, at least a silicon germanium (SiGe) epitaxial region disposed in the semiconductor substrate, and a contact structure disposed on the SiGe epitaxial region. The contact structure includes a titanium nitride (TiN) barrier layer and a metal layer surrounded by the TiN barrier layer. A crystalline titanium germanosilicide stressor layer is disposed in the SiGe epitaxial region and between the TiN barrier layer and the SiGe epitaxial region.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: January 12, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Cheng-Yeh Huang, Te-Chang Hsu, Chun-Jen Huang, Che-Hsien Lin, Yao-Jhan Wang
  • Patent number: 10833107
    Abstract: Provided are a thin film transistor and manufacturing method therefor, and an array substrate, and a display device. The method includes: forming a source electrode and a drain electrode on a substrate; forming a photoresist layer at the side of the source electrode and the drain electrode away from the substrate; performing exposure and developing treatment on the photoresist layer so as to obtain a photoresist pattern; successively forming a semiconductor layer, a first insulation layer and a conducting layer in sequence on at the side of the photoresist pattern away from the substrate; and removing the photoresist pattern so as to obtain an active layer a gate insulation layer and a gate electrode.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: November 10, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Fengjuan Liu, Youngsuk Song, Hongda Sun
  • Patent number: 10818792
    Abstract: Structures for a field-effect transistor and methods of forming structures for a field-effect transistor. A layer stack includes nanosheet channel layers arranged to alternate with sacrificial layers. First and second gate structures are formed that extend across the layer stack and that are separated by a first gap. First and second sidewall spacers are formed over the layer stack and within the first gap respectively adjacent to the first and second gate structures, and the layer stack is subsequently etched to form first and second body features that are separated by a second gap. The sacrificial layers are recessed relative to the nanosheet channel layers to define indents in the first and second body features, and the first and second sidewall spacers are subsequently removed. After removing the first and second sidewall spacers, a conformal layer is deposited in the second gap that fills the indents to define inner spacers.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: October 27, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Julien Frougier, Ruilong Xie, Daniel Chanemougame
  • Patent number: 10790302
    Abstract: Provided herein is a semiconductor device and a method of manufacturing the same. The semiconductor device has improved erase characteristics by using a select gate enclosing a portion a first semiconductor region overlapping a second semiconductor region. The first semiconductor region and the second semiconductor region are formed of different semiconductor materials.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: September 29, 2020
    Assignee: SK hynix Inc.
    Inventor: Jin Ha Kim
  • Patent number: 10679900
    Abstract: A method includes forming Shallow Trench Isolation (STI) regions in a semiconductor substrate and a semiconductor strip between the STI regions. The method also include replacing a top portion of the semiconductor strip with a first semiconductor layer and a second semiconductor layer over the first semiconductor layer. The first semiconductor layer has a first germanium percentage higher than a second germanium percentage of the second semiconductor layer. The method also includes recessing the STI regions to form semiconductor fins, forming a gate stack over a middle portion of the semiconductor fin, and forming gate spacers on sidewalls of the gate stack. The method further includes forming fin spacers on sidewalls of an end portion of the semiconductor fin, recessing the end portion of the semiconductor fin, and growing an epitaxial region over the end portion of the semiconductor fin.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Chiang, Ting-Hung Hsu, Chao-Hsiung Wang, Chi-Wen Liu
  • Patent number: 10658489
    Abstract: A semiconductor device and a fabrication method are provided. The fabrication method includes providing a gate structure on a substrate and a first protective layers on the gate structure; forming an initial sidewall spacer on a sidewall of each of the gate structure and the first protective layer; forming a first sidewall spacer on a sidewall of the initial sidewall spacer, the first and initial sidewall spacers being made of different materials; forming a second sidewall spacer by removing a portion of the initial sidewall spacer, leaving a trench formed above the second sidewall spacer and between the first sidewall spacer and the first protective layer; and forming a second protective layer in the trench, the second protective layer and the first sidewall spacer being made of a same material. The second sidewall spacer has a top surface higher than or level with a top surface of the gate structure.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: May 19, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Er Hu Zheng, Lu Jun Zou