With Channel Containing Layer, E.g., P-base, Fo Rmed In Or On Drain Region, E.g., Dmos Transistor (epo) Patents (Class 257/E21.417)
  • Patent number: 10050115
    Abstract: Approaches for LDMOS devices are provided. A method of forming a semiconductor structure includes forming a gate dielectric including a first portion having a first uniform thickness, a second portion having a second uniform thickness different than the first uniform thickness, and a transition portion having tapered surface extending from the first portion to the second portion. The gate dielectric is formed on a planar upper surface of a substrate. The tapered surface is at an acute angle relative to the upper surface of the substrate.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: August 14, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Brennan J. Brown, Natalie B. Feilchenfeld, Max G. Levy, Santosh Sharma, Yun Shi, Michael J. Zierak
  • Patent number: 10032905
    Abstract: Integrated circuits and methods of producing integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a substrate and a gate overlying the substrate. A drain is defined within the substrate, where the drain and the gate are separated by a drain distance. A source is defined within the substrate adjacent to the gate, wherein the source is divided into two or more source sections.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: July 24, 2018
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventor: Guowei Zhang
  • Patent number: 9954098
    Abstract: A semiconductor structure and a method of manufacturing the semiconductor structure are provided. The semiconductor structure includes at least a substrate, an isolated structure, a gate, a source, a drain, a deep well, and a body well. The deep well extends under the isolated structure, and the body well is formed in the deep well between the gate and the isolated structure, wherein the body well has a convex region extending under the isolated structure. The deep well has a drive-in region outside the convex region of the body well, and the drive-in region has a lower doping concentration than remainder of the deep well.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: April 24, 2018
    Assignee: MACRONIX International Co., Ltd.
    Inventor: Yu-Jui Chang
  • Patent number: 9947787
    Abstract: Devices, structures, and methods thereof for providing a Schottky or Schottky-like contact as a source region and/or a drain region of a power transistor are disclosed. A power transistor structure comprises a substrate of a first dopant polarity, a drift region formed on or within the substrate, a body region formed on or within the drift region, a gate structure formed on or within the substrate, a source region adjacent to the gate structure, a drain region formed adjacent to the gate structure. At least one of the source region and the drain region is formed from a Schottky or Schottky-like contact substantially near a surface of the substrate, comprising a silicide layer and an interfacial dopant segregation layer. The Schottky or Schottky-like contact is formed by low-temperature annealing a dopant segregation implant in the source and/or drain region.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: April 17, 2018
    Assignee: SILICET, LLC
    Inventors: Gary M. Dolny, William R. Richards, Jr., Randall Milanowski
  • Patent number: 9685528
    Abstract: A semiconductor device and method of manufacturing a semiconductor device using a semiconductor fin is provided. In an embodiment the fin is formed from a substrate, a middle section of the fin is covered, and then portions of the fin on either side of the middle section are removed. A series of implants is then performed and a gate dielectric and a gate electrode are formed to form a tunneling field effect transistor from the fin.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: June 20, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Blandine Duriez, Aryan Afzalian
  • Patent number: 9443975
    Abstract: Forming a transistor transistor includes forming a surface region, a gate, a source dopant region, a drain dopant region, a drift dopant region, a set of electrically conductive shield plates, and a shield plate dopant region. A sidewall of the gate aligns with a drain side boundary of the surface region. The drain dopant region is formed within the surface region on the drain side. The drift dopant region is formed within the surface region between the drain side boundary and the drain dopant region. The set of electrically conductive shield plates includes a first shield plate overlying the drift dopant region. The shield plate dopant region is formed within the drift dopant region and underlies the set of shield plates.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: September 13, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Zihao M. Gao, David C. Burdeaux, Agni Mitra
  • Patent number: 9385230
    Abstract: A semiconductor device including a first conductor layer, a second conductor layer formed over the first conductor layer, a third conductor layer formed over the second conductor layer, a gate trench which passes through the third conductor layer and is formed in the second conductor layer, a first insulating film formed on an inner wall of the gate trench, a second insulating film formed on the inner wall of the gate trench, a first buried conductor layer formed in the gate trench, a gate electrode formed in the gate trench, a fourth conductor layer of the second conductivity type formed on a lower end of the first buried conductor layer and a lower end of the gate trench, and a fifth conduction layer of the first conductivity type formed over the third conductor layer. The first insulating film is thicker than the second insulating film.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: July 5, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Akihiro Shimomura, Yutaka Akiyama, Saya Shimomura, Yasutaka Nakashiba
  • Patent number: 9034711
    Abstract: An LDMOS is formed with a second gate stack over the n? drift region, having a common gate electrode with the gate stack, and having a higher work function than the gate stack. Embodiments include forming a first conductivity type well, having a source, surrounded by a second conductivity type well, having a drain, in a substrate, forming first and second gate stacks on the substrate over a portion of the first well and a portion of the second well, respectively, the first and second gate stacks sharing a common gate electrode, and tuning the work functions of the first and second gate stacks to obtain a higher work function for the second gate stack. Other embodiments include forming the first gate stack with a first high-k dielectric and the second gate stack with a second high-k dielectric, and forming the first and second gate stacks with asymmetric dielectrics.
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: May 19, 2015
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Eng Huat Toh, Jae Gon Lee, Chung Foong Tan, Elgin Quek
  • Patent number: 9024383
    Abstract: A super junction semiconductor device comprises a semiconductor portion with mesa regions protruding from a base section. The mesa regions are spatially separated in a lateral direction parallel to a first surface of the semiconductor portion. A compensation structure with at least two first compensation layers of a first conductivity type and at least two second compensation layers of a complementary second conductivity type may cover sidewalls of the mesa regions and portions of the base section between the mesa regions. Buried lateral faces of segments of the compensation structure may cut the first and second compensation layers between the mesa regions. A drain connection structure of the first conductivity type may extend along the buried lateral faces and may structurally connect the first compensation layers in an economic way keeping the thermal budget low.
    Type: Grant
    Filed: May 1, 2013
    Date of Patent: May 5, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Stefan Gamerith, Armin Willmeroth, Franz Hirler
  • Patent number: 9013007
    Abstract: A depletion type MOS transistor includes a well region having a first conductivity type and formed on a semiconductor substrate, a gate insulating film formed on the well region, and a gate electrode formed on the gate insulating film. Source and drain regions having a second conductivity type different from the first conductivity type are formed on respective sides of the gate electrode and within the well region. A first low concentration impurity region has the second conductivity type and is formed below the gate insulating film between the source and drain regions and within the well region. A second low concentration impurity region has the first conductivity type and is formed below the first low concentration impurity region between the source and drain regions and within the well region.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: April 21, 2015
    Assignee: Seiko Instruments Inc.
    Inventor: Hirofumi Harada
  • Patent number: 8987820
    Abstract: A LDMOS device includes a substrate having opposite first and second surfaces; a well region in a portion of the substrate; a gate structure over a portion of the substrate; a first doped region disposed in a portion of the well region from a first side; a second doped region disposed in the well region from a second side; a third doped region disposed in the first doped region; a fourth doped region disposed in the second doped region; a first trench in the third doped region, the first doped region, the well region, and the substrate adjacent to the first surface; a conductive contact in the first trench; a second trench in the substrate adjacent to the second surface; a first conductive layer in second trench; and a second conductive layer over the second surface of the substrate and the first conductive layer.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: March 24, 2015
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Tsung-Hsiung Lee, Jui-Chun Chang
  • Patent number: 8981475
    Abstract: A lateral diffusion metal oxide semiconductor (LDMOS) comprises a semiconductor substrate having an STI structure in a top surface of the substrate, a drift region below the STI structure, and a source region and a drain region on opposite sides of the STI structure. A gate conductor is on the substrate over a gap between the STI structure and the source region and partially overlaps the drift region. A conformal dielectric layer is on the top surface and forms a mesa above the gate conductor. The conformal dielectric layer has a conformal etch-stop layer embedded therein. Contact studs extend through the dielectric layer and the etch-stop layer, and are connected to the source region, drain region, and gate conductor. A source electrode contacts the source contact stud, a gate electrode contacts the gate contact stud, and a drain electrode contacts the drain contact stud. A drift electrode is over the drift region.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: March 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Santosh Sharma, Yun Shi, Anthony K. Stamper
  • Patent number: 8969913
    Abstract: A high voltage laterally diffused metal-oxide-semiconductor (HV LDMOS) device, particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate having at least one highly doped buried portion, a first doped well grown over the substrate, a gate structure formed on the first well, a source and a drain formed on either side of the gate structure, and a second doped well having a U-shaped cross section formed in the first well. A portion of the drain is formed over the first well outside of the second well.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: March 3, 2015
    Assignee: Taiwan Semiconductor Maufacturing Company, Ltd.
    Inventors: Ker Hsiao Huo, Chih-Chang Cheng, Ru-Yi Su, Jen-Hao Yeh, Fu-Chih Yang, Chun Lin Tsai
  • Patent number: 8962397
    Abstract: At least one N-well implant having a different doping level is formed in a silicon substrate by first etching the substrate with an alignment target for aligning future process masks thereto. This alignment target is outside of any active device area. By using at least one N-well implant having a different doping level in combination with the substrate, a graded junction in the drift area of a metal oxide semiconductor (MOS) field effect transistor (FET) can be created and a pseudo Ldd structure may be realized thereby.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: February 24, 2015
    Assignee: Microchip Technology Incorporated
    Inventors: Gregory Dix, Leighton E. McKeen, Ian Livingston, Roger Melcher, Rohan Braithwaite
  • Patent number: 8940608
    Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate including a first region of a first doping type, a second region of the first doping type spaced from the first region, a drift region of the first doping type positioned between the first region and the second region, and regions of the opposite doping type. A mask covering both the drift region and the regions of the opposite doping type is formed. Then, a source/drain ion implantation is performed into the first region and the second region. The mask prevents the drift region and the regions of the opposite doping type from receiving the source/drain ion implantation.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: January 27, 2015
    Assignee: Globalfoundries, Inc.
    Inventors: Jia Feng, Kuldeep Amarnath, Kevin J. Yang
  • Patent number: 8912057
    Abstract: A semiconductor device with an n-type transistor and a p-type transistor having an active region is provided. The active region further includes two adjacent gate structures. A portion of a dielectric layer between the two adjacent gate structures is selectively removed to form a contact opening having a bottom and sidewalls over the active region. A bilayer liner is selectively provided within the contact opening in the n-type transistor and a monolayer liner is provided within the contact opening in the p-type transistor. The contact opening in the n-type transistor and p-type transistor is filled with contact material. The monolayer liner is treated to form a silicide lacking nickel in the p-type transistor.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: December 16, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Derya Deniz
  • Patent number: 8890244
    Abstract: A lateral power MOSFET with a low specific on-resistance is described. Stacked P-top and N-grade regions in patterns of articulated circular arcs separate the source and drain of the transistor.
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: November 18, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Cheng-Chi Lin, Chen-Yuan Lin, Shih-Chin Lien, Shyi-Yuan Wu
  • Patent number: 8866224
    Abstract: Disclosed are a TFT array substrate for decreasing a bezel width and a display device including the same. The display device includes a first substrate including a display area (including a pixel formed in a pixel area defined by a gate line and a data line which intersect) and a non-display area that includes a built-in shift register connected to the gate line and a gate link part connected to the built-in shift register, a second substrate facing the first substrate, and a seal pattern formed in the non-display area of the first substrate in correspondence with an edge portion of the second substrate to facing-couple the first and second substrates. The seal pattern includes a first hardening area hardened by a first hardening process, and a second hardening area hardened by a second hardening process.
    Type: Grant
    Filed: April 5, 2013
    Date of Patent: October 21, 2014
    Assignee: LG Display Co., Ltd.
    Inventors: Byong Wook Shin, Ji Eun Chae, Tae Keun Lee
  • Patent number: 8865541
    Abstract: An integrated circuit contains a voltage protection structure having a diode isolated DENMOS transistor with a guard element proximate to the diode and the DENMOS transistor. The guard element includes an active area coupled to ground. The diode anode is connected to an I/O pad. The diode cathode is connected to the DENMOS drain. The DENMOS source is grounded. A process of forming the integrated circuit is also disclosed.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: October 21, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Farzan Farbiz, Akram A. Salman
  • Patent number: 8853022
    Abstract: A method of forming a device is presented. The method includes providing a substrate having a device region which includes a source region, a gate and a drain region defined thereon. The method also includes implanting the gate. The gate comprises one or more doped portions with different dopant concentrations. A source and a drain are formed in the source region and drain region. The drain is separated from the gate on a second side of the gate and the source is adjacent to a first side of the gate.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: October 7, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventor: Guowei Zhang
  • Patent number: 8847332
    Abstract: A high voltage semiconductor device is provided. The device includes a semiconductor substrate having a high voltage well with a first conductivity type therein. A gate structure is disposed on the semiconductor substrate of the high voltage well. A source doped region and a drain doped region are in the high voltage well on both sides of the gate structure, respectively. A lightly doped region with the first conductivity type is between the source and drain doped regions and relatively near to the source doped region. The disclosure also presents a method for fabricating a high voltage semiconductor device.
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: September 30, 2014
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Wei-Chun Chou, Yi-Hung Chiu, Chu-Feng Chen, Cheng-Yi Hsieh, Chung-Ren Lao
  • Patent number: 8841190
    Abstract: This invention relates to a MOS device for making the source/drain region closer to the channel region and a method of manufacturing the same, comprising: providing an initial structure, which includes a substrate, an active region, and a gate stack; performing ion implantation in the active region on both sides of the gate stack, such that part of the substrate material undergoes pre-amorphization to form an amorphous material layer; forming a first spacer; with the first spacer as a mask, performing dry etching, thereby forming a recess, with the amorphous material layer below the first spacer kept; performing wet etching using an etchant solution that is isotropic to the amorphous material layer and whose etch rate to the amorphous material layer is greater than or substantially equal to the etch rate to the {100} and {110} surfaces of the substrate material but is far greater than the etch rate to the {111} surface of the substrate material, thus removing the amorphous material layer below the first space
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: September 23, 2014
    Assignee: The Institute of Microelectronics Chinese Academy of Science
    Inventors: Changliang Qin, Huaxiang Yin
  • Patent number: 8836026
    Abstract: On a doped well (2) for a drift section, at least two additional dielectric regions (7,9) having different thicknesses are present between a first contact region (4) for a drain and a second contact region (5) for source on the upper face (10) of the substrate (1), and the gate electrode (11) or an electric conductor, which is electrically conductively connected to the gate electrode, covers each of said additional dielectric regions at least partially.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: September 16, 2014
    Assignee: AMS AG
    Inventor: Georg Roehrer
  • Patent number: 8823051
    Abstract: A diode-connected lateral transistor on a substrate of a first conductivity type includes a vertical parasitic transistor through which a parasitic substrate leakage current flows. Means for shunting at least a portion of the flow of parasitic substrate leakage current away from the vertical parasitic transistor is provided.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: September 2, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Jun Cai, Micheal Harley-Stead, Jim G. Holt
  • Patent number: 8803235
    Abstract: A lateral-diffused metal oxide semiconductor device (LDMOS) includes a substrate, a first deep well, at least a field oxide layer, a gate, a second deep well, a first dopant region, a drain and a common source. The substrate has the first deep well which is of a first conductive type. The gate is disposed on the substrate and covers a portion of the field oxide layer. The second deep well having a second conductive type is disposed in the substrate and next to the first deep well. The first dopant region having a second conductive type is disposed in the second deep well. The doping concentration of the first dopant region is higher than the doping concentration of the second deep well.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: August 12, 2014
    Assignee: United Microelectronics Corp.
    Inventors: An-Hung Lin, Hong-Ze Lin, Bo-Jui Huang, Wei-Shan Liao, Ting-Zhou Yan, Kun-Yi Chou, Chun-Wei Chen
  • Patent number: 8790966
    Abstract: A method of forming a device is disclosed. The method includes providing a substrate having a device region. The device region includes a source region, a gate region and a drain region defined thereon. The substrate is prepared with gate layers on the substrate. The gate layers are patterned to form a gate in the gate region and a field structure surrounding the drain region. A source and a drain are formed in the source region and drain region respectively. The drain is separated from the gate on a second side of the gate and the source is adjacent to a first side of the gate. An interconnection to the field structure is formed. The interconnection is coupled to a potential which distributes the electric field across the substrate between the second side of the gate and the drain.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: July 29, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Guowei Zhang, Purakh Raj Verma, Baofu Zhu
  • Patent number: 8785987
    Abstract: An IGFET device includes: —a semiconductor body having a major surface, —a source region of first conductivity type abutting the surface, —a drain region of the first conductivity-type abutting the surface and spaced from the source region with a channel therefrom, —an active gate overlying the channel and insulated from the channel by a first dielectric material forming the gate oxide of the IGFET device, —a dummy gate positioned between the active gate and the drain and insulated from the active gate by a second dielectric material so that a capacitance is formed between the active gate and the dummy gate, and insulated from the drain region by the gate oxide, wherein the active gate and the dummy gate are forming the electrodes of the capacitance substantially perpendicular to the surface.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: July 22, 2014
    Assignee: Acco
    Inventor: Denis Masliah
  • Patent number: 8748277
    Abstract: According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: June 10, 2014
    Assignee: Broadcom Corporation
    Inventors: Xiangdong Chen, Wei Xia, Henry Kuo-Shun Chen
  • Patent number: 8748271
    Abstract: An LDMOS is formed with a field plate over the n? drift region, coplanar with the gate stack, and having a higher work function than the gate stack. Embodiments include forming a first conductivity type well, having a source, surrounded by a second conductivity type well, having a drain, in a substrate, forming first and second coplanar gate stacks on the substrate over a portion of the first well and a portion of the second well, respectively, and tuning the work functions of the first and second gate stacks to obtain a higher work function for the second gate stack. Other embodiments include forming the first gate stack of a high-k metal gate and the second gate stack of a field plate on a gate oxide layer, forming the first and second gate stacks with different gate electrode materials on a common gate oxide, and forming the gate stacks separated from each other and with different gate dielectric materials.
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: June 10, 2014
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Eng Huat Toh, Jae Gon Lee, Chung Foong Tan, Elgin Quek
  • Patent number: 8729630
    Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: May 20, 2014
    Assignee: Richtek Tehnology Corporation, R.O.C.
    Inventors: Ching-Yao Yang, Tsung-Yi Huang, Huan-Ping Chu, Hung-Der Su
  • Publication number: 20140124858
    Abstract: A semiconductor device is provided. The device includes a semiconductor substrate and a gate structure thereon. A well region is formed in the semiconductor substrate. A drain region and a source region are respectively formed in the semiconductor substrate inside and outside of the well region. At least one set of the first and second heavily doped regions is formed in the well region between the drain region and the source region, wherein the first and second heavily doped regions are stacked vertically from bottom to top and have a doping concentration which is larger than that of the well region. The semiconductor substrate and the first heavily doped region have a first conductivity type and the well region and the second heavily doped region have a second conductivity type. A method for fabricating a semiconductor device is also disclosed.
    Type: Application
    Filed: November 7, 2012
    Publication date: May 8, 2014
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Wen-Cheng LIN, Shang-Hui TU, Shin-Cheng LIN
  • Publication number: 20140124856
    Abstract: A semiconductor device including a semiconductor substrate of a first conductivity type and an epitaxial structure of the first conductivity type disposed thereon is disclosed. A well region of a second conductivity type is formed in the epitaxial structure and the semiconductor substrate. A drain region and a source region are respectively formed in the epitaxial structure inside and outside of the well region. At least one set of the first and second heavily doped regions is formed in the well region between the drain region and the source region, wherein the first and second heavily doped regions of the first and second conductivity type, respectively, are stacked vertically from bottom to top and have a doping concentration which is larger than that of the well region. A gate structure is disposed on the epitaxial structure. A method for fabricating a semiconductor device is also disclosed.
    Type: Application
    Filed: November 7, 2012
    Publication date: May 8, 2014
    Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Wen-Cheng LIN, Shang-Hui TU, Shin-Cheng LIN
  • Patent number: 8716793
    Abstract: Disclosed are an LDMOS device and a method for manufacturing the same capable of decreasing the concentration of a drift region between a source finger tip and a drain, thereby increasing a breakdown voltage. An LDMOS device includes a gate which is formed on a substrate, a source and a drain which are separately arranged on both sides of the substrate with the gate interposed therebetween, a field oxide film which is formed to have a step between the gate and the drain, a drift region which is formed of first condition type impurity ions between the gate and the drain on the substrate, and at least one internal field ring which is formed inside the drift region and formed by selectively ion-implanting second conduction type impurity ions in accordance with the step of the field oxide film.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: May 6, 2014
    Assignee: Dongbu HiTek Co., Ltd.
    Inventors: Jae Hyun Yoo, Jong Min Kim
  • Patent number: 8716795
    Abstract: Methods of making, structures, devices, and/or applications for lateral double-diffused metal oxide semiconductor (LDMOS) transistors are disclosed. In one embodiment, a method of fabricating an LDMOS transistor with source, drain, and gate regions on a substrate, can include: forming p-type and n-type buried layer (PBL, NBL) regions; growing an epitaxial (N-EPI) layer on the NBL/PBL regions; forming a p-doped deep p-well (DPW) region on the PBL region; forming a well region in the N-EPI layer; forming a doped body region; forming an active area and a field oxide (FOX) region, and forming a drain oxide between the source and drain regions of the LDMOS transistor; forming a gate oxide adjacent to the source and drain regions, and forming a gate on the gate oxide and a portion of the drain oxide; and forming a doped drain region, and first and second doped source regions.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: May 6, 2014
    Assignees: Silergy Technology, Silergy Semiconductor Technology (Hangzhou) Ltd.
    Inventor: Budong You
  • Publication number: 20140117444
    Abstract: A lateral MOSFET comprises a plurality of isolation regions formed in a substrate, wherein a first isolation region is of a top surface lower than a top surface of the substrate. The lateral MOSFET further comprises a gate electrode layer having a first gate electrode layer formed over the first isolation region and a second gate electrode layer formed over the top surface of the substrate, wherein a top surface of the first gate electrode layer is lower than a top surface of the second gate electrode layer.
    Type: Application
    Filed: November 1, 2012
    Publication date: May 1, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Huei-Ru Liu, Chien-Chih Chou, Kong-Beng Thei
  • Publication number: 20140117446
    Abstract: A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and having a first conductivity type, a gate structure supported by the semiconductor substrate between the source and drain regions, a well region in the semiconductor substrate, having a second conductivity type, and in which a channel region is formed under the gate structure during operation, and a shunt region adjacent the well region in the semiconductor substrate and having the second conductivity type. The shunt region has a higher dopant concentration than the well region to establish a shunt path for charge carriers of the second conductivity type that electrically couples the well region to a potential of the source region.
    Type: Application
    Filed: October 31, 2012
    Publication date: May 1, 2014
    Inventors: Xiaowei Ren, David C. Burdeaux, Robert P. Davidson, Michele L. Miera
  • Patent number: 8709900
    Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: April 29, 2014
    Assignee: Richtek Technology Corporation, R.O.C.
    Inventors: Ching-Yao Yang, Tsung-Yi Huang, Huan-Ping Chu, Hung-Der Su
  • Patent number: 8686503
    Abstract: The present disclosure discloses a lateral high-voltage transistor and associated method for making the same.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: April 1, 2014
    Assignee: Monolithic Power Systems, Inc.
    Inventors: Donald R. Disney, Ognjen Milic
  • Patent number: 8686501
    Abstract: A semiconductor device includes: a p-type active region; a gate electrode traversing the active region; an n-type LDD region having a first impurity concentration and formed from a drain side region to a region under the gate electrode; a p-type channel region having a second impurity concentration and formed from a source side region to a region under the gate electrode to form an overlap region with the LDD region under the gate electrode, the channel region being shallower than the LDD region; an n-type source region formed outside the gate electrode; and an n+-type drain region having a third impurity concentration higher than the first impurity concentration formed outside and spaced from the gate electrode, wherein an n-type effective impurity concentration of an intermediate region between the gate electrode and the n+-type drain region is higher than an n-type effective impurity concentration of the overlap region.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: April 1, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Masashi Shima
  • Patent number: 8679930
    Abstract: A semiconductor structure and a manufacturing method for the same are provided. The semiconductor structure includes a first doped well, a first doped electrode, a second doped electrode, doped strips and a doped top region. The doped strips are on the first doped well between the first doped electrode and the second doped electrode. The doped strips are separated from each other. The doped top region is on the doped strips and extended on the first doped well between the doped strips. The first doped well and the doped top region have a first conductivity type. The doped strips have a second conductivity type opposite to the first conductivity type.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: March 25, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Chen-Yuan Lin, Cheng-Chi Lin, Shih-Chin Lien, Shyi-Yuan Wu
  • Patent number: 8673712
    Abstract: Presented herein is a field effect transistor device, optionally a lateral power transistor, and a method for forming the same, comprising providing a substrate, creating a doped buried layer, and creating a primary well in the substrate on the buried layer. A drift drain may be created in the primary well and a counter implant region implanted in the primary well and between the drift drain and the buried layer. The primary well may comprise a first and second implant region with the second implant region at a depth less than the first. The counter implant may be at a depth between the first and second implant regions. The primary well and counter implant region may comprise dopants of the same conductivity type, or both p+-type dopants. A gate may be formed over a portion of a drift drain.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: March 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Kuang Hsiao, Chen-Liang Chu, Yi-Sheng Chen, Fei-Yuh Chen, Kong-Beng Thei
  • Publication number: 20140061786
    Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes a first conductive type substrate, a second conductive type high voltage well, a first conductive type deep buried region, a field oxide region, a first conductive type body region, a gate, a second conductive type source, and a second conductive type drain. The deep buried region is formed below the high voltage well with a gap in between, and the gap is not less than a predetermined distance.
    Type: Application
    Filed: September 4, 2012
    Publication date: March 6, 2014
    Inventors: Tsung-Yi Huang, Chien-Wei Chiu
  • Publication number: 20140054694
    Abstract: A device includes a semiconductor substrate, a drift region in the semiconductor substrate and having a first conductivity type, an isolation region within the drift region, and around which charge carriers drift on a path through the drift region during operation, and a protection region adjacent the isolation region in the semiconductor substrate, having a second conductivity type, and disposed along a surface of the semiconductor substrate.
    Type: Application
    Filed: August 21, 2012
    Publication date: February 27, 2014
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Won Gi Min, Hongning Yang, Jiangkai Zuo
  • Publication number: 20140054696
    Abstract: An improved nLDMOS ESD protection device having an increased holding voltage is disclosed. Embodiments include: providing in a substrate a DVNW region; providing a HVPW region in the DVNW region; providing bulk and source regions in the HVPW region; providing a drain region in the DVNW region, separate from the HVPW region; and providing a polysilicon gate over a portion of the HVPW region and the DVNW region.
    Type: Application
    Filed: August 21, 2012
    Publication date: February 27, 2014
    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventor: Da-Wei LAI
  • Patent number: 8659081
    Abstract: According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: February 25, 2014
    Assignee: Broadcom Corporation
    Inventors: Xiangdong Chen, Wei Xia, Henry Kuo-Shun Chen
  • Publication number: 20140048874
    Abstract: LDD regions are provided with high implant energy in devices with reduced thickness poly-silicon layers and source/drain junctions. Embodiments include forming an oxide layer on a substrate surface, forming a poly-silicon layer over the oxide layer, forming first and second trenches through the oxide and poly-silicon layers and below the substrate surface, defining a gate region therebetween, implanting a dopant in a LDD region through the first and second trenches, forming spacers on opposite side surfaces of the gate region and extending into the first and second trenches, and implanting a dopant in a source/drain region below each of the first and second trenches.
    Type: Application
    Filed: August 16, 2012
    Publication date: February 20, 2014
    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Guowei ZHANG, Purakh Raj VERMA, Zhiqing LI
  • Patent number: 8653594
    Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: February 18, 2014
    Assignee: Richtek Technology Corporation, R.O.C.
    Inventors: Ching-Yao Yang, Tsung-Yi Huang, Huan-Ping Chu, Hung-Der Su
  • Publication number: 20140042537
    Abstract: A semiconductor device includes a drift region in a first region of a semiconductor body. The drift region includes dopants of a first conductivity type. A dopant retarding region is formed at least adjacent an edge of the drift region. Dopants of a second conductivity type are implanted into the semiconductor body. The semiconductor body is annealed to form a body region so that dopants of the second conductivity type are driven into the semiconductor body at a first diffusion rate. The dopant retarding region prevents the dopants from diffusing into the drift region at the first diffusion rate.
    Type: Application
    Filed: August 13, 2012
    Publication date: February 13, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Albert Birner, Helmut Brech
  • Patent number: 8643137
    Abstract: A short channel Lateral MOSFET (LMOS) and method are disclosed with interpenetrating drain-body protrusions (IDBP) for reducing channel-on resistance while maintaining high punch-through voltage. The LMOS includes lower device bulk layer; upper source and upper drain region both located atop lower device bulk layer; both upper source and upper drain region are in contact with an intervening upper body region atop lower device bulk layer; both upper drain and upper body region are shaped to form a drain-body interface; the drain-body interface has an IDBP structure with a surface drain protrusion lying atop a buried body protrusion while revealing a top body surface area of the upper body region; gate oxide-gate electrode bi-layer disposed atop the upper body region forming an LMOS with a short channel length defined by the horizontal length of the top body surface area delineated between the upper source region and the upper drain region.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: February 4, 2014
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Shekar Mallikarjunaswamy, Amit Paul
  • Patent number: 8637370
    Abstract: A high voltage trench MOS and its integration with low voltage integrated circuits is provided. Embodiments include forming, in a substrate, a first trench with a first oxide layer on side surfaces, a narrower second trench, below the first trench with a second oxide layer on side and bottom surfaces, and spacers on sides of the first and second trenches; removing a portion of the second oxide layer from the bottom surface of the second trench between the spacers; filling the first and second trenches with a first poly-silicon to form a drain region; removing the spacers, exposing side surfaces of the first poly-silicon; forming a third oxide layer on side and top surfaces of the first poly-silicon; and filling a remainder of the first and second trenches with a second poly-silicon to form a gate region on each side of the drain region.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: January 28, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Purakh Raj Verma, Yi Liang, Dong Yemin