SEMICONDUCTOR DEVICES WITH GRADED DOPANT REGIONS
Most semiconductor devices manufactured today, have uniform dopant concentration, either in the lateral or vertical device active (and isolation) regions. By grading the dopant concentration, the performance in various semiconductor devices can be significantly improved. Performance improvements can be obtained in application specific areas like increase in frequency of operation for digital logic, various power MOSFET and IGBT ICS, improvement in refresh time for DRAM's, decrease in programming time for nonvolatile memory, better visual quality including pixel resolution and color sensitivity for imaging ICs, better sensitivity for varactors in tunable filters, higher drive capabilities for JFET's, and a host of other applications.
This application is a Divisional of U.S. application Ser. No. 10/934,915, filed on Sep. 3, 2004, which application is incorporated herein by reference.
FIELD OF INVENTIONThis present invention relates to all semiconductor devices and systems. Particularly it applies to diffused diodes, avalanche diodes, Schottky devices, power MOS transistors, JFET's, RF bipolar transistors, IGBTs (Insulated Gate Bipolar Transistors), varactors, digital VLSI, mixed signal circuits and sensor devices including camera ICs employing CCD (Charge Coupled Device) as well as CMOS technologies.
BACKGROUND OF INVENTIONBipolar Junction transistors (BJT) are minority carrier devices as the principle device conduction mechanism. However, majority carriers also a small yet finite role in modulating the conductivity in BJTs. Consequently, both carriers (electrons and holes) play a role in the switching performance of BJTs. The maximum frequency of operation in BJTs is limited by the base transit time as well as the quick recombination of the majority carriers when the device is switched off (prior to beginning the next cycle). The dominant carrier mechanism in BJTs is carrier diffusion. Carrier drift current component is fairly small, especially in uniformly doped base BJTs. Efforts have been made in graded base transistors to create an ‘aiding drift field’, to enhance the diffusing minority carrier's speed from emitter to collector. However, most semiconductor devices, including various power MOSFETs (traditional, DMOS, lateral, vertical and a host of other configurations), IGBT's (Insulated Gated Base Transistors), still use a uniformly doped drift epitaxial region in the base.
‘Retrograde’ wells have been attempted, with little success, to help improve soft error immunity in SRAM's and visual quality in imaging circuits.
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
The relative doping concentrations of emitter and collector regions varies from 1018 to 1020/cm3, where as the base region is 1014 to 1016/cm3 depending on the desired characteristics of the BJT. In graded base p-n-p transistors, the donor dopant concentration may be 10 to 100× at the emitter-base junction, relative to the base-collector junction (1×). The gradient can be linear, quasi linear, exponential or complimentary error function. The relative slope of the donor concentration throughout the base, creates a suitable aiding drift electric field, to help the holes (p-n-p transistor) transverse from emitter to collector. Since the aiding drift field helps hole conduction, the current gain at a given frequency is enhanced, relative to a uniformly-doped-(base) BJT. The improvement in cut-off frequency (or, frequency at unity gain, fT) can be as large as 2×-5×. Similar performance improvements are also applicable to n-p-n transistors.
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The following paragraph, beginning on page 5, line 6, and ending on page 11, line 28, is amended as indicated in the marked up version below:
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One of ordinary skill and familiarity in the art will recognize that the concepts taught herein can be customized and tailored to a particular application in many advantageous ways. For instance, minority carriers can be channeled to the surface, to aid programming in nonvolatile memory devices (NOR, NAND, multivalued-cell). Moreover, single well, as well triple-well CMOS fabrication techniques can also be optimized to incorporate these embodiments, individually and collectively. Any modifications of such embodiments (described here) fall within the spirit and scope of the invention. Hence, they fall within the scope of the claims described below
Although the invention has been described with reference to specific embodiments, these descriptions are not meant to be construed in a limiting sense. Various modifications of the disclosed embodiments, as well as alternative embodiments of the invention will become apparent to persons skilled in the art upon reference to the description of the invention. It should be appreciated by those skilled in the art that the conception and the specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.
It is therefore, contemplated that the claims will cover any such modifications or embodiments that fall within the true scope of the invention.
Claims
1-8. (canceled)
9. A semiconductor device comprising:
- a surface layer;
- a substrate;
- an active region including at least one emitter, at least one base and at least one collector disposed in the above said device;
- at least one drift layer positioned between said emitter and said collector, said drift layer having at least one graded concentration of dopants, said drift layer further having a first static unidirectional electric field to aid movement of carriers from said emitter to said collector; and
- at least one isolation region disposed in the semiconductor device, said isolation region having a graded concentration of dopants and a second static unidirectional electric field to aid isolation between active regions.
10. The semiconductor device of claim 9 wherein said static unidirectional electric fields are adapted to respective grading of dopants to aid movements of carriers in respective active regions.
11. A semiconductor device comprising:
- at least one active region with a channel conduction surface;
- at least one active device with a vertical conduction;
- a first static unidirectional electric field in said channel conducting region; said first unidirectional electric field having a graded dopant concentration;
- a second static unidirectional electric field in said vertical conduction; said second static unidirectional electric field having a graded dopant concentration; and
- a third static unidirectional electric field; said third static unidirectional electric field having a graded dopant concentration.
12. The semiconductor device of claim 9 wherein the semiconductor device is a silicon substrate.
13. The semiconductor device of claim 9 wherein the semiconductor device is an III-V compound substrate.
14. The semiconductor device of claim 9 wherein the semiconductor device is an II-VI compound substrate.
15. The semiconductor device of claim 9 wherein the semiconductor device is an organic material substrate.
16. The semiconductor device of claim 9 wherein the semiconductor device is a silicon carbide substrate.
17. The semiconductor device of claim 9 wherein the semiconductor device has at least one bipolar transistor.
18. The semiconductor device of claim 9 wherein the semiconductor device has at least one vertical bipolar transistor.
19. The semiconductor device of claim 9 wherein the semiconductor device has at least one planar bipolar transistor with a conducting surface layer.
20. The semiconductor device of claim 9 wherein the semiconductor device has at least one MOS transistor.
21. The semiconductor device of claim 9 wherein the semiconductor device has at least one IGBT.
22. A semiconductor device comprising:
- a substrate;
- a surface layer;
- an active region including at least one emitter and one collector disposed in the device;
- a single drift layer disposed between said emitter and said collector, said drift layer having at least one graded concentration of dopants, said drift layer further having a first static unidirectional electric field to aid movement of carriers from said emitter to said collector; and
- at least one isolation region disposed in the semiconductor device, said isolation region having a graded concentration of dopants and a second static unidirectional electric field to aid movement of carriers.
23. The semiconductor device of claim 22 wherein the semiconductor device is a varactor.
24. The semiconductor device of claim 22 wherein the semiconductor device is a varistor.
25. The semiconductor device of claim 22 wherein the semiconductor device is an avalanche transistor.
26. The semiconductor device of claim 22 wherein the semiconductor device is a Zener diode.
27. The semiconductor device of claim 22 wherein the semiconductor device is a Schottky diode.
28. The semiconductor device of claim 22 wherein the semiconductor device is a tunneling diode.
29. The semiconductor device of claim 22 wherein the semiconductor device is an Esaki diode.
Type: Application
Filed: Apr 1, 2013
Publication Date: Aug 29, 2013
Inventor: G.R. Mohan Rao (Richardson, TX)
Application Number: 13/854,319
International Classification: H01L 29/36 (20060101);