With Emitter Region Having Specified Doping Concentration Profile (e.g., High-low Concentration Step) Patents (Class 257/591)
  • Patent number: 10685866
    Abstract: Integrated chips and methods of forming the same include oxidizing a portion of a semiconductor fin to electrically isolate active regions of the semiconductor fin. A semiconductor device is formed on each of the active regions.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: June 16, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Huimei Zhou, Gen Tsutsui, Andrew M. Greene, Dechao Guo, Huiming Bu, Robert Robison, Veeraraghavan S. Basker, Reinaldo Vega
  • Patent number: 8912632
    Abstract: According to one embodiment, a semiconductor device includes a first major electrode, a first semiconductor layer, a first conductivity type base layer, a second conductivity type base layer, a first conductivity type second semiconductor layer, a gate insulating film, a gate electrode, and a second major electrode. The gate insulating film is provided on a side wall of a trench penetrating the second conductivity type base layer to reach the first conductivity type base layer. The gate electrode is provided inside the gate insulating film in the trench. The second major electrode is provided on the second semiconductor layer and electrically connected with the second semiconductor layer. A maximum impurity concentration in the second semiconductor layer is within ten times a maximum impurity concentration in the second conductivity type base layer.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: December 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tsuneo Ogura
  • Publication number: 20140339678
    Abstract: An integrated circuit containing a bipolar transistor including an emitter diffused region with a peak doping density higher than 1·1020 atoms/cm3, and an emitter-base junction less than 40 nanometers deep in a base layer. A process of forming the bipolar transistor, which includes forming an emitter dopant atom layer between a base layer and an emitter layer, followed by a flash or laser anneal step to diffuse dopant atoms from the emitter dopant atom layer into the base layer.
    Type: Application
    Filed: August 4, 2014
    Publication date: November 20, 2014
    Inventors: Rick L. WISE, Hiroshi YASUDA
  • Patent number: 8853825
    Abstract: An ESD protection apparatus comprises a substrate, a low voltage p-type well and a low voltage n-type well formed on the substrate. The ESD protection device further comprises a first P+ region formed on the low voltage p-type well and a second P+ region formed on the low voltage n-type well. The first P+ region and the second P+ region are separated by a first isolation region. The breakdown voltage of the ESD protection apparatus is tunable by adjusting the length of the first isolation region.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: October 7, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jam-Wem Lee, Yi-Feng Chang
  • Patent number: 8829563
    Abstract: An insulated gate bipolar device is disclosed which can include layers of different conductivity types between an emitter electrode on an emitter side and a collector electrode on a collector side in the following order: a source region of a first conductivity type, a base layer of a second conductivity type, which contacts the emitter electrode in a contact area, an enhancement layer of the first conductivity type, a floating compensation layer of the second conductivity type having a compensation layer thickness tp, a drift layer of the first conductivity type having lower doping concentration than the enhancement layer and a collector layer of the second conductivity type.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: September 9, 2014
    Assignee: ABB Technology AG
    Inventors: Munaf Rahimo, Marco Bellini, Maxi Andenna, Friedhelm Bauer, Iulian Nistor
  • Patent number: 8791546
    Abstract: A bipolar transistor comprises at least first and second connected emitter-base (EB) junctions having, respectively, different first and second EB junction depths, and a buried layer (BL) collector having a greater third depth. The emitters and bases corresponding to the different EB junctions are provided during a chain implant. An isolation region overlies the second EB junction location thereby providing its shallower EB junction depth. The BL collector does not underlie the first EB junction and is laterally spaced therefrom by a variable amount to facilitate adjusting the transistor's properties. In other embodiments, the BL collector can underlie at least a portion of the second EB junction. Regions of opposite conductivity type over-lie and under-lie the BL collector, which is relatively lightly doped, thereby preserving the breakdown voltage. The transistor can be readily “tuned” by mask adjustments alone to meet various device requirements.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: July 29, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Xin Lin, Bernhard H. Grote, Jiang-Kai Zuo
  • Patent number: 8736023
    Abstract: A method for forming a field effect transistor (FET) device includes forming a dielectric layer on a substrate, forming a first metal layer on the dielectric layer, removing a portion of the first metal layer to expose a portion of the dielectric layer, forming a second metal layer on the dielectric layer and the first metal layer, and removing a portion of the first metal layer and the second metal layer to define a boundary region between a first FET device and a second FET device.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: May 27, 2014
    Assignee: International Business Machines Corporation
    Inventors: Dechao Guo, Shu-Jen Han, Chung-Hsun Lin, Yanfeng Wang
  • Patent number: 8710627
    Abstract: An epitaxial layer is supported on top of a substrate. First and second body regions are formed within the epitaxial layer separated by a predetermined lateral distance. Trigger and source regions are formed within the epitaxial layer. A first source region is transversely adjacent the first body region between first and second trigger regions laterally adjacent the first source region and transversely adjacent the first body region. A second source region is located transversely adjacent the second body region between third and fourth trigger regions laterally adjacent the second source region and transversely adjacent the second body region. A third source region is laterally adjacent the fourth trigger region. The fourth trigger region is between the second and third source regions. An implant region within the fourth trigger region is laterally adjacent the third source region.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: April 29, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Lingpeng Guan, Madhur Bobde, Anup Bhalla
  • Patent number: 8664697
    Abstract: To provide a transistor device, which is composed of a compound semiconductor, having a multilayer structure in which a high electron mobility transistor (HEMT) and a heterojunction bipolar transistor (HBT) are overlapped on the same substrate and epitaxial-grown thereon, wherein a band gap energy of an indium gallium phosphide layer (InGaP) included in an epitaxial layer, is set to 1.91 eV or more.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: March 4, 2014
    Assignee: Hitachi Cable, Ltd.
    Inventors: Takeshi Meguro, Jiro Wada, Yoshihiko Moriya
  • Patent number: 8664080
    Abstract: A method for forming a vertical electrostatic discharge (ESD) protection device includes depositing a multi-layer n-type epitaxial layer on a substrate having p-type surface including first epitaxial depositing to form a first n-type epitaxial layer on the p-type surface, and second epitaxial depositing to form a second n-type epitaxial layer formed on the first n-type epitaxial layer. The first type epitaxial layer has a peak doping level which is at least double that of the second n-type epitaxial layer. A p+ layer is formed on the second n-type epitaxial layer. An etch step etches through the p+ layer and multi-layer n-type epitaxial layer to reach the substrate to form a trench. The trench is filled with a filler material to form a trench isolation region. A metal contact is formed on the p+ layer for providing contact to the p+ layer.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: March 4, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Toshiyuki Tani, Hiroshi Yamasaki, Kentaro Takahashi, Lily Springer
  • Patent number: 8618606
    Abstract: Provided is a semiconductor device comprising: a PW layer formed at a surface of a semiconductor substrate; an NW layer formed at the surface of the semiconductor substrate to be in contact with the PW layer; a p+ base layer formed at the surface of the semiconductor substrate in the PW layer; an n+ collector layer formed at the surface of the semiconductor substrate in the NW layer; an n+ emitter layer located between the p+ base layer and the n+ collector layer and formed at the surface of the semiconductor substrate in the PW layer; and an n± layer formed between the n+ collector layer and the PW layer to be in contact with the n+ collector layer.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: December 31, 2013
    Assignee: Seiko Instruments Inc.
    Inventors: Tomomitsu Risaki, Shoji Nakanishi, Koichi Shimazaki
  • Publication number: 20130320500
    Abstract: A bipolar semiconductor component, in particular a diode, comprising an anode structure which controls its emitter efficiency in a manner dependent on the current density in such a way that the emitter efficiency is low at small current densities and sufficiently high at large current densities, and an optional cathode structure, which can inject additional holes during commutation, and production methods therefor.
    Type: Application
    Filed: May 21, 2013
    Publication date: December 5, 2013
    Inventors: Roman Baburske, Josef Lutz, Ralf Siemieniec, Hans-Joachim Schulze
  • Patent number: 8525233
    Abstract: A pnp SiGe heterojunction bipolar transistor (HBT) reduces the rate that p-type dopant atoms in the p+ emitter of the transistor out diffuse into a lowly-doped region of the base of the transistor by epitaxially growing the emitter to include a single-crystal germanium region and an overlying single-crystal silicon region.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: September 3, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey A. Babcock, Alexei Sadovnikov
  • Patent number: 8525300
    Abstract: The present disclosure provides an ESD protection device. The device contains a bipolar junction transistor device that includes a collector, a base, and an emitter. The collector includes a first doped element and a more heavily doped second doped element disposed over the first doped element. The first and second doped elements each have a first doping polarity. The base is located adjacent to the collector and includes a third doped element having a second doping polarity different from the first doping polarity. A p-n junction is formed between the third doped element and one of the first and second doped elements. The emitter is formed over the base. The emitter includes a fourth doped element having the first doping polarity and forming a p-n junction with the third doped element. The fourth doped element is more heavily doped than the third doped element.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: September 3, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsi-Yu Kuo, Chi-Kuang Chen
  • Publication number: 20130221488
    Abstract: Most semiconductor devices manufactured today, have uniform dopant concentration, either in the lateral or vertical device active (and isolation) regions. By grading the dopant concentration, the performance in various semiconductor devices can be significantly improved. Performance improvements can be obtained in application specific areas like increase in frequency of operation for digital logic, various power MOSFET and IGBT ICS, improvement in refresh time for DRAM's, decrease in programming time for nonvolatile memory, better visual quality including pixel resolution and color sensitivity for imaging ICs, better sensitivity for varactors in tunable filters, higher drive capabilities for JFET's, and a host of other applications.
    Type: Application
    Filed: April 1, 2013
    Publication date: August 29, 2013
    Inventor: G.R. Mohan Rao
  • Publication number: 20130193557
    Abstract: The invention relates to an electronic device with a bipolar transistor having an emitter, a base and a collector. The base has a first region of a first concentration of the first dopant for forming an electrically active region of the base and a second region of a second concentration of the first dopant close to the surface of the base region. The first region is separated from the second region by a region of a third concentration of the first dopant and the third concentration is lower than the first and the second concentration.
    Type: Application
    Filed: July 25, 2012
    Publication date: August 1, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Philipp MENZ, Berthold STAUFER, Yasuda HIROSHI
  • Publication number: 20130119472
    Abstract: Provided is a semiconductor device comprising: a PW layer formed at a surface of a semiconductor substrate; an NW layer formed at the surface of the semiconductor substrate to be in contact with the PW layer; a p+ base layer formed at the surface of the semiconductor substrate in the PW layer; an n+ collector layer formed at the surface of the semiconductor substrate in the NW layer; an n+ emitter layer located between the p+ base layer and the n+ collector layer and formed at the surface of the semiconductor substrate in the PW layer; and an n± layer formed between the n+ collector layer and the PW layer to be in contact with the n+ collector layer.
    Type: Application
    Filed: November 1, 2012
    Publication date: May 16, 2013
    Applicant: SEIKO INSTRUMENTS INC.
    Inventor: SEIKO INSTRUMENTS INC.
  • Publication number: 20130119433
    Abstract: Among other things, an electrostatic discharge (ESD) device is provided. The ESD device comprises a dielectric isolation structure that is formed between an emitter and a collector of the ESD device. During an ESD event, current flows from the emitter, substantially under the dielectric isolation structure, to the collector, to protect associated circuitry. The dielectric isolation structure is formed to a depth that is less than a depth of at least one of the emitter or the collector, or doped regions thereof, thereby decreasing a length of a current path from the emitter to the collector, because the current is not obstructed by the dielectric isolation structure. Accordingly, the ESD device can carry higher current during the ESD event because the shorter current path has less resistance than a longer path that would otherwise be traveled if the dielectric isolation structure was not formed at the shallower depth.
    Type: Application
    Filed: October 26, 2012
    Publication date: May 16, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Taiwan Semiconductor Manufacturing Company L
  • Publication number: 20130092977
    Abstract: A power semiconductor diode is provided. The power semiconductor diode includes a semiconductor substrate having a first emitter region of a first conductivity type, a second emitter region of a second conductivity type, and a drift region of the first conductivity type arranged between the first emitter region and the second emitter region. The drift region forms a pn-junction with the second emitter region. A first emitter metallization is in contact with the first emitter region. The first emitter region includes a first doping region of the first conductivity type and a second doping region of the first conductivity type. The first doping region forms an ohmic contact with the first emitter metallization, and the second doping region forms a non-ohmic contact with the first emitter metallization. A second emitter metallization is in contact with the second emitter region.
    Type: Application
    Filed: October 17, 2011
    Publication date: April 18, 2013
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Holger Huesken, Anton Mauder, Hans-Joachim Schulze, Wolfgang Roesner
  • Patent number: 8421124
    Abstract: An NPN bipolar junction transistor is disclosed that exhibits a collector-to-emitter breakdown voltage greater than 10 volts and a beta greater than 300. The large value of beta is obtained by fabricating the transistor with an extra N-type layer that reduces recombination of electrons and holes.
    Type: Grant
    Filed: March 15, 2010
    Date of Patent: April 16, 2013
    Assignee: Macronix International Co., Ltd.
    Inventors: Cheng-Chi Lin, Shuo-Lun Tu, Shih-Chin Lien
  • Publication number: 20130082353
    Abstract: The present disclosure provides an ESD protection device. The device contains a bipolar junction transistor device that includes a collector, a base, and an emitter. The collector includes a first doped element and a more heavily doped second doped element disposed over the first doped element. The first and second doped elements each have a first doping polarity. The base is located adjacent to the collector and includes a third doped element having a second doping polarity different from the first doping polarity. A p-n junction is formed between the third doped element and one of the first and second doped elements. The emitter is formed over the base. The emitter includes a fourth doped element having the first doping polarity and forming a p-n junction with the third doped element. The fourth doped element is more heavily doped than the third doped element.
    Type: Application
    Filed: May 11, 2012
    Publication date: April 4, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsi-Yu Kuo, Chi-Kuang Chen
  • Patent number: 8390096
    Abstract: An electrostatic discharge (ESD) protection structure comprises a bipolar PNP transistor having an emitter formed by a first high voltage P type implanted region disposed underneath a first P+ region and a collector formed by a second high voltage P type implanted region disposed underneath a second P+ region. The ESD protection structure can have an adjustable threshold voltage by controlling the distance between the first high voltage P type implanted region and the second high voltage P type implanted region. Based upon a basic ESD protection structure, the ESD protection device can provide a reliable ESD protection for semiconductor devices having different voltage ratings.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: March 5, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsin-Yen Hwang
  • Patent number: 8384193
    Abstract: Insufficient gain in bipolar transistors (20) is improved by providing an alloyed (e.g., silicided) emitter contact (452) smaller than the overall emitter (42) area. The improved emitter (42) has a first emitter (FE) portion (42-1) of a first dopant concentration CFE, and a second emitter (SE) portion (42-2) of a second dopant concentration CSE. Preferably CSE?CFE. The SE portion (42-2) desirably comprises multiple sub-regions (45i, 45j, 45k) mixed with multiple sub-regions (47m, 47n, 47p) of the FE portion (42-1). A semiconductor-metal alloy or compound (e.g., a silicide) is desirably used for Ohmic contact (452) to the SE portion (42-2) but substantially not to the FE portion (42-1). Including the FE portion (42-1) electrically coupled to the SE portion (42-2) but not substantially contacting the emitter contact (452) on the SE portion (42-2) provides gain increases of as much as ˜278.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: February 26, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Xin Lin, Daniel J. Blomberg, Jiang-Kai Zuo
  • Publication number: 20130009169
    Abstract: Methods of making semiconductor devices such as vertical junction field effect transistors (VJFETs) or bipolar junction transistors (BJTs) are described. The methods do not require ion implantation. The VJFET device has an epitaxially regrown n-type channel layer and an epitaxially regrown p-type gate layer as well as an epitaxially grown buried gate layer. Devices made by the methods are also described.
    Type: Application
    Filed: September 13, 2012
    Publication date: January 10, 2013
    Applicant: SS SC IP, LLC
    Inventor: Lin Cheng
  • Patent number: 8349663
    Abstract: In a first aspect, a method for forming a non-volatile memory cell is provided. The method includes (1) forming a metal-insulator-metal (MIM) antifuse stack including (a) a first metal layer; (b) a silicon dioxide, oxynitride or silicon nitride antifuse layer formed above the first metal layer; and (c) a second metal layer formed above the antifuse layer. The method also includes (2) forming a contiguous p-i-n diode above the MIM antifuse stack, the contiguous p-i-n diode comprising deposited semiconductor material; (3) forming a layer of a silicide, silicide-germanide, or germanide in contact with the deposited semiconductor material; and (4) crystallizing the deposited semiconductor material in contact with the layer of silicide, silicide-germanide, or germanide. The memory cell comprises the contiguous p-i-n diode and the MIM antifuse stack. Other aspects are provided.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: January 8, 2013
    Assignee: SanDisk 3D LLC
    Inventors: S. Brad Herner, Tanmay Kumar
  • Patent number: 8344481
    Abstract: By providing a novel bipolar device design implementation, a standard CMOS process can be used unchanged to fabricate useful bipolar transistors and other bipolar devices having adjustable properties by partially blocking the P or N well doping used for the transistor base. This provides a hump-shaped base region with an adjustable base width, thereby achieving, for example, higher gain than can be obtained with the unmodified CMOS process alone. By further partially blocking the source/drain doping step used to form the emitter of the bipolar transistor, the emitter shape and effective base width can be further varied to provide additional control over the bipolar device properties. The embodiments thus include prescribed modifications to the masks associated with the bipolar device that are configured to obtain desired device properties. The CMOS process steps and flow are otherwise unaltered and no additional process steps are required.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: January 1, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Xin Lin, Bernhard H. Grote, Hongning Yang, Jiang-Kai Zuo
  • Patent number: 8324687
    Abstract: Provided is a semiconductor device comprising: a PW layer formed at a surface of a semiconductor substrate; an NW layer formed at the surface of the semiconductor substrate to be in contact with the PW layer; a p+ base layer formed at the surface of the semiconductor substrate in the PW layer; an n+ collector layer formed at the surface of the semiconductor substrate in the NW layer; an n+ emitter layer located between the p+ base layer and the n+ collector layer and formed at the surface of the semiconductor substrate in the PW layer; and an n± layer formed between the n+ collector layer and the PW layer to be in contact with the n+ collector layer.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: December 4, 2012
    Assignee: Seiko Instruments Inc.
    Inventors: Tomomitsu Risaki, Shoji Nakanishi, Koichi Shimazaki
  • Patent number: 8258545
    Abstract: An integrated circuit includes a bipolar transistor disposed over a substrate. The bipolar transistor includes a base electrode disposed around at least one germanium-containing layer. An emitter electrode is disposed over the at least one germanium-containing layer. At least one isolation structure is disposed between the emitter electrode and the at least one germanium-containing layer. A top surface of the at least one isolation structure is disposed between and electrically isolating a top surface of the emitter electrode from a top surface of the at least one germanium-containing layer.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: September 4, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Tung Huang, Chun-Tsung Kuo, Shih-Chang Liu, Yeur-Luen Tu
  • Patent number: 8212292
    Abstract: An improved bipolar transistor (40, 40?) is provided, manufacturable by a CMOS IC process without added steps. The improved transistor (40, 40?) comprises an emitter (48) having first (482) and second (484) portions of different depths (4821, 4841), a base (46) underlying the emitter (48) having a central portion (462) of a first base width (4623) underlying the first portion (482) of the emitter (48), a peripheral portion (464) having a second base width (4643) larger than the first base width (4623) partly underlying the second portion (484) of the emitter (48), and a transition zone (466) of a third base width (4644) and lateral extent (4661) lying laterally between the first (462) and second (464) portions of the base (46), and a collector (44) underlying the base (46). The gain of the transistor (40, 40?) is much larger than a conventional bipolar transistor (20) made using the same CMOS process.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: July 3, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Xin Lin, Daniel J. Blomberg, Jiang-Kia Zuo
  • Publication number: 20120119330
    Abstract: An electrostatic discharge (ESD) protection structure comprises a bipolar PNP transistor having an emitter formed by a first high voltage P type implanted region disposed underneath a first P+ region and a collector formed by a second high voltage P type implanted region disposed underneath a second P+ region. The ESD protection structure can have an adjustable threshold voltage by controlling the distance between the first high voltage P type implanted region and the second high voltage P type implanted region. Based upon a basic ESD protection structure, the ESD protection device can provide a reliable ESD protection for semiconductor devices having different voltage ratings.
    Type: Application
    Filed: November 23, 2010
    Publication date: May 17, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsin-Yen Hwang
  • Patent number: 8084814
    Abstract: A semiconductor device is provided in which a semiconductor substrate can be prevented from being broken while elements can be prevented from being destroyed by a snap-back phenomenon. After an MOS gate structure is formed in a front surface of an FZ wafer, a rear surface of the FZ wafer is ground. Then, the ground surface is irradiated with protons and irradiated with two kinds of laser beams different in wavelength simultaneously to thereby form an N+ first buffer layer and an N second buffer layer. Then, a P+ collector layer and a collector electrode are formed on the proton-irradiated surface. The distance from a position where the net doping concentration of the N+ first buffer layer is locally maximized to the interface between the P+ collector layer and the N second buffer layer is set to be in a range of 5 ?m to 30 ?m, both inclusively.
    Type: Grant
    Filed: January 22, 2009
    Date of Patent: December 27, 2011
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Michio Nemoto, Haruo Nakazawa
  • Publication number: 20110291242
    Abstract: In a semiconductor device in which an IGBT, a control circuit for the IGBT and so on are formed on an SOI substrate divided by trenches, the invention is directed to providing the IGBT with a higher breakdown voltage, an enhanced turn-off characteristic and so on. An N type epitaxial layer is formed on a dummy semiconductor substrate, a trench is formed in the N type epitaxial layer, an N type buffer layer and then a P type embedded collector layer are formed on the sidewall of the trench and the front surface of the N type epitaxial layer, and the bottom of the trench and the P+ type embedded collector layer are covered by an embedded insulation film. The embedded insulation film is covered by a polysilicon film, and a P type semiconductor substrate is attached to the polysilicon film with an insulation film being interposed therebetween.
    Type: Application
    Filed: May 27, 2011
    Publication date: December 1, 2011
    Applicant: ON Semiconductor Trading, Ltd. a Bermuda limited liability company
    Inventor: Mitsuru SOMA
  • Patent number: 7989844
    Abstract: The invention relates to a semiconductor device with a substrate (11) and a semiconductor body (12) with a heterojunction bipolar, in particular npn, transistor with an emitter region (1), a base region (2) and a collector region (3), which are provided with, respectively, a first, a second and a third connection conductor (4, 5, 6), and wherein the bandgap of the base region (2) is smaller than that of the collector region (3) or of the emitter region (1), for example by the use of a silicon-germanium mixed crystal instead of pure silicon in the base region (2). Such a device is characterized by a very high speed, but its transistor shows a relatively low BVeeo. In a device (10) according to the invention the doping flux of the emitter region (1) is locally reduced by a further semiconductor region (20) of the second conductivity type which is embedded in the emitter region (1).
    Type: Grant
    Filed: February 12, 2004
    Date of Patent: August 2, 2011
    Assignee: NXP B.V.
    Inventors: Rob Van Dalen, Prabhat Agarwal, Jan Willem Slotboom, Gerrit Elbert Johannes Koops
  • Publication number: 20110169137
    Abstract: An NPN bipolar junction transistor is disclosed that exhibits a collector-to-emitter breakdown voltage greater than 10 volts and a beta greater than 300. The large value of beta is obtained by fabricating the transistor with an extra N-type layer that reduces recombination of electrons and holes.
    Type: Application
    Filed: March 15, 2010
    Publication date: July 14, 2011
    Inventors: Cheng-Chi Lin, Shuo-Lun Tu, Shih-Chin Lien
  • Patent number: 7952166
    Abstract: A semiconductor device with switch electrode and gate electrode and a method for switching a semiconductor device. One embodiment provides a semiconductor substrate with an emitter region, a drift region, a body region and a source region. The drift region is formed between the emitter and the body region while the body region is formed between the drift and the source region. A first trench structure extends from the source region at least partially into the drift region. The first trench structure includes a gate electrode arranged next to the body region and a switch electrode arranged in portions next to the drift region, wherein the switch and gate electrodes are electrically insulated from each other in the trench structure. A first gate driver is electrically connected to the gate electrode while a second gate driver is electrically connected to the switch gate.
    Type: Grant
    Filed: May 22, 2008
    Date of Patent: May 31, 2011
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Thomas Raker
  • Patent number: 7932541
    Abstract: Disclosed are embodiments of a hetero-junction bipolar transistor (HBT) structure and method of forming the structure that provides substantially lower collector-to-base parasitic capacitance and collector resistance, while also lowering or maintaining base-to-emitter capacitance, emitter resistance and base resistance in order to achieve frequency capabilities in the THz range. The HBT is a collector-up HBT in which a dielectric layer and optional sidewall spacers separate the raised extrinsic base and the collector so as to reduce collector-to-base capacitance. A lower portion of the collector is single crystalline semiconductor so as to reduce collector resistance. The raised extrinsic base and the intrinsic base are stacked single crystalline epitaxial layers, where link-up is automatic and self-aligned, so as to reduce base resistance. The emitter is a heavily doped region below the top surface of a single crystalline semiconductor substrate so as to reduce emitter resistance.
    Type: Grant
    Filed: January 14, 2008
    Date of Patent: April 26, 2011
    Assignee: International Business Machines Corporation
    Inventors: Alvin J. Joseph, Andreas D. Stricker
  • Patent number: 7911033
    Abstract: This invention discloses a novel apparatus of fully depleted emitter so that the built-in potential between emitter and the base becomes lower and the charge storage between the emitter and base becomes small. This concept also applies to the diodes or rectifiers. With depleted junction, this results in very fast switching of the diodes and transistors. Another novel structure utilizes the strip base structure to achieve lower on resistance of the bipolar transistor. The emitter region of the strip base can be a normal emitter or depleted emitter.
    Type: Grant
    Filed: July 20, 2010
    Date of Patent: March 22, 2011
    Inventor: Ho-Yuan Yu
  • Publication number: 20110057289
    Abstract: An integrated circuit containing a bipolar transistor including an emitter diffused region with a peak doping density higher than 1·1020 atoms/cm3, and an emitter-base junction less than 40 nanometers deep in a base layer. A process of forming the bipolar transistor, which includes forming an emitter dopant atom layer between a base layer and an emitter layer, followed by a flash or laser anneal step to diffuse dopant atoms from the emitter dopant atom layer into the base layer.
    Type: Application
    Filed: March 5, 2010
    Publication date: March 10, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rick L. Wise, Hiroshi Yasuda
  • Patent number: 7902635
    Abstract: Improved radio frequency gain in a silicon-based bipolar transistor may be provided by adoption of a common-base configuration, preferably together with excess doping of the base to provide extremely low base resistances boosting performance over similar common-emitter designs.
    Type: Grant
    Filed: July 11, 2005
    Date of Patent: March 8, 2011
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Zhenqiang Ma, Ningyue Jiang
  • Publication number: 20110049678
    Abstract: Conduction between source and drain or emitter and collector regions is an important characteristic in transistor operation, particularly for lateral bipolar transistors. Accordingly, techniques that can facilitate control over this characteristic can mitigate yield loss by promoting the production of transistors that have an increased likelihood of exhibiting desired operational performance. As disclosed herein, well regions are established in a semiconductor substrate to facilitate, among other things, control over the conduction between the source and drain regions of a lateral bipolar transistor, thus mitigating yield loss and other associated fabrication deficiencies. Importantly, an additional mask is not required in establishing the well regions, thus further mitigating (increased) costs associated with promoting desired device performance.
    Type: Application
    Filed: November 8, 2010
    Publication date: March 3, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Kamel Benaissa
  • Publication number: 20110012191
    Abstract: A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal oxide is deposited over the charge trapping layer to form a thick oxide on top of the core source/drain region and a pinch off and a void at the top of the STI trench. An etch is performed on the pinch-off oxide and the thin oxide on the trapping layer on the STI oxide. The trapping layer is then partially etched between the core cells. A dip-off of the oxide on the trapping layer is performed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide and thus isolate the trap layer.
    Type: Application
    Filed: September 27, 2010
    Publication date: January 20, 2011
    Inventors: Shenqing FANG, Kuo-Tung CHANG, Tim THURGATE, YouSeok SUH, Allison HOLBROOK
  • Patent number: 7821037
    Abstract: A heterojunction bipolar transistor includes a first conductivity type subcollector layer, a first collector layer containing a first conductivity type impurity, a third collector layer containing a higher concentration of the first conductivity type impurity than the first collector layer, a second collector layer containing a lower concentration of the first conductivity type impurity than the first collector layer, a second conductivity type base layer, a first conductivity type emitter layer containing a semiconductor with a wider bandgap than the base layer, and a first conductivity type emitter cap layer.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: October 26, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Takaki Niwa, Naoto Kurosawa
  • Publication number: 20100187608
    Abstract: Provided is a semiconductor device comprising: a PW layer formed at a surface of a semiconductor substrate; an NW layer formed at the surface of the semiconductor substrate to be in contact with the PW layer; a p+ base layer formed at the surface of the semiconductor substrate in the PW layer; an n+ collector layer formed at the surface of the semiconductor substrate in the NW layer; an n+ emitter layer located between the p+ base layer and the n+ collector layer and formed at the surface of the semiconductor substrate in the PW layer; and an n± layer formed between the n+ collector layer and the PW layer to be in contact with the n+ collector layer.
    Type: Application
    Filed: January 28, 2010
    Publication date: July 29, 2010
    Inventors: Tomomitsu Risaki, Shoji Nakanishi, Koichi Shimazaki
  • Patent number: 7714329
    Abstract: The present invention has an object to provide an active-matrix liquid crystal display device that realizes the improvement in productivity as well as in yield. In the present invention, a laminate film comprising the conductive film comprising metallic material and the second amorphous semiconductor film containing an impurity element of one conductivity type and the amorphous semiconductor film is selectively etched with the same etching gas to form a side edge of the first amorphous semiconductor film 1001 into a taper shape. Thereby, a coverage problem of a pixel electrode 1003 can be solved and an inverse stagger type TFT can be completed with three photomask.
    Type: Grant
    Filed: August 22, 2008
    Date of Patent: May 11, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideomi Suzawa, Yoshihiro Kusuyama, Shunpei Yamazaki
  • Publication number: 20100078765
    Abstract: A power semiconductor component is described. One embodiment provides a semiconductor body having an inner zone and an edge zone. A base zone of a first conduction type is provided. The base zone is arranged in the at least one inner zone and the at least one edge zone. An emitter zone of a second conduction type is provided. The emitter zone is arranged adjacent to the base zone in a vertical direction of the semiconductor body. A field stop zone of the first conduction type is provided. The field stop zone is arranged in the base zone and has a first field stop zone section having a first dopant dose in the edge zone and a second field stop zone section having a second dopant dose in the inner zone. The first dopant dose is higher than the second dopant dose.
    Type: Application
    Filed: September 30, 2008
    Publication date: April 1, 2010
    Applicant: Infineon Technologies Austria AG
    Inventors: Hans-Joachim Schulze, Manfred Pfaffenlehner
  • Patent number: 7671447
    Abstract: The invention relates to a semiconductor device (10) with a semiconductor body (12) comprising a bipolar transistor with an emitter region (1), a base region (2) and a collector region (3) of, respectively, a first conductivity type, a second conductivity type, opposite to the first conductivity type, and the first conductivity type, wherein, viewed in projection, the emitter region (1) is positioned above or below the base region (2), and the collector region (3) laterally borders the base region (2). According to the invention, the base region (2) comprises a highly doped subregion (2A) the doping concentration of which has a delta-shaped profile in the thickness direction, and said highly doped sub-region (2A) extends laterally as far as the collector region (3). Such a lateral bipolar transistor has excellent high-frequency properties and a relatively high breakdown voltage between the base and collector regions (2, 3), implying that the device is suitable for high power applications.
    Type: Grant
    Filed: July 7, 2005
    Date of Patent: March 2, 2010
    Assignee: NXP B.V.
    Inventors: Andreas Hubertus Montree, Jan Willem Slotboom, Prabhat Agarwal, Philippe Meunier-Beillard
  • Patent number: 7671371
    Abstract: A semiconductor layer structure includes a donor substrate and a detach region carried by the donor substrate. A device structure is carried by the donor substrate and positioned proximate to the detach region. The device structure includes a stack of crystalline semiconductor layers. The stack of crystalline semiconductor layers includes a pn junction.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: March 2, 2010
    Inventor: Sang-Yun Lee
  • Patent number: 7666787
    Abstract: An interconnect structure of the single or dual damascene type and a method of forming the same, which substantially reduces the electromigration problem that is exhibited by prior art interconnect structures, are provided. In accordance with the present invention, a grain growth promotion layer, which promotes the formation of a conductive region within the interconnect structure that has a bamboo microstructure and an average grain size of larger than 0.05 microns is utilized. The inventive structure has improved performance and reliability.
    Type: Grant
    Filed: February 21, 2006
    Date of Patent: February 23, 2010
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Shom Ponoth
  • Patent number: 7659179
    Abstract: A method of forming a memory device includes forming first and second isolation structures on a semiconductor substrate, the first and second isolation structures defining an active region therebetween; and etching a portion of the semiconductor substrate provided within the active region to define a step profile, so that the active region includes a first vertical portion and an upper primary surface, the first vertical portion extending above the upper primary surface.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: February 9, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hyun Hu
  • Patent number: 7655977
    Abstract: An IGBT for controlling the application of power to a plasma display panel has an increased current conduction capability and a reduced conduction loss at the expense of a reduced safe operating area. For a device with a 300 volt breakdown voltage rating, the die has a substrate resistivity less than 10 m ohm cm; a buffer layer thickness of about 8 ?m resistivity in the range of 0.05 to 0.10 ohm cm, and an epi layer for receiving junction patterns and trenches, which has a thickness of from 31 to 37 ?m and resistivity in te range of 14 to 18 ohm cm.
    Type: Grant
    Filed: October 18, 2005
    Date of Patent: February 2, 2010
    Assignee: International Rectifier Corporation
    Inventors: Chiu Ng, Davide Chiola