Abstract: A semiconductor device package includes a substrate, a silicon (Si) or silicon carbide (SiC) semiconductor die, and a metal layer on a surface of the semiconductor die. The metal layer includes a bonding surface that is attached to a surface of the substrate by a die attach material. The bonding surface includes opposing edges that extend along a perimeter of the semiconductor die, and one or more non-orthogonal corners that are configured to reduce stress at an interface between the bonding surface and the die attach material. Related devices and fabrication methods are also discussed.

Abstract: Methods and apparatus for measuring the melt depth of a substrate during pulsed laser melting are provided. The apparatus can include a heat source, a substrate support with an opening formed therein, and an interferometer positioned to direct coherent radiation toward the toward the substrate support. The method can include positioning the substrate with a first surface in a thermal processing chamber, heating a portion of the first surface with a heat source, directing infrared spectrum radiation at a partially reflective mirror creating control radiation and interference radiation, directing the interference radiation to a melted surface and directing the control radiation to a control surface, and measuring the interference between the reflected radiation. The interference fringe pattern can be used to determine the precise melt depth during the melt process.

Abstract: A module unit includes a carrier substrate and an antenna substrate. The carrier substrate at least includes an embedded chip and a redistribution layer arranged on the first main surface. The antenna substrate including a base material includes an antenna structure arranged on the side of the first main surface, and a cavity introduced on the side of the second main surface, the cavity being aligned with the antenna structure at least in areas. The antenna substrate is connected with the second main surface to the first main surface of the carrier substrate, so that the antenna substrate and the carrier substrate form a layer stack.

Abstract: Provided is a semiconductor device including a semiconductor substrate; a hydrogen donor that is provide inside the semiconductor substrate in a depth direction, has a doping concentration that is higher than a doping concentration of a dopant of the semiconductor substrate, has a doping concentration distribution peak at a first position that is a predetermined distance in the depth direction of the semiconductor substrate away from one main surface of the semiconductor substrate, and has a tail of the doping concentration distribution where the doping concentration is lower than at the peak, farther on the one main surface side than where the first position is located; and a crystalline defect region having a crystalline defect density center peak at a position shallower than the first position, in the depth direction of the semiconductor substrate.

Abstract: The method of producing a semiconductor epitaxial wafer includes: a first step of irradiating a surface of a semiconductor wafer with cluster ions containing carbon, phosphorus, and hydrogen as constituent elements to form a modified layer that is located in a surface layer portion of the semiconductor wafer and that contains the constituent elements of the cluster ions as a solid solution; and a second step of forming an epitaxial layer on the modified layer of the semiconductor wafer. The ratio y/x of the number y of the phosphorus atoms with respect to the number x of the carbon atoms satisfies 0.5 or more and 2.0 or less, where the number of atoms of carbon, phosphorus, and hydrogen in the cluster ions is expressed by CxPyHz (x, y, and z are integers each equal to or more than 1).

Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a shield layer is formed over the first conductive layer forming a bilayer structure, a capping layer is formed over the shield layer, a first annealing operation is performed after the capping layer is formed, the capping layer is removed after the first annealing operation, and a gate electrode layer is formed after the capping layer is removed.

Abstract: A semiconductor component includes a semiconductor body having opposing first surface and second surfaces, and a side surface surrounding the semiconductor body. The semiconductor component also includes an active region including a first semiconductor region of a first conductivity type, which is electrically contacted via the first surface, and a second semiconductor region of a second conductivity type, which is electrically contacted via the second surface. The semiconductor component further includes an edge termination region arranged in a lateral direction between the first semiconductor region of the active region and the side surface, and includes a first edge termination structure and a second edge termination structure. The second edge termination structure is arranged in the lateral direction between the first edge termination structure and the side surface and extends from the first surface in a vertical direction more deeply into the semiconductor body than the first edge termination structure.

Abstract: In a surface layer of a rear surface of the semiconductor substrate, an n+-type cathode region and a p-type cathode region are each selectively provided. The n+-type cathode region and the p-type cathode region constitute a cathode layer and are adjacent to each other along a direction parallel to the rear surface of the semiconductor substrate. The n+-type cathode region and the p-type cathode region are in contact with a cathode electrode. In an n?-type drift layer, plural n-type FS layers are provided at differing depths deeper from the rear surface of the semiconductor substrate than is the cathode layer. With such configuration, in a diode, a tradeoff relationship of forward voltage reduction and reverse recovery loss reduction may be improved and soft recovery may be realized.

Abstract: Hydrogen atoms and crystal defects are introduced into an n? semiconductor substrate by proton implantation. The crystal defects are generated in the n? semiconductor substrate by electron beam irradiation before or after the proton implantation. Then, a heat treatment for generating donors is performed. The amount of crystal defects is appropriately controlled during the heat treatment for generating donors to increase a donor generation rate. In addition, when the heat treatment for generating donors ends, the crystal defects formed by the electron beam irradiation and the proton implantation are recovered and controlled to an appropriate amount of crystal defects. Therefore, for example, it is possible to improve a breakdown voltage and reduce a leakage current.

Abstract: In a surface layer of a rear surface of the semiconductor substrate, an n+-type cathode region and a p-type cathode region are each selectively provided. The n+-type cathode region and the p-type cathode region constitute a cathode layer and are adjacent to each other along a direction parallel to the rear surface of the semiconductor substrate. The n+-type cathode region and the p-type cathode region are in contact with a cathode electrode. In an n?-type drift layer, plural n-type FS layers are provided at differing depths deeper from the rear surface of the semiconductor substrate than is the cathode layer. With such configuration, in a diode, a tradeoff relationship of forward voltage reduction and reverse recovery loss reduction may be improved and soft recovery may be realized.

Abstract: A method for forming a power semiconductor device is provided. The method includes: providing a semiconductor wafer grown by a Czochralski process and having a first side; forming an n-type substrate doping layer in the semiconductor wafer at the first side, the substrate doping layer having a doping concentration of at least 1017/cm3; and forming an epitaxy layer on the first side of the semiconductor wafer after forming the n-type substrate doping layer.

Abstract: A semiconductor device includes a device doping region of an electrical device arrangement disposed in a semiconductor substrate. A portion of the device doping region has a vertical dimension of more than 500 nm and a doping concentration of greater than 1*1015 dopant atoms per cm3. The doping concentration of the portion of the device doping region varies by less than 20% from a maximum doping concentration in the device doping region.

Abstract: An epitaxial substrate and a method for forming the same are disclosed. The epitaxial substrate includes a substrate, a deposition layer, a buffer layer and an epitaxial layer. The deposition layer is directly formed on the substrate, wherein the deposition layer includes a gradient doping concentration, and has a first surface and a second surface which are opposite to each other; the gradient doping concentration has a minimum value at the first surface. The buffer layer is formed on the deposition layer, and an epitaxial layer is formed on the buffer layer. The epitaxial layer is mainly formed of group III-V nitride. The substrate and the deposition layer are formed of homogeneous material. Since the deposition layer is directly formed on the substrate, and the deposition layer and the substrate are formed of a homogeneous material, the epitaxial substrate includes a good heat dissipation efficiency and low leakage current.

Abstract: First and second p-type anode layers (2,3) are provided side by side on a drift layer (1). N-type cathode layer (5) and p-type cathode layer (6) are provided side by side below the drift layer (1). An n-type buffer layer (7) is provided between the drift layer (1) and the n-type cathode layer (5) and between the drift layer (1) and the p-type cathode layer (6). The first p-type anode layer (2,2a,2b) has a greater diffusion depth than a diffusion depth of the second p-type anode layer (3). The first p-type anode layer (2,2a,2b) has a greater impurity concentration than an impurity concentration of the second p-type anode layer (3). The n-type cathode layer (5) has a greater diffusion depth than a diffusion depth of the p-type cathode layer (6). The n-type cathode layer (5) has a greater impurity concentration than an impurity concentration of the p-type cathode layer (6).

Abstract: According to various embodiments, a method for processing a semiconductor region, wherein the semiconductor region comprises at least one precipitate, may include: forming a precipitate removal layer over the semiconductor region, wherein the precipitate removal layer may define an absorption temperature at which a chemical solubility of a constituent of the at least one precipitate is greater in the precipitate removal layer than in the semiconductor region; and heating the at least one precipitate above the absorption temperature.

Abstract: A heterostructure includes a substrate; an intermediate layer disposed on the substrate; and a group III-V layer having a first primary surface disposed on the intermediate layer and a dopant concentration that varies in a manner including a plurality of ramps with at least one of increasing dopant concentration and decreasing dopant concentration, along the growth direction from the first primary surface throughout the layer's thickness before terminating in a second primary surface.

Abstract: Proton irradiation is performed a plurality of times from rear surface of an n-type semiconductor substrate, which is an n? drift layer, forming an n-type FS layer having lower resistance than the n-type semiconductor substrate in the rear surface of the n? drift layer. When the proton irradiation is performed a plurality of times, the next proton irradiation is performed to as to compensate for a reduction in mobility due to disorder which remains after the previous proton irradiation. In this case, the second or subsequent proton irradiation is performed at the position of the disorder which is formed by the previous proton irradiation. In this way, even after proton irradiation and a heat treatment, the disorder is reduced and it is possible to prevent deterioration of characteristics, such as increase in leakage current. It is possible to form an n-type FS layer including a high-concentration hydrogen-related donor layer.

Abstract: An image sensor with a pinned photodiode includes a photodiode formed in a substrate by implanting dopants of a first type through one or more dielectric layers formed over the substrate. A pinning layer for the photodiode may be formed by implanting dopants of a second type through the same one or more dielectric layers. The pinning layer may be formed over a photodiode region of the substrate. The concentration of dopants of the second type may have a maximum value in dielectric layers over the photodiode that exceeds the concentration of dopants of the second type in the substrate below. The photodiode and pinning layer may both be formed by implanting ions of the first and second type respectively through a dielectric layer formed after etching away a portion of another dielectric layer, having a different thickness, and having different optical transmission properties than the another dielectric layer.

Abstract: Methods, apparatuses and devices related to the manufacturing of compensation devices are provided. In some cases, an n/p-codoped layer is deposited for calibration purposes to minimize a net doping concentration. In other cases, alternatingly n- and p-doped layers are then deposited. In other embodiments, an n/p-codoped layer is deposited in a trench where n- and p-dopants have different diffusion behavior. To obtain different doping profiles, a heat treatment may be performed.

Abstract: An electronic device includes a silicon carbide layer having a first conductivity type and a main junction adjacent a surface of the silicon carbide layer, and a junction termination region at the surface of the silicon carbide layer adjacent the main junction. Charge in the junction termination region decreases with lateral distance from the main junction, and a maximum charge in the junction termination region may be less than about 2×1014 cm?2.

Abstract: A method of producing a seminconductor device is disclosed in which, after proton implantation is performed, a hydrogen-induced donor is formed by a furnace annealing process to form an n-type field stop layer. A disorder generated in a proton passage region is reduced by a laser annealing process to form an n-type disorder reduction region. As such, the n-type field stop layer and the n-type disorder reduction region are formed by the proton implantation. Therefore, it is possible to provide a stable and inexpensive semiconductor device which has low conduction resistance and can improve electrical characteristics, such as a leakage current, and a method for producing the semiconductor device.

Abstract: A thin film layer and manufacturing method thereof, a substrate for display and a liquid crystal display are provided. The embodiments according to the present invention can solve the problem that the gradient at the edge of the thin film layer produced with current methods is too steep or perpendicular, thus the thin film layer deposited in the next step easily has step coverage defect or even breakage. The thin film layer of the embodiments of the present invention comprises a plurality of sub-layers with different densities, wherein, the density of an upper sub-layer is smaller than that of a lower sub-layer. The yield and reliability of the thin film transistor and the thin film transistor liquid crystal display produced with the thin film layer of the embodiments of the present invention are high.

Abstract: A semiconductor device includes a SOI substrate including a silicon substrate, an oxide layer on the silicon substrate, and a silicon layer on the oxide layer; a source region and a drain region formed in the silicon layer; and an acceptor-doped layer formed between the oxide layer and the silicon substrate, the acceptor-doped layer being doped with acceptors.

Abstract: A method of fabricating an optoelectronic device includes creating an optoelectronic structure on a first substrate. The optoelectronic structure includes a release layer and a plurality of inorganic semiconductor layers supported by the release layer. The plurality of inorganic semiconductor layers is configured to be active in operation of the optoelectronic device. The plurality of inorganic semiconductor layers are permanently attached to a second substrate, which is flexible. The plurality of inorganic semiconductor layers are released from the first substrate after the attaching step, and the second substrate is deformed to a non-planar configuration.

Abstract: In a semiconductor device a barrier region is sandwiched between a drift region and a charge carrier transfer region. The barrier and charge carrier transfer regions form a pn junction. The barrier and drift regions form a homojunction. A mean impurity concentration in the barrier region is at least ten times as high as an impurity concentration in the drift region. A control structure is arranged to form an inversion layer in the drift and barrier regions in an inversion state. No inversion layer is formed in the drift and barrier regions in a non-inversion state.

Abstract: A semiconductor device having first and second portions with opposite conductivity types. There are first through fourth layers in the semiconductor device. A peak value of the impurity concentration of the fourth layer is higher than the peak value of the impurity concentration of the second layer and lower than the peak value of the impurity concentration of a first portion of the third layer. The fourth layer includes a third portion located on the first portion and a fourth portion which is located on the second portion. The semiconductor device allows a decrease in the forward voltage drop and also allows an improvement of the safe operating area tolerance. Thus, it is possible to decrease the forward voltage drop, improve the maximum reverse voltage, and suppress oscillations at the time of recovery.

Abstract: A method of forming a superjunction device includes forming at least one trench in a first surface of a first semiconductor layer of a first doping type, and a semiconductor mesa region adjoining the at least one trench. A second semiconductor layer is formed at least on sidewalls and a bottom of the at least one trench. The second semiconductor layer is etched by filling the at least one trench with an etchant, and applying a voltage between the first semiconductor layer and the etchant such that a space charge region expands in the second semiconductor layer and in the first semiconductor layer. The voltage is adjusted such that there is a first region in the semiconductor mesa region that is free of the space charge region when the voltage is applied.

Abstract: According to one embodiment, a semiconductor device includes a base layer, a second conductivity type semiconductor layer, a first insulating film, and a first electrode. The first insulating film is provided on an inner wall of a plurality of first trenches extending from a surface of the second conductivity type semiconductor layer toward the base layer side, but not reaching the base layer. The first electrode is provided in the first trench via the first insulating film, and provided in contact with a surface of the second conductivity type semiconductor layer. The second conductivity type semiconductor layer includes a first second conductivity type region, and a second second conductivity type region. The first second conductivity type region is provided between the first trenches. The second second conductivity type region is provided between the first second conductivity type region and the base layer, and between a bottom part of the first trench and the base layer.

Abstract: Method of producing a vertically inhomogeneous platinum or gold distribution in a semiconductor substrate with a first and a second surface opposite the first surface, with diffusing platinum or gold into the semiconductor substrate from one of the first and second surfaces of the semiconductor substrate, removing platinum- or gold-comprising residues remaining on the one of the first and second surfaces after diffusing the platinum or gold, forming a phosphorus- or boron-doped surface barrier layer on the first or second surface, and heating the semiconductor substrate for local gettering of the platinum or gold by the phosphorus- or boron-doped surface barrier layer.

Abstract: A Multi-Gate Field-Effect Transistor includes a fin-shaped structure, a gate structure, at least an epitaxial structure and a gradient cap layer. The fin-shaped structure is located on a substrate. The gate structure is disposed across a part of the fin-shaped structure and the substrate. The epitaxial structure is located on the fin-shaped structure beside the gate structure. The gradient cap layer is located on each of the epitaxial structures. The gradient cap layer is a compound semiconductor, and the concentration of one of the ingredients of the compound semiconductor has a gradient distribution decreasing from inner to outer. Moreover, the present invention also provides a Multi-Gate Field-Effect Transistor process forming said Multi-Gate Field-Effect Transistor.

Abstract: A semiconductor device includes a substrate having a supporting substrate, wherein a first epitaxial layer and a second epitaxial are sequentially stacked, an isolation region including a first buried impurity region of a second conductivity type and a second buried impurity region of the second conductivity type wherein the first buried impurity region is formed from the supporting substrate to the first epitaxial layer, and the second buried impurity region is formed from the first epitaxial layer to the second epitaxial layer and is in contact with an edge of the first buried impurity region, a third buried impurity region of a first conductivity type formed from the first epitaxial layer to the second epitaxial layer, located in the second buried impurity region and overlapped with the first buried impurity region, and a transistor formed over the second epitaxial layer and overlapped with the third buried impurity region.

Abstract: A voltage compensation structure includes a first semiconductor or insulating material disposed along one or more sidewalls of a trench formed in a doped epitaxial semiconductor material. The first semiconductor or insulating material has a dopant diffusion constant which is at least 2× different for n-type dopant atoms than p-type dopant atoms. The voltage compensation structure further includes a doped second semiconductor material disposed in the trench so that the first semiconductor or insulating material is interposed between the doped second semiconductor material and the doped epitaxial semiconductor material. The doped second semiconductor material has a different dopant diffusion constant than the first semiconductor or insulating material so that a lateral charge separation occurs between the doped second semiconductor material and the doped epitaxial semiconductor material.

Abstract: A semiconductor device including a p or p+ doped portion and an n or n+ doped portion separated from the p or p+ doped portion by a semiconductor drift portion. The device further includes at least one termination portion provided adjacent to the drift portion. The at least one termination portion comprises a Super Junction structure.

Abstract: A semiconductor apparatus includes a p-type doped layer, an n-type doped layer, and an internal electrical connection layer that is deposited and electrically coupled between the p-type doped layer and the n-type doped layer. In one embodiment, the internal electrical connection layer includes a group IV element and a nitrogen element, and the number of atoms of the group IV element and the nitrogen element is greater than 50% of the total number of atoms in the internal electrical connection layer. In another embodiment, the internal electrical connection layer includes carbon element with a concentration greater than 1017 atoms/cm3. In a further embodiment, the internal electrical connection layer is formed at a temperature lower than those of the p-type doped layer and the n-type doped layer.

Abstract: Embodiments of a semiconductor die having a semiconductor device implemented on the semiconductor die and an edge termination structure around a periphery of the semiconductor device and methods of fabricating the same are disclosed. In one embodiment, a semiconductor die includes a semiconductor device and an edge termination structure around a periphery of the semiconductor device, where the edge termination structure includes negative features (e.g., trenches and/or divots) that vary dose in a corresponding edge termination region to approximate a desired dose profile. In one embodiment, the desired dose profile is a substantially decreasing or substantially linearly decreasing dose from an edge of a main junction of the semiconductor device to an edge of the edge termination region. In this manner, electric field crowding at the edge of the main junction of the semiconductor device is substantially reduced, which in turn substantially improves a break-down voltage of the semiconductor device.

Abstract: Systems and methods are provided for activating dopants in a semiconductor structure. For example, a semiconductor structure including a plurality of dopants is provided. One or more microwave-absorption materials are provided, the microwave-absorption materials being capable of increasing an electric field density associated with the semiconductor structure. Microwave radiation is applied to the microwave-absorption materials and the semiconductor structure to activate the plurality of dopants for fabricating semiconductor devices. The microwave-absorption materials are configured to increase the electric field density in response to the microwave radiation so as to increase the semiconductor structure's absorption of the microwave radiation to activate the dopants.

Abstract: A power semiconductor device includes a semiconductor body having a first side, a second side opposite the first side and an outer rim. The semiconductor body includes an active region, an edge termination region arranged between the active region and the outer rim, a first doping region in the active region and connected to a first electrode arranged on the first side, a second doping region in the active region and the edge termination region and connected to a second electrode arranged on the second side, a drift region between the first doping region and the second doping region, the drift region including a first portion adjacent to the first side and a second portion arranged between the first portion and the second doping region, and an insulating region arranged in the edge termination region between the second doping region and the first portion of the drift region.

Abstract: A method for producing a semiconductor includes providing a p-doped semiconductor body having a first side and a second side; implanting protons into the semiconductor body via the first side to a target depth of the semiconductor body; bonding the first side of the semiconductor body to a carrier substrate; forming an n-doped zone in the semiconductor body by heating the semiconductor body such that a pn junction arises in the semiconductor body; and removing the second side of the semiconductor body at least as far as a space charge zone spanned at the pn junction.

Abstract: A p-type anode layer (2) provided on an n-type drift layer (1) in the active region. A p-type diffusion layer (3) is provided on the n-type drift layer (1) in a termination region outside the active region. An oxide film (4) covers an outer periphery of the p-type anode layer (2). An anode electrode (5) is connected to a portion of the p-type anode layer (2) not covered with the oxide film (4). An n+-type cathode layer (7) is provided below the n-type drift layer (1). A cathode electrode (8) is connected to the n+-type cathode layer (7). An area of a portion of the p-type anode layer (2) covered with the oxide film (4) is 5 to 30% of a total area of the p-type anode layer (2).

Abstract: According to one embodiment, a semiconductor device includes a second electrode opposite to a first electrode, a first semiconductor layer provided above the first electrode, the first semiconductor layer having first semiconductor regions of a first conductivity type alternating with second semiconductor regions of a second conductivity type in a direction generally parallel to the first electrode A second semiconductor layer of the second conductivity type is provided on the first semiconductor layer Third extend into the first semiconductor layer from the second semiconductor layer. At least one first semiconductor region includes a first portion containing hydrogen ions and a second portion between the first portion and the second semiconductor layer that has a dopant concentration lower than that of the first portion.

Abstract: An ESD protection device includes a substrate having a first conductive type. A doped well having a second conductive type is disposed in the substrate. A first doped region having the first conductive type is disposed in the doped well. A second doped region having the first conductive type is disposed in the substrate, wherein part of the second doped region is in the doped well, and the remaining part of the second doped region is separate from the doped well. A front terminal electrically connects the first doped region. A back terminal is disposed on a back side of the substrate.

Abstract: A method of forming an epitaxial layer includes the following steps. At first, a first epitaxial growth process is performed to form a first epitaxial layer on a substrate, and a gas source of silicon, a gas source of carbon, a gas source of phosphorous and a gas source of germanium are introduced during the first epitaxial growth process to form the first epitaxial layer including silicon, carbon, phosphorous and germanium. Subsequently, a second epitaxial growth process is performed to form a second epitaxial layer, and a number of elements in the second epitaxial layer is smaller than a number of elements in the first epitaxial layer.

Abstract: A bi-directional electrostatic discharge diode structure consumes substantially less silicon real estate and provides ultra-low capacitance by utilizing a p? epitaxial layer that touches and lies between an n+ lower epitaxial layer and an n+ upper epitaxial layer. A metal contact touches and lies over a p+ layer, which touches and lies over the n+ upper epitaxial layer.

Abstract: The use of doped silicon nanoparticle inks and other liquid dopant sources can provide suitable dopant sources for driving dopant elements into a crystalline silicon substrate using a thermal process if a suitable cap is provided. Suitable caps include, for example, a capping slab, a cover that may or may not rest on the surface of the substrate and a cover layer. Desirable dopant profiled can be achieved. The doped nanoparticles can be delivered using a silicon ink. The residual silicon ink can be removed after the dopant drive-in or at least partially densified into a silicon material that is incorporated into the product device. The silicon doping is suitable for the introduction of dopants into crystalline silicon for the formation of solar cells.

Abstract: A semiconductor device includes a drift zone of a first conductivity type formed within a semiconductor body, wherein one side of opposing sides of the drift zone adjoins a first zone within the semiconductor body and the other side adjoins a second zone within the semiconductor body. First semiconductor subzones of a second conductivity type different from the first conductivity type are formed within each of the first and second zones opposing each other along a lateral direction extending parallel to a surface of the semiconductor body. A second semiconductor subzone is formed within each of the first and second zones and between the first semiconductor subzones along the lateral direction. An average concentration of dopants within the second semiconductor subzone along 10% to 90% of an extension of the second semiconductor subzone along a vertical direction perpendicular to the surface is smaller than the average concentration of dopants along a corresponding section of extension within the drift zone.

Abstract: System and method for controlling the channel thickness and preventing variations due to formation of small features. An embodiment comprises a fin raised above the substrate and a capping layer is formed over the fin. The channel carriers are repelled from the heavily doped fin and confined within the capping layer. This forms a thin-channel that allows greater electrostatic control of the gate.

Abstract: Embodiments of the present invention relate to a rectifier circuit and methods of making the same for use in wireless devices (e.g., RFID tags). The present invention is drawn to a rectifier circuit comprising first and second diode-wired transistors in series, each having a gate oxide layers of the same target thickness. The first diode-wired transistor receives an alternating current and the second diode-wired transistor provides a rectifier output. The first and second diode-wired transistors are configured to divide between them a first voltage differential across the rectifier circuit. The gate oxides are exposed to a peak stress that is similar to a stress on the gate oxide of logic transistors made using the same process.

Abstract: Semiconductor component or device is provided which includes a current barrier element and for which the impedance may be tuned (i.e. modified, changed, etc.) using a focused heating source.

Abstract: A resistance random access memory device according to an embodiment includes a first electrode, a second electrode and a variable resistance film provided between the first electrode and the second electrode. The second electrode includes material selected from the group consisting of silver, copper, zinc, gold, titanium, nickel, cobalt, tantalum, aluminum, and bismuth, alloys thereof, and silicides thereof. The variable resistance film includes silicon oxynitride. The variable resistance film includes a first resistance change layer having a first nitrogen concentration and a second resistance change layer having a second nitrogen concentration lower than the first nitrogen concentration.

Abstract: A semiconductor component is disclosed. One embodiment provides a semiconductor body having a cell region with at least one zone of a first conduction type and at least one zone of a second conduction type in a rear side. A drift zone of the first conduction type in the cell region is provided. The drift zone contains at least one region through which charge carriers flow in an operating mode of the semiconductor component in one polarity and charge carriers do not flow in an operating mode of the semiconductor component in an opposite polarity.