Method and Apparatus for Reading a Programmable Anti-Fuse Element in a High-Voltage Integrated Circuit

Abstract

A semiconductor device comprises an N type well region in a P type substrate. A source region of a MOSFET is laterally separated from a boundary of the well region, which comprises the drain of the MOSFET. An insulated gate of the MOSFET extends laterally from the source region to at least just past the boundary of the well region. A polysilicon layer, which forms a first plate of a capacitive anti-fuse, is insulated from an area of the well region, which forms the second plate of the anti-fuse. The anti-fuse is programmed by application of a voltage across the first and second capacitive plates sufficient to destroy at least a portion of the second dielectric layer, thereby electrically shorting the polysilicon layer to the drain of the HVFET. This abstract is provided to allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.

Description

TECHNICAL FIELD

The present disclosure generally relates to semiconductor processes for fabricating high-voltage integrated circuits with programmable electrical connections.

BACKGROUND

A common type of integrated circuit (IC) device is a metal-oxide-semiconductor field effect transistor (MOSFET). A MOSFET is a field-effect device that includes a source region, a drain region, a channel region extending between the source and drain regions, and a gate provided over the channel region. The gate includes a conductive gate structure disposed over the channel region. The conductive gate is typically insulated from the channel region by a thin oxide layer.

High-voltage, field-effect transistors (HVFETs) are also well known in the semiconductor arts. Many HVFETs employ a device structure that includes an extended drain region that supports or “blocks” the applied high-voltage (e.g., 200 volts or more) when the device is in the “off” state. Conventional HVFETs are commonly formed as lateral or vertical device structures. In a lateral HVFET, current flow in the on-state is horizontal or substantially parallel to a surface of the semiconductor substrate. On the other hand, in a vertical HVFET current flows vertically through the semiconductor material, e.g., from a top surface of the substrate where the source region is disposed, down to the bottom of the substrate where the drain region is located.

Conventional power IC devices often employ a large vertical or lateral high-voltage output transistor in a configuration wherein the drain of the output transistor is coupled directly to an external pin. The power IC device typically includes a controller circuit that is separate from the high-voltage output transistor. Both the controller and output transistor are usually housed in the same IC package. To provide start-up current for the controller circuit of the IC, a high external voltage may be applied to the external pin. The controller is typically limit-protected from the high externally-applied voltage by a junction field-effect transistor (JFET) “tap” structure. For example, when the drain of the high voltage output transistor is taken to, say 550V, the tap transistor limits the maximum voltage coupled to the controller to approximately 50V, thereby providing a small (2-3 mA) current for start-up of the device. By way of further background, U.S. Pat. No. 7,002,398 discloses a three-terminal JFET transistor that operates in this manner.

The operating characteristics of a power IC device is typically set or programmed by selectively opening (or closing) one or more electrical connections. A zener diode is one type of electrical element used to trim or program analog parameters (e.g., frequency) of a power IC device. A zener diode provides a normally off or non-conducting electrical connection. To change the conducting state of the zener element a high voltage (>10V) is typically applied to breakdown the zener, with the large resulting current (150-200 mA) shorting the anode and cathode terminals of the zener permanently. The cumulative current flowing through the zener elements may be used to program one or more analog parameters. For example, based on the state of one or more zener elements, an analog parameter such as frequency may be set within a specified tolerance in the controller section of the power IC.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example, and not limitation, in the figures of the accompanying drawings, wherein:

FIG. 1 illustrates an example power IC device block diagram.

FIG. 2 illustrates an example cross-section of an anti-fuse structure.

FIG. 3 illustrates an example circuit schematic diagram of an anti-fuse trimming architecture for a power IC.

FIG. 4 illustrates an example cross-section of a programming element comprising an integrated transistor and anti-fuse device structure.

FIG. 5 is an equivalent circuit schematic diagram of the integrated device structure shown in FIG. 4.

FIG. 6 illustrates another example circuit schematic diagram of an anti-fuse trimming architecture for a power IC.

FIG. 7 illustrates an example cross-section of a soft high-voltage (HV) clamp device structure.

FIG. 8 is an equivalent circuit schematic diagram of the device structure shown in FIG. 7.

FIG. 9 is an equivalent circuit schematic diagram of the soft HV clamp device structure shown in FIG. 7 coupled with the integrated device structure shown in FIG. 5.

FIG. 10 is an example flow diagram of a sequence of steps for programming an anti-fuse element.

FIG. 11 is an example flow diagram of a sequence of steps for reading an anti-fuse element.

FIG. 12 illustrates an example cross-section of another anti-fuse device structure.

DESCRIPTION OF EXAMPLE EMBODIMENTS

A novel integrated anti-fuse device structure for use with a new trimming technology is disclosed. In the following description specific details are set forth, such as material types, voltages, structural features, manufacturing steps, etc., in order to provide a thorough understanding of the disclosure herein. However, persons having ordinary skill in the relevant arts will appreciate that these specific details may not be needed to practice the embodiments described. References throughout this description to “one embodiment”, “an embodiment”, “one example” or “an example” means that a particular feature, structure or characteristic described in connection with the embodiment or example is included in at least one embodiment. The phrases “in one embodiment”, “in an embodiment”, “one example” or “an example” in various places throughout this description are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures or characteristics may be combined in any suitable combinations and/or sub-combinations in one or more embodiments or examples.

It should be understood that the elements in the figures are representational, and are not drawn to scale in the interest of clarity. It is also appreciated that although an IC utilizing mostly N-channel transistor devices (both high-voltage and low-voltage) are disclosed. P-channel transistors may also be fabricated by utilizing the opposite conductivity types for all of the appropriate doped regions.

In the context of the present application a high-voltage or power transistor is any semiconductor transistor structure that is capable of supporting 150V or more in an “off” state or condition. In one embodiment, a power transistor is illustrated as an N-channel metal oxide semiconductor field-effect transistor (MOSFET) with the high-voltage being supported between the source and drain regions. In other embodiments, a power transistor may comprise a bipolar junction transistor (BJT), an insulated gate field effect transistor (IGFET), or other device structures that provide a transistor function.

For purposes of this disclosure, “ground” or “ground potential” refers to a reference voltage or potential against which all other voltages or potentials of a circuit or IC are defined or measured. A “pin” provides a point of external electrical connection to an IC device or package, thereby allowing external components, circuits, signals, power, loads, etc., to be coupled to the internal components and circuitry of the power IC device.

In the context of the present disclosure a tap transistor is a three terminal (Le., electrode) transistor device structure in which a voltage at a first or tap terminal is substantially proportional to an applied voltage across the second and third terminals when the applied voltage is less than a pinch-off voltage of the transistor device. When the applied voltage across the second and third terminals exceeds the pinch-off voltage, the voltage provided at the tap terminal is substantially constant or unchanging with increased applied voltage. In one embodiment, a tap transistor comprises a junction field-effect transistor (JFET).

Furthermore, in the context of the present disclosure, an anti-fuse is a circuit element that provides a normally open electrical connection in a device structure like that of a capacitor, with two or more layers of metal, polysilicon, or doped semiconductor material separated by a dielectric layer (e.g., oxide, nitride, etc.). The electrical connection between the two layers of metal can be permanently closed by applying a large voltage across the metal conductors which acts to break down or destroys the dielectric layer, thereby electrically shorting the two metal layers.

FIG. 1 illustrates an example power IC device block diagram comprising a high-voltage output transistor component section 10 that includes one or more large-sized, high-voltage output transistors which control the current flaw to one or more external loads. In a switch-mode power supply IC, for example, a single, large, high-voltage output transistor may control the current through the primary winding of a transformer, thereby controlling the power delivered by the power supply. The drain of the high-voltage output transistor is typically connected directly to an external pin.

The conceptual block diagram of FIG. 1 also includes an anti-fuse programmable memory 11 coupled to HV output transistor section 10 through an isolation transistor element 14. Anti-fuse programmable memory 11 is coupled, in turn, to Read/Write block 12 via an isolation transistor element 15. Read/Write block 12 is shown being coupled to the controller section of the power IC device. Anti-fuse programmable memory 11 comprises a series or array of anti-fuse structural elements that may be programmed through the drain pin of HV output transistor section 10. During programming, isolation transistor element 14 is turned “on” to couple an externally-applied high voltage to a selected anti-fuse element of memory 11. At the same time, isolation transistor element 15 is turned on for the read/write element associated with the selected anti-fuse element. All of the other read/write elements of block 12 associated with unselected anti-fuse elements are turned “off”. During reading of each of the anti-fuse elements in memory 11 isolation transistor element 14 and isolation transistor element 15 are both turned on (for all read/write elements in block 12). It is appreciated that during normal operation of the power IC device isolation transistor elements 14 and 15 are both off.

FIG. 2 illustrates an example cross-section of an anti-fuse structure 20 that may be utilized as a programming element. In one embodiment, anti-fuse structure 20 comprises a tiny (˜10 μm²) gate oxide capacitor 32 having a first terminal or electrode 21 (e.g., aluminum, tungsten alloy, or other metals) which connects to an underlying N+ semiconductor region 23, and a second electrode 22 (e.g., polysilicon) separated from underlying N+ region 23 and N-type well region 24 by a thin gate oxide layer 26, N-well region 24 is shown formed in a P-type substrate 25.

Prior to programming, anti-fuse structure 20 does not pass any current; that is, it appears as an open circuit to a normal D.C. operating voltage (e.g., VDD=5-6V). Anti-fuse structure 20 may be programmed (i.e., trimmed) by applying a high voltage pulse across terminals 21 and 22 (e.g., 30-35V, 0.5-1.0 mA for 2-5 ms). The voltage required to blow the anti-fuse will depend on the gate oxide thickness (e.g., ˜30V for 25 nm oxide). Application of such a high-voltage pulse causes gate oxide 26 to rupture, resulting in a permanent short between electrodes 21 & 22 with a resistance typically on the order of a few thousand ohms. The state of anti-fuse structure 20 can then be read by sensing its resistance. As will be described in detail below, the trimming pulse utilized to trim the anti-fuse structure is provided externally through the drain pin which connects to the high-voltage output MOSFET device.

Practitioners in the art will appreciate that the amount of current required to trim anti-fuse structure 20 is significantly smaller as compared to existing zener diodes, which normally require >150 mA. Additionally, persons of skill in the art will understand that the integrated anti-fuse device structures disclosed herein may reduce the overall size of the trimming block of a power IC device by a factor of about five or more as compared to prior art designs.

FIG. 3 illustrates an example circuit schematic diagram of an anti-fuse trimming architecture for a power IC which comprises an anti-fuse block 30 with multiple anti-fuse programming elements 31. Node 36 of anti-fuse block 30 is shown coupled to node 43 through isolation unit 45. Voltage regulator 44 is coupled between node 43 and ground. Node 43 also comprises a first or “tap” terminal of tap transistor 41, which in one embodiment, comprises a JFET. A second terminal of tap transistor 41 is connected to an external drain pin or node 42 (labeled V_EXTERNAL), which is also connected to the drain of high-voltage output MOSFET 40. The third terminal, the gate of the JFET structure, is normally grounded. Persons of skill in the semiconductor arts will appreciate that tap transistor 41 and high-voltage output MOSFET 40 may be integrated into a single device structure. Also, anti-fuse block 30 and the controller section of the power IC are normally fabricated on the same piece of silicon material.

In the embodiment of FIG. 3, anti-fuse block 30 is shown integrating the programming memory and Read/Write sections of FIG. 1 into a single architectural block. Anti-fuse block 30 comprises multiple anti fuse programming elements 31₁, 31₂ . . . 31_n, where n is an integer. Each anti-fuse programming element 31 is connected between node 36 and a corresponding Read/Write (R/W) block 34 that stores a logical state (“0” or “1”) which reflects the current flowing through capacitive anti-fuse 32 and associated MOSFET 33. For example, in the event that anti-fuse 32₁ is not trimmed (i.e., programmed state=“0”), little or no current flows through anti-fuse programming element 31₁. Conversely, application of a high voltage (HV) pulse to trim anti-fuse 32₂ produces current flow through anti-fuse programming element 31₂, (i.e., programmed state=“1”).

In the example of FIG. 3, a programming or trimming HV pulse may be applied to the V_EXTERNAL pin of the power IC at node 42 and transferred to anti-fuse block at node 36 through tap transistor 41 and isolation unit 45. In normal operating conditions, isolation unit 45 isolates anti-fuse block 30 from the voltage appearing at node 43 of tap transistor 41. To program a selected anti fuse 32, the gate of the corresponding trimming MOSFET 33 (labeled “AFH_n”) is raised to a high potential and the source is connected to ground (GND) through a low-impedance switch. All of the other trimming MOSFETs (associated with unselected anti-fuses) are off (e.g., gate grounded with their sources connected to ground through a high-impedance). Isolation unit 45 is turned on, which connects anti-fuse block 30 to tap transistor 41. Voltage regulator 44 is turned off during programming to allow node 43 (and also node 36) to rise to a relatively high positive voltage. Note that the pulsed voltage V_EXTERNAL applied to the drain pin of the power IC device may be several hundred volts (e.g., 600-700V), but tap transistor 41 limits the voltage appearing at node 43 to a much lower voltage potential (e.g., 30-50V). Persons of ordinary skill will appreciate that high-voltage output MOSFET 40 is designed and fabricated to withstand the high pulsed voltage V_EXTERNAL e.g. 600-700V) without damage to the transistor device.

When the high-voltage pulse is applied across the selected anti-fuse 32, the gate oxide separating the two terminals or capacitive plates ruptures, thereby programming (shorting) the anti-fuse structure.

For the unselected anti-fuses 32—i.e., the ones that are not intended to be blown or shorted—the gate of the corresponding MOSFET 33 is grounded such that MOSFET 33 is off. Consequently, the voltage appearing at the bottom capacitive plate (connected to the drain of MOSFET 33) rises in potential, substantially tracking that of the top plate (connected to node 36). Hence, the gate oxides of the unselected anti-fuses 32 are not ruptured and the device structures remain open circuits.

The state of each anti-fuse programming element 31 may be read at the startup of the power supply, which normally occurs when the VDD power supply line of the controller section of the IC is first charged. Voltage regulator 44 is turned on at that point so that the maximum voltage at node 43 is regulated, e.g., under 12V. To read the programming state of the array of elements 31 which comprise block 30, the drain pin (V_EXTERNAL) is raised to greater than about 10V, isolation unit 45 is turned on, and a small current (several microamperes) is pulled through each of the read/write blocks 34. If a particular anti-fuse 32 is programmed, the source of the associated trimming MOSFET 33 (labeled “AFHn”) floats up to the gate-to-source voltage (Vgs) minus the threshold voltage (Vt) of MOSFET 33. On the other hand, if the particular anti-fuse 32 is untrimmed or open, the source of the associated MOSFET 33 is at ground potential. The state of each anti-fuse programming element 31 is latched in the corresponding R/W block 34 when the VDD voltage potential crosses a certain value (˜5V). Thereafter, isolation unit 45 is turned off, thereby isolating node 36 from node 43, and no current flows through anti fuses 32 under the normal operating condition of the power IC.

FIG. 4 illustrates an example cross-section of one embodiment of an anti-fuse programming element 31 that includes an integrated high-voltage field-effect transistor (HVFET) and anti-fuse device structure. FIG. 5 is an equivalent circuit schematic diagram of the integrated device structure shown in FIG. 4. As can be seen the anti-fuse capacitor 32 shown in FIG. 5 comprises a polysilicon layer 48 that is separated from an underlying N-type well region 47 by a thin gate oxide layer 49 (see FIG. 4). Polysilicon layer 48 and N-well region 47 form the two plates of the capacitive anti-fuse structure. N-well region 47 also forms the drain region of MOSFET 33. A source electrode 58 provides an electrical connection with N+ source region 57 and P+ region 56, both of which are disposed in a P-type well region 55 that adjoins N-well region 47. An area of P-well region 55 which forms the channel region of MOSFET 33 laterally separates N+ source region 57 from the boundary or edge between P-well region 55 and N-well region 47. The gate of MOSFET 33 comprises a polysilicon layer 52 that is insulated from the underlying P-type substrate 25 and N+ well region by a thin gate oxide layer 51. A gate electrode 59 provides an electrical connection with polysilicon layer 52.

In one implementation, MOSFET 33 is designed to have a breakdown voltage of approximately 50V, whereas gate oxide 49 of the capacitive anti-fuse structure is manufactured to have a breakdown voltage of about 30V.

The device structure of FIG. 4 also includes a first plurality of substantially-parallel, vertically spaced-apart P-type buried regions 53 disposed in the left-hand area of N-well 47. A corresponding plurality of JFET conduction channels 55 are shown formed by the vertical spacing of buried regions 53. A second plurality of substantially-parallel, vertically spaced-apart P-type buried regions 54 is shown disposed in the right-hand area of N-well 47. Buried regions 53 and 54 are disposed beneath thick field oxide regions 50. The uppermost buried regions are shown coincident with field oxide region 50 on both the left and right-hand sides of N-well 47.

As can be seen, P-type buried regions 53 and 54 do not extend laterally beneath thin oxide layers 51 or 49. In one embodiment, a deep implant (not shown) or any other type of equivalent structure may be used to electrically connect each of buried regions 53 & 54. This allows P-type buried regions 53 and 54 which comprise the gate of the JFET to be electrically connected (along with source electrode 58) to a potential at or near ground when anti-fuse programming element 31 is intended to be left untrimmed or open.

FIG. 12 illustrates an example cross-section of another anti-fuse device structure that is identical in all respects to that of FIG. 4, except that P-type buried regions 53 and 54 are omitted. In other words, it is appreciated that in certain embodiments, P-type buried regions 53 and 54 are an optional feature in the integrated anti-fuse device structure utilized in the anti-fuse programming memory described herein.

FIG. 6 illustrates another example circuit schematic diagram of an anti-fuse trimming architecture for a power IC device. Output transistor section 10 is the same as shown in FIG. 3, with external drain pin (node) 42 being directly connected to the drain of high-voltage output MOSFET 40 and a second terminal of JFET tap transistor 41. Node 43 comprises the first (tap) terminal of tap transistor 41, which is shown coupled to the drain of NMOS HV transistor 71 (labeled N1) of voltage regulator 44. The source of transistor 71 is shown connected to 6V regulator 73 at node 70, which also comprises an external VDD pin of the power IC device. In one embodiment, VDD pin 70 comprises the supply pin of the controller section of the power IC device, and voltage regulator 44 comprises a shunt regulator that regulates VDD pin 70 to ˜6V.

Node 43 is also shown connected to the source of PMOS HV transistor 78 (labeled P1) and to one end of resistor 74 of isolation unit 45. The other end of resistor 74 (node 75) is shown connected to the gate of transistor 78, and also to the drain of HV transistor 76 (labeled N2). The drain of PMOS HV transistor 78 is coupled to one end of resistor 79 at node 36. The other end of resistor 79 is coupled to the drain of HV transistor 77 (labeled N3). The sources of transistors 76 & 77 are coupled to ground.

Practitioners will appreciate that PMOS HV transistor 78 of isolation unit 45 functions to isolate anti fuse block 30 from tap transistor 41 under normal operating conditions. Transistor 76 (N2) and resistor 74 function to level shift the gate control signal of PMOS HV transistor 78. In one implementation, the current through transistor 76 and resistor 74 may be designed such that when the transistor 76 is turned on, the gate-to-source voltage of PMOS HV transistor 78 is limited to about 10V. In certain embodiments, the gate of transistor 78 may be clamped.

It should be understood that transistor 77 (N3) and resistor 79 are optional, and may be used to connect anti-fuse structures 32 to ground. In alternative embodiments, transistor 77 (N3) and resistor 79 may be eliminated so that anti-fuse structures 32 are left floating during normal operation.

In one embodiment, isolation unit 45, voltage regulator 44 and trimming MOSFETs 33a-33n (labeled AFH₁-AFH_n) are should be capable of withstanding the maximum tap voltage (˜50V). For example, the circuit components labeled as high-voltage (HV) devices in FIG. 6 should withstand applied voltages in the 60-70V range before breakdown occurs.

As discussed above, voltage regulator 44 of FIG. 6 is shown coupled between node 43 and ground. Node 43 also comprises a first or “tap” terminal of tap transistor 41, which in one embodiment, comprises a JFET. A second terminal of tap transistor 41 is connected to an external drain pin or node 42 (labeled V_EXTERNAL) which is also connected to the drain of high-voltage output MOSFET 40.

Continuing with the example of FIG. 6, node 36 of anti-fuse block 30 is shown connected to the drain of PMOS HV transistor 78 and to one terminal of each of anti-fuses 32a-32n. The other terminal of anti-fuses 32 is coupled to the drain of associated trimming MOSFET 33. The source of each MOSFET 33, in turn, is connected to the drain of an associated low-voltage (LV) NMOS transistor 82 and a corresponding latch circuit element 81. The source of each transistor 82 is coupled to ground. The gates of all the low voltage NMOS transistors 82a-82n (labeled AFL₁-AFL_n) are coupled to corresponding Read/Write signal lines, whereas the gates of the NMOS (HV) trimming transistors 33a-33n (labeled AFH₁-AFH_n) are coupled to the output of a decoder (not shown) that selects the trim bit (i.e., which one of the anti-fuses 32 is to be blown or trimmed).

To program an individual bit of block 30, the read/write signal line coupled to the gate of the corresponding LV MOSFET 82 is connected to VDD (˜6V) so that the source of associated trimming MOSFET 33 is effectively shorted to ground. The gates of all of the other LV MOSFETs are connected to ground, thereby turning these transistors off. By way of example, to program anti-fuse 32a, the gate of the LV MOSFET 82a is taken to VDD, and the gates of MOSFETs 82b-82n are grounded.

To read the programming state of anti-fuse block 30, the read/write signal coupled to transistors 82 is fed from a current mirror such that each of the LV MOSFETs have few microamps flowing through them.

The example of FIG. 6 also includes optional “soft” HV clamp elements 80, each of which is coupled across a corresponding anti-fuse 32. For instance, soft clamp element 80a is coupled across anti-fuse 32a; soft clamp element 80b is coupled across anti-fuse 32b; etc. Each of the soft clamp elements 80 functions to avoid unintentional programming of a non-selected (not selected for trimming) anti-fuse by clamping the voltage that appears across the corresponding anti fuse 32. Practitioners will understand that when programming a particular anti-fuse, the top plates of all the anti-fuses (node 36) are simultaneously taken to high voltage of (e.g., ˜50V). When the trimming MOSFET 33 of an unselected anti-fuse 32 is off, the voltage of the lower plate (coupled to the drain of the associated MOSFET 33) of anti-fuse 32 typically follows the voltage applied to the upper plate via capacitive coupling, with some small leakage current flowing through the anti-fuse. However, there is a risk that the lower capacitive plate of anti-fuse 32 may not track or follow the voltage on the upper capacitive plate, in which case the anti-fuse structure may be damaged by the unexpected voltage difference between the two plates. To alleviate this potential risk, in one embodiment, a parasitic PMOS transistor comprising a polysilicon layer that covers a relatively thick field oxide layer is utilized as a soft HV clamp in parallel to the anti-fuse.

By way of example, the parasitic PMOS transistor utilized as a soft HV clamp may have a threshold voltage (V_t) of ˜20V and a BV similar to that of PMOS HV transistor 78, e.g., 55-60V. The gate of the parasitic PMOS transistor may be connected to ground potential. During programming, when node 36 of anti fuse block 30 goes higher than the threshold voltage of the parasitic PMOS transistor, soft clamp element 80 begins flowing a small current, e.g., a few microamperes. For the particular anti-fuse which is being programmed this current will be added to the trim current that flows through the anti-fuse (500 uA-1 mA). For the remaining group of unselected anti-fuses, this low current charges the bottom capacitive plate, thereby reducing the voltage build-up across each of the unselected anti-fuses. During read cycle, the voltage at node 36 does not exceed ˜12V, so each of soft clamp elements 80a-80n is off.

FIG. 7 illustrates an example cross-section of a soft high-voltage (HV) clamp device structure comprising a parasitic PMOS transistor 62 suitable for use as a soft clamp element 80 in the embodiment of FIG. 6. FIG. 8 is an equivalent circuit schematic diagram of parasitic PMOS transistor 62. FIG. 9 shows transistor 62 coupled with the integrated device structure shown in FIG. 5 to implement a soft clamp across anti-fuse 32. In the example of FIG. 7, a polysilicon layer 64, which forms the gate of transistor 62, is shown disposed on a thick field oxide layer 66 over the area of N well region 67 between P-type regions 68 & 72. N-well region 67 is disposed in P-type substrate 25. It is appreciated that N-well 67 of PMOS transistor 62 is separate from the N-well used to form the anti-fuse structure (e.g., N-well 47 in FIG. 4). An N+ region 70 is also disposed in N-well region 67 to electrically connect N-well region 67 to source electrode 63. A P+ source region 69, which is disposed in P-type region 68, is also electrically connected to source electrode 63. A P+ drain region 71 disposed in P-type region 72 is shown electrically connected to drain electrode 65.

It is further appreciated that the gate capacitance of transistor 62 is substantially lower as compared to the capacitance of anti-fuse 32 due to the relative thickness of field oxide layer 66. In one embodiment, the threshold voltage of transistor 62, which is largely determined by the thickness of field oxide layer 66, is approximately 15-20V. The drain-to-source breakdown voltage of transistor 62 is greater than 50V.

FIG. 10 is an example flow diagram of a sequence of steps for programming an anti-fuse element shown in the embodiment of FIG. 6. The sequence begins at block 90 with the application of 5V to the external drain pin (e.g., node 42 in FIG. 6) of the power IC device. A counter/decoder may be utilized (e.g., clocked through) to then select and turn on the appropriate trimming MOSFET 33 (block 91). That is, a voltage is applied to the gate of the trimming MOSFET 33 that corresponds to the anti-fuse element selected to be programmed, the gate voltage being sufficiently high so as to turn on that trimming MOSFET. The other trimming MOSFETs associated with the unselected anti-fuse elements have their gates connected to ground to ensure that they remain off. The write signal may be applied (block 92) by taking the gates of the LV NMOS transistors 82 to VDD (˜6V) thereby shorting the source of MOSFETs 33 to ground through a low-impedance. Transistors 71 & 77 (N1 & N3) are turned off (block 93), and transistor 76 (N2) is turned on, which causes transistor 78 (P1) to turn on (block 94). Person of ordinary skill will understand that steps 92-95 may be performed in any sequence or order.

The next step in the example sequence shown in FIG. 10 is to pulse drain pin with a high voltage; that is, node 42 is raised to ˜50V and then lowered back down to 5V (block 95). In one embodiment, a 2 ms duration pulse having a rise time/fall time of ˜100 μs may be applied. The post-trim current flowing into the drain pin at node 42 may then be measured and compared to the pre-trim current to confirm that the anti-fuse has been properly trimmed.

FIG. 11 is an example flow diagram of a sequence of steps for reading an anti-fuse element in the embodiment of FIG. 6. The read cycle begins with the raising of the Drain pin (node 42) to higher than about 10V (block 110). Next, transistor 71 (N1) of voltage regulator 44 is turned on (block 111), transistor 77 (N3) is turned off (block 112), and transistor 76 (N2) is turned on (block 113). Turning on transistor 76 has the effect of also turning on transistor 78 (P1), thereby turning on isolation unit 45. All of trimming MOSFETs 33a-33n are then turned on (block 114).

At this point a read signal may be applied to the gates of transistors 82a-82n such that a small current (˜several microamperes) is simultaneously pulled through each leg of anti-fuse block 30 (block 115). For example, the read signal coupled to the gates of transistors 82 may be fed from a current mirror to establish the small current flow through transistors 82 for purposes of reading the state of each anti fuse 32. In this configuration, the sources of each of the trimming MOSFETs 33 are essentially connected to ground through a high-impedance. In the event that a particular anti-fuse 32 is programmed, the potential at the source of the associated trimming MOSFET 33 floats up to the difference between the gate-to-source voltage (Vgs) and the threshold voltage (V_t) of the associated trimming MOSFET 33. In other words, the voltage at the source (Vs) of a particular MOSFET 33 associated with an anti-fuse element 32 that has been blown (programmed) is Vs=Vgs−Vt. On the other hand, if a particular anti-fuse 32 remains open (not programmed), then the source of the associated trimming MOSFET 33 is at or near ground potential.

After the read signal has been applied to anti-fuse block 30, the source voltage of each of trimming MOSFETs 33 may be latched (stored) in corresponding latch element 81 (block 116). In one embodiment, latching of the state of each anti-fuse programming element occur when the VDD pin (node 70) crosses 5V. Latch element 81 may comprise any one of a number of well-known latch circuits or devices, e.g., an ordinary Set/Reset (R/S) latch. After the source voltages of each MOSFET 33 have been latched in each of the corresponding latch elements 81, transistor 76 (N2) is turned off, thereby turning off transistor 78 (P1). Transistor 77 (N3) is also turned on. These later steps effectively turn off isolation unit 45, causing anti-fuse block 30 to be isolated from the voltage produced by tap transistor 41 at node 43, thereby transitioning the power IC device back to a normal mode of operation.

Although the present invention has been described in conjunction with specific embodiments, those of ordinary skill in the arts will appreciate that numerous modifications and alterations are well within the scope of the present invention. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims

1-14. (canceled)

15. A method for reading a programmable anti-fuse block of a power integrated circuit (IC) comprising:

providing a first voltage at a common node of the programmable anti-fuse block, the common node being coupled to a plurality of anti-fuses, each anti-fuse having a programmed state;

generating a read signal that turns on a plurality of selector switches, each selector switch being coupled to a corresponding one of the anti-fuses; and

latching a voltage potential at a second node of each selector switch, the voltage potential being representative of the programmed state of each anti-fuse.

16. The method of claim 15 further comprising reading the latched programmed state of each anti-fuse by a controller of the power IC.

17. The method of claim 15 further comprising decoupling the programmable anti-fuse block from the first node.

18. The method of claim 15 wherein each selector switch comprises a field-effect transistor (FET) having a drain coupled to a corresponding one of the anti-fuses, each selector switch also having a gate and a source.

19. The method of claim 15 further comprising applying an external voltage to a pin of the power IC, the pin being coupled to circuitry that lowers the external voltage to the first voltage at a common node.

20. The method of claim 19 wherein the circuitry comprises a tap transistor element.

21. The method of claim 19 wherein the circuitry comprises a level shift transistor.

22. The method of claim 15 wherein the read signal is generated by the controller.