Abstract: A method and a device for monitoring a plurality of parallel-connected semiconductor switches. The method includes subjecting the plurality of semiconductor switches to a heating pulse, in which a predefined load current flows for a predefined period of time in order to achieve a predefined temperature change of the semiconductor switches, a variable of a semiconductor switch to be monitored from the plurality of semiconductor switches being detected both before and after the application of the heating pulse, and a state of the semiconductor switch to be monitored and/or an electronics packaging, which corresponds to the semiconductor switch to be monitored, being ascertained on the basis of a deviation of the change of the at least one variable from a predefined reference value. The method enables a measurement of individual semiconductor switches to be monitored from the plurality of semiconductor switches.

Abstract: An illuminator system for semiconductor chip testing has a rotary plate and a first light source and second light source mounted on the rotary plate. A controller is configured to rotate the rotary plate to provide a desired light output. A light output of the illuminator system is aligned to the desired first or second light source. A first semiconductor chip receives illumination from the desired source. The rotary plate is rotated until the desired light source is aligned to the light output. A quality or characteristic of light emitted by the first light source can be measured, and then the first light source can be adjusted, or an alert can be generated, if the quality or characteristic falls outside of a preconfigured range.

Abstract: A near-field testing method proposed in the present invention includes steps of: in a selected coordinate system, controlling a mover to cause random relative movement of the DUT and the probe to generate multiple random test points, determining one or more postures of the probe, and obtaining the electromagnetic field coefficients of the probe corresponding the postures of the probe respectively; obtaining measured values of the electromagnetic field signals collected by the probes, and obtaining a set of measured values; according to the set of measured values, the electromagnetic field coefficients of the probe, and according to the Lorenz reciprocity theorem in electromagnetism, determining electromagnetic field coefficients of the DUT through convex optimization; obtaining, according to the electromagnetic field coefficients of the DUT, a far field pattern of the DUT or an electric field and/or a magnetic field at any point outside the DUT.

Abstract: A III-N-based vertical transistor includes a III-N substrate, a source, a drain, and a channel comprising a III-N crystal material and extending between the source and the drain. The channel includes at least one sidewall surface aligned ±0.3° with respect to an m-plane of the III-N crystal material. The III-N-based vertical transistor also includes a gate electrically coupled to the at least one sidewall surface of the channel.

Abstract: A pulse receiving circuit constituting a signal transmission device includes a first pulse detector that receives a differential input between a first reception pulse signal, i.e. an internal signal at a secondary winding of a first transformer and a second reception pulse signal, i.e. an internal signal at a secondary winding of a second transformer; a second pulse detector that receives the differential input between the first reception pulse signal and the second reception pulse signal with input polarity reversed to that of the first pulse detector; and a logic unit that generates a reception pulse signal based on output signals of the first and second pulse detectors, respectively.

Abstract: Various embodiments of the present disclosure are directed towards a method for non-destructive inspection of cell etch redeposition. In some embodiments of the method, a grayscale image of a plurality of cells on a wafer is captured. The grayscale image provides a top down view of the cells and, in some embodiments, is captured in situ after etching to form the cells. The cells are identified in the grayscale image to determine non-region of interest (non-ROI) pixels corresponding to the cells. The non-ROI pixels are subtracted from the grayscale image to determine ROI pixels. The ROI pixels are remaining pixels after the subtracting and correspond to material on sidewalls of, and in recesses between, the cells. An amount of etch redeposition on the sidewalls and in the recesses is then scored based on gray levels of the ROI pixels. Further, the wafer is processed based on the score.

Abstract: A measurement probe for producing a test signal for a measurement instrument includes a probe head structured to be connected to at least a first testing point and a second testing point of a Device Under Test (DUT), a current detector in the measurement probe structured to determine a current flowing between the first testing point and the second testing point of the DUT, a first selectable signal path that causes a voltage signal from the first testing point or a voltage signal from the second testing point to be routed to the measurement instrument as a selected voltage test signal, and a second selectable signal path that causes a current signal from an output of the current detector to be routed to the measurement instrument as a selected current test signal. Methods of testing a DUT using the measurement probe are also described, as well as a system for measuring signals from a DUT using the measurement probe.

Abstract: A method for testing LEDs includes: Step 1: providing a wafer including a plurality of LEDs and selecting N LEDs from the plurality of LEDs to form an LED group; Step 2: selecting n LEDs from the LED group, where 1<n<N, and testing the n LEDs at a time to obtain a subgroup optical parameter of the LED group; Step 3: performing the Step 2 on the N LEDs repeatedly and alternately for another n LEDs in the LED group to obtain a plurality of the subgroup optical parameters; and Step 4: obtaining an optical parameter of each of the LEDs in the LED group from the plurality of the subgroup optical parameters.

Abstract: A probe head includes a test board configured to test a reliability of a semiconductor substrate by contacting the semiconductor substrate, a load pusher provided on the test board, the load pusher including a frame, a plurality of elastic structures, and a loader blade, the frame having a penetration region, the plurality of elastic structures extending from an inner surface of the frame within the penetration region and spaced apart from each other along a circumferential direction, the loader blade configured to protrude the test board toward the semiconductor substrate, the loader blade connecting to the frame through the plurality of elastic structures, and a support tensioner configured to support the load pusher.

Abstract: Device under test (DUT) simulation equipment includes: a first circuit board including a first field programmable gate array (FPGA); a second circuit board including a processor; and a power distribution board, wherein the first circuit board is connected to the power distribution board, and the power of the first circuit board is supplied by the power distribution board, wherein the second circuit board is connected to the power distribution board, and the power of the second circuit board is supplied by the power distribution board, wherein when the DUT simulation equipment is connected to a tester to perform testing, the DUT simulation equipment simulates the performance of a DUT providing a response signal after receiving a test signal from the tester, and wherein, in the DUT simulation equipment, only the first circuit board receives the test signal from the tester, and the second circuit board controls the first circuit board by means of a control signal.

Abstract: In one example, an integrated circuit comprises a die. The die has a first surface and a second surface, the second surface opposite to the first surface. The die also includes: a first contact on the first surface and a second contact on the second surface; a through silicon via having a first end and a second end, the first end coupled to the first contact and the second end coupled to the second contact; and a scan cell having a control input, a response input, and a stimulus output, the response input coupled to the first end and the stimulus output coupled to the second end.

Abstract: An electronic detection interface for testing micro photoelectric chips or micro semiconductor chips comprises a substrate structure and a plurality of detection units in array, responsive to the micro photoelectric chips or the micro semiconductor chips. The substrate structure includes a circuit layer, which comprises a plurality of circuit units in array. The detection units are disposed on a surface of the substrate structure, and are corresponded to the circuit units in a respect manner. Each of the detection units includes at least one resilient conductive pillar, which is electrically connected to each of the circuit units. Each of the resilient conductive pillars comprises a non-conductive photoresist and a conductive layer entirely covering the non-conductive photoresist.

Abstract: Embodiments provide a ring oscillator and test method. The ring oscillator includes a first logic gate, a second logic gate, and a switch circuit. The first logic gate is configured to receive a test signal. The second logic gate includes a first NAND gate and a first NOR gate connected in sequence. An output terminal of the second logic gate is connected to an input terminal of the first logic gate, and the second logic gate is configured to receive output of the first logic gate to form a loop. The switch circuit includes a first switch circuit and a second switch circuit. The first switch circuit may be configured to control on/off of a power supply terminal of the first NAND gate and a ground terminal of the first NOR gate. The second switch circuit is configured to control on/off of a ground terminal of the first NAND gate.

Abstract: A method for operating a multi-level bridge power converter of an electrical power system connected to a power grid includes receiving a commanded state for one or more switching devices thereof. The method also includes receiving a gate-emitter voltage of one or more of the switching devices. Further, the method includes comparing, via at least one comparator, the gate-emitter voltage of the one or more switching devices to a reference voltage range corresponding to the commanded state of the one or more switching devices. In addition, the method includes determining an actual state of the one or more switching devices based on the comparison. Thus, the method also includes implementing a control action based on the actual state of the one or more switching devices.

Abstract: The present disclosure relates to the field of design for testability of super-large-scale integrated circuits, and discloses a flexible configurable module (FCM) based chiplet test circuit. The core structure of the circuit is located at an interposer. The test circuit includes FCMs, a control signal configuration module and a test state control module, where the FCM adopts a two-way skew-symmetric structure to implement data transmission in the horizontal direction and the vertical direction; the control signal configuration module is connected to control signals of all the FCMs, so as to control the data transmission directions as well as switch on and switch off states of all the FCMs; and the test state control module controls the shift and update operations of data inside the FCMs and the control signal configuration module.

Abstract: A detection result recording and outputting device of an IC is operable to record and output detection results at different speeds respectively. The device includes a sensing circuit, a decision circuit, a storage circuit, and a control circuit. The sensing circuit detects the variation in a characteristic of a target circuit and generates detection results at a first speed. The decision circuit receives the detection results and generates a trigger signal or changes its level when finding that a detection result satisfies a predetermined condition. The control circuit writes the detection result and subsequent (N?1) detection results into the storage circuit at a second speed according to the trigger signal, and then reads out the detection results from the storage circuit at a third speed and outputs them at a fourth speed. The second speed is not higher than the first speed, but higher than the fourth speed.

Abstract: This document discloses a power leakage sensor for a circuit, comprising: a power switch controller circuit coupled with at least one power switch for the digital circuit, the power switch controller configured to control the at least one power switch, to monitor power supply of the digital circuit, and to perform the following: a. in response to the detecting that the power supply to the circuit is powered on, output a power-off signal to the at least one power switch; and b. in response to the measured power supply metric falling below a threshold in response to the power-off signal, output a power-on signal to the at least one power switch. The power leakage sensor further comprises a frequency counter circuit configured to count a frequency of executing steps a. and b., the frequency indicating a proportion of power leakage in the digital circuit.

Abstract: A probe card with a voltage terminal configured to be coupled to a voltage supply and a current terminal configured to be coupled to a current supply. The voltage terminal and the current terminal are configured to be coupled to an input node of a device under test (DUT) field effect transistor (FET) through probe needles. The probe card has an overlap resistor capacitor (RC) element coupled to the input node. The probe card includes an analog to digital (ADC) voltage capture module configured to be coupled to the input node of the DUT FET and to an output node of the DUT FET through the probe needles. The probe card has a resistive element configured to be coupled to the output node of the DUT FET through the probe needles and to an electrically neutral node and an ADC current capture module coupled in parallel to the resistive element.

Abstract: A method and system are directed to designing a low-dropout regulator (LDO) circuit and using the LDO circuit to detect recycled counterfeit integrated circuits. The LDO circuit includes, in part, a reference path circuit and a stressed path circuit. Each of the reference path circuit and the stressed path circuit is coupled to a control signal that can enable the corresponding path circuit for the LDO. LDO parameters can then be measured while the reference path circuit and the stressed path circuit is enabled respectively. The difference between the LDO parameters measured while the reference path circuit is enabled and while the stressed path circuit is enabled is used to determine if an integrated circuit comprising the LDO circuit is a recycled counterfeit.

Abstract: An electronic component testing apparatus for testing a device under test (DUT) includes: a socket unit that is electrically connected to the DUT; a first wiring board that includes a board opening; and a tester that includes a test head in which the first wiring board is mounted. The socket unit includes a first socket that faces a first main surface of the DUT and is electrically connected to the DUT and the first wiring board. The second socket that is exposed from the first wiring board through the board opening, contacts a second main surface of the DUT on a side opposite to the first main surface, and includes: a base that contacts the second main surface; and a test antenna unit that is electrically connected to the tester and faces a device antenna unit of the DUT.

Abstract: A system for calibration management is described. The system includes at least one measurement instrument for testing a device under test and a monitoring device. The monitoring device is connected with the measurement instrument. The monitoring device collects parameters from the measurement instrument during the testing. The monitoring device creates a calibration fingerprint based on the parameters collected, which is indicative of the calibration status of the measurement instrument. The system includes an interface via which information based on the calibration fingerprint is outputted, indicating if a new calibration of the measurement instrument is necessary or not. Further, a method of managing calibration of a measurement instrument is described.

Abstract: An integrated circuit includes first to nth metal layers vertically stacked on a substrate, and a test circuit outputting a test result signal according to a characteristic of each of the first to nth metal layers. The test circuit includes first to nth test circuits for generating a plurality of clock signals. Each clock signal of the plurality of clock signal has a frequency according to a characteristic of a corresponding metal layer among the first to nth metal layers, and n is a natural number.

Abstract: The present application provides a testing device. The testing device includes: a box, a pressing mechanism, a sliding mechanism, a transmission mechanism, and first clamping mechanisms. The pressing mechanism is located inside the box. A gap between the pressing mechanism and the first side of the box is used to place substrates to be tested. The pressing mechanism is slidably connected to the sliding mechanism. The transmission mechanism is connected to the pressing mechanism to drive the pressing mechanism to move. Each first clamping mechanism is used to hold one of the substrates to be tested.

Abstract: The present application relates to a test circuit, comprising: M test units, each test unit having a first terminal and a second terminal, a first terminal of each test unit being connected to a power wire, a second terminal of each test unit being connected to a ground wire, M being a positive integer; each test unit comprises a TDDB test component, a switch, and a control circuit; the TDDB test component has a first equivalent resistance before being broken down, the TDDB test component has a second equivalent resistance after being broken down, and the first equivalent resistance is greater than the second equivalent resistance.

Abstract: Aspects described herein include a method of fabricating an optical component, the optical component, and a method of operating the optical component. A method includes electrically coupling a first laser channel and a second laser channel of a laser die to different electrical leads and testing (i) a first optical coupling of the first laser channel and a second optical coupling of the second laser channel or (ii) a first spectral performance of the first laser channel and a second spectral performance of the second laser channel. The method also includes optically aligning an optical fiber with the first laser channel and designating the second laser channel as a heater element for the first laser channel based at least in part on (i) the first optical coupling being greater than the second optical coupling or (ii) the first spectral performance relative to the second spectral performance.

Abstract: A test and measurement device, including a first input structured to receive a first voltage from a first conductor of a first triaxial cable, a second input structured to receive a second voltage from a second conductor of the first triaxial cable or a second triaxial cable, circuitry configured to change modes based on the first voltage and the second voltage; and an output structured to output a signal.

Abstract: The touch sensor includes a touch detection area with at least a part of a curved area having a curved edge. In the touch detection area, a plurality of first electrodes and second electrodes disposed side by side in a first direction and in a second direction are disposed. A plurality of first electrodes disposed side by side in the first direction are connected to each other. A plurality of second electrodes disposed side by side in the second direction are connected to each other. In the curved area, distances between the plurality of first electrodes and the second electrodes in the first direction gradually change in the second direction.

Abstract: Embodiments of the present disclosure relate to a monitoring circuit and a semiconductor device, and particularly, to a monitoring circuit including an oscillation circuit configured to generate an oscillation signal having a rising characteristic or a falling characteristic according to a threshold voltage level and a counter configured to count the number of rises or the number of falls of the oscillation signal, and a semiconductor device including the monitoring circuit.

Abstract: A burn-in resilient integrated circuit is provided. The burn-in resilient integrated circuit includes an inverter chain and a plurality of inverter circuits on the inverter chain. The burn-in resilient integrated circuit also includes a loop providing an electrical connection from an output of the inverter chain to an input of the inverter chain. The loop is selectable in accordance with a burn-in operation.

Abstract: A method for operating a multi-level bridge power converter includes arranging a plurality of switching devices including at least four inner switching devices and at least two outer switching devices in an active neutral point clamped topology. The method also includes determining whether any of the switching devices is experiencing a failure condition by implementing a failure detection algorithm. The failure detection algorithm includes generating a blocking state logic signal by comparing a switching device voltage and a threshold reference voltage for each of the switching devices, determining an expected voltage blocking state for each of the switching devices based on gate drive signals of the switching devices and an output current direction, and detecting whether a failure condition is present in any of the switching devices based on the blocking state logic signals and the expected voltage blocking states of the switching devices.

Abstract: The present disclosure relates to a semiconductor device, and a test apparatus and method thereof, capable of accurately detecting a defect by using a plurality of resistor circuits in a test process. The test apparatus of a semiconductor device according to an aspect of the present disclosure may include semiconductor chips each including an external resistor circuit disposed to be dispersed along an outer region of a chip and an internal resistor circuit disposed in an inner region of the chip in order to test cracks, and test equipment that drives the external resistor circuit and the internal resistor circuit and compares an output of the external resistor circuit with an output of the internal resistor circuit to detect whether a defect occurs in each of the semiconductor chips.

Abstract: A test kit for testing a device under test (DUT) includes a socket structure for containing the DUT, and a plunger assembly detachably coupled with the socket structure. The plunger assembly includes a multi-layered structure having at least an interposer substrate sandwiched by a top socket and a nest.

Abstract: An optical inspection apparatus includes a stage that supports a target substrate, the target substrate including a plurality of light emitting elements, a jig that applies an electrical signal to the target substrate, the jig including a regulation resistor, a microscope that generates magnified image data of the target substrate, a camera that captures the magnified image data to generate a color image of the target substrate, and an optical measurement unit that captures the magnified image data of the target substrate to generate a spectrum image and measure optical characteristics of the target substrate.

Abstract: A current detection circuit includes normally-on-type and a first normally-off-type switching elements with main current paths that are connected in series, and a second normally-off-type switching element that has a source and a gate that are connected to a source and a gate of the first normally-off-type switching element and a drain that is connected to a constant current source, and executes a division process by using drain voltages of the two normally-off-type switching elements.

Abstract: An apparatus for measuring a device current of a device under test (DUT) includes a first circuit including a first terminal for coupling to a first connection terminal of the DUT. The first circuit is configured to supply a first test voltage for the first terminal and to output a first output voltage sensed at the first terminal. The apparatus further includes a second circuit having a second terminal for coupling to a second connection terminal of the DUT. The second circuit is configured to supply a second test voltage for the second terminal and to output a second output voltage sensed at the second terminal. The apparatus further includes a third circuit configured to determine the device current of the DUT based on the first output voltage, the second output voltage, the first test voltage and the second test voltage. The first circuit and the second circuit are identical.

Abstract: Various approaches to can be used to interrogate a surface such as a surface of a layered semiconductor structure on a semiconductor wafer. Certain approaches employ Second Harmonic Generation and in some cases may utilize pump and probe radiation. Other approaches involve determining current flow from a sample illuminated with radiation.

Abstract: A display panel, a display method thereof, and a display equipment are provided. The display panel includes a flat display part and a bending display part. A first thin film transistor is in the flat display part, and a second thin film transistor is in the bending display part. A ratio of a channel width to a channel length of an active layer of the first thin film transistor is greater than a ratio of a channel width to a channel length of an active layer of the second thin film transistor of the second thin film transistor. The display method includes a step of making a luminescence intensity of the bending display part greater than a luminescence intensity of the flat display part. The display equipment includes the display panel mentioned above.

Abstract: A test circuit and a method for testing an integrated circuit are provided. The integrated circuit includes a test circuit. The test circuit includes a conductive track extending over at least a portion of the periphery of the integrated circuit, at least one component and an activation circuit adapted to deviating an input data signal into the conductive track during a test mode, and to transmitting the input data signal to the at least one component during a normal operating mode.

Abstract: An electronic component testing apparatus is used for testing a device under test (DUT). The electronic component testing apparatus includes: a socket unit that is electrically connected to the DUT; a first wiring board; and a tester that comprises a test head in which the first wiring board is mounted. The socket unit includes a first socket and a second socket. The second socket includes a base and a test antenna unit. The tester tests the DUT by transmitting and receiving radio waves between a device antenna unit of the DUT and the test antenna unit while the DUT is electrically connected to the first socket and the first socket is electrically connected to the test head through the second socket.

Abstract: A circuit and method for detecting crack damage of a die are provided. The circuit comprises: a test circuit located within a seal ring of the die for outputting a pulse detection signal; a crack detection loop arranged outside a guard ring of an internal processing circuit of the die, having an input end connected to an output end of the test circuit and an output end connected to an output pin of the die; and a relay driving unit arranged between the input end and output end for increasing a capability of transmission of the pulse detection signal, wherein the seal ring surrounds the whole die; in a test mode, the test circuit outputs the pulse detection signal to the crack detection loop, and a test machine determines whether the die is damaged by a crack by reading a signal on the output pin of the die.

Abstract: A timer circuit includes a plurality of n-type field effect transistors (NFETs) powered by a current source, a plurality of electromigration detection elements each electrically connected to a respective NFET of the plurality of NFETs, and a read-out circuit electrically connected to the plurality of electromigration detection elements to meter usage of each of the NFETs.

Abstract: A power supply for supplying a power to a heating mechanism used for heating a measurement target that emits a measurement signal includes an input device configured to output an input signal that reflects a control signal in a differentiable periodic waveform having a frequency of 1 kHz or less. The power supply includes a switching amplifier configured to amplify the input signal from the input device and output the amplified signal.

Abstract: An input capacitance measurement circuit includes a transformer, a first capacitor, a second capacitor, and a third capacitor. A primary wire of the transformer has a first end provided so as to be connectable to an anode of the semiconductor device. The primary wire of the transformer has a second end connected to a first end of the first capacitor. A secondary wire of the transformer has a first end provided so as to be connectable to a cathode of the semiconductor device. The secondary wire of the transformer has a second end connected to a first end of the second capacitor. The third capacitor has a first end provided so as to be connectable to the cathode of the semiconductor device. A second end of the first capacitor, a second end of the second capacitor, and a second end of the third capacitor are electrically connected to each other.

Abstract: Techniques and mechanisms for providing interconnected circuitry of an integrated circuit (IC) die stack. In an embodiment, first integrated circuitry of a first IC die is configured to couple, via a first interconnects of the first IC die, to second integrated circuitry of a second IC die. When the first IC die and the second IC die are coupled to one another, second interconnects of the first IC die are further coupled to the second integrated circuitry, wherein the second interconnects are coupled to each of two opposite sides of the first IC die. In another embodiment, the second integrated circuitry includes processor logic, and the first integrated circuitry is configured to cache data for access by the processor logic. In another embodiment, the first integrated circuitry includes a power delivery circuit and an on-package input-output interface to cache data for access by the processor logic at higher bandwidth with lower power consumption.

Abstract: A method for detecting errors or malfunctions in electrical or electronic components of circuits, wherein each of the circuits is located on a circuit board and wherein a plurality of circuit boards border one another on a circuit board panel, includes populating each of the circuit boards of the circuit board panel with electrical or electronic components corresponding to the circuits; for each of the analog, electrical or electronic components used for the construction of the circuits, placing a corresponding test component in an edge region of the circuit board panel; providing the analog, electrical or electronic test components placed in the edge region of the circuit board panel with test points; and checking for the correct function value and/or the correct poling of the analog, electrical or electronic test components provided with test points and located in the edge region of the circuit board panel.

Abstract: Various embodiments of the present disclosure are directed towards a method for non-destructive inspection of cell etch redeposition. In some embodiments of the method, a grayscale image of a plurality of cells on a wafer is captured. The grayscale image provides a top down view of the cells and, in some embodiments, is captured in situ after etching to form the cells. The cells are identified in the grayscale image to determine non-region of interest (non-ROI) pixels corresponding to the cells. The non-ROI pixels are subtracted from the grayscale image to determine ROI pixels. The ROI pixels are remaining pixels after the subtracting and correspond to material on sidewalls of, and in recesses between, the cells. An amount of etch redeposition on the sidewalls and in the recesses is then scored based on gray levels of the ROI pixels. Further, the wafer is processed based on the score.

Abstract: Systems, apparatuses, and methods related to a printed circuit board (PCB) with a plurality of layers are described. An edge connector may be formed on an end of the PCB substrate and may include contact pins on an outer layer of the plurality of layers. The edge connector may also include an intra-pair coupling block disposed on one or more interior layers such that at least a portion of the intra-pair coupling block is colinear with at least one contact pin on the outer layer. The electronic device may also include at least one integrated circuit on the PCB and electrically connected to the contact pins. The intra-pair coupling component may induce coupling of signals carried by the contact pins.

Abstract: A method of treatment of an electronic circuit including at a location at least one electrically-conductive test pad having a first exposed surface. The method includes the at least partial etching of the test pad from the first surface, and the forming on the electronic circuit of an interconnection level covering said location and including, on the side opposite to said location, a second planar surface adapted for the performing of a hybrid molecular bonding.

Abstract: As a semiconductor device is miniaturized, a scribe area on a wafer also tends to decrease. Accordingly, it is necessary to reduce the size of a TEG arranged in the scribe area, and efficiently arrange an electrode pad for probe contact. Therefore, it is necessary to associate probes and the efficient layout of the electrode pad. The purpose of the present invention is to provide a technique for associating probes and the layout of the electrode pads of a TEG so as to facilitate the evaluation of electrical characteristics. According to an evaluation apparatus for a semiconductor device of the present invention, the above described problems can be solved by providing a plurality of probes arranged in a fan shape or probes manufactured by Micro Electro Mechanical Systems (MEMS) technology.

Abstract: Methods and systems for selectively compressing data lines of a memory device in selective compression circuitry. The selective compression circuitry receives multiple data lines and compression circuitry that selectively compresses inputs. The selective compression circuitry also includes control circuitry to receive data over via the data lines. The control circuitry, when in a compressed mode, transmits data from each of the data lines to the compression circuitry. Alternatively, in an uncompressed mode, the control circuitry transmits data from a first subset of the data lines to the compression circuitry while blocking data from a second subset of the data lines from being transmitted to the compression circuitry.