Test Of Semiconductor Device Patents (Class 324/762.01)
  • Patent number: 11215513
    Abstract: A semiconductor device includes a plurality of active area structures. One or more active devices include portions of the plurality of active area structures. A metal layer is formed on the plurality of active area structures and separated from the one or more active devices by one or more dummy gate layers. The metal layer is configured to measure, due to a change of resistance in the metal layer, a temperature of the plurality of active area structures.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: January 4, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Zeng Kang, Wen-Shen Chou, Yung-Chow Peng
  • Patent number: 11193218
    Abstract: A sputtering equipment configured to grow a gallium oxide film on a substrate is proposed, and the sputtering equipment may include: a chamber; a stage located in the chamber and configured to secure the substrate thereon; a gallium target located in the chamber and including gallium elements; a first power supply configured to apply voltage to the gallium target; and an oxygen element supplier configured to supply oxygen elements into the chamber.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: December 7, 2021
    Assignee: DENSO CORPORATION
    Inventor: Shuhei Ichikawa
  • Patent number: 11187745
    Abstract: An example method of stabilizing a voltage at a device under test (DUT) includes identifying one or more characteristics of a deviation in a first voltage to appear at the DUT. The deviation may result from a digital signal and a concomitant transient current in the DUT. The digital signal may be part of a test flow to be sent over one or more test channels of automatic test equipment (ATE) to the DUT. The one or more characteristics may be identified prior to sending the test flow to the DUT. The method also includes generating a second voltage to apply to the DUT. The second voltage may be based on the one or more characteristics and being shaped to reduce the deviation.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: November 30, 2021
    Assignee: TERADYNE, INC.
    Inventors: Jason A. Messier, Bryce M. Wynn, Anja Deric
  • Patent number: 11169201
    Abstract: A method to establish a degradation state of electrical connections in a power semiconductor device comprising: measuring at least two voltage drop values under two respective current values for the same temperature value. The two current values are strictly different or the measurements are made under two distinct gate levels of a transistor; saving the measured values as calibration data; monitoring operational conditions of said power semiconductor device; measuring at least two voltage drop values under respective same current values as preceding, and at two respective moments during which the monitored operational conditions corresponding to two respective predefined sets of criteria related to states of operation and to a common temperature; saving the at least two values as operational data; calculating a numerical index in a manner to estimate a degradation state of said power semiconductor device.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: November 9, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Nicolas Degrenne, Julio Cezar Brandelero
  • Patent number: 11137910
    Abstract: Fast Address to Sector Number/Offset Translation to Support Odd Sector Size Testing. A machine-implemented method of determining a sector number from a given address for testing a solid state drive (SSD), wherein the SSD sector size is not an integral power of 2, includes determining an approximate sector size as the closest power of 2 less than the sector size and determining an error factor as the ratio of the approximate sector size divided by the sector size. The method also includes forming the sector number by shifting the address right by the base 2 logarithm of the approximate sector size.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: October 5, 2021
    Assignee: Advantest Corporation
    Inventor: Duane Champoux
  • Patent number: 11119146
    Abstract: Examples described herein generally relate to testing of bonded wafers and structures implemented for such testing. In an example method, power is applied to a first pad on a stack of bonded wafers. A wafer of the stack includes a process control monitor (PCM) region that includes structure regions. Each structure region is a device under test region, dummy region, and/or chain interconnect region (CIR). The stack includes a serpentine chain test structure (SCTS) electrically connected between first and second metal features in the wafer in first and second CIRs, respectively, in the PCM region. The SCTS includes segments, one or more of which are disposed between neighboring structure regions in the PCM region that are not the first and second CIRs. A signal is detected from a second pad on the stack. The first and second pads are electrically connected to the first and second metal features, respectively.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: September 14, 2021
    Assignee: XILINX, INC.
    Inventors: Nui Chong, Yan Wang, Hui-Wen Lin
  • Patent number: 11092639
    Abstract: A display device and an inspection method of the display device includes: a display area including pixels and data lines; and a non-display area located around the display area and including an inspection unit, in which a first data line includes a first inspection line located in the inspection unit, a second data line adjacent to the first data line includes a second inspection line located in the inspection unit, the first inspection line extends in a second direction different from the first direction, the second inspection line includes a first portion extending in the second direction, a second portion bent toward the first inspection line from the first portion and then extending toward the first inspection line, and a third portion bent from the second portion and extending in parallel with the first inspection line, and end portions of the first and second inspection lines are spaced apart.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: August 17, 2021
    Inventors: Soo Hong Cheon, Dong Hee Shin
  • Patent number: 11085959
    Abstract: A system for testing wireless communication equipment which includes a beamforming antenna, the system comprising: a probe for coupling an antenna element of the beamforming antenna of the wireless communication equipment to be tested to a test and measurement unit; and a lid configured to cover the beamforming antenna, wherein the lid is provided with a port for receiving the probe, such that the probe couples to the antenna element.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: August 10, 2021
    Assignee: VIAVI SOLUTIONS INC.
    Inventors: Charalampos Kalatzis, Adrian Jones
  • Patent number: 11081411
    Abstract: A semiconductor structure (100; 200) is provided.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: August 3, 2021
    Assignee: X-FAB SEMICONDUCTOR FOUNDRIES GMBH
    Inventor: Matthias Pittner
  • Patent number: 11063588
    Abstract: A reset device includes a power-on reset (POR) circuit configured to output a reset signal to reset a circuit part to an initial state when supply voltage is lower than a threshold level, a first switch provided in a path connecting a first line to supply the supply voltage to the circuit part and a second line to supply the supply voltage to the POR circuit, a second switch provided in a path connecting a signal line of the circuit part and the second line, and a control circuit configured to turn on the first switch and turn off the second switch in a normal mode, and to turn off the first switch and turn on the second switch in a test mode. The control circuit turns on the first switch and turns off the second switch in response to the reset signal being output from the POR circuit.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: July 13, 2021
    Assignee: ALPS ALPINE CO., LTD.
    Inventors: Hiroki Sato, Tomoyuki Sawataishi, Akira Shoji, Takehiko Kan
  • Patent number: 11011438
    Abstract: A display device is disclosed. In one aspect, the display device includes a display area configured to display an image, a peripheral area neighboring the display area, and at least one test element group (TEG) including a test thin film transistor (TFT) formed in the peripheral area and a plurality of test pads electrically connected to the test TFT. The display device also includes first to third dummy circuits separated from the test TFT, each of the first to third dummy circuits including a plurality of first dummy semiconductor layers and a plurality of first dummy gate electrodes overlapping at least a portion of the first dummy semiconductor layers in the depth dimension of the display device.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: May 18, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Moo Soon Ko, Jeong-Soo Lee, Jung Hwa Kim
  • Patent number: 11009542
    Abstract: A thyristor valve test system based on cooperation of logic functions of software, wherein the test system comprises: a thyristor valve (5) to be tested, a VBE (3) and a tester (4), and the VBE (3) has a dedicated test mode, the tester (4) provides three steps for each test item. The thyristor valve (5) to be tested and the VBE (3) are connected by optical fibers (1), and the thyristor valve (5) to be tested and the tester (4) are connected by cables (2), and there is no connection between the VBE (3) and the tester (4).
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: May 18, 2021
    Assignees: NR ELECTRIC CO., LTD, NR ENGINEERING CO., LTD
    Inventors: Fan Yang, Lei Liu, Xiang Zhang, Chen Zhou, Weiming Pan, Taixun Fang
  • Patent number: 11004530
    Abstract: Embodiments generally relate to integrated circuit devices having through silicon vias (TSVs). In one embodiment, an integrated circuit (IC) device includes a field of TSVs and an address decoder that selectably couples at least one of the TSVs to at least one of a test input and a test evaluation circuit. In another embodiment, a method includes selecting one or more TSVs from a field of TSVs in at least one IC device, and coupling each selected TSV to at least one of a test input and a test evaluation circuit.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: May 11, 2021
    Assignee: Rambus Inc.
    Inventors: Thomas Vogelsang, William Ng, Frederick A. Ware
  • Patent number: 10989664
    Abstract: The disclosed technology generally relates to characterization of semiconductor structures, and more particularly to optical characterization of high-k dielectric materials. A method includes providing a semiconductor structure comprising a semiconductor and a high-k dielectric layer formed over the semiconductor, wherein the dielectric layer has electron traps formed therein. The method additionally includes at least partially transmitting an incident light having an incident energy through the high-k dielectric layer and at least partially absorbing the incident light in the semiconductor. The method additionally includes measuring a nonlinear optical spectrum resulting from the light having the energy different from the incident energy, the nonlinear optical spectrum having a first region and a second region, wherein the first region changes at a different rate in intensity compared to the second region.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: April 27, 2021
    Assignee: California Institute of Technology
    Inventors: Philippe C. Adell, Harry A. Atwater
  • Patent number: 10970627
    Abstract: Some embodiments provide a three-dimensional (3D) circuit structure that has two or more vertically stacked bonded layers with a machine-trained network on at least one bonded layer. As described above, each bonded layer can be an IC die or an IC wafer in some embodiments with different embodiments encompassing different combinations of wafers and dies for the different bonded layers. The machine-trained network in some embodiments includes several stages of machine-trained processing nodes with routing fabric that supplies the outputs of earlier stage nodes to drive the inputs of later stage nodes. In some embodiments, the machine-trained network is a neural network and the processing nodes are neurons of the neural network. In some embodiments, one or more parameters associated with each processing node (e.g., each neuron) is defined through machine-trained processes that define the values of these parameters in order to allow the machine-trained network (e.g.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: April 6, 2021
    Assignee: Xcelsis Corporation
    Inventors: Steven L. Teig, Kenneth Duong, Javier DeLaCruz
  • Patent number: 10971042
    Abstract: Disclosed are a reliability test fixture and an online test device for a flexible display component. The fixture comprises a support and a rotating shaft rotatably mounted on the support. An engagement recess for fixing a flexible display component is provided in an axial direction on the surface of the rotating shaft. A test module used to detect an electrical parameter of an internal circuit of the flexible display component is disposed inside the rotating shaft. The test module has a test contact for electrically connecting to the flexible display component. During a test, the flexible display component is fixed in the engagement recess and is electrically connected to the test module.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: April 6, 2021
    Assignee: Kunshan New Flat Panel Disp. Tech. Center Co., Ltd
    Inventors: Jingxun Zhao, Sheng Gao, Bo Yuan, Xiuqi Huang
  • Patent number: 10972693
    Abstract: An image sensor and an image processing system including the same are provided. The image sensor includes a pixel array including a plurality of pixels each connected to one of first through m-th column lines to output a pixel signal, where “m” is an integer of at least 2; analog-to-digital converters each configured to receive the pixel signal corresponding to one of the first through m-th column lines, to compare the pixel signal with a ramp signal, and to convert the pixel signal to a digital pixel signal; and a blocking circuit connected to an input terminal of at least one of the analog-to-digital converters to block an influence of an operation of others among the analog-to-digital converters.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: April 6, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae Hong Kim, Seung Hyun Lim, Han Kook Cho, Dong Hun Lee, Seog Heon Ham
  • Patent number: 10955451
    Abstract: A testing device includes a testing socket, a first transmission medium and a second transmission medium. The testing socket defines a radiation space. The first transmission medium is disposed in the radiation space of the testing socket. The first transmission medium is configured for supporting a device under test (DUT). The second transmission medium is disposed in the radiation space of the testing socket.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: March 23, 2021
    Assignee: ASE TEST, INC.
    Inventors: Yen-Chun Wang, Hung-Jen Huang, Chen-Kuo Chu, I-Chun Liu
  • Patent number: 10951199
    Abstract: A timing data acquisition device includes a data signal generator, which is configured to generate a plurality of data signals by repeatedly delaying a first periodic timing signal in increments of a first delay value, and a clock signal generator, which is configured to generate a plurality of clock signals by repeatedly delaying a second periodic timing signal in increments of a second delay value exceeding the first delay value. A plurality of D flip-flops are also provided. The flip-flops have: (i) data terminals responsive to respective ones of the plurality of data signals, and (ii) clock terminals responsive to respective ones of the plurality of clock signals.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: March 16, 2021
    Inventors: Yeonho Jung, Mijoung Kim, Jekyun Ryu
  • Patent number: 10930363
    Abstract: Disclosed herein is an apparatus that includes a first semiconductor chip having a plurality of pad electrodes and a plurality of first latch circuits assigned to an associated one of the pad electrodes, a second semiconductor chip having a plurality of TSVs each electrically connected to an associated one of the pad electrodes and a plurality of second latch circuits assigned to an associated one of the TSVs, and a training circuit configured to perform a training operation on a signal path including the selected one of the pad electrodes and the selected one of the TSVs. The training circuit is configured to activate a fail signal when the signal path is determined to be defective. The fail signal is stored in the selected one of the first latch circuits and the selected one of the second latch circuits.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: February 23, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Naohisa Nishioka
  • Patent number: 10908182
    Abstract: An electrical connecting apparatus includes a contact unit provided on a substrate to contact an electrode terminal of a test subject in response to receipt of a load. The contact unit includes multiple plate-like members stacked in the thickness directions of the plate-like members and supported on the substrate in such a manner that a contact surface formed at an end surface of each of the plate-like members contacts a wiring pattern on the substrate. At least some of the multiple plate-like members are contacts including a base, and an arm having one end supported by the base and an opposite end where a tip portion to contact the electrode terminal is formed. The arm has a surface to contact a surface of an adjacent one of the plate-like members to form a conductive path connecting the tip portion and the wiring pattern through the adjacent plate-like member.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: February 2, 2021
    Assignee: KABUSHIKI KAISHA NIHON MICRONICS
    Inventor: Eichi Osato
  • Patent number: 10868642
    Abstract: A system for near-field measurement of a device under test in a far-field environment is provided. The system comprises a communication unit adapted to establish a far-field connection with the device under test. The system further comprises a measuring unit adapted to measure a magnitude and a phase of at least two field components. Moreover, the system comprises a processing unit adapted to perform far-field to near-field and/or near-field to near-field transformation of the field components in order to calculate field components at a specific surface in the near-field of the device under test.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: December 15, 2020
    Assignee: ROHDE & SCHWARZ GMBH & CO. KG
    Inventors: Niels Petrovic, Jose Fortes, Edwin Menzel
  • Patent number: 10862192
    Abstract: A radio frequency (RF) loopback substrate or printed circuit board (PCB) which contains receive and transmit antennas located on the bottom of the loopback substrate which are aligned with the complementary transmit and receive antennas on an antenna on package (AOP) device under test. The loopback substrate receive and transmit antennas are coupled to each other. The device under test contacts are driven by a conventional tester, which causes RF circuitry in the integrated circuit to drive an AOP transmit antenna. The corresponding loopback substrate receive antenna receives the RF signal from the AOP transmit antenna and provides it to the loopback substrate transmit antennas. The integrated circuit package AOP receive antennas then receive the RF signals from the loopback substrate transmit antennas. The signals at the integrated circuit package AOP receive antennas are monitored through the integrated circuit contacts to monitor the received RF signals.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: December 8, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Meysam Moallem, Guor-Chaur Jung, Brian P. Ginsburg
  • Patent number: 10847849
    Abstract: An inspection method of an electrical storage device includes: setting a pseudo parasitic resistance value to be small in a case where a power storage capacity of the electrical storage device is large, while setting the pseudo parasitic resistance value to be large in the case where the power storage capacity is small; in a state where the pseudo parasitic resistance value is set, acquiring a current value after convergence of a current flowing through a circuit such that the circuit is formed by connecting an external power source to the charged electrical storage device in a direction where a voltage is applied thereto; and determining quality of the electrical storage device based on the current value.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: November 24, 2020
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Takeshi Goto, Kiwamu Kobayashi
  • Patent number: 10768238
    Abstract: A circuit is formed by connecting an external power source to a charged electrical storage device so that a polarity of a voltage of the external power source is reverse to a polarity of a voltage of the charged electrical storage device, and the voltage of the external power source is adjusted so that a current does not flow right after the connection. Then, current measurement to acquire a current value after convergence of the current flowing through the circuit due to a voltage drop of the electrical storage device and quality determination based on the current value after convergence are performed. In the current measurement, resistance measurement to actually measure a circuit resistance and prediction to predict a convergence timing of the current based on the actually measured circuit resistance are performed. The current value is acquired when a predicted convergence timing comes.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: September 8, 2020
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Takeshi Goto, Kiwamu Kobayashi
  • Patent number: 10760961
    Abstract: The present invention relates to a method for testing a retinal implant. After an implantable device for interfacing with retinal cells is provided, an external stimulus is applied to the implantable device so that the implantable device transmits a first pulse to a processing device through a wireless interface. When a conversion unit is controlled to gradually decrease an output voltage until the implantable device outputs an output voltage lower than a reference voltage, the implantable device transmits a signal different from the first pulse to the processing device through the wireless interface. The processing device determines a current value of a pixel unit according to a time difference between the first pulse and the signal.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: September 1, 2020
    Assignee: IRIDIUM MEDICAL TECHNOLOGY CO., LTD.
    Inventors: Long-Sheng Fan, Hsin Chen, Yung-Chan Chen
  • Patent number: 10733922
    Abstract: A display device includes: a substrate; pixels provided in a display area of the substrate; signal lines provided on the substrate and connected to the pixels; and a pad portion provided in a peripheral area and including pads. The signal lines include a first crack detecting line provided in the peripheral area and connected to a first test voltage pad, first data lines including first ends connected to the first crack detecting line through corresponding first transistors and second ends connected to corresponding pixels from among the pixels, and first connecting wires for connecting the first data lines and pads corresponding to the first data lines from among the pads, and the first connecting wires are provided on one layer from among at least two layers.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: August 4, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jong Won Park, Hyun Woong Kim
  • Patent number: 10725105
    Abstract: Disclosed is a test and measurement switch matrix. The test and measurement switch matrix includes a solid state switch to couple a test signal from a Device Under Test (DUT) to a test system. The solid state switch has a dual tee guard arrangement providing low leakage when off. The solid state switch also includes an optically coupled drive, which further improves isolation and reduces undesirable charge injection when changing switch states.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: July 28, 2020
    Assignee: Keithley Instruments, LLC
    Inventors: Matthew Holtz, James Niemann, Martin Rice
  • Patent number: 10712390
    Abstract: During scan testing a voltage regulator is programmed to supply a first voltage to logic under test during a shift portion of the scan test, a second voltage during a first portion of a capture portion of the scan test and at least a third voltage during a second portion of the capture portion of the scan test. The availability of a programmable voltage regulator during shift and capture portions of scan testing allows a less stressful voltage to be used during a shift portion of the scan test to reduce shift failures and allows various voltages to be used during capture portions of the scan testing as a surrogate for testing at different temperatures and to provide more flexibility in testing margins.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: July 14, 2020
    Assignee: Silicon Laboratories Inc.
    Inventor: Vivek Sarda
  • Patent number: 10703395
    Abstract: The invention relates to a device and a method for monitoring an electric network in a rail vehicle. The electric network includes at least one power converter, at least one permanent magnet machine, and at least one first phase line for the electrical connection of the at least one power converter and the at least one permanent magnet machine. The first phase line is interrupted. A potential difference is determined between a machine-side part of the first phase line and a reference potential and a potential-difference-dependent variable, wherein a speed of the permanent magnet machine and, as a function of the speed, a speed-dependent reference variable are determined. A deviation of the potential-difference-dependent variable from the speed-dependent reference variable is determined, wherein a network fault is detected if the deviation is greater than a predetermined threshold value.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: July 7, 2020
    Assignee: Bombardier Transportation GmbH
    Inventors: Fabian Streiff, Gerhard Isepponi
  • Patent number: 10699970
    Abstract: An extension of conventional IC fabrication processes to include some of the concepts of flip-chip assemblies while producing a final “non-flip chip” circuit structure suitable for conventional packaging or for direct usage by customers. Multiple IC dies are fabricated on a semiconductor wafer in a conventional fashion, solder bumped or the like, and singulated. The singulated dies, which may be of different sizes and functionality, are then flip-chip assembled onto a single tile substrate of thin-film material which has been patterned with vias, peripheral connection pads, and one or more ground planes. Once dies are flip-chip mounted to the thin-film tile, all of the dies on the entire tile may be probed using automated testing equipment. Sets of dies of different functionality may be tested as a system or subsystem. Once test probing is complete, the dies (or sets of dies) and tile are singulated into die/tile assemblies.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: June 30, 2020
    Assignee: pSemi Corporation
    Inventors: Mark Moffat, Andrew Christie, Duncan Pilgrim, Ronald Eugene Reedy
  • Patent number: 10678438
    Abstract: A scheduler of a memory system is provided. The scheduler may include a pattern storage part and a pattern selector. The pattern storage part may have a plurality of storage patterns, each of the storage patterns provide for a process sequence for a plurality of instructions. The pattern selector may be configured to select one of the plurality of storage patterns in the pattern storage part and generate a schedule such that external instructions are executed in the process sequence set by the selected storage pattern.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: June 9, 2020
    Assignee: SK hynix Inc.
    Inventors: Donggun Kim, Jung Hyun Kwon
  • Patent number: 10656214
    Abstract: A circuit is formed by connecting an external power source to a charged electrical storage device so that a polarity of a voltage of the external power source is reverse to a polarity of a voltage of the charged electrical storage device, and the voltage of the external power source is adjusted so that a current does not flow right after the connection. Then, current measurement to acquire a current value after convergence of the current flowing through the circuit due to a voltage drop of the electrical storage device and quality determination based on the current value after convergence are performed. In the current measurement, resistance measurement to actually measure a circuit resistance and prediction to predict a convergence timing of the current based on the actually measured circuit resistance are performed. The current value is acquired when a predicted convergence timing comes.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: May 19, 2020
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Takeshi Goto, Kiwamu Kobayashi
  • Patent number: 10650198
    Abstract: The present invention provides a method and an apparatus for detecting anti-skimming magnetic interference, wherein the method comprises the steps of: S1: generating an original magnetic strip signal; acquiring an interfered magnetic strip signal by combining the original magnetic strip signal and an interference signal of an electromagnetic interference source to be tested; S2: decoding the interfered magnetic strip signal to obtain a decoded parameter; and S3: determining whether an original magnetic strip parameter is consistent with the decoded parameter; if so, obtaining a first test result that the electromagnetic interference source is unqualified to satisfy a magnetic card reading device's requirement for electromagnetic interference; otherwise, obtaining a second test result that the electromagnetic interference source is qualified to satisfy the magnetic card reading device's requirement for electromagnetic interference whereby security of the magnetic card reading device can be enhanced and the mag
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: May 12, 2020
    Assignees: GRG BANKING EQUIPMENT CO., LTD., GRG BANKING IT CO., LTD.
    Inventors: Lixian Shangguan, Wenchuan Gong, Xiaofeng Jin
  • Patent number: 10613955
    Abstract: A system includes test control circuitry in parallel with power control circuitry. The power control circuitry enables a core processor and memory interface drivers responsive to a reset. The test control circuitry can enable the memory interface drivers separately from the core processor to enable testing of the connections to the memory devices. The test control circuitry is triggered separately from the other power control circuitry, and can be protected to allow only secured access for testing.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: April 7, 2020
    Assignee: Intel Corporation
    Inventors: Lakshminarayana Pappu, Navneet Dour, Christopher E. Cox
  • Patent number: 10594318
    Abstract: An electric circuit arrangement and a method for generating electric current pulses to a load, the electric circuit arrangement including a switch and a current source in series connection with the load; wherein the switch is arranged to operate in at least an on state and an off state, thereby selectively connecting or disconnecting the current source to or from the load so as to generate the electric current pulses. With such architecture, the circuit performs with a better efficiency than a cascaded architecture.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: March 17, 2020
    Assignee: CITY UNIVERSITY OF HONG KONG
    Inventors: Shu Hung Henry Chung, Chung Pui Tung, Wing To Fan, Po Wa Chow, Sui Pung Cheung
  • Patent number: 10566266
    Abstract: A semiconductor device includes a plurality of stacked chips is disclosed. Each of the stacked chips includes a plurality of through vias arranged in a regular polygonal shape. The through vias of each chip are formed at corresponding positions in a stacked direction. The respective through vias of each chip are electrically connected to through vias of a chip adjacent in the stacked direction in a manner that the connected through vias are spaced apart from one another in substantially the same direction.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: February 18, 2020
    Assignee: SK hynix Inc.
    Inventors: Heat Bit Park, Ji Hwan Kim, Dong Uk Lee
  • Patent number: 10551439
    Abstract: An integrated circuit including a first multiplexor configured to receive one of a plurality of diagnostic signals from circuitry under test (DUT), the first multiplexor responsive to diagnostic signals provided thereto and configured to selectively output one of the diagnostic signals in response to a control signal, a second multiplexor configured to receive one of a plurality of reference signals from one of a plurality of nodes on a reference circuit, the second multiplexor configured to selectively output one of the diagnostic signals in response to a control signal, and a comparator configured to compare the diagnostic signal elicited from the first multiplexor with the reference signal elicited from the second multiplexor, the comparator further configured to output the result of the comparison between the diagnostic signal and the reference signal.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: February 4, 2020
    Assignee: Allegro MicroSystems, LLC
    Inventors: Mathew Drouin, Jonathan Zimmermann
  • Patent number: 10516054
    Abstract: Provided are electronic devices having a two-dimensional (2D) material layer. The electronic device includes an electrode layer that directly contacts an edge of the 2D material layer. The electrode layer may include a conductive material having a high work function or may have a structure in which an electrode layer includes a conductive material having a high work function and an electrode layer includes a conductive material having a low work function.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: December 24, 2019
    Assignees: Research & Business Foundation Sungkyunkwan University, Samsung Electronics Co., Ltd.
    Inventors: Seunggeol Nam, Wonjong Yoo, Zheng Yang
  • Patent number: 10476374
    Abstract: The present invention discloses a short circuit and/or bad connection detection method for use in a power supply system. The power supply system includes a power converter which converts an input voltage to an output voltage and supplies an output current to an electronic device. In the short circuit detection method, the conversion from the input voltage to the output voltage is disabled in a disable time period, and whether a short circuit occurs is determined according to the decreasing speed of the output voltage. In the bad connection detection method, an actual voltage and an actual current received by the electronic device are compared with the output voltage and the output current, to determine whether a bad connection occurs.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: November 12, 2019
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Yi-Min Shiu, Isaac Y. Chen
  • Patent number: 10461000
    Abstract: A semiconductor test system has a wafer holder with a tape portion and one or more openings through the tape portion. A semiconductor wafer is mounted over the opening in the tape portion of the wafer holder with an electrical connection to the semiconductor wafer through the opening in the tape portion during probe test. A plurality of bumps can be formed on the semiconductor wafer. The semiconductor wafer can be a stacked semiconductor wafer. A conductive trace can be formed on the tape portion and the semiconductor wafer probe tested through the conductive trace. An active surface or non-active surface of the semiconductor wafer can be oriented toward the tape portion. The electrical connection to the semiconductor wafer through the opening in the tape portion can be a ground reference node. A conductive layer is formed over a non-active surface of the semiconductor wafer.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: October 29, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Heng Chen Lee
  • Patent number: 10444279
    Abstract: A design for test (DfT) architecture is provided that enables pre-bond parametric testing of through-silicon vias (TSVs). A grouping of N number of input/output (I/O) segments are configured to receive a test signal in a feedback loop, where each I/O segment includes one or more buffers (or inverters) and a TSV connected at one end to the one or more buffers. The TSV acts as a shunt-connected capacitor—when defect free—and includes a load resistance when the TSV contains a defect. Each I/O segment can also include one or two multiplexers to control whether the I/O segment receives a test or functional signal and, optionally, whether the I/O segment is bypassed or included in the ring oscillator. The varying loads caused by the defects cause variations in the delay across the buffers (or inverters) of an I/O segment that can be detected in the output signal.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: October 15, 2019
    Assignee: DUKE UNIVERSITY
    Inventors: Krishnendu Chakrabarty, Sergej Deutsch
  • Patent number: 10422828
    Abstract: A system and method utilize a stand-alone controller for a multiplexed handler test cell in automated and robotic semiconductor test equipment for indexless tandem semiconductor testing. The stand-alone controller is configured such that functions relating to both the handler drivers and the data post-processor of the multiplexed handler tested cell are included within the stand-alone controller. The system and method also include provisions for using a virtual multiplexed handler test cell in a preliminary stage prior to actual implementation of the actual multiplexed handler test cell. This configuration permits the stand-alone controller to control the functions of the multiplexed handlers and to coordinate their activity with the tester.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: September 24, 2019
    Assignee: CELERINT, LLC.
    Inventor: Howard H. Roberts, Jr.
  • Patent number: 10401407
    Abstract: An integrated circuit (IC) includes a first transistor having a first dopant type and a second transistor having a second dopant type opposite to the first dopant type. The first transistor includes a first terminal configured to receive a current, a second terminal connected to a node, and a first gate, and the second transistor includes a first terminal connected to a device under test (DUT), a second terminal connected to the node, and a second gate. Each one of the first gate, the node, or the second gate is capable of receiving a first voltage from a first voltage source simultaneously with another one of the first gate, the node, or the second gate receiving a second voltage from a second voltage source, the first voltage being different from the second voltage.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: September 3, 2019
    Assignee: TAIWAN SEMICONDUCOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Shen Chou, Po-Zeng Kang, Yung-Chow Peng
  • Patent number: 10386405
    Abstract: A method is provided for performing continuous single insertion semiconductor testing of a group of semiconductors that are divided into a first subgroup and a second subgroup at multiple different temperatures. The single insertion semiconductor testing is performed by sequentially executing testing cycles, characterized by the tester alternately executing temperature testing periods and temperature ramping periods for the first subgroup, while simultaneously executing temperature ramping periods and temperature testing periods for the second subgroup. The temperature testing periods operate at two or more different temperatures. The single insertion testing sequence entirely eliminates tester index time when the testing time is equal to or greater than the ramping times, and substantially reduces tester index time when the testing time is less that the ramping times.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: August 20, 2019
    Assignee: CELERINT, LLC
    Inventor: Howard H. Roberts, Jr.
  • Patent number: 10347595
    Abstract: A device includes a first chip having a front side and a back side. A second chip is stacked with the first chip and located on the back side of the first chip. A first loop includes first and second through vias located in the first chip. Each through via has a first end on the front side of the first chip and a second end on the back side of the first chip. The first loop also includes a first track that connects the first ends of the first and second through vias is located in the first chip on the front side thereof and a second track that connects the second ends of the first and second through vias is located in the second chip. A detection circuit can detect an electrical characteristic of the first loop.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: July 9, 2019
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Clement Champeix, Nicolas Borrel
  • Patent number: 10256330
    Abstract: A switching circuit may be provided with: a parallel circuit including a first IGBT and a second IGBT connected in parallel; a controller configured to receive a signal indicating a turn-on timing and a turn-off timing. The controller is configured to: turn on both of the first and second IGBTs at the turn-on timing, execute a first control in which one of the first and second IGBTs is turned off before the turn-off timing and the other of the first and second IGBTs is turned off at the turn-off timing in a case where current flowing through the parallel circuit is equal to or lower than a threshold value, and execute a second control in which both of the first and second IGBTs are turned off at the turn-off timing in a case where the current flowing through the parallel circuit is higher than the threshold value.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: April 9, 2019
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Ken Toshiyuki, Yusuke Shindo, Tomotaka Suzuki
  • Patent number: 10224253
    Abstract: A display device is disclosed. In one aspect, the display device includes a display area configured to display an image, a peripheral area neighboring the display area, and at least one test element group (TEG) including a test thin film transistor (TFT) formed in the peripheral area and a plurality of test pads electrically connected to the test TFT. The display device also includes first to third dummy circuits separated from the test TFT, each of the first to third dummy circuits including a plurality of first dummy semiconductor layers and a plurality of first dummy gate electrodes overlapping at least a portion of the first dummy semiconductor layers in the depth dimension of the display device.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: March 5, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Moo Soon Ko, Jeong-Soo Lee, Jung Hwa Kim
  • Patent number: 10215796
    Abstract: A system and a method determine a quality of a doped semiconductor layer in terms of a charge carrier density gradient by measuring two magnetic-field-dependent resistances using four contacts of a specimen.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: February 26, 2019
    Assignee: Northwestern University
    Inventors: Matthew Grayson, Wang Zhou
  • Patent number: 10197618
    Abstract: Provided are a measurement apparatus and a measurement method capable of measuring inter-terminal capacitances of a three-terminal device while reproducibility is high and influences of residual inductances are cancelled. The measurement apparatus includes: a route selector including a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, and a sixth terminal, the fourth to sixth terminals being configured to connect to any of the first to third terminals; an LCR meter; a device under test, which is a three-terminal device; first, second, and third cables for respectively connecting the fourth to sixth terminals of the first route selector and first, second, and third terminals of the device under test to each other; and fourth, fifth, and sixth cables for respectively connecting the first to third terminals of the first route selector and first, second, and third terminals of the LCR meter to each other.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: February 5, 2019
    Assignee: Keysight Technologies, Inc.
    Inventors: Koji Tokuno, Yoshimi Nagai