Test Of Semiconductor Device Patents (Class 324/762.01)
  • Patent number: 10847849
    Abstract: An inspection method of an electrical storage device includes: setting a pseudo parasitic resistance value to be small in a case where a power storage capacity of the electrical storage device is large, while setting the pseudo parasitic resistance value to be large in the case where the power storage capacity is small; in a state where the pseudo parasitic resistance value is set, acquiring a current value after convergence of a current flowing through a circuit such that the circuit is formed by connecting an external power source to the charged electrical storage device in a direction where a voltage is applied thereto; and determining quality of the electrical storage device based on the current value.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: November 24, 2020
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Takeshi Goto, Kiwamu Kobayashi
  • Patent number: 10768238
    Abstract: A circuit is formed by connecting an external power source to a charged electrical storage device so that a polarity of a voltage of the external power source is reverse to a polarity of a voltage of the charged electrical storage device, and the voltage of the external power source is adjusted so that a current does not flow right after the connection. Then, current measurement to acquire a current value after convergence of the current flowing through the circuit due to a voltage drop of the electrical storage device and quality determination based on the current value after convergence are performed. In the current measurement, resistance measurement to actually measure a circuit resistance and prediction to predict a convergence timing of the current based on the actually measured circuit resistance are performed. The current value is acquired when a predicted convergence timing comes.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: September 8, 2020
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Takeshi Goto, Kiwamu Kobayashi
  • Patent number: 10760961
    Abstract: The present invention relates to a method for testing a retinal implant. After an implantable device for interfacing with retinal cells is provided, an external stimulus is applied to the implantable device so that the implantable device transmits a first pulse to a processing device through a wireless interface. When a conversion unit is controlled to gradually decrease an output voltage until the implantable device outputs an output voltage lower than a reference voltage, the implantable device transmits a signal different from the first pulse to the processing device through the wireless interface. The processing device determines a current value of a pixel unit according to a time difference between the first pulse and the signal.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: September 1, 2020
    Assignee: IRIDIUM MEDICAL TECHNOLOGY CO., LTD.
    Inventors: Long-Sheng Fan, Hsin Chen, Yung-Chan Chen
  • Patent number: 10733922
    Abstract: A display device includes: a substrate; pixels provided in a display area of the substrate; signal lines provided on the substrate and connected to the pixels; and a pad portion provided in a peripheral area and including pads. The signal lines include a first crack detecting line provided in the peripheral area and connected to a first test voltage pad, first data lines including first ends connected to the first crack detecting line through corresponding first transistors and second ends connected to corresponding pixels from among the pixels, and first connecting wires for connecting the first data lines and pads corresponding to the first data lines from among the pads, and the first connecting wires are provided on one layer from among at least two layers.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: August 4, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jong Won Park, Hyun Woong Kim
  • Patent number: 10725105
    Abstract: Disclosed is a test and measurement switch matrix. The test and measurement switch matrix includes a solid state switch to couple a test signal from a Device Under Test (DUT) to a test system. The solid state switch has a dual tee guard arrangement providing low leakage when off. The solid state switch also includes an optically coupled drive, which further improves isolation and reduces undesirable charge injection when changing switch states.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: July 28, 2020
    Assignee: Keithley Instruments, LLC
    Inventors: Matthew Holtz, James Niemann, Martin Rice
  • Patent number: 10712390
    Abstract: During scan testing a voltage regulator is programmed to supply a first voltage to logic under test during a shift portion of the scan test, a second voltage during a first portion of a capture portion of the scan test and at least a third voltage during a second portion of the capture portion of the scan test. The availability of a programmable voltage regulator during shift and capture portions of scan testing allows a less stressful voltage to be used during a shift portion of the scan test to reduce shift failures and allows various voltages to be used during capture portions of the scan testing as a surrogate for testing at different temperatures and to provide more flexibility in testing margins.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: July 14, 2020
    Assignee: Silicon Laboratories Inc.
    Inventor: Vivek Sarda
  • Patent number: 10703395
    Abstract: The invention relates to a device and a method for monitoring an electric network in a rail vehicle. The electric network includes at least one power converter, at least one permanent magnet machine, and at least one first phase line for the electrical connection of the at least one power converter and the at least one permanent magnet machine. The first phase line is interrupted. A potential difference is determined between a machine-side part of the first phase line and a reference potential and a potential-difference-dependent variable, wherein a speed of the permanent magnet machine and, as a function of the speed, a speed-dependent reference variable are determined. A deviation of the potential-difference-dependent variable from the speed-dependent reference variable is determined, wherein a network fault is detected if the deviation is greater than a predetermined threshold value.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: July 7, 2020
    Assignee: Bombardier Transportation GmbH
    Inventors: Fabian Streiff, Gerhard Isepponi
  • Patent number: 10699970
    Abstract: An extension of conventional IC fabrication processes to include some of the concepts of flip-chip assemblies while producing a final “non-flip chip” circuit structure suitable for conventional packaging or for direct usage by customers. Multiple IC dies are fabricated on a semiconductor wafer in a conventional fashion, solder bumped or the like, and singulated. The singulated dies, which may be of different sizes and functionality, are then flip-chip assembled onto a single tile substrate of thin-film material which has been patterned with vias, peripheral connection pads, and one or more ground planes. Once dies are flip-chip mounted to the thin-film tile, all of the dies on the entire tile may be probed using automated testing equipment. Sets of dies of different functionality may be tested as a system or subsystem. Once test probing is complete, the dies (or sets of dies) and tile are singulated into die/tile assemblies.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: June 30, 2020
    Assignee: pSemi Corporation
    Inventors: Mark Moffat, Andrew Christie, Duncan Pilgrim, Ronald Eugene Reedy
  • Patent number: 10678438
    Abstract: A scheduler of a memory system is provided. The scheduler may include a pattern storage part and a pattern selector. The pattern storage part may have a plurality of storage patterns, each of the storage patterns provide for a process sequence for a plurality of instructions. The pattern selector may be configured to select one of the plurality of storage patterns in the pattern storage part and generate a schedule such that external instructions are executed in the process sequence set by the selected storage pattern.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: June 9, 2020
    Assignee: SK hynix Inc.
    Inventors: Donggun Kim, Jung Hyun Kwon
  • Patent number: 10656214
    Abstract: A circuit is formed by connecting an external power source to a charged electrical storage device so that a polarity of a voltage of the external power source is reverse to a polarity of a voltage of the charged electrical storage device, and the voltage of the external power source is adjusted so that a current does not flow right after the connection. Then, current measurement to acquire a current value after convergence of the current flowing through the circuit due to a voltage drop of the electrical storage device and quality determination based on the current value after convergence are performed. In the current measurement, resistance measurement to actually measure a circuit resistance and prediction to predict a convergence timing of the current based on the actually measured circuit resistance are performed. The current value is acquired when a predicted convergence timing comes.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: May 19, 2020
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Takeshi Goto, Kiwamu Kobayashi
  • Patent number: 10650198
    Abstract: The present invention provides a method and an apparatus for detecting anti-skimming magnetic interference, wherein the method comprises the steps of: S1: generating an original magnetic strip signal; acquiring an interfered magnetic strip signal by combining the original magnetic strip signal and an interference signal of an electromagnetic interference source to be tested; S2: decoding the interfered magnetic strip signal to obtain a decoded parameter; and S3: determining whether an original magnetic strip parameter is consistent with the decoded parameter; if so, obtaining a first test result that the electromagnetic interference source is unqualified to satisfy a magnetic card reading device's requirement for electromagnetic interference; otherwise, obtaining a second test result that the electromagnetic interference source is qualified to satisfy the magnetic card reading device's requirement for electromagnetic interference whereby security of the magnetic card reading device can be enhanced and the mag
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: May 12, 2020
    Assignees: GRG BANKING EQUIPMENT CO., LTD., GRG BANKING IT CO., LTD.
    Inventors: Lixian Shangguan, Wenchuan Gong, Xiaofeng Jin
  • Patent number: 10613955
    Abstract: A system includes test control circuitry in parallel with power control circuitry. The power control circuitry enables a core processor and memory interface drivers responsive to a reset. The test control circuitry can enable the memory interface drivers separately from the core processor to enable testing of the connections to the memory devices. The test control circuitry is triggered separately from the other power control circuitry, and can be protected to allow only secured access for testing.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: April 7, 2020
    Assignee: Intel Corporation
    Inventors: Lakshminarayana Pappu, Navneet Dour, Christopher E. Cox
  • Patent number: 10594318
    Abstract: An electric circuit arrangement and a method for generating electric current pulses to a load, the electric circuit arrangement including a switch and a current source in series connection with the load; wherein the switch is arranged to operate in at least an on state and an off state, thereby selectively connecting or disconnecting the current source to or from the load so as to generate the electric current pulses. With such architecture, the circuit performs with a better efficiency than a cascaded architecture.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: March 17, 2020
    Assignee: CITY UNIVERSITY OF HONG KONG
    Inventors: Shu Hung Henry Chung, Chung Pui Tung, Wing To Fan, Po Wa Chow, Sui Pung Cheung
  • Patent number: 10566266
    Abstract: A semiconductor device includes a plurality of stacked chips is disclosed. Each of the stacked chips includes a plurality of through vias arranged in a regular polygonal shape. The through vias of each chip are formed at corresponding positions in a stacked direction. The respective through vias of each chip are electrically connected to through vias of a chip adjacent in the stacked direction in a manner that the connected through vias are spaced apart from one another in substantially the same direction.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: February 18, 2020
    Assignee: SK hynix Inc.
    Inventors: Heat Bit Park, Ji Hwan Kim, Dong Uk Lee
  • Patent number: 10551439
    Abstract: An integrated circuit including a first multiplexor configured to receive one of a plurality of diagnostic signals from circuitry under test (DUT), the first multiplexor responsive to diagnostic signals provided thereto and configured to selectively output one of the diagnostic signals in response to a control signal, a second multiplexor configured to receive one of a plurality of reference signals from one of a plurality of nodes on a reference circuit, the second multiplexor configured to selectively output one of the diagnostic signals in response to a control signal, and a comparator configured to compare the diagnostic signal elicited from the first multiplexor with the reference signal elicited from the second multiplexor, the comparator further configured to output the result of the comparison between the diagnostic signal and the reference signal.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: February 4, 2020
    Assignee: Allegro MicroSystems, LLC
    Inventors: Mathew Drouin, Jonathan Zimmermann
  • Patent number: 10516054
    Abstract: Provided are electronic devices having a two-dimensional (2D) material layer. The electronic device includes an electrode layer that directly contacts an edge of the 2D material layer. The electrode layer may include a conductive material having a high work function or may have a structure in which an electrode layer includes a conductive material having a high work function and an electrode layer includes a conductive material having a low work function.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: December 24, 2019
    Assignees: Research & Business Foundation Sungkyunkwan University, Samsung Electronics Co., Ltd.
    Inventors: Seunggeol Nam, Wonjong Yoo, Zheng Yang
  • Patent number: 10476374
    Abstract: The present invention discloses a short circuit and/or bad connection detection method for use in a power supply system. The power supply system includes a power converter which converts an input voltage to an output voltage and supplies an output current to an electronic device. In the short circuit detection method, the conversion from the input voltage to the output voltage is disabled in a disable time period, and whether a short circuit occurs is determined according to the decreasing speed of the output voltage. In the bad connection detection method, an actual voltage and an actual current received by the electronic device are compared with the output voltage and the output current, to determine whether a bad connection occurs.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: November 12, 2019
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Yi-Min Shiu, Isaac Y. Chen
  • Patent number: 10461000
    Abstract: A semiconductor test system has a wafer holder with a tape portion and one or more openings through the tape portion. A semiconductor wafer is mounted over the opening in the tape portion of the wafer holder with an electrical connection to the semiconductor wafer through the opening in the tape portion during probe test. A plurality of bumps can be formed on the semiconductor wafer. The semiconductor wafer can be a stacked semiconductor wafer. A conductive trace can be formed on the tape portion and the semiconductor wafer probe tested through the conductive trace. An active surface or non-active surface of the semiconductor wafer can be oriented toward the tape portion. The electrical connection to the semiconductor wafer through the opening in the tape portion can be a ground reference node. A conductive layer is formed over a non-active surface of the semiconductor wafer.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: October 29, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Heng Chen Lee
  • Patent number: 10444279
    Abstract: A design for test (DfT) architecture is provided that enables pre-bond parametric testing of through-silicon vias (TSVs). A grouping of N number of input/output (I/O) segments are configured to receive a test signal in a feedback loop, where each I/O segment includes one or more buffers (or inverters) and a TSV connected at one end to the one or more buffers. The TSV acts as a shunt-connected capacitor—when defect free—and includes a load resistance when the TSV contains a defect. Each I/O segment can also include one or two multiplexers to control whether the I/O segment receives a test or functional signal and, optionally, whether the I/O segment is bypassed or included in the ring oscillator. The varying loads caused by the defects cause variations in the delay across the buffers (or inverters) of an I/O segment that can be detected in the output signal.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: October 15, 2019
    Assignee: DUKE UNIVERSITY
    Inventors: Krishnendu Chakrabarty, Sergej Deutsch
  • Patent number: 10422828
    Abstract: A system and method utilize a stand-alone controller for a multiplexed handler test cell in automated and robotic semiconductor test equipment for indexless tandem semiconductor testing. The stand-alone controller is configured such that functions relating to both the handler drivers and the data post-processor of the multiplexed handler tested cell are included within the stand-alone controller. The system and method also include provisions for using a virtual multiplexed handler test cell in a preliminary stage prior to actual implementation of the actual multiplexed handler test cell. This configuration permits the stand-alone controller to control the functions of the multiplexed handlers and to coordinate their activity with the tester.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: September 24, 2019
    Assignee: CELERINT, LLC.
    Inventor: Howard H. Roberts, Jr.
  • Patent number: 10401407
    Abstract: An integrated circuit (IC) includes a first transistor having a first dopant type and a second transistor having a second dopant type opposite to the first dopant type. The first transistor includes a first terminal configured to receive a current, a second terminal connected to a node, and a first gate, and the second transistor includes a first terminal connected to a device under test (DUT), a second terminal connected to the node, and a second gate. Each one of the first gate, the node, or the second gate is capable of receiving a first voltage from a first voltage source simultaneously with another one of the first gate, the node, or the second gate receiving a second voltage from a second voltage source, the first voltage being different from the second voltage.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: September 3, 2019
    Assignee: TAIWAN SEMICONDUCOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Shen Chou, Po-Zeng Kang, Yung-Chow Peng
  • Patent number: 10386405
    Abstract: A method is provided for performing continuous single insertion semiconductor testing of a group of semiconductors that are divided into a first subgroup and a second subgroup at multiple different temperatures. The single insertion semiconductor testing is performed by sequentially executing testing cycles, characterized by the tester alternately executing temperature testing periods and temperature ramping periods for the first subgroup, while simultaneously executing temperature ramping periods and temperature testing periods for the second subgroup. The temperature testing periods operate at two or more different temperatures. The single insertion testing sequence entirely eliminates tester index time when the testing time is equal to or greater than the ramping times, and substantially reduces tester index time when the testing time is less that the ramping times.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: August 20, 2019
    Assignee: CELERINT, LLC
    Inventor: Howard H. Roberts, Jr.
  • Patent number: 10347595
    Abstract: A device includes a first chip having a front side and a back side. A second chip is stacked with the first chip and located on the back side of the first chip. A first loop includes first and second through vias located in the first chip. Each through via has a first end on the front side of the first chip and a second end on the back side of the first chip. The first loop also includes a first track that connects the first ends of the first and second through vias is located in the first chip on the front side thereof and a second track that connects the second ends of the first and second through vias is located in the second chip. A detection circuit can detect an electrical characteristic of the first loop.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: July 9, 2019
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Clement Champeix, Nicolas Borrel
  • Patent number: 10256330
    Abstract: A switching circuit may be provided with: a parallel circuit including a first IGBT and a second IGBT connected in parallel; a controller configured to receive a signal indicating a turn-on timing and a turn-off timing. The controller is configured to: turn on both of the first and second IGBTs at the turn-on timing, execute a first control in which one of the first and second IGBTs is turned off before the turn-off timing and the other of the first and second IGBTs is turned off at the turn-off timing in a case where current flowing through the parallel circuit is equal to or lower than a threshold value, and execute a second control in which both of the first and second IGBTs are turned off at the turn-off timing in a case where the current flowing through the parallel circuit is higher than the threshold value.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: April 9, 2019
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Ken Toshiyuki, Yusuke Shindo, Tomotaka Suzuki
  • Patent number: 10224253
    Abstract: A display device is disclosed. In one aspect, the display device includes a display area configured to display an image, a peripheral area neighboring the display area, and at least one test element group (TEG) including a test thin film transistor (TFT) formed in the peripheral area and a plurality of test pads electrically connected to the test TFT. The display device also includes first to third dummy circuits separated from the test TFT, each of the first to third dummy circuits including a plurality of first dummy semiconductor layers and a plurality of first dummy gate electrodes overlapping at least a portion of the first dummy semiconductor layers in the depth dimension of the display device.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: March 5, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Moo Soon Ko, Jeong-Soo Lee, Jung Hwa Kim
  • Patent number: 10215796
    Abstract: A system and a method determine a quality of a doped semiconductor layer in terms of a charge carrier density gradient by measuring two magnetic-field-dependent resistances using four contacts of a specimen.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: February 26, 2019
    Assignee: Northwestern University
    Inventors: Matthew Grayson, Wang Zhou
  • Patent number: 10197618
    Abstract: Provided are a measurement apparatus and a measurement method capable of measuring inter-terminal capacitances of a three-terminal device while reproducibility is high and influences of residual inductances are cancelled. The measurement apparatus includes: a route selector including a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, and a sixth terminal, the fourth to sixth terminals being configured to connect to any of the first to third terminals; an LCR meter; a device under test, which is a three-terminal device; first, second, and third cables for respectively connecting the fourth to sixth terminals of the first route selector and first, second, and third terminals of the device under test to each other; and fourth, fifth, and sixth cables for respectively connecting the first to third terminals of the first route selector and first, second, and third terminals of the LCR meter to each other.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: February 5, 2019
    Assignee: Keysight Technologies, Inc.
    Inventors: Koji Tokuno, Yoshimi Nagai
  • Patent number: 10181785
    Abstract: The present invention discloses a short circuit and/or bad connection detection method for use in a power supply system. The power supply system includes a power converter which converts an input voltage to an output voltage and supplies an output current to an electronic device. In the short circuit detection method, the conversion from the input voltage to the output voltage is disabled in a disable time period, and whether a short circuit occurs is determined according to the decreasing speed of the output voltage. In the bad connection detection method, an actual voltage and an actual current received by the electronic device are compared with the output voltage and the output current, to determine whether a bad connection occurs.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: January 15, 2019
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Yi-Min Shiu, Isaac Y. Chen
  • Patent number: 10163741
    Abstract: A semiconductor device structure, including integrated circuits of semiconductor chips and scribe lanes between the regions in which the circuits have been formed, has at least one redistribution pad disposed in one of the scribe lanes for simultaneously testing a group of the integrated circuits, and a metal interconnection structure disposed beneath the redistribution pad(s). The metal interconnection structure includes at least conductive via contacting the redistribution pad at the bottom of the pad. The conductive via(s) is/are arranged so that at least a portion of each via remains attached to the redistribution pad when the structure is sawed along the scribe lane.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: December 25, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Ho Kim, Ho-Sung Song, Jeong-Sik Nam, Kyoung-Min Kim, Tae-Hyeong Lee
  • Patent number: 10141235
    Abstract: Semiconductor layer 110 is formed on semiconductor substrate 101. Semiconductor layer 110 has a plurality of well regions 103 in a surface remote from semiconductor substrate 101. Semiconductor layer 110 includes drift region 102 in addition to the plurality of well regions 103. The plurality of well regions 103 each include body region 105, source region 108, and contact region 109. Source region 108 is in contact with body region 105. Contact region 109 is in contact with both body region 105 and source region 108. Body region 105, source region 108, and source wire 118 are at an identical potential because of contact region 109. Semiconductor layer 110 includes ineffective region R at the surface remote from semiconductor substrate 101.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: November 27, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Tsutomu Kiyosawa
  • Patent number: 10094752
    Abstract: A folding test machine to measure the durability against folding can be operated by minor adjustment even if a radius of curvature of the folding or an arc length of the folding is changed. A fixed wall and a moveable wall are opposingly provided in an approximately box-shaped frame and a holding part to hold a workpiece is provided on the top of each of the fixed wall and the moveable wall in a rotatable manner in a vertical plane of the rotation. And the workpiece and a plate spring are held on the respective opposing end portions so as to be bridged between the fixed wall and the moveable wall in a curved manner such that the moveable wall is moved closer to and farther from the fixed wall repeatedly such that the work is folded repeatedly.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: October 9, 2018
    Assignee: Yuasa System Co., Ltd.
    Inventors: Yasuhisa Okazaki, Naotsugu Ando, Hisao Sasaki
  • Patent number: 10031160
    Abstract: A test fixture has a flexible plastic cable that acts as a waveguide. The Device-Under-Test (DUT) is a small transceiver and antenna that operate in the Extremely High-Frequency (EHF) band of 30-300 GHz. The size of the DUT transceiver is very small, limiting the power of emitted electromagnetic radiation so that close-proximity communication is used. The envelope for reception may only extend for about a centimeter from the DUT transceiver, about the same size as the test socket. A slot is formed in the test socket very near to the antenna. The slot receives one end of the plastic waveguide. The slot extends into the envelope by the DUT transceiver so that close-proximity radiation is captured by the plastic waveguide. The waveguide has a high relative permittivity and reflective metalized walls so that the radiation may be carried to a receiver that is outside the envelope.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: July 24, 2018
    Assignee: Keyssa, Inc.
    Inventors: Roger Isaac, Bhupendra Sarhad, Gary Davis McCormack, Ian A. Kyles, Frederick George Weiss, Christopher Scott Sansom
  • Patent number: 9977072
    Abstract: An integrated circuit (IC) and a method for operating the IC are provided. The IC comprises a device under test and a first heater. The first heater is located at a first side of the device and provides heat to control a temperature of the device. The first heater comprises a semiconductor device having a first doped region and a second doped region having a conductivity type opposite to that of the first doped region, the first doped region interfacing with the second doped region.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: May 22, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jiaw-Ren Shih, Jhong-Sheng Wang, Shih-Hsin Chen, Jen-Hao Lee, Ting-Sheng Huang
  • Patent number: 9972232
    Abstract: A liquid crystal display (LCD) device and a method for testing pixels of the LCD device are disclosed, in which pixels adjacent to each other vertically are arranged in a display area to share a gate line and an auto probe test pattern of the pixels is arranged in a non-display area. The LCD device comprises a plurality of pixels arranged in a display area; and a test pattern arranged in a non-display area, for supplying a test signal to each of the plurality of pixels, wherein two pixels, which are adjacent to each other vertically, among the plurality of pixels, share a single gate line and receive data voltages from different data lines different from each other, and the test pattern includes at least one data shorting bar and at least one switching unit to supply the test signal to each of the plurality of pixels per color.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: May 15, 2018
    Assignee: LG Display Co., Ltd.
    Inventor: Jun Yeob Lee
  • Patent number: 9946332
    Abstract: A semiconductor device which makes it possible to reduce a wasteful standby time at power-on is provided. In this semiconductor device, a reset of an internal circuit is canceled as described below. When a data signal stored in a storage section is at “0,” the reset is canceled by bringing an internal reset signal to the “H” level when a relatively short time has passed after the rising edge of a power on reset signal. When the data signal is at “1,” the reset is canceled by bringing the internal reset signal to the “H” level when a relatively long time has passed after the rising edge of the power on reset signal. Therefore, a wasteful standby time at power-on can be reduced by writing the data signal logically equivalent to the rise time of supply voltage to the storage section.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: April 17, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshinori Tokioka, Soichi Kobayashi, Akira Oizumi
  • Patent number: 9912224
    Abstract: The present invention discloses a short circuit and/or bad connection detection method for use in a power supply system. The power supply system includes a power converter which converts an input voltage to an output voltage and supplies an output current to an electronic device. In the short circuit detection method, the conversion from the input voltage to the output voltage is disabled in a disable time period, and whether a short circuit occurs is determined according to the decreasing speed of the output voltage. In the bad connection detection method, an actual voltage and an actual current received by the electronic device are compared with the output voltage and the output current, to determine whether a bad connection occurs.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: March 6, 2018
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Yi-Min Shiu, Isaac Y. Chen
  • Patent number: 9887010
    Abstract: Provided is a highly integrated semiconductor device which can hold data and includes a NAND cell array. Each of the plurality of memory cells of the NAND cell array includes a first transistor, a second transistor, a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal is electrically connected to one electrode connected to a channel region of the first transistor. The second terminal is electrically connected to the other electrode connected to the channel region of the first transistor. The third terminal is electrically connected to a gate electrode of the second transistor. The fourth terminal is electrically connected to one electrode connected to a channel region of the second transistor. A gate electrode of the first transistor is in contact with the other electrode connected to the channel region of the second transistor. A string of the plurality of memory cells is formed by connecting the first terminals and the second terminals.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: February 6, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshinobu Asami
  • Patent number: 9871009
    Abstract: A semiconductor device and method of manufacturing is provided, whereby a support structure is utilized to provide additional support for a conductive element in order to eliminate or reduce the formation of a defective surface such that the conductive element may be formed to have a thinner structure without suffering deleterious structures.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: January 16, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Ming-Che Ho, Hung-Jui Kuo, Yi-Wen Wu, Tzung-Hui Lee
  • Patent number: 9858367
    Abstract: A parameterizable integrated circuit (IC) and method for designing, refining and implementing a circuit including the parameterizable IC are described. The method begins with receiving information on candidate sensing sub-circuits, parameterizable ICs and user specified requirements for the circuit including physical properties to be sensed and target values for the circuit. Each of the parameterizable ICs include a number of parametric analog and digital circuit elements, and a scheduler to schedule resources of the IC according to measurement priorities, measurement rates and the available circuit elements. Next, each of the candidate sensor-sub-circuits is evaluated with reference to the specified requirements, and each of the candidate ICs evaluated with reference to the requirements and the sensor-sub-circuits. Generally, the method further includes communicating to a user a number of candidate circuit-designs within a predetermined percentage of the one or more target values for the circuit.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: January 2, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventors: Antonio Visconti, David LeHoty
  • Patent number: 9817040
    Abstract: A minute current measurement method is provided. In the current measurement method, a first potential is applied to a first terminal of a transistor under test, a second potential is applied to a first terminal of a first transistor, the first transistor is turned on to accumulate a predetermined charge in a node electrically connecting a second terminal of the transistor under test with a second terminal of the first transistor, a third potential of an output terminal of a read circuit electrically connected to the node is measured, the first transistor is turned off, a fourth potential of the output terminal of the read circuit electrically connected to the node is measured, the amount of the charge held by the node is estimated from the amount of change in the potential of the output terminal of the read circuit (e.g.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: November 14, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masashi Tsubuku, Kazuma Furutani, Atsushi Hirose, Toshihiko Takeuchi
  • Patent number: 9817025
    Abstract: A test fixture has a flexible plastic cable that acts as a waveguide. The Device-Under-Test (DUT) is a small transceiver and antenna that operate in the Extremely High-Frequency (EHF) band of 30-300 GHz. The size of the DUT transceiver is very small, limiting the power of emitted electromagnetic radiation so that close-proximity communication is used. The envelope for reception may only extend for about a centimeter from the DUT transceiver, about the same size as the test socket. A slot is formed in the test socket very near to the antenna. The slot receives one end of the plastic waveguide. The slot extends into the envelope by the DUT transceiver so that close-proximity radiation is captured by the plastic waveguide. The waveguide has a high relative permittivity and reflective metalized walls so that the radiation may be carried to a receiver that is outside the envelope.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: November 14, 2017
    Assignee: Keyssa, Inc.
    Inventors: Roger Isaac, Bhupendra Sarhad, Gary Davis McCormack, Ian A. Kyles, Frederick George Weiss, Christopher Scott Sansom
  • Patent number: 9772779
    Abstract: Methods for operating a distributed controller system in a memory device include receiving a read command, a master controller generating an indication to a data cache controller in response to the read command, and the data cache controller accepting data from a memory array of the memory device in response to the indication.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: September 26, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Luca De Santis, Luigi Pilolli
  • Patent number: 9696371
    Abstract: A test method and system for cut-in voltage. The method comprises: coarse scanning of the cut-in voltage: a grid voltage, i.e., the cut-in voltage, is quickly determined when a drain terminal current is greater than a target current for the first time (100); accurate scanning of the cut-in voltage: a scanning step length is shortened continuously until the scanning step length is shorter than a preset step length, and each time the scanning step length is shortened, the scanning is conducted according to the current shortened scanning step length on the basis of the cut-in voltage determined in the former time, and then the cut-in voltage under the condition of the current shortened scanning step length is determined again (200). The scanning voltage is automatically increased or decreased by the test method and system through adding high resolution and high precision test conversion into a second scanning test, and therefore the testing of the cut-in voltage becomes more efficient and more accurate.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: July 4, 2017
    Assignee: CSMC Technologies Fab2 Co., Ltd.
    Inventors: Ming Wang, Xiaoqian Lian, Yaojun Lin, Wenhui Xu, Hanshun Chen
  • Patent number: 9647132
    Abstract: A semiconductor device that can measure a minute current. The semiconductor device includes a first transistor, a second transistor, a node, and a capacitor. The first transistor includes an oxide semiconductor in a channel formation region. The node is electrically connected to a gate of the second transistor and a first terminal of the capacitor. The node is brought into an electrically floating state by turning off the first transistor after a potential V0 is supplied. Change in a potential VFN of the node over time is expressed by Formula (1). In Formula (1), t is elapsed time after the node is brought into the electrically floating state, ? is a constant with a unit of time, and ? is a constant greater than or equal to 0.4 and less than or equal to 0.6.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: May 9, 2017
    Assignee: Semiconductor Energy Laboratory Co., LTD.
    Inventors: Masashi Tsubuku, Kazuaki Ohshima, Masashi Fujita, Daigo Shimada, Tsutomu Murakawa
  • Patent number: 9640562
    Abstract: A display panel is disclosed and includes an active area and a non-active area. A first, a second, a third, a fourth, a fifth, and a sixth charging scanning lines and a first, a second, a third, a fourth, a fifth, and a sixth charge-sharing scanning lines of an array unit on the active area are connected to a first, a second, a third, a fourth, a fifth, and a sixth pixel row, respectively. A first, a second, and a third detection lines on the non-active area are connected to the active area.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: May 2, 2017
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventors: Zui Wang, Jinbo Guo
  • Patent number: 9613207
    Abstract: Provided is a technology which creates an autorun file that is used in autorun for preventing the autorun of a USB-based portable storage, thereby allowing an arbitrary user or worm virus not to manipulate the autorun file. A method for preventing autorun of portable storage accesses at least one of a master file table entry of a root directory and a master file table entry of an autorun file, and sets non-autorun in the at least one accessed master file table entry.
    Type: Grant
    Filed: August 3, 2010
    Date of Patent: April 4, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Hyun Uk Hwang, Ki Bom Kim, Gi Han Kim, Sung Il Lee, Tae Joo Chang, Cheol Won Lee
  • Patent number: 9579040
    Abstract: Apparatus are provided for monitoring a condition of a tissue based on a measurement of an electrical property of the tissue. In an example, the electrical property of the tissue is performed using an apparatus disposed above the tissue, where the apparatus includes at least two conductive structures, each having a non-linear configuration, where the at least two conductive structures are disposed substantially parallel to each other. In another example, the electrical property of the tissue is performed using an apparatus disposed above the tissue, where the apparatus includes at least one inductor structure.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: February 28, 2017
    Assignee: MC10, Inc.
    Inventors: Conor Rafferty, Jeffrey D. Carbeck, Alexander Dickson, Kevin Dowling, Yung-Yu Hsu, Isaiah Kacyvenski, Benjamin Schlatka, Henry Wei
  • Patent number: 9530705
    Abstract: Some embodiments relate to a wafer. The wafer includes a first dummy component comprising two or more first dummy component transmission lines. One of the first dummy component transmission lines operably couples a first signal test pad to a second signal test pad, and an other of the first dummy component transmission lines operably couples a third signal test pad to a fourth signal test pad. A second dummy component comprises two or more second dummy component transmission lines. One of the second dummy component transmission lines operably couples a fifth signal test pad to a sixth signal test pad, and an other of the second dummy component transmission lines operably couples a seventh signal test pad to an eighth signal test pad. Other embodiments are also disclosed.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: December 27, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiao-Tsung Yen, Chin-Wei Kuo, Chih-Yuan Chang, Min-Chie Jeng
  • Patent number: 9524922
    Abstract: The integrated circuit includes first and second vias, a first buffer configured to receive a signal transmitted from the first via, a second buffer configured to receive a signal transmitted from the second via, a first detour circuit configured to receive a signal transmitted through the second buffer, a second detour circuit configured to receive a signal transmitted through the first buffer, a first selector configured to selectively output one of the signal transmitted from the first via and a signal transmitted through the first detour circuit, and a second selector configured to selectively output one of the signal transmitted from the second via and a signal transmitted through the second detour circuit. Each of the first and second buffers and the first and second detour circuits transmits a signal in only one direction.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: December 20, 2016
    Assignees: SAMSUNG ELECTRONICS CO., LTD., SNU R&DB FOUNDATION
    Inventors: Kyounghwan Lim, Hyoun Soo Park, Kee Sup Kim, Bonghyun Lee, Chul Rim, JungYun Choi, Taewhan Kim, Heechun Park
  • Patent number: 9500706
    Abstract: Various aspects described or referenced herein are directed to different methods, systems, and computer program products for implementing hybrid on-chip clock controller techniques for facilitating at-speed scan testing and scan architecture support.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: November 22, 2016
    Assignee: NVIDIA Corporation
    Inventors: Amit Sanghani, Sagar Nataraj, Karthikeyan Natarajan, Bo Yang