Abstract: A test and measurement device, including a first input structured to receive a first voltage from a first conductor of a first triaxial cable, a second input structured to receive a second voltage from a second conductor of the first triaxial cable or a second triaxial cable, circuitry configured to change modes based on the first voltage and the second voltage; and an output structured to output a signal.

Abstract: The touch sensor includes a touch detection area with at least a part of a curved area having a curved edge. In the touch detection area, a plurality of first electrodes and second electrodes disposed side by side in a first direction and in a second direction are disposed. A plurality of first electrodes disposed side by side in the first direction are connected to each other. A plurality of second electrodes disposed side by side in the second direction are connected to each other. In the curved area, distances between the plurality of first electrodes and the second electrodes in the first direction gradually change in the second direction.

Abstract: Embodiments of the present disclosure relate to a monitoring circuit and a semiconductor device, and particularly, to a monitoring circuit including an oscillation circuit configured to generate an oscillation signal having a rising characteristic or a falling characteristic according to a threshold voltage level and a counter configured to count the number of rises or the number of falls of the oscillation signal, and a semiconductor device including the monitoring circuit.

Abstract: A method for operating a multi-level bridge power converter includes arranging a plurality of switching devices including at least four inner switching devices and at least two outer switching devices in an active neutral point clamped topology. The method also includes determining whether any of the switching devices is experiencing a failure condition by implementing a failure detection algorithm. The failure detection algorithm includes generating a blocking state logic signal by comparing a switching device voltage and a threshold reference voltage for each of the switching devices, determining an expected voltage blocking state for each of the switching devices based on gate drive signals of the switching devices and an output current direction, and detecting whether a failure condition is present in any of the switching devices based on the blocking state logic signals and the expected voltage blocking states of the switching devices.

Abstract: A burn-in resilient integrated circuit is provided. The burn-in resilient integrated circuit includes an inverter chain and a plurality of inverter circuits on the inverter chain. The burn-in resilient integrated circuit also includes a loop providing an electrical connection from an output of the inverter chain to an input of the inverter chain. The loop is selectable in accordance with a burn-in operation.

Abstract: The present disclosure relates to a semiconductor device, and a test apparatus and method thereof, capable of accurately detecting a defect by using a plurality of resistor circuits in a test process. The test apparatus of a semiconductor device according to an aspect of the present disclosure may include semiconductor chips each including an external resistor circuit disposed to be dispersed along an outer region of a chip and an internal resistor circuit disposed in an inner region of the chip in order to test cracks, and test equipment that drives the external resistor circuit and the internal resistor circuit and compares an output of the external resistor circuit with an output of the internal resistor circuit to detect whether a defect occurs in each of the semiconductor chips.

Abstract: A test kit for testing a device under test (DUT) includes a socket structure for containing the DUT, and a plunger assembly detachably coupled with the socket structure. The plunger assembly includes a multi-layered structure having at least an interposer substrate sandwiched by a top socket and a nest.

Abstract: An optical inspection apparatus includes a stage that supports a target substrate, the target substrate including a plurality of light emitting elements, a jig that applies an electrical signal to the target substrate, the jig including a regulation resistor, a microscope that generates magnified image data of the target substrate, a camera that captures the magnified image data to generate a color image of the target substrate, and an optical measurement unit that captures the magnified image data of the target substrate to generate a spectrum image and measure optical characteristics of the target substrate.

Abstract: A current detection circuit includes normally-on-type and a first normally-off-type switching elements with main current paths that are connected in series, and a second normally-off-type switching element that has a source and a gate that are connected to a source and a gate of the first normally-off-type switching element and a drain that is connected to a constant current source, and executes a division process by using drain voltages of the two normally-off-type switching elements.

Abstract: Various approaches to can be used to interrogate a surface such as a surface of a layered semiconductor structure on a semiconductor wafer. Certain approaches employ Second Harmonic Generation and in some cases may utilize pump and probe radiation. Other approaches involve determining current flow from a sample illuminated with radiation.

Abstract: A display panel, a display method thereof, and a display equipment are provided. The display panel includes a flat display part and a bending display part. A first thin film transistor is in the flat display part, and a second thin film transistor is in the bending display part. A ratio of a channel width to a channel length of an active layer of the first thin film transistor is greater than a ratio of a channel width to a channel length of an active layer of the second thin film transistor of the second thin film transistor. The display method includes a step of making a luminescence intensity of the bending display part greater than a luminescence intensity of the flat display part. The display equipment includes the display panel mentioned above.

Abstract: An apparatus for measuring a device current of a device under test (DUT) includes a first circuit including a first terminal for coupling to a first connection terminal of the DUT. The first circuit is configured to supply a first test voltage for the first terminal and to output a first output voltage sensed at the first terminal. The apparatus further includes a second circuit having a second terminal for coupling to a second connection terminal of the DUT. The second circuit is configured to supply a second test voltage for the second terminal and to output a second output voltage sensed at the second terminal. The apparatus further includes a third circuit configured to determine the device current of the DUT based on the first output voltage, the second output voltage, the first test voltage and the second test voltage. The first circuit and the second circuit are identical.

Abstract: A test circuit and a method for testing an integrated circuit are provided. The integrated circuit includes a test circuit. The test circuit includes a conductive track extending over at least a portion of the periphery of the integrated circuit, at least one component and an activation circuit adapted to deviating an input data signal into the conductive track during a test mode, and to transmitting the input data signal to the at least one component during a normal operating mode.

Abstract: A circuit and method for detecting crack damage of a die are provided. The circuit comprises: a test circuit located within a seal ring of the die for outputting a pulse detection signal; a crack detection loop arranged outside a guard ring of an internal processing circuit of the die, having an input end connected to an output end of the test circuit and an output end connected to an output pin of the die; and a relay driving unit arranged between the input end and output end for increasing a capability of transmission of the pulse detection signal, wherein the seal ring surrounds the whole die; in a test mode, the test circuit outputs the pulse detection signal to the crack detection loop, and a test machine determines whether the die is damaged by a crack by reading a signal on the output pin of the die.

Abstract: An electronic component testing apparatus is used for testing a device under test (DUT). The electronic component testing apparatus includes: a socket unit that is electrically connected to the DUT; a first wiring board; and a tester that comprises a test head in which the first wiring board is mounted. The socket unit includes a first socket and a second socket. The second socket includes a base and a test antenna unit. The tester tests the DUT by transmitting and receiving radio waves between a device antenna unit of the DUT and the test antenna unit while the DUT is electrically connected to the first socket and the first socket is electrically connected to the test head through the second socket.

Abstract: A timer circuit includes a plurality of n-type field effect transistors (NFETs) powered by a current source, a plurality of electromigration detection elements each electrically connected to a respective NFET of the plurality of NFETs, and a read-out circuit electrically connected to the plurality of electromigration detection elements to meter usage of each of the NFETs.

Abstract: A power supply for supplying a power to a heating mechanism used for heating a measurement target that emits a measurement signal includes an input device configured to output an input signal that reflects a control signal in a differentiable periodic waveform having a frequency of 1 kHz or less. The power supply includes a switching amplifier configured to amplify the input signal from the input device and output the amplified signal.

Abstract: An input capacitance measurement circuit includes a transformer, a first capacitor, a second capacitor, and a third capacitor. A primary wire of the transformer has a first end provided so as to be connectable to an anode of the semiconductor device. The primary wire of the transformer has a second end connected to a first end of the first capacitor. A secondary wire of the transformer has a first end provided so as to be connectable to a cathode of the semiconductor device. The secondary wire of the transformer has a second end connected to a first end of the second capacitor. The third capacitor has a first end provided so as to be connectable to the cathode of the semiconductor device. A second end of the first capacitor, a second end of the second capacitor, and a second end of the third capacitor are electrically connected to each other.

Abstract: A method for detecting errors or malfunctions in electrical or electronic components of circuits, wherein each of the circuits is located on a circuit board and wherein a plurality of circuit boards border one another on a circuit board panel, includes populating each of the circuit boards of the circuit board panel with electrical or electronic components corresponding to the circuits; for each of the analog, electrical or electronic components used for the construction of the circuits, placing a corresponding test component in an edge region of the circuit board panel; providing the analog, electrical or electronic test components placed in the edge region of the circuit board panel with test points; and checking for the correct function value and/or the correct poling of the analog, electrical or electronic test components provided with test points and located in the edge region of the circuit board panel.

Abstract: Various embodiments of the present disclosure are directed towards a method for non-destructive inspection of cell etch redeposition. In some embodiments of the method, a grayscale image of a plurality of cells on a wafer is captured. The grayscale image provides a top down view of the cells and, in some embodiments, is captured in situ after etching to form the cells. The cells are identified in the grayscale image to determine non-region of interest (non-ROI) pixels corresponding to the cells. The non-ROI pixels are subtracted from the grayscale image to determine ROI pixels. The ROI pixels are remaining pixels after the subtracting and correspond to material on sidewalls of, and in recesses between, the cells. An amount of etch redeposition on the sidewalls and in the recesses is then scored based on gray levels of the ROI pixels. Further, the wafer is processed based on the score.

Abstract: Techniques and mechanisms for providing interconnected circuitry of an integrated circuit (IC) die stack. In an embodiment, first integrated circuitry of a first IC die is configured to couple, via a first interconnects of the first IC die, to second integrated circuitry of a second IC die. When the first IC die and the second IC die are coupled to one another, second interconnects of the first IC die are further coupled to the second integrated circuitry, wherein the second interconnects are coupled to each of two opposite sides of the first IC die. In another embodiment, the second integrated circuitry includes processor logic, and the first integrated circuitry is configured to cache data for access by the processor logic. In another embodiment, the first integrated circuitry includes a power delivery circuit and an on-package input-output interface to cache data for access by the processor logic at higher bandwidth with lower power consumption.

Abstract: Systems, apparatuses, and methods related to a printed circuit board (PCB) with a plurality of layers are described. An edge connector may be formed on an end of the PCB substrate and may include contact pins on an outer layer of the plurality of layers. The edge connector may also include an intra-pair coupling block disposed on one or more interior layers such that at least a portion of the intra-pair coupling block is colinear with at least one contact pin on the outer layer. The electronic device may also include at least one integrated circuit on the PCB and electrically connected to the contact pins. The intra-pair coupling component may induce coupling of signals carried by the contact pins.

Abstract: A method of treatment of an electronic circuit including at a location at least one electrically-conductive test pad having a first exposed surface. The method includes the at least partial etching of the test pad from the first surface, and the forming on the electronic circuit of an interconnection level covering said location and including, on the side opposite to said location, a second planar surface adapted for the performing of a hybrid molecular bonding.

Abstract: As a semiconductor device is miniaturized, a scribe area on a wafer also tends to decrease. Accordingly, it is necessary to reduce the size of a TEG arranged in the scribe area, and efficiently arrange an electrode pad for probe contact. Therefore, it is necessary to associate probes and the efficient layout of the electrode pad. The purpose of the present invention is to provide a technique for associating probes and the layout of the electrode pads of a TEG so as to facilitate the evaluation of electrical characteristics. According to an evaluation apparatus for a semiconductor device of the present invention, the above described problems can be solved by providing a plurality of probes arranged in a fan shape or probes manufactured by Micro Electro Mechanical Systems (MEMS) technology.

Abstract: Methods and systems for selectively compressing data lines of a memory device in selective compression circuitry. The selective compression circuitry receives multiple data lines and compression circuitry that selectively compresses inputs. The selective compression circuitry also includes control circuitry to receive data over via the data lines. The control circuitry, when in a compressed mode, transmits data from each of the data lines to the compression circuitry. Alternatively, in an uncompressed mode, the control circuitry transmits data from a first subset of the data lines to the compression circuitry while blocking data from a second subset of the data lines from being transmitted to the compression circuitry.

Abstract: A test method for testing connectivity of a semiconductor structure includes operations as follows. A semiconductor structure and a detection transistor are provided. The semiconductor structure includes a through silicon via structure having a first terminal and a second terminal arranged to be opposite. An intrinsic conductivity factor of the detection transistor is obtained. The detection transistor is turned on upon receiving a test signal, and a test voltage is provided to the second terminal, to enable the detection transistor to operate in a deep triode region, and a current flowing through the second terminal is obtained during operation of the detection transistor in the deep triode region. A resistance of the through silicon via structure is obtained based on the intrinsic conductivity factor, an operating voltage, the test voltage, and the current flowing through the second terminal.

Abstract: Regulation of a voltage gradient may be provided. A plurality of test voltage values associated with a corresponding plurality of locations associated with an electronic device may be received. Then, based on the plurality of test voltage values, a target setpoint may be determined for a power supply that supplies power to the electronic device. The target setpoint may be configured to cause a maximum of voltage values at the plurality of locations to be below a maximum voltage level defined by a specification for the electronic device. The target setpoint may also be configured to cause a minimum of the voltage values at the plurality of locations to be above a minimum voltage level defined by the specification for the electronic device. The power supply may then be driven at the target setpoint.

Abstract: The fault detection system described provides an efficient method to test and monitor component to component connectivity in an electronic package using on chip test circuits and on chip components, which reduces the need for external testing equipment and analysis. The on chip nature allows for both real time testing in the assembly process of the electronic packages and during use of the electronic package by determining an on chip reference measurement and using the reference measurement to determine an operational status of the package.

Abstract: An aspect relates to an apparatus including a set of one or more receivers; a first replica circuit being a substantial replica of at least a portion of one of the set of one or more receivers; a first control circuit generates an output signal selectively coupled to an input of the first replica circuit; a second replica circuit being a substantial replica of at least a portion of one of the set of one or more receivers; a comparator including a first input coupled to a first output of the first replica circuit, a second input coupled to a second output of the second replica circuit, and an output; and a second control circuit including an input coupled to the output of the comparator, and an output coupled to the first replica circuit and to the set of one or more receivers.

Abstract: A memory temperature controlling method and a memory temperature controlling system are provided. The method includes: performing, by a testing equipment, test modes on a memory storage device, and obtaining a first internal temperature of a memory control circuit unit, a second internal temperature of each memory package and a surface temperature of each memory package to establish a linear relationship expression of the first internal temperature, the second internal temperature and the surface temperature; using, by the memory storage device, the linear relationship expression to calculate a predicted surface temperature of a rewritable non-volatile memory based on a first current internal temperature of the memory control circuit unit and a second current internal temperature of each memory package; adjusting, by the memory storage device, an operating frequency for accessing the rewritable non-volatile memory based on the predicted surface temperature.

Abstract: Provided is a method of evaluating a silicon wafer manufacturing process for mass-producing multiple silicon wafers. Lifetime measurement to silicon wafers mass-produced in the silicon wafer manufacturing process is performed in different locations within a surface of each of the silicon wafers and multiple measurement values are obtained. The representative value is determined for each of the silicon wafers from the multiple measurement values. The determination threshold is obtained for each wafer group including multiple silicon wafers using the representative value for each of the silicon wafers included in the wafer group. Whether the wafer group includes a silicon wafer having a lifetime outlier determined on the basis of the determination threshold among the multiple measurement values obtained for each of the silicon wafers is determined, and whether the manufacturing process may cause a defective product to be produced is determined.

Abstract: A TSV detecting circuit, TSV detecting methods, and an integrated circuit thereof are disclosed by the present disclosure. The TSV detecting circuit includes a first detecting module includes: a first comparison unit; a first input unit, for transmitting an input signal to a first input of the first comparison unit controlled by a first clock signal; a first switching unit for transmitting a signal of a first node to a second input of the first comparison unit controlled by a first detection control signal, the first node coupled to a first terminal of the TSV; and a second detecting module includes: a second input unit for transmitting the input signal to a second node controlled by a second clock signal; a second switching unit for transmitting a signal of the second node to a second terminal of the TSV controlled a second detection control signal.

Abstract: A wafer inspection system and a wafer inspection equipment thereof are provided. The wafer inspection system includes a susceptor device, probe card, and bridge module. The susceptor device includes a susceptor unit for placing a wafer under test. The probe card includes a probing portion and conducting portion. The conducting portion is disposed at the periphery of the probing portion and has a contact surface. The bridge module includes transmission units extended upward, positioned adjacent to a wafer placement area, and coupled to the susceptor unit. When the probing portion comes into contact with a testing point of the wafer, the contact surface of the conducting portion gets coupled to the transmission units to transmit a test signal to the probe card via the transmission units and conducting portion and thus form a test loop. Thus, the test loop path can be shortened and the accuracy of signal transmission and inspection can be enhanced.

Abstract: Aspects described herein include a method of fabricating an optical component. The method comprises electrically coupling different laser channels of a laser die to different electrical leads, testing a respective optical coupling of each of the different laser channels, optically aligning an optical fiber with a first laser channel of the different laser channels having the greatest optical coupling, and designating a second laser channel of the different laser channels as a heater element for the first laser channel.

Abstract: A method of operating a storage device includes sensing a standby current flowing through the storage device, determining based on the sensed standby current and at least one reference value whether a product abnormality has occurred within the storage device, and when it is determined the product abnormality has occurred, performing a step-wise control operation in which two or more control processes associated with an operation of the storage device are sequentially executed.

Abstract: An inspection apparatus is provided to inspect an imaging device formed on an inspection object by bringing a contact terminal into electrical contact with a wiring layer of the imaging device while causing light to enter the imaging device. The light enters the imaging device from a back surface that is a surface on the side opposite to the side on which the wiring layer is formed. The inspection apparatus includes a substrate support made of a light-transmissive material and on which the inspection object is supported such that the substrate support faces a back surface of the imaging device, and a light irradiation mechanism disposed to be opposite to the inspection object with the substrate support interposed therebetween and having a plurality of LEDs such that light from the LEDs is oriented toward the inspection object.

Abstract: One embodiment of the present invention provides a method for evaluating the electrical defect density of a semiconductor layer, which comprises: a step for measuring an electric current by applying a voltage to a semiconductor element 1 which comprises a GaN layer 12 that serves as a semiconductor layer; and a step for deriving the electrical defect density in the GaN layer 12 with use of the measured electric current value.

Abstract: A sectioned field effect transistor (“FET”) for implementing a rapidly changing sense range ratio dynamically in response to changing load and main supply conditions. The sectioned FET may have multiple main FET sections, and multiple sense FET sections. These sections can be dynamically connected and disconnected from the sectioned FET. The sections may also be connected by a common gate. There may also be common drain or source connections for the main FET sections, and also common drain or source connections for the sense FET sections. The sectioned FET allows for the sense range to be extended by a multiple of k+1, where k is the size ratio or factor of the additional sense FET sections. This allows the current sense range ratio to be extended to (m+n)/n*(k+1).

Abstract: Methods are provided that performs continuous semiconductor testing during long soak time testing using a chamberless single insertion model (SIM) handler and also using a chamberless asynchronous insertion model (AIM) handler having two manipulators. The methods include dividing a group of semiconductors having an ambient temperature into a first subgroup having a plurality of portions and a second subgroup having a plurality of portions, the second subgroup being identical to the first subgroup. The methods also include using thermal chucks to change the temperature of the first portion of the first subgroup and the first portion of a second subgroup prior to testing from ambient temperature to a stabilized designated temperature during a soak time. The methods also include testing all of the portions of the first subgroup and the second subgroup using predetermined protocols that include Soak Time, Test Time, Index Time, and sometimes Wait Time.

Abstract: A testing circuit includes a command pad, a first circuit, a second circuit, a first latch, and a second latch. The command pad receives an operation command. The first integrated circuit performs a corresponding test operation according to the operation command and an internal selection signal. The second integrated circuit performs the corresponding test operation according to the operation command and an internal selection signal. The first latch provides the operation command to the first integrated circuit according to the internal selection signal. The second latch provides the operation command to the second integrated circuit according to the internal selection signal.

Abstract: Techniques and mechanisms for providing interconnected circuitry of an integrated circuit (IC) die stack. In an embodiment, first integrated circuitry of a first IC die is configured to couple, via a first interconnects of the first IC die, to second integrated circuitry of a second IC die. When the first IC die and the second IC die are coupled to one another, second interconnects of the first IC die are further coupled to the second integrated circuitry, wherein the second interconnects are coupled to each of two opposite sides of the first IC die. In another embodiment, the second integrated circuitry includes processor logic, and the first integrated circuitry is configured to cache data for access by the processor logic. In another embodiment, the first integrated circuitry includes a power delivery circuit and an on-package input-output interface to cache data for access by the processor logic at higher bandwidth with lower power consumption.

Abstract: A current supply device includes a multiplexed digital bus, an output terminal, and a group of power supplies connected in parallel between the multiplexed digital bus and the output terminal. The group of power supplies are controlled via the multiplexed digital bus such that a combined output current of the group of power supplies is applied to the output terminal.

Abstract: A testing device includes a transmitter circuit, a receiver circuit, and a loopback circuit. The transmitter circuit is configured to receive a plurality of first test signals. The receiver circuit is configured to receive input data from a plurality of pads in a normal mode. The loopback circuit is coupled to the plurality of pads and input terminals of a sampler circuit, and the loopback circuit is configured to transmit the plurality of first test signals from the transmitter circuit to the input terminals of the sampler circuit, in order to generate test data for subsequent analysis.

Abstract: A chip testing circuit and a testing method thereof are provided. The chip testing circuit includes a parameter measurement circuit, a plurality of power supply circuits, a plurality of switch circuits, and a control circuit. The plurality of power supply circuits respectively provide power supply to a plurality of chips carried by a plurality of sockets. Each switch circuit is electrically connected between one socket and one power supply circuit. The control circuit is connected in parallel to a plurality of signal pins of the plurality of chips carried by the plurality of sockets, so that when the control circuit outputs test data, all the chips can simultaneously receive the test data. When executing a parametric test mode, the control circuit controls one of the switch circuits to be turned on and controls the parameter measurement circuit to perform an electrical performance test on the chips.

Abstract: An insulation resistance measurement device includes a jig unit, a control unit and a transfer mechanism. The jig unit includes a lower jig having a reference surface, an upper jig having an abutting surface, a probe unit and a servomotor. When the upper jig is lowered toward the lower jig by the servomotor, the probe contacts a portion to be measured. When the upper jig is lowered further and the abutting surface of the upper jig abuts the reference surface, a torque of the servomotor increases. When the torque reaches a predetermined value, an insulation resistance is measured by the probe in a state where the torque is maintained.

Abstract: Various embodiments are presented of a system including an alignment fixture for testing (e.g., rapidly and cheaply) phased array antennas and other devices configured for radio frequency (RF) transmission and/or reception. A device to be tested (e.g., the device under test (DUT)) may be positioned in a testing position by the alignment fixture. The alignment fixture may provide a configurable level of friction to retain the DUT in the testing position. The alignment fixture may provide isolation from electromagnetic interference for the DUT while in the testing position.

Abstract: A semiconductor die may include a first delay circuit formed on a substrate and configured to delay a test signal, the first delay circuit including first delay stages connected in series, a second delay circuit formed on the substrate and configured to delay the test signal, the second delay circuit including second delay stages connected in series, at least one through silicon via connected to at least one output terminal of output terminals of the first delay stages, the at least one through silicon via penetrating through the substrate, and a load determinator configured to compare a first delay signal output from one of the first delay stages with a second delay signal output from one of the second delay stages and determine a load of the at least one through silicon via.

Abstract: An organic light emitting display device includes a display part including a plurality of scan lines, a plurality of data lines, a plurality of power source lines, and a plurality of pixels each including an organic light emitting diode, a driving transistor coupled to the organic light emitting diode and to a power source line of the power source lines, and a switching transistor coupled to a scan line of the scan lines and to a data line of the data lines, and a sensing driver configured to sample a sensing current from the power source line while a sensing data voltage is applied to one of the pixels, and to calculate a threshold voltage value of the driving transistor using the sensing current in a sensing mode.

Abstract: Aspects of the invention include systems and methods directed to a portable chip tester. A non-limiting example of a system includes a housing, a printed circuit board mounted on the housing, in which the printed circuit board includes a first interface operable to permit electrical communication between the printed circuit board and a device under test. The system further includes a mount operable to enable an electrical connection with an integrated circuit, in which the integrated circuit is operable to manage testing the device under test under a testing protocol. The system further includes a power supply and a software platform that includes a memory having computer readable instructions and one or more processors for executing the computer readable instructions. The computer readable instructions controlling the processors to perform operations including directing the integrated circuit to manage testing of the device under test pursuant to the testing protocol.

Abstract: A semiconductor device includes a plurality of active area structures. One or more active devices include portions of the plurality of active area structures. A metal layer is formed on the plurality of active area structures and separated from the one or more active devices by one or more dummy gate layers. The metal layer is configured to measure, due to a change of resistance in the metal layer, a temperature of the plurality of active area structures.