Abstract: A computing system including a quantum computing device. The quantum computing device includes a Majorana island, a quantum dot (QD), an electrical ground, and a capacitance sensor. The computing system further includes a controller configured to, in each of a plurality of sampling iterations, control the quantum computing device to electrically couple the Majorana island to the electrical ground, disconnect the Majorana island from the electrical ground, electrically couple the Majorana island to the QD, scan over values of a first plunger gate voltage applied to a first plunger gate and a second plunger gate voltage applied to a second plunger gate, and output quantum capacitance measurements. The controller is further configured to receive the quantum capacitance measurements and determine a measured distribution of resonance regions associated with the sampling iterations.

Abstract: The performance of a microelectronic circuit can be configured by making an operating parameter assume an operating parameter value. An operating method comprises selectively setting the microelectronic circuit into a test mode that differs from a normal operating mode of the microelectronic circuit, and utilizing said test mode to input test input signals consisting of test input values into one or more adaptive processing paths within the microelectronic circuit. An adaptive processing path comprises processing logic and register circuits configured to produce output values from input values input to them. The performance of such an adaptive processing path can be configured by making an operating parameter assume an operating parameter value.

Abstract: According to one embodiment, a deterioration checking apparatus includes an inductor that is connected in series to a main current path of a MOS transistor to be checked, and forms a closed loop together with the MOS transistor when the MOS transistor is in an ON-state, a control circuit that controls ON/OFF of the MOS transistor, a current sensor that detects a current released from the inductor, and a calculation circuit that calculates an ON-resistance of the MOS transistor from an attenuation characteristic of a current released from the inductor when the MOS transistor is in an ON-state, and calculates a threshold voltage of the MOS transistor from an attenuation characteristic of a current released from the inductor when the MOS transistor is in an OFF-state. Therefore, it is possible to easily check a deterioration state of the MOS transistor.

Abstract: A circuit and diagnosis method capable of individually diagnosing abnormality of a plurality of internal FETs constituting a MOSFET provided between a secondary battery pack and an electric vehicle. Voltage at both ends of each of the internal FETs is measured while individually turning ON/OFF the internal FETs, and is compared with a diagnosis table in order to determine abnormality thereof.

Abstract: A design-for-test circuit for evaluating a BTI effect is disclosed, the circuit includes a number of stress generators having logic circuits with input and output terminals. Each output terminal is connected to the grid of the device to be tested. In a stress mode, a stress input signal is selected from a frequency signal, a first direct current voltage, and a second direct current voltage, all stress output signals formed by all the stress generators comprise the first direct current voltage, a series of frequency signals with different duty cycles, and the second direct current voltage, and all the stress output signals are used in combination such that the stress times regarding the device under test within the same test time have different values, so as to evaluate the BTI effect of the device under test which has different values of the stress times.

Abstract: The present invention provides a system and method for measuring an intermittent operating life (IOL) of a GaN-based device under test (DUT) is provided. The system is operable in a stressing mode, a cooling mode and a measure mode. A power regulation approach is adopted to ensure that DUT of the same thermal resistance have same temperature increase during the IOL test. The present invention eliminates the influence caused by parasitic parameters of testing circuits and the inconsistency of threshold voltage and drain-source resistance of the device itself. Through power regulation, it is the junction temperature of the device, not the housing temperature of the device, being directly controlled. Therefore, higher measurement accuracy can be achieved.

Abstract: Aspects of the present application relate to techniques for computing convolutions and cross-correlations of input matrices. A first technique is based on the transformation of convolution operations into a matrix-vector product. A second technique is based on two-dimensional matrix multiplication. A third technique is based on the convolution theorem, which states that convolutions correspond to multiplications in a transform space. Embodiments include methods for computing convolutions of a filter matrix and an input data matrix; apparatuses for computing convolutions of a filter matrix and an input data matrix; and a non-transitory computer readable medium programmed with instructions that, when executed by a processor perform a method for computing convolutions of a filter matrix and an input data matrix.

Abstract: The present invention concerns a method and device for monitoring the gate signal of a power semiconductor (SI), the gate signal of the power semiconductor (SI) being provided by a gate driver (12), generates an expected signal (VGexp) that corresponds to the signal outputted by the gate driver (12) when no deterioration of the gate driver (12) and/or of the power semiconductor (SI) and/or of a load linked to the power semiconductor (SI) exists, compares the expected signal (VGexp) and the signal (VGmeas) outputted by the gate driver (12), determines if a deterioration of the gate driver (12) and/or of the power semiconductor (SI) and/or of a load linked to the power semiconductor (SI) exists using the result of the comparing of the expected signal (VGexp) and the signal (VGmeas) outputted by the gate driver (12).

Abstract: An unbalanced failure detector circuit according to one aspect of the present disclosure is provided for detecting an unbalanced failure of an electronic device apparatus including electronic devices, and the electronic device apparatus includes a plurality of current paths connected in parallel. The unbalanced failure detector circuit includes a detector unit, and a controller. The detector unit has a plurality of coils connected in series and arranged to surround the plurality of current paths, respectively, and is configured to output a coil sum voltage which is a sum of induced voltages generated across the plurality of coils by currents flowing through the plurality of current paths. The controller is configured to detect the unbalanced failure of the electronic device apparatus when the coil sum voltage outputted from the detector unit exceeds a predetermined value range.

Abstract: Provided is a circuit including a switching transistor having a control terminal configured to receive a control signal and having a current flow path therethrough. The switching transistor becomes conductive in response to the control signal having a first value. The current flow path through the switching transistor provides a current flow line between two nodes. In a non-conductive state, a voltage drop stress is across the switching transistor. The circuit comprises a sense transistor that is coupled to and a scaled replica of the switching transistor. The sense transistor has a sense current therethrough. The sense current is indicative of the current of the switching transistor. The circuit includes coupling circuitry configured to apply the voltage drop stress across the sense transistor in response to the switching transistor being non-conductive. In the non-conductive state, the voltage drop stress is replicated across both the switching transistor and the sense transistor.

Abstract: A method is provided to increase processor frequency in an integrated circuit (IC). The method includes identifying a gate included in the IC, the gate having a gate threshold voltage and performing a plasma process to form an antenna signal path in signal communication with the gate. The method further comprises adjusting the plasma process or circuit design to increase plasma induced damage (PID) applied to the gate so as to alter the gate threshold voltage.

Abstract: In an ignition apparatus, a deterioration determination circuit performs a deterioration determination task of (i) monitoring an absolute increase in a temperature parameter during a predetermined deterioration detection period that has been started since an energization command signal being inputted to a control circuit, and (ii) performing a comparison between the absolute increase in the temperature parameter and a predetermined deterioration detection threshold to thereby determine whether a level of deterioration of a switching circuit is within an acceptable level.

Abstract: A power switch circuit with current sensing is disclosed. The power switch circuit is coupled between an input voltage and an output terminal. The power switch circuit includes a power switch, a first sensing switch, an adjusting circuit and a second sensing switch. The power switch is coupled to the input voltage. The first sensing switch is coupled in series between the power switch and the output terminal. There is a first node between the first sensing switch and the power switch. The adjusting circuit is coupled to the first node. The second sensing switch is coupled between the adjusting circuit and the output terminal. A control terminal of the power switch is coupled to a first control voltage. Control terminals of the first sensing switch and the second sensing switch are coupled to a second control voltage. The second control voltage is different from the first control voltage.

Abstract: A sectioned field effect transistor (“FET”) for implementing a rapidly changing sense range ratio dynamically in response to changing load and main supply conditions. The sectioned FET may have multiple main FET sections, and multiple sense FET sections. These sections can be dynamically connected and disconnected from the sectioned FET. The sections may also be connected by a common gate. There may also be common drain or source connections for the main FET sections, and also common drain or source connections for the sense FET sections. The sectioned FET allows for the sense range to be extended by a multiple of k+1, where k is the size ratio or factor of the additional sense FET sections. This allows the current sense range ratio to be extended to (m+n)/n*(k+1).

Abstract: The present disclosure provides a method for preparing a semiconductor device. The semiconductor device includes a substrate, a first region, a second region, a third region, a fourth region, a fifth region and a sixth region. The first type region is disposed on the substrate and has a ring structure. The second type region is disposed on the substrate and disposed in the center of the first type region. A plurality of second well regions are formed in the first region, the second region, the fourth region, the fifth region and the sixth region. A plurality of second well regions in the first region, the second region, the fourth region, the fifth region and the sixth region. The first well region, the second well region, the first type region and the second type region are formed by ion implantation.

Abstract: Provided is a testing apparatus for testing a semiconductor device including a first main terminal to which a first power source voltage is applied and a second main terminal to which a second power source voltage is applied, comprising: a condition setting unit for setting a changing speed of a terminal voltage of the first main terminal at turn-off of the device; an operation controlling unit for turning off the device under a condition set by the condition setting unit; and a determining unit for screening the device based on an operation result of the device, wherein: a time waveform of the terminal voltage at turn-off of the device includes a maximum changing point where a changing speed becomes maximum; and the condition setting unit sets the changing speed at a first set voltage higher than a voltage at the maximum changing point, to a predetermined value.

Abstract: Embodiments according to the invention can provide methods of testing a SiC MOSFET, that can include applying first and second voltage levels across a gate-source junction of a SiC MOSFET and measuring first and second voltage drops across a reverse body diode included in the SiC MOSFET responsive to the first and second voltage levels, respectively, to provide an indication of a degradation of a gate oxide of the SiC MOSFET and an indication of contact resistance of the SiC MOSFET, respectively.

Abstract: An electrical combination, a motorized device system, a motor assembly, a battery pack, and operating methods. The combination may include an electrical device including a device housing, a load supported by the device housing, the load being operable to output at least about 1800 watts (W), and a device terminal electrically connected to the load; a battery pack including a pack housing, battery cells supported by the pack housing, the battery cells being electrically connected and having a nominal voltage of up to about 20 volts, and a pack terminal electrically connectable to the device terminal to transfer current between the battery pack and the electrical device; and a controller operable to control the transfer of current.

Abstract: A test system, a method for manufacturing an electronic device, and a method for testing a wafer or electronic device that includes coupling a transistor in a series circuit with a capacitor and a resistor, coupling a voltage source to the capacitor to charge the capacitor to a non-zero DC voltage while the transistor is turned off, disconnecting the voltage source from the capacitor while the transistor is turned off, turning the transistor on while the voltage source is disconnected from the capacitor, measuring a voltage signal across the resistor while the transistor is turned on, and determining a test result indicating whether the transistor has an acceptable dynamic on-state resistance according to the voltage signal across the resistor.

Abstract: Systems and methods for providing VCONN to configuration channel line in USB-interface, involving a sense switch and a VCONN switch coupled with the VCONN supply and a gate control unit; an over current protection (OCP) reference current unit configured to provide a predetermined current through the sense branch; a preamplifier configured to amplify a differential voltage between source terminal voltages of the sense switch and the VCONN switch; an Over Current detection comparator configured to generate an Over Current fault signal when the source terminal voltage at the VCONN switch is lower than the source terminal voltage at the sense switch; and a control unit configured to: activate, upon receipt of the generated Over Current fault signal, the gate control unit, wherein the gate control unit, upon activation, is configured to disable the sense switch and the VCONN switch respectively to protect the VCONN and CC_P from over current.

Abstract: A method for testing and analyzing a display panel, comprising: providing a display panel including a circuitry and a pixel connected to the circuitry, wherein the pixel includes a capacitor, a transistor and an electrode electrically connected to the capacitor and the transistor; measuring a first parameter of the display panel; disabling the pixel; measuring a second parameter of the display panel; and deriving a third parameter of the pixel by subtracting the second parameter from the first parameter.

Abstract: Various embodiments provide a health monitor circuit including an n-type sensor to determine a first health indicator associated with n-type transistors of a circuit block and a p-type sensor to determine a second health indicator associated with p-type transistors of the circuit block. The n-type sensor and p-type sensor may be on a same die as the circuit block. The health monitor circuit may further include a control circuit to adjust one or more operating parameters, such as operating voltage and/or operating frequency, for the circuit block based on the first and second health indicators. Other embodiments may be described and claimed.

Abstract: An example method provides a power MOSFET, a voltage source coupled to the power MOSFET, and a current measurement device coupled to a first non-control terminal of the power MOSFET. The voltage source, the current measurement device, and a second non-control terminal of the power MOSFET couple to ground. The method uses the voltage source to apply a voltage between a gate terminal and the second non-control terminal of the power MOSFET, the voltage greater than zero volts and less than a threshold voltage of the power MOSFET. The method also uses the current measurement device to measure a first current flowing through the first non-control terminal while applying the voltage. The method further uses the first current to predict a second current through the first non-control terminal for a voltage between the gate terminal and the second non-control terminal that is approximately zero.

Abstract: Semiconductor device structures and techniques are provided for measuring contact resistance. A semiconductor device is disclosed including a first source/drain region and a contact disposed on the first source/drain region and configured to supply energy to the semiconductor device. A fin extends between the first source/drain region and a second source/drain region of the semiconductor device. A first contact material layer is disposed on the second source/drain region and a first active drain contact is disposed on the first contact material layer. A first sensor drain contact is also disposed on the first contact material layer. A second contact material layer is disposed on the second source/drain region and a second active drain contact is disposed on the second contact material layer. A third contact material layer is disposed on the second source/drain region and a second sensor drain contact is disposed on the third contact material layer.

Abstract: The present disclosure provides a semiconductor device and a method for preparing the same. The semiconductor device includes a substrate, a first type region, and a second type region. The first type region is disposed on the substrate and has a ring structure. The second type region is disposed on the substrate and disposed in the center of the first type region. The second type region has a square shape and includes a plurality of corners.

Abstract: Systems and methods for testing radio frequency FET switches at high RF voltages. Embodiments utilize an impedance transformer, or resonator, to step up the available voltage from an RF signal generator and amplifier to a device under test (DUT). The resonator reduces the RF power required to test at higher voltages, resulting in lower cost and other benefits. When a DUT begins to exhibit excessive non-linear distortion, resonance is lost, applied RF test signal power is reflected back as a reflected signal, and current to the DUT is starved by the resonator, protecting the DUT from destructive power levels. Measuring the amplitude of the reflected signal at the harmonic frequencies of the RF test signal allows detection of a harmonic knee point for selected reflected signal harmonics, and consequently allows determination of the power level of the RF test signal at which excessive non-linear distortion occurs.

Abstract: Embodiments are directed to a system for measuring a degradation characteristic of a plurality of electronic components. The system includes a parallel stress generator communicatively coupled to the plurality of electronic components, and a serial electronic measuring component communicatively coupled to the plurality of electronic components. The parallel stress generator is configured to generate a plurality of stress signals, apply the plurality of stress signals in parallel to the plurality of electronic components and remove the plurality of stress signals from the plurality of electronic components. The serial electronic measuring component is configured to, subsequent to the removal of the plurality of stress signals, sequentially measure the degradation characteristic of each one of the plurality of electronic components in order to determine their degradation resulting from the applied stress signals.

Abstract: A probe card includes a printed circuit board (PCB), a connection substrate electrically connected with the PCB, a probe head, and a signal path switching module disposed on a lateral periphery surface or a bottom surface of the connection substrate, electrically connected with probe needles of the probe head and the connection substrate and including first and second circuit lines with first and second inductors respectively, and a capacitor electrically connected between the first and second circuit lines. A test signal from a tester is transmitted between the tester and a device under test (DUT) via the PCB, the connection substrate, the first and second circuit lines and the probe needles. A loopback test signal from the DUT is transmitted back to the DUT via the probe needles, parts of the first and second circuit lines and the capacitor.

Abstract: A method and circuit of monitoring an effective age of a target circuit are provided. A standby mode is activated in the target circuit. A standby current of a first number of circuit blocks of the target circuit is measured. The measured standby current of the first number of circuit blocks is compared to a first baseline standby current of the first number of circuit blocks. Upon determining that the measured standby current of the first number of circuit blocks is below a first predetermined factor of a baseline standby current of the first number of circuit blocks, the first number of circuit blocks is identified to have a bias temperature instability (BTI) degradation concern.

Abstract: A voltage generation circuit, having a circuit scale significantly reduced as compared with the related art, is provided. The voltage generation circuit of the disclosure includes a charge pump outputting a boosted voltage to an output node, a resistor connected between the output node and another output node, and a current source circuit having first and second current paths connected in parallel between the another output node and a reference potential. The first current path includes a resistor and a first DAC. The first DAC generates a first constant current corresponding to a voltage generation code. The second current path includes a second DAC. The second DAC generates a second constant current corresponding to a code obtained by inverting the voltage generation code. Thereby, a driving voltage obtained by lowering the boosted voltage is generated at the other output node.

Abstract: A measurement apparatus (1) comprising a high frequency measurement unit (2) adapted to measure high frequency parameters (HFP) of a device under test (DUT) connected to ports of said measurement apparatus (1) and a multimeter unit (3) adapted to measure DC characteristics parameters (DCP) of said device under test (DUT) connected via control signal lines (CL) to a control bus interface (6) of said measurement apparatus (1).

Abstract: A detection method and a detection device of a display pane are provided. The detection method includes: detecting an actual value of an electric signal at a first electrode of a driving transistor in each of pixel units when the display panel reaches target brightness, the electric signal including a current signal and/or a voltage signal; and determining according to the actual value of the electrical signal corresponding to each of the pixel units, whether each of the pixel units is defective. The present disclosure may help an operator determine if each of the pixel units is defective quickly.

Abstract: An electronic apparatus for testing an integrated circuit (IC) that includes a ring oscillator is provided. The apparatus configures the ring oscillator to produce oscillation at a first frequency and configures the ring oscillator to produce oscillation at a second frequency. The apparatus then compares the second frequency with an integer multiple of the first frequency to determine a resistive voltage drop between a voltage applied to the IC and a local voltage at the ring oscillator. The ring oscillator has a chain of inverting elements forming a long ring and a short ring. The ring oscillator also has an oscillation selection circuit that is configured to disable the short ring so that the ring oscillator produces a fundamental oscillation based on signal propagation through the long ring and enable the short ring so that the ring oscillator produces a harmonic oscillation based on a signal propagation through the short ring and the long ring.

Abstract: A test circuit, a test method, an array substrate and a manufacturing method thereof are provided. The test circuit includes a plurality of to-be-tested units and plurality of test electrodes connected to the to-be-tested units. The plurality of to-be-tested units are arranged in a matrix. At least one of the test electrodes is multiplexed by the plurality of to-be-tested units in a row direction and at least one of the test electrodes is multiplexed by the plurality of to-be-tested units in a column direction.

Abstract: A pulse laser test system including a conditioning pulse circuit, a probe pulse circuit, a pulse laser, a trigger mode controller, and a laser pulse modulator. The conditioning pulse circuit provides asynchronous conditioning trigger pulses at a selected rate. The probe pulse circuit provides a synchronized probe trigger pulse. The trigger mode controller selects the probe pulse circuit while the synchronized probe trigger pulse is provided causing the pulse laser to provide a synchronized probe laser pulse, and otherwise selects the output of the conditioning pulse circuit causing the pulse laser to provide asynchronous conditioning laser pulses. The laser pulse modulator has an optical input coupled to the laser output of the pulse laser, has a gating input receiving a gate signal from the trigger mode controller, and has an optical output that provides laser pulses passed from the pulse laser while the gate signal is asserted.

Abstract: Fermi filter field effect transistors having a Fermi filter between a source and a source contact, systems incorporating such transistors, and methods for forming them are discussed. Such transistors may include a channel between a source and a drain both having a first polarity and a Fermi filter between the source and a source contact such that the Fermi filter has a second polarity complementary to the first polarity.

Abstract: Disclosed is a method for optimizing a wetting current, for a device for monitoring sensors with contact switches including a current source and at least two switch/resistor assemblies (CT1/R1, CT2/R2) in parallel, including the following steps: the current source (A) supplies the circuit with a nominal current; if a voltage (Vm) measured across the terminals of the switch/resistor assemblies is greater than a threshold voltage (Vs), the threshold voltage being lower than the supply voltage of the current source and than the saturation voltage of the analog-to-digital converter (CAN), then the current source is stopped and a unit for discharging the circuit are implemented; and the current source supplies the circuit again with a supply current (Iwet_c) equal to the nominal current reduced by a predetermined increment. These two last steps are repeated until the measured voltage is lower than the threshold voltage.

Abstract: A computer-implemented method capable of evaluating a plasma-induced charging effect to a transistor in a plasma-based process for a dielectric layer performed above the transistor on which a metal layer is formed is provided. The method may include receiving parameters relating to the transistor, receiving parameters relating to an interconnection, receiving parameters relating to the plasma-based process, assigning first potentials to terminals of the transistor, calculating second potentials at the terminals of the transistor, and determining a degradation state of the transistor according to the second potentials at the terminals of the transistor.

Abstract: A system is disclosed which provides a dynamic current limit circuit that accurately defines both the lower and the upper limits for the current limit. The circuit ensures both the lower and upper current limits are well-controlled. The lower current limit is matched to the normal pulse-frequency modulation (PFM) limit, and the upper current limit is matched to the pulse-width modulation (PWM) limit. This implementation has several key benefits, including making the peak current limit accurate in both sync and dynamic sleep modes. If the scheme is carefully designed, the dynamic sleep current limit gives the best load transient response.

Abstract: A threshold voltage measuring device may include a metal-oxide-semiconductor (MOS) transistor, a drain voltage clamping circuit configured to control a drain voltage of the MOS transistor wherein the drain voltage having a substantially constant level, and a constant current supply circuit configured to cause a drain-source current to flow through the MOS transistor wherein the drain-source current having a substantially constant magnitude.

Abstract: An integrated-circuit design tool system capable of minimizing a plasma induced charging effect to a transistor in a plasma-based process performed for a dielectric layer on a metal layer comprises a pre-processing unit, a charging evaluator engine, a charging eliminator engine, a post-processing unit, and a non-transitory computer readable medium.

Abstract: A method performed at least partially by a processor includes performing a test sequence. In the test sequence, a test pattern is loaded into a circuit. The test pattern is configured to cause the circuit to output a predetermined test response. A test response is unloaded from the circuit after a test wait time period has passed since the loading of the test pattern into the circuit. The unloaded test response is compared with the predetermined test response.

Abstract: An amplifier system having: an amplifier having a linear operating region where an output signal produced by the amplifier at the output terminal has a power level increasing proportionally with the increasing input signal power level up to a compression region of the amplifier where the output power is inhibited from increasing with increasing input signal power; and a DC current limiting circuit, coupled between a DC power supply and the amplifier, to: supply DC current from the DC power supply that is equal to quiescent current to the amplifier from the DC power supply when the amplifier operates in the linear region; enable the amplifier to draw increasing DC current from the DC power supply above the quiescent current with increasing input signal power until the output signal power reaches the desired compression point level which is lower than that of a stand-alone amplifier without the DC current limiting circuit; and, then limits the current drawn by the amplifier from the DC power supply.

Abstract: Transistors degrade when subjected to voltage stress. Methods are described for reducing this aging problem by applying a reverse voltage to the gates of the circuit on an intermittent or periodic basis. By applying such a voltage for a brief period of time such as one second, the aging process is essentially nullified.

Abstract: Described are test structures and methods for measuring silicon thickness in fully depleted silicon-on-insulator technologies.

Abstract: A preferred method for efficiently tuning RF ports while avoiding conventional labor intensive, step-by-step processes is disclosed. The method may use at least three tuning blocks (comprised of capacitors and inductors) in a series topology and at least three tuning blocks in a shunt topology. These tuning blocks will yield two circles that can be charted on the Smith chart. Those circles may then be centered along the centerline of the Smith chart to adjust for latency, and then expanded to adjust for the losses. Once those circles have been expanded, the circle (either series or shunt) that encompasses one the Smith chart reference circles is used and the traditional Smith chart methodology can be used to tune the RF port.

Abstract: A power amplifier (PA) system includes an amplifying transistor having a base, a collector, and an emitter. The PA system further includes a radio-frequency (RF) input configured to receive an RF input signal having an RF component and a DC bias component, a bias circuit coupled to the base of the amplifying transistor, and a bias tee circuit configured to receive the RF input signal and pass at least a portion of the DC component to the bias circuit and at least a portion of the RF component to the base of the amplifying transistor.

Abstract: Circuits comprising: digital-to-amplitude converter (DAC), comprising: binary weighted switching transistors (BWSTs), each having gate coupled to amplitude control bit ACB, and wherein the drain of each of the BWSTs are connected together and wherein the source of each of the BWSTs are connected together; transistor M1 having gate coupled to input signal and first bias voltage BV1 and source coupled to the drains of the BWSTs; transistor M2 having gate coupled to BV2 and source coupled to the drain of M1; transistor M3 having gate coupled to BV3 and source coupled to the drain of M2; transistor having gate coupled to BV4, source coupled to the drain of M3; and inverter having input coupled to another ACB and having output coupled to the output of the DAC and the drain of M4.

Abstract: A static random access memory (SRAM) includes a first bitcell and a second bitcell. The first bitcell includes an aging transistor and the second bitcell includes a non-aging transistor. An aging sensor is coupled between the first bitcell and the second bitcell to determine an amount of aging associated with the aging transistor. In one aspect, the amount of aging associated with the aging transistor is determined based on a difference between a voltage or current associated with the aging transistor and a voltage or current associated with the non-aging transistor.

Abstract: Electrical conductance measurement system including a one-dimensional semiconducting channel, with electrical conductance sensitive to electrostatic fluctuations, in a circuit for measuring channel electrical current. An electrically-conductive element is disposed at a location at which the element is capacitively coupled to the channel; a midpoint of the element aligned with about a midpoint of the channel, and connected to first and second electrically-conductive contact pads that are together in a circuit connected to apply a changing voltage across the element. The electrically-conductive contact pads are laterally spaced from the midpoint of the element by a distance of at least about three times a screening length of the element, given in SI units as (K?0/e2D(EF))1/2, where K is the static dielectric constant, ?0 is the permittivity of free space, e is electron charge, and D(EF) is the density of states at the Fermi energy for the element.