METHOD OF MANUFACTURING THREE-DIMENSIONAL NANOCHANNEL DEVICE
A method of manufacturing a three-dimensional nanochannel device is provided. In the method, a first insulation layer is formed on a substrate, a first opening is formed in the first insulation layer, and a patterned photoresist is formed on the first insulation layer. The patterned photoresist includes at least one second opening, wherein the second opening is adjacent to the first opening and exposes the first insulation layer. Afterwards, the first insulation layer is etched and the substrate is also continued to be etched by using the patterned photoresist as a mask, so as to form a housing space, wherein a depth of the housing space is at least two orders greater than a thickness of the first insulation layer. Thereafter, the patterned photoresist is removed, and a second insulation layer is formed on a surface of the substrate.
This application is a divisional of and claims priority benefit of U.S. application Ser. No. 13/205,640, filed on Aug. 9, 2011, now allowed, which claims the priority benefit of Taiwan application serial no. 100112991, filed Apr. 14, 2011. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
TECHNICAL FIELDThe disclosure relates to a method of manufacturing a three-dimensional nanochannel device.
BACKGROUNDIn March 2010, the Health Care and Education Reconciliation Act was passed in the United States, and personalized health care was included in this Act. The testing of biomarkers is one of the key technologies in personalized healthcare. Currently, concentrations of biomarkers range from 101 to 10−12 mg/mL (ppt), including as high as 13 orders of magnitude. For thousands of testing procedures, each of them should be completed with 50-500 nanoliters (nL) of blood plasma; in such volumes, the numbers of molecules which have very low concentrations are relatively rare. However, for the testing of low-concentration samples, the volumes of the specimens is too little to become invalid samples. Therefore, a microchannel which is able to both contain sufficient samples and rapidly concentrate biomarkers is important for testing.
Dielectrophoresis is a kind of method to effectively concentrate protein. However, dielectrophoresis with metal electrode has problems such as electrode hydrolysis, low concentration efficiency, and generation of joule heat. In recent years, electrode-less dielectrophoresis has been developed to resolve the problems in dielectrophoresis with metal electrode. According to the dielectrophoresis equation (FDEP=2πa3εmRe(K*(ω))∇E2), in order to generate enough dielectrophoretic force, a great enough electric field gradient is required. Electrode-less dielectrophoresis mainly uses a structural design to generate a condensed electric field. There are different designs such as a rectangle, a column, and a triangle. The use of a design of a triangular condensed structure which is able to completely concentration the sample at a structural limiting space is the most efficient condensing method. However, since a nanostructure is manufactured by electron beam lithography, when used in conjunction with a channel about 100 nm deep, a reaction volume is only at the picoliter (pL) level. The molecular sizes of some biomarkers are about several tens of nanometers. However, in such low reaction volumes, for the testing of very low concentrations, the number of molecules included in such volumes is relatively reduced, even to zero.
SUMMARYA method of manufacturing a three-dimensional nanochannel device is further introduced herein. In the method, a first insulation layer is formed on a substrate, a first opening is formed in the first insulation layer, and a patterned photoresist is formed on the first insulation layer. The patterned photoresist includes at least one second opening, wherein the second opening is adjacent to the first opening and exposes the first insulation layer. Afterwards, the first insulation layer is etched and the substrate is also continued to be etched by using the patterned photoresist as a mask, so as to form a housing space, wherein a depth of the housing space is at least two orders greater than a thickness of the first insulation layer. Thereafter, the patterned photoresist is removed, and a second insulation layer is formed on a surface of the substrate.
A method of manufacturing a three-dimensional nanochannel device is yet introduced herein. In the method, a silicon chip is etched to form a condensed channel through the silicon chip because different lattice planes have different etch rates. The sizes of the condensed channel on the X-Y plane and the X-Z plane are shrunken at least two orders in scale.
In order to make the aforementioned and other objects, features and advantages of the disclosure comprehensible, embodiments accompanied with figures are described in detail below.
The accompanying drawings are included to provide further understanding, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments and, together with the description, serve to explain the principles of the disclosure.
In the following description, please refer to the accompanying drawings, so that the embodiments of the disclosure may be illustrated more fully. However, the disclosure may be implemented in multiple different manners and is not limited to the embodiments described herein. In addition, for the sake for clarity, sizes or relative sizes of layers and areas shown in the drawings may not be drawn to scale.
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A difference between the first size S1 and the second size S2 is about at least two orders in scale, and a difference between the third size S3 and the fourth size S4 is about at least two orders in scale. For example, the profile of the condensed channel 214 on the X-Y plane may be gradually shrunken from the first size S1 of several hundreds of micrometers to the second size S2 of several hundreds of nanometers (as shown in
Moreover, the three-dimensional nanochannel device according to above exemplary embodiments may be manufactured by any suitable process. In point of manufacturing costs, the device may be fabricated by the following method.
First, a substrate 300 such as a silicon chip is provided, and an insulation layer 302 of an oxide layer which is, for example, several hundred nanometers thick is deposited on the substrate, as shown in
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The above processes only describes one of the methods of manufacturing the three-dimensional nanochannel device 100 in
Moreover, a number, a shape, and an arrangement of the channel 108 and a number and a shape of the condensed channel 114 of the three-dimensional nanochannel device may all be altered, as long as the sizes on the X-Y plane and the X-Z plane are both reduced. By utilizing three dimensional channel designs, the electric field generates a regional high electric field greater than a conventional 2D device, thereby achieving the purpose of fixed-amount concentration.
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In the condensed channel 400 shown in
Moreover, the positions where the condensed channels 114 in the three-dimensional nanochannel device 100 have the smallest sizes are between the channel layers 106 and the second substrate 102, as shown in
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The following describes multiple simulation experiments to verify the effects described in the disclosure.
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- Simulation experiments
- Simulation voltage: 10 Vp-p
- Simulation frequency: 10 kHz
- Configured channel width: 500 μm
- Comparative embodiment: when the channel device only has a reduction in size on the X-Y plane, as shown in
FIG. 9 , a dielectrophoretic force in the X direction (FDEP-X) equals 8 fN, and a dielectrophoretic force in the Y direction (FDEP-y) equals 8 fN. - Experimental embodiment: however, for a device which utilizes the three-dimensional nanochannel device according to the disclosure (as shown in
FIG. 10 ), not only does FDEP-X reach 800 fN and FDEP-y reach 800 fN, an effect of having a dielectrophoretic force in the Z direction (FDEP-z) of 80 fN is also achieved since there is also an electric field gradient on the X-Z plane.
In summary, compared with conventional dielectrophoresis technologies, the disclosure not only further includes the condensation structure in the Z direction, so that condensation of the electric field is more efficient, but also omits the use of expensive nanoprocess technologies. By using technologies such as polymer rollover, a condensed electric field that reaches 107 V/m is able to be generated. More importantly, the three-dimensional structure increases the reactive volume to the nanoliter level, so that a sufficient number of molecules is provided for detection.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims and their equivalents.
Claims
1. A method of manufacturing a three-dimensional nanochannel device, comprising:
- forming a first insulation layer on a substrate;
- forming a first opening in the first insulation layer;
- forming a first patterned photoresist on the first insulation layer, the patterned photoresist comprises at least one second opening, wherein the second opening is adjacent to the first opening and exposes the first insulation layer;
- etching the first insulation layer and continuing to etch the substrate by using the patterned photoresist as a mask, so as to form a housing space, wherein a depth of the housing space is at least two orders greater than a thickness of the first insulation layer;
- removing the patterned photoresist; and
- forming a second insulation layer on an etched surface of the substrate.
2. The method of manufacturing the three-dimensional nanochannel device as claimed in claim 1, wherein the substrate comprises a silicon chip, and the first insulation layer comprises an oxide layer.
3. The method of manufacturing the three-dimensional nanochannel device as claimed in claim 1, wherein a bottom of the housing space is smaller than a top of the housing space.
4. A method of manufacturing a three-dimensional nanochannel device, comprising:
- etching a silicon chip, so as to form a condensed channel through the silicon chip because different lattice planes in the silicon chip have different etch rates, wherein sizes of the condensed channel on an X-Y plane and sizes of the condensed channel on an X-Z plane are shrunken at least two orders in scale.
5. The method of manufacturing the three-dimensional nanochannel device as claimed in claim 4, wherein the condensed channel is completed by utilizing a single wet etching process.
Type: Application
Filed: Jul 22, 2013
Publication Date: Nov 21, 2013
Applicant: Inndustrial Technology Research Institute (Hsinchu)
Inventors: Liang-Ju Chien (Kaohsiung City), Chi-Han Chiou (Tainan City)
Application Number: 13/948,154
International Classification: B44C 1/22 (20060101);