Forming Groove Or Hole In A Substrate Which Is Subsequently Filled Or Coated Patents (Class 216/39)
  • Patent number: 11402209
    Abstract: According to one embodiment, a sensor includes a movable member including a first movable portion and a second movable portion, and a first fixed member. At least a portion of the first fixed member is between the first movable portion and the second movable portion. The first fixed member includes a first fixed counter portion opposing the first movable portion, and a second fixed counter portion opposing the second movable portion. The first fixed counter portion includes a first fixed protruding portion protruding toward the first movable portion. The second fixed counter portion includes a second fixed protruding portion protruding toward the second movable portion.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: August 2, 2022
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shiori Kaji, Ryunosuke Gando, Yasushi Tomizawa, Kei Masunishi, Tamio Ikehashi
  • Patent number: 11264246
    Abstract: An etching method is provided for selectively etching a first region of silicon oxide with respect to a second region of silicon nitride by performing plasma processing on a target object including the first region and the second region. In the etch method, first, a plasma of a processing gas including a fluorocarbon gas is generated in a processing chamber where the target object is accommodated. Next, the plasma of the processing gas including the fluorocarbon gas is further generated in the processing chamber where the target object is accommodated. Next, the first region is etched by radicals of fluorocarbon contained in a deposit which is formed on the target object by the generation and the further generation of the plasma of the processing gas containing the fluorocarbon gas. A high frequency powers used for the plasma generation is smaller than a high frequency power used for plasma further generation.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: March 1, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hikaru Watanabe, Akihiro Tsuji
  • Patent number: 11227790
    Abstract: One or more photonic structures are formed within one or more layers over a surface of a substrate, and multiple trenches are formed through the one or more layers housing devices coupled to one or more of the photonic structures. The trenches may include: a first trench that has a bottom surface within the substrate that has a first surface topology characterized by a first surface roughness at a first depth within the substrate relative to the surface of the substrate, and a second trench that has a bottom surface within the substrate that has a second surface topology characterized by a second surface roughness at a second depth within the substrate relative to the surface of the substrate. The first surface roughness may be greater than the second surface roughness, and the second depth may be greater than the first depth.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: January 18, 2022
    Assignee: Ciena Corporation
    Inventors: Benoît Filion, Charles Baudot, François Pelletier, Christine Latrasse
  • Patent number: 11178781
    Abstract: This application relates to a composite part that can include a non-metal layer having attachment features, and a metal part that is joined with the non-metal layer. The metal part can include a plurality of interlocking structures that are disposed at an external surface of the metal part, where each of the interlocking structures can include an opening characterized as having a first width, and an undercut region, where the opening leads into the undercut region, and the undercut region is characterized as having a second width that is greater than the first width such that the undercut region captures and retains one of the attachment features of the non-metal layer.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: November 16, 2021
    Assignee: Apple Inc.
    Inventors: Todd S. Mintz, Shi Hua Zhang, Abhijeet Misra, Eric W. Hamann
  • Patent number: 11139272
    Abstract: A method of forming a bonded assembly includes providing a first semiconductor die containing a first substrate, first semiconductor devices, and first bonding pads that are electrically connected to a respective node of the first semiconductor devices, forming a first oxidation barrier layer on physically exposed surfaces of the first bonding pads, providing a second semiconductor die containing a second substrate, second semiconductor devices, and second bonding pads that are electrically connected to a respective node of the second semiconductor devices, and bonding the second bonding pads to the first bonding pads with at least the first oxidation barrier layer located between the respective first and second bonding pads.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: October 5, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Raghuveer S. Makala, Johann Alsmeier
  • Patent number: 10818678
    Abstract: A three-dimensional semiconductor memory device includes a substrate including a peripheral circuit region and a cell array region, a plurality of peripheral gate stacks disposed in the peripheral circuit region, and an electrode structure disposed in the cell array region. The electrode structure includes a lower electrode, a lower insulating layer disposed on the lower electrode, and upper electrodes and upper insulating layers alternately stacked on the lower insulating layer. The lower insulating layer extends from the cell array region into the peripheral circuit region and covers the peripheral gate stacks. The lower insulating layer includes a first lower insulating layer and a second lower insulating layer sequentially stacked on one another. The first lower insulating layer includes a first insulating material, and the second lower insulating layer includes a second insulating material different from the first insulating material.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: October 27, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Min Hwang, Dong-Sik Lee, Joon-Sung Lim
  • Patent number: 10629480
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first layer over a second layer. The method includes forming a first recess and a second recess in the first layer. The first recess is narrower than the second recess. The method includes forming a first covering layer in the first recess and the second recess. The first covering layer in the first recess is thinner than the first covering layer in the second recess. The method includes removing the first covering layer in the first recess and the first covering layer covering the first bottom surface to form a first opening in the first covering layer in the second recess. The method includes removing the first portion and the second portion through the first recess and the first opening.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Xi-Zong Chen, Chih-Hsuan Lin, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu
  • Patent number: 10504726
    Abstract: A nanoscale structure includes an array of pillars over an underlying layer, a separation wall layer including first separation walls formed over sidewalls of the pillars, and a block co-polymer (BCP) layer formed over the separation wall layer and filling gaps between the pillars. The BCP layer is phase-separated to include first domains that provide second separation walls formed over the first separation walls and second domains that are separated from each other by the first domains.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: December 10, 2019
    Assignee: SK HYNIX INC.
    Inventors: Keun Do Ban, Jung Gun Heo, Cheol Kyu Bok, Myoung Soo Kim
  • Patent number: 10446665
    Abstract: Embodiments of the present invention provide methods and structures for protecting gates during epitaxial growth. An inner spacer of a first material is deposited adjacent a transistor gate. An outer spacer of a different material is deposited adjacent the inner spacer. Stressor cavities are formed adjacent the transistor gate. The inner spacer is recessed, forming a divot. The divot is filled with a material to protect the transistor gate. The stressor cavities are then filled. As the gate is safely protected, unwanted epitaxial growth (“mouse ears”) on the transistor gate is prevented.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: October 15, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xiuyu Cai, Ying Hao Hsieh
  • Patent number: 10355268
    Abstract: A carbon-metal oxide composite material comprising: (i) carbon-carbon composite particles in which an amorphous carbon black core is bonded to crystalline graphitic carbon shells; and (ii) a metal oxide material bonded with said carbon-carbon composite particles, wherein said metal oxide material is included in an amount of at least about 10 wt. % by weight of said carbon-carbon composite particles and metal oxide material. Alkali-ion batteries containing the above-described composite as anode are also described. Methods for producing the above-described composite are also described. The method can include, for example, subjecting pulverized rubber tire waste to a sulfonation process and pyrolyzing the sulfonated rubber to produce the carbon-carbon composite particles, as described above, followed by admixing and compounding a metal oxide material with the carbon-carbon composite particles.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: July 16, 2019
    Assignees: UT-Battelle, LLC, University of Tennesse Research Foundation
    Inventors: Yunchao Li, Mariappan Parans Paranthaman, Amit K. Naskar, Kokouvi M. Akato
  • Patent number: 10104478
    Abstract: According to an embodiment, a method of operating a microelectromechanical systems (MEMS) transducer that has a membrane includes transducing between out-of-plane deflection of the membrane and voltage on a first pair of electrostatic drive electrodes using the first pair of electrostatic drive electrodes. The first pair of electrostatic drive electrodes is formed on the membrane extending in an out-of-plane direction and form a variable capacitance between the first pair of electrostatic drive electrodes.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: October 16, 2018
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Christoph Glacer, Alfons Dehe
  • Patent number: 10023459
    Abstract: A method and apparatus are provided to prevent or reduce stiction of a MEMS device. The MEMS device may include a protrusion extending from a surface of the MEMS device. During manufacture, the protrusion may be connected across an opening in the MEMS device to a sidewall of the substrate. Before manufacture of the MEMS device is completed, at least a portion of the protrusion connecting the MEMS device to the substrate may be removed. During operation, the protrusion may provide stiction prevention or reduction for the surface from which the first protrusion may extend. A plurality of protrusions may be formed along a plurality of surfaces for the MEMS device to prevent or reduce stiction along the corresponding surfaces. Protrusions may also be formed on devices surrounding or encapsulating the MEMS device to prevent or reduce stiction of the MEMS device to the surrounding or encapsulating devices.
    Type: Grant
    Filed: April 11, 2013
    Date of Patent: July 17, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Sung Chang, Ting-Hau Wu
  • Patent number: 9941388
    Abstract: Embodiments of the present invention provide methods and structures for protecting gates during epitaxial growth. An inner spacer of a first material is deposited adjacent a transistor gate. An outer spacer of a different material is deposited adjacent the inner spacer. Stressor cavities are formed adjacent the transistor gate. The inner spacer is recessed, forming a divot. The divot is filled with a material to protect the transistor gate. The stressor cavities are then filled. As the gate is safely protected, unwanted epitaxial growth (“mouse ears”) on the transistor gate is prevented.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: April 10, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xiuyu Cai, Ying Hao Hsieh
  • Patent number: 9922669
    Abstract: Implementations disclosed and claimed herein include a method of write head core located in a slider, the write head core comprising a first end operative to serve as a write pole, a second end operative to serve as a return pole, wherein the first end comprises a substantially smaller cross-sectional area than the second end, and wherein the write head core has a substantially smooth curvature.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: March 20, 2018
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Kirill Rivkin, Ned Tabat, Mourad Benakli, Michael A. Seigler
  • Patent number: 9860620
    Abstract: A method for forming a layered structural member may include providing a first outer layer of material and a second outer layer of material, placing between the first outer layer and the second outer layer a layer of core material, and placing between the first outer layer and the second outer layer a piezoelectric transducer, the piezoelectric transducer configured to convert an audio signal received by the piezoelectric transducer into at least one of a mechanical pressure, acceleration, strain and force causing the layered structured member to generate sound.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: January 2, 2018
    Assignee: Dell Products L.P.
    Inventors: Deeder M. Aurongzeb, Mitchell Anthony Markow, Andrew Thomas Sultenfuss, Chuan Beng Sim, Douglas Jarrett Peeler
  • Patent number: 9765171
    Abstract: Disclosed are self-assembling diblock copolymers of the formula (I): wherein R1-R4, n, and m are as described herein, which find use in preparing self-assembled structures and porous membranes. Embodiments of the self-assembled structures contain the diblock copolymer in a cylindrical morphology. Also disclosed is a method of preparing such copolymers.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: September 19, 2017
    Assignee: Pall Corporation
    Inventor: Khaled Abdel-Hakim Helmy Aamer
  • Patent number: 9708453
    Abstract: The method of the present disclosure is a method for producing a porous polymer film including: irradiating a strip-shaped polymer film with an ion beam while moving the polymer film transversely to the ion beam, so as to form a polymer film that has collided with ions in the beam; and chemically etching the formed polymer film so as to form openings and/or through holes corresponding to tracks left by the colliding ions in the polymer film. The ion beam (11) with which the polymer film is irradiated is obtained by folding a tail of an original beam (51) inwardly toward a center of the original beam by nonlinear focusing. The original beam is composed of ions accelerated in a cyclotron and has a cross-sectional intensity distribution profile in which an intensity is maximum at the center of the original beam and continuously decreases from the center toward the tail of the original beam, and the profile is an intensity distribution profile in a cross section perpendicular to a direction of the original beam.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: July 18, 2017
    Assignee: NITTO DENKO CORPORATION
    Inventors: Satoru Furuyama, Yozo Nagai, Junichi Moriyama, Yosuke Yuri, Takahiro Yuyama, Tomohisa Ishizaka, Ikuo Ishibori, Ken-ichi Yoshida, Yasunari Maekawa, Hiroshi Koshikawa, Tetsuya Yamaki, Masaharu Asano
  • Patent number: 9593217
    Abstract: Disclosed are self-assembled structures formed from a self-assembling diblock copolymer of the formula (I): wherein R1-R4, n, and m are as described herein, which find use in preparing porous membranes. In an embodiment, the diblock copolymer is present in the self-assembled structures in a cylindrical morphology. Also disclosed is a method of preparing a self-assembled structure, which involves spin coating a polymer solution containing the diblock copolymer to obtain a thin film, followed by solvent annealing of the film.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: March 14, 2017
    Assignee: Pall Corporation
    Inventors: Khaled Abdel-Hakim Helmy Aamer, Selina Shi
  • Patent number: 9505165
    Abstract: A nanoimprinting mold includes: a mold main body having a fine pattern of protrusions and recesses on a surface thereof; and a mold release layer formed on the surface of the mold main body. The mold release layer is formed within a mold release layer forming region, which is a region of the mold main body that includes a patterned region where the fine pattern of protrusions and recesses is formed and has an outer edge positioned outside the outer edge of the patterned region. An outer peripheral mold release layer has a thickness distribution in which the thickness of the outer peripheral mold release layer is locally maximal at positions outside the outer edge of the patterned region, substantially continuously along the entire periphery. Thereby, it becomes possible to restrict the region in which resist flows during nanoimprinting, without employing a mesa type substrate.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: November 29, 2016
    Assignee: FUJIFILM Corporation
    Inventors: Kazuharu Nakamura, Satoshi Wakamatsu
  • Patent number: 9502236
    Abstract: There is provided a method of manufacturing a semiconductor device by processing a substrate by alternately supplying a first processing gas and a second processing gas plasmatized by a plasma unit to a processing container. The method includes: starting a supply of an electric power to plasmatize the second processing gas to the plasma unit without supplying the second processing gas to the plasma unit; and starting a supply of the second processing gas with the electric power being supplied to the plasma unit.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: November 22, 2016
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Yukitomo Hirochi, Kazuyuki Toyoda, Kazuhiro Morimitsu, Taketoshi Sato, Tetsuo Yamamoto
  • Patent number: 9139897
    Abstract: A coated part is exposed to a gas flow. The gas flow has a characteristic gas flow direction distribution over a surface of the coated part. The coated part has a substrate having a substrate surface and a coating over the substrate surface. The coating comprises at least one coating layer. A first such layer is columnar and has a column boundary direction distribution. The column boundary direction distribution is selected for partial local alignment with the gas flow direction distribution.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: September 22, 2015
    Assignee: United Technologies Corporation
    Inventors: Igor V. Belousov, Yuriy G. Kononenko, Vadim I. Bondarchuk, Anatoly Kuzmichev, John F. Mullooly, Jr.
  • Publication number: 20150140420
    Abstract: The present invention relates to a method for manufacturing a carbon-sulfur composite, a carbon-sulfur composite manufactured by the method, and an electrochemical device including the same. Since the carbon-sulfur composite manufactured by the carbon-sulfur composite manufacturing method of the present invention includes the hollow carbon ball having the inner hollow which is uniformly filled with sulfur, a sulfur content increases to increase a capacity characteristic increases. In addition, even though sulfur is changed into a liquid state during charge and discharge processes, an electrode structure is not destroyed to realize a stable lifetime characteristic.
    Type: Application
    Filed: May 2, 2013
    Publication date: May 21, 2015
    Applicant: IUCF-HYU (INUSTRY-UNIVERSITY COOPERATION FOUNDATIO HANYANG UNIVERSITY
    Inventors: Yang-Kook Sun, Dong Ju Lee, Ju Won Park
  • Publication number: 20150129544
    Abstract: Graphite-based devices with a reduced characteristic dimension and methods for forming such devices are provided. One or more thin films are deposited onto a substrate and undesired portions of the deposited thin film or thin films are removed to produce processed elements with reduced characteristic dimensions. Graphene layers are generated on selected processed elements or exposed portions of the substrate after removal of the processed elements. Multiple sets of graphene layers can be generated, each with a different physical characteristic, thereby producing a graphite-based device with multiple functionalities in the same device.
    Type: Application
    Filed: October 21, 2014
    Publication date: May 14, 2015
    Inventor: Mark Alan Davis
  • Publication number: 20150122774
    Abstract: A method of manufacturing an inlaid ceramic element for a timepiece including: a) forming a ceramic or cermet body; b) etching at least one recess in one face of the ceramic or cermet body, each at least one recess forming a pattern cavity for a decoration; c) changing a surface state of a bottom of the at least one recess to increase contact surface thereof; d) filling the at least one recess with a composite ceramic to form the decoration; e) flattening the composite ceramic so that the composite ceramic remains only in a hollow of the at least one recess.
    Type: Application
    Filed: April 25, 2013
    Publication date: May 7, 2015
    Applicant: The Swatch Group Research and Development Ltd.
    Inventors: Maria Fernandez Ciurleo, Juliette Muller, Stewes Bourban
  • Publication number: 20150119807
    Abstract: A method of preparing a substantially planar microdevice comprising a plurality of reservoirs is provided. In general, the method comprises forming a plurality of microdevices comprising a plurality of reservoirs from a planar layer of a biocompatible polymer. The method also comprises depositing one or more bioactive agents into the reservoirs. The microdevice is configured to attach to a target tissue and release the bioactive agent in close proximity to the tissue.
    Type: Application
    Filed: May 24, 2013
    Publication date: April 30, 2015
    Applicant: The Regents of the University of California
    Inventors: Tejal A. Desai, Hariharasudhan D. Chirra
  • Patent number: 9018100
    Abstract: Damascene processes using physical vapor deposition (PVD) sputter carbon film as a chemical mechanical planarization (CMP) stop layer for forming a magnetic recording head are provided. In one embodiment, one such process includes providing an insulator, removing a portion of the insulator to form a trench within the insulator, depositing a carbon material on first portions of the insulator using a physical vapor deposition process, disposing at least one ferromagnetic material on second portions of the insulator to form a pole including a portion of the ferromagnetic material within the trench, and performing a chemical mechanical planarization on the at least one ferromagnetic material using at least a portion of the carbon material as a stop for the chemical mechanical planarization.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: April 28, 2015
    Assignee: Western Digital (Fremont), LLC
    Inventors: Yanfeng Chen, Yunjun Tang, Yana Qian, Ming M. Yang, Yunfei Li, Paul E. Anderson
  • Patent number: 9017563
    Abstract: Provided is a plating method of a circuit substrate comprising a conductive pattern in which a metal layer containing at least silver and copper is exposed on an outer surface. The plating method comprises: step (A) of treating the circuit substrate with a first liquid agent containing an oxidizing agent; step (B) of treating the circuit substrate after the step (A) with a second liquid agent which dissolves copper oxide, and thereby removing copper oxide from the conductive pattern's surface; step (C) of treating the circuit substrate after the step (B) with a third liquid agent whose rate of dissolving silver oxide (I) at 25° C. is 1000 times or more faster than its rate of dissolving copper (0) at 25° C., and thereby removing silver oxide from the conductive pattern's surface; and step (D) of performing electroless plating on the conductive pattern of the circuit substrate after the step (C).
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: April 28, 2015
    Assignee: Tokuyama Corporation
    Inventors: Emi Ushioda, Tetsuo Imai
  • Publication number: 20150111002
    Abstract: A method for manufacturing composite of resin and other materials includes the following steps. A shaped piece made by materials different with resin is provided, and is degreased and cleaned. A resist layer with a lot of location holes is formed on the surface of the heterogeneous member by nano-imprint lithography, and a lot of small holes are formed on the surface of the heterogeneous member while the resist layer is removed. Then the heterogeneous member is inserted in an injection mold, and molten crystalline thermoplastic resin is injected into the mold, thus the resin embedded into the holes and bonding with the shaped piece. The method is environmentally friendly and suitable for mass production.
    Type: Application
    Filed: October 14, 2014
    Publication date: April 23, 2015
    Inventors: SHYAN-JUH LIU, KAR-WAI HON, SHA-SHA LIU
  • Patent number: 9012244
    Abstract: The present disclosure relates to a method to form a plurality of openings within a substrate with a single photo exposure and a single etch process. A photoresist layer is disposed over a substrate and aligned with a photomask, wherein the photomask comprises a transparent area, a grayscale area, and an opaque area. The photomask and substrate are exposed to radiation comprising a single illumination step to form a first 3-dimensional pattern within the photoresist layer. The 3-dimensional pattern comprises a first opening comprising a first thickness formed by transmitting the radiation through the transparent area with full intensity, and a second opening comprising a second thickness formed by transmitting the radiation through the grayscale area with partial intensity. The 3-dimensional pattern is transferred to form a plurality of openings of varying depths within the substrate through a single etch step.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: April 21, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lin-Ya Huang, Chi-Sheng Juan, Chien-Lin Tseng, Chang-Sheng Tsao
  • Patent number: 9005756
    Abstract: Disclosed are block copolymer nanostructures formed on surface patterns different from nanostructure of the block copolymer and preparation methods thereof.
    Type: Grant
    Filed: April 11, 2008
    Date of Patent: April 14, 2015
    Assignee: Advanced Institute of Science and Technology
    Inventors: Sang Ouk Kim, Dong Ok Shin, Bong Hoon Kim
  • Patent number: 8999446
    Abstract: The present disclosure is directed to systems and methods for adjusting adhesion strength between materials during semiconductor sensor processing. One or more embodiments are directed to using various surface treatments to a substrate to adjust adhesion strength between the substrate and a polymer. In one embodiment, the surface of the substrate is roughened to decrease the adhesive strength between the substrate and the polymer. In another embodiment, the surface of the substrate is smoothed to increase the adhesive strength between the substrate and the polymer.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: April 7, 2015
    Assignee: STMicroelectronics Pte Ltd.
    Inventors: Ying Yu, TienChoy Loh, ShianYeu Kam
  • Patent number: 8999179
    Abstract: A method of forming a conductive via in a substrate includes forming a via hole covered by a dielectric layer followed by an annealing process. The dielectric layer can getter the mobile ions from the substrate. After removing the dielectric layer, a conductive material is formed in the via hole, forming a conductive via in the substrate.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Der-Chyang Yeh
  • Patent number: 8999852
    Abstract: A method of forming a pattern on a substrate comprises forming spaced, upwardly-open, cylinder-like structures projecting longitudinally outward of a base. Sidewall lining is formed over inner and over outer sidewalls of the cylinder-like structures, and that forms interstitial spaces laterally outward of the cylinder-like structures. The interstitial spaces are individually surrounded by longitudinally-contacting sidewall linings that are over outer sidewalls of four of the cylinder-like structures. Other embodiments are disclosed, including structure independent of method.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: April 7, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sipani, Anton J. deVillers, William R. Brown, Shane J. Trapp, Ranjan Khurana, Kevin R. Shea
  • Publication number: 20150092524
    Abstract: The invention relates to a method of manufacturing an inlaid ceramic element for a timepiece comprising the following steps: a) forming a ceramic body; b) etching at least one recess in one face of the ceramic body, each at least one recess forming the pattern cavity for a decoration; c) changing the surface state of the bottom of said at least one recess in order to increase the contact surface thereof; d) depositing, by thermal spraying, a second ceramic material above said at least one recess in order to totally fill said at least one recess; e) flattening said second ceramic material so that said second ceramic material remains only in the hollow of said at least one recess.
    Type: Application
    Filed: September 16, 2014
    Publication date: April 2, 2015
    Applicant: Montres Rado SA
    Inventor: Christian VERDON
  • Publication number: 20150079384
    Abstract: A metal composite, a method of preparing the metal composite, a metal-resin composite, and a method of preparing the metal-resin composite are provided. The metal composite comprises: a metal substrate comprising a first layer formed on a surface of the metal substrate and an anodic oxidation layer formed on the first layer. The first layer comprises a first pore having an average diameter of about 10 nanometers to about 1 millimeter, and the metal composite comprises aluminum alloy or aluminum. The anodic oxidation layer comprises a second layer contacted with the first layer of the metal substrate and a third layer formed on an outer surface of the second layer, and the second layer comprises a second pore having an average diameter of about 10 nanometers to about 800 microns, and the third layer comprises a third pore having an average diameter of about 10 nanometers to about 800 microns.
    Type: Application
    Filed: November 26, 2014
    Publication date: March 19, 2015
    Inventors: Xiao ZHANG, Lili TANG, Yun CHENG, Qiang GUO, Liang CHEN
  • Publication number: 20150064915
    Abstract: A method is disclosed for forming a row of mutually spaced lithography features on a substrate, such as contact electrodes for a NAND device. The method involves forming and/or using a narrow slot over the substrate defined between the edge of a hard mask layer and a side wall of a trench in a resist layer overlying the edge and the substrate. A self-assemblable block copolymer is deposited and ordered in the trench for use as a further resist for patterning the substrate along the slot. The method allows for a sub-resolution contact array to be formed using UV lithography by overlapping the trench with the hard mask edge to provide the narrow slot in which the contact electrodes may be formed.
    Type: Application
    Filed: March 19, 2013
    Publication date: March 5, 2015
    Applicant: ASML Netherlands B.V.
    Inventor: Sander Frederik Wuister
  • Patent number: 8968583
    Abstract: A method for cleaning a dielectric and metal structure within a microelectronic structure uses an oxygen containing plasma treatment, followed by an alcohol treatment, in turn followed by an aqueous organic acid treatment. Another method for cleaning a dielectric and metal structure within a microelectronic structure uses an aqueous surfactant treatment followed by an alcohol treatment and finally followed by an aqueous organic acid treatment. The former method may be used to clean a plasma etch residue from a dual damascene aperture. The second method may be used to clean a chemical mechanical polish planarizing residue from a dual damascene structure. The two methods may be used sequentially, absent any intervening or subsequent sputtering method, to provide a dual damascene structure within a microelectronic structure.
    Type: Grant
    Filed: July 25, 2007
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Mary Beth Rothwell, Roy Rongqing Yu
  • Patent number: 8970242
    Abstract: Provided is a method for manufacturing a probe card which inspects electrical characteristics of a plurality of semiconductor devices in batch. The method includes: a step of forming a plurality of probes, which are to be brought into contact with external terminals of the semiconductor devices, on one side of a board which forms the base body of the probe card; a step of forming on the board, by photolithography and etching, a plurality of through-holes which reach the probes from the other side of the board; a step of forming, in the through-holes, through electrodes to be conductively connected with the probes, respectively; and a step of forming wiring, which is conductively connected with the through electrodes, on the other side of the board.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: March 3, 2015
    Assignee: Rohm Co, Ltd.
    Inventors: Goro Nakatani, Masahiro Sakuragi, Koichi Niino
  • Patent number: 8946835
    Abstract: A planarization process may planarize a media disk that has data trenches between data features and larger servo trenches between servo features. A filler material layer is deposited on the media disk and provides step coverage of the trenches. The filler material has data recesses over the data trenches and servo recesses over the servo trenches that must be removed to produce a planar media surface. A first planarization process is used to remove the data recesses and a second planarization process is used to remove the servo recesses.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: February 3, 2015
    Assignee: Seagate Technology LLC
    Inventors: Yuan Xu, Wei Hu, Justin Jia-Jen Hwu, Gene Gauzner, Koichi Wago, David Shiao-Min Kuo
  • Patent number: 8936730
    Abstract: An apparatus used for forming stud bumps may be formed by providing a first clamp plate comprising a clamping surface, forming a notcher on the clamping surface, and forming a contact stopper on the clamping surface. The apparatus may include a clamp that includes at least two opposing plates, and at least one of the opposing plates includes a protruding feature that intersects the wire when the wire is clamped forming a first notch in the wire. The method for forming stud bumps includes bonding wire to a bonding surface, releasing the wire from the clamp, passing the wire a notch pitch distance through the clamp, clamping the wire with the clamp forming a second notch in the wire, and breaking the wire leaving a bonded portion of the wire on the bonding surface.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: January 20, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yeong-Jyh Lin, Hsin-Hung Liao, Chien Ling Hwang, Chung-Shi Liu, Mirng-Ji Lii, Chen-Hua Yu, Yi-Li Hsiao
  • Publication number: 20150004480
    Abstract: Electrodes, energy storage devices using such electrodes, and associated methods are disclosed. In an example, an electrode for use in an energy storage device can comprise porous silicon having a plurality of channels and a surface, the plurality of channels opening to the surface; and a structural material deposited within the channels; wherein the structural material provides structural stability to the electrode during use.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 1, 2015
    Inventors: Donald S. Gardner, Charles W. Holzwarth
  • Publication number: 20150004207
    Abstract: An interventional medical device and manufacturing method thereof, the interventional medical device comprising a stent body (1); the stent body (1) is provided with a drug releasing structure on the surface, the drug in the drug releasing structure being a drug for inhibiting adventitial fibroblast proliferation. When the interventional medical device is implanted into a human body, the drug for inhibiting the adventitial fibroblast proliferation can be slowly released into vessel wall cells in contact with the stent body (1), thus inhibiting the proliferation of the adventitial fibroblasts, promoting vascular compensatory expansion, and reducing the incidence rate of instent restenosis.
    Type: Application
    Filed: January 17, 2012
    Publication date: January 1, 2015
    Applicant: SHANGHAI MICROPORT MEDICAL (GROUP) CO., LTD.
    Inventors: Xu Cai, Dadong Zhang, Yan Hu, Peng Huang, Junfei Li, Chengyun Yue, Zhirong Tang, Qiyi Luo
  • Patent number: 8914970
    Abstract: A tunneling magnetoresistive sensor has an extended pinned layer wherein both the MgO spacer layer and the underlying ferromagnetic pinned layer extend beyond the back edge of the ferromagnetic free layer in the stripe height direction and optionally also beyond the side edges of the free layer in the trackwidth direction. A patterned photoresist layer with a back edge is formed on the sensor stack and a methanol (CH3OH)-based reactive ion etching (RIE) removes the unprotected free layer, defining the free layer back edge. The methanol-based RIE terminates at the MgO spacer layer without damaging the underlying reference layer. A second patterned photoresist layer may be deposited and a second methanol-based RIE may be performed if it is desired to have the reference layer also extend beyond the side edges of the free layer in the trackwidth direction.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: December 23, 2014
    Assignee: HGST Netherlands B.V.
    Inventor: Jordan Asher Katine
  • Patent number: 8914969
    Abstract: A method fabricates a magnetic transducer. A sacrificial leading shield is provided on an etch stop layer. A nonmagnetic layer is provided on the sacrificial leading shield. A pole trench is formed in the nonmagnetic layer and on the sacrificial leading shield. A pole is formed. The pole has a bottom and a top wider than the bottom in a pole tip region. Part of the pole in the pole tip region is in the pole trench and at the ABS location. The sacrificial leading shield and part of the nonmagnetic layer adjacent to the pole are removed. An air bridge thus resides in place of the sacrificial leading shield between the portion of the pole and the etch stop layer. As least one shield layer is provided. The at least one shield layer substantially fills the air bridge and form a monolithic shield including a leading and side shields.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: December 23, 2014
    Assignee: Western Digital (Fremont), LLC
    Inventors: Xiaotian Zhou, Hongzhou Jiang, Donghong Li, Lien-Chang Wang, Ching-Huang Lu, Wencheng Su, Lieping Zhong, Tao Pan
  • Publication number: 20140369005
    Abstract: A thermal management device including a first face configured to be in contact with a hot source and a second face opposite the first face configured to be in contact with a cold source, and at least one network of cells filled with a solid/liquid phase-change material located in a cavity between the first and second faces, wherein the cells include walls formed of carbon nanotubes, wherein the nanotubes extend roughly from the first to the second face, thermally connecting the first face to the second face.
    Type: Application
    Filed: January 8, 2013
    Publication date: December 18, 2014
    Applicant: Commissariat a l'energie atomique et aux ene alt
    Inventors: Jerome Gavillet, Jean Dijon
  • Patent number: 8910380
    Abstract: Described is a process for producing an inkjet printhead comprising an aperture face having an oleophobic surface. The process includes forming an aperture plate by disposing a silicon layer on an aperture plate; using photolithography to create a textured pattern on an outer surface of the silicon layer; and chemically modifying the textured surface by disposing a conformal, oleophobic coating on the textured surface. The oleophobic aperture plate may be used as a front face surface for an inkjet printhead.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: December 16, 2014
    Assignee: Xerox Corporation
    Inventors: Kock-Yee Law, Hong Zhao
  • Publication number: 20140363631
    Abstract: A method for integrally molding a metal and a resin and a metal-resin composite structure obtainable by the same are provided. The method comprises forming a nanopore in a surface of a metal sheet; melting a thermoplastic resin on the surface of the metal sheet formed with the nanopore; and injection molding the thermoplastic resin onto the surface of the metal sheet. The thermoplastic resin includes a mixture of a main resin and a polyolefin resin, the main resin is a polycarbonate, and the polyolefin resin has a melting point of about 65° C. to about 105° C.
    Type: Application
    Filed: August 22, 2014
    Publication date: December 11, 2014
    Inventors: Qing GONG, Xiong ZHANG, Yihu ZHANG, Wei ZHOU
  • Publication number: 20140363686
    Abstract: A method of preparing aluminum alloy-resin composite and an aluminum alloy-resin composite obtained by the same are provided. of the method comprises: S1: anodizing a surface of an aluminum alloy substrate to form an oxide layer on the surface, the oxide layer including nanopores; S2: immersing the resulting aluminum alloy substrate obtained in step S1 in a buffer solution having a pH of about 10 to about 13, to form a corrosion pores on an outer surface of the oxide layer; and S3: injection molding a resin onto the surface of the resulting aluminum alloy substrate obtained in step S2 in a mold to obtain the aluminum alloy-resin composite.
    Type: Application
    Filed: August 22, 2014
    Publication date: December 11, 2014
    Inventors: Jian SUN, Yanqin WU, Qiang GUO, Liang CHEN
  • Publication number: 20140363660
    Abstract: A method for integrally molding a metal and a resin and a metal-resin composite structure obtainable by the same are provided. The method comprises forming a nanopore in a surface of a metal sheet; melting a thermoplastic resin on the surface of the metal sheet formed with the nanopore; and injection molding the thermoplastic resin onto the surface of the metal sheet. The thermoplastic resin is a mixture of a main resin and a polyolefin resin, the main resin is a mixture of polyphenylene oxide and a polyamide, and the polyolefin resin has a melting point of about 65° C. to about 105° C.
    Type: Application
    Filed: August 22, 2014
    Publication date: December 11, 2014
    Inventors: Qing GONG, Xiong ZHANG, Yihu ZHANG, Wei ZHOU
  • Publication number: 20140363658
    Abstract: An aluminum alloy, an aluminum alloy resin composite, a method of preparing aluminum alloy, and a method of preparing aluminum alloy-resin composite are provided. The aluminum alloy may comprise: an aluminum alloy substrate; and an oxide layer formed on the surface of the aluminum alloy substrate. The oxide layer comprises an outer surface and an inner surface. The outer surface contains corrosion pores having an average diameter of about 200 nm to about 2000 nm; and the inner surface contains nanopores having an average diameter of about 10 nm to about 100 nm.
    Type: Application
    Filed: August 22, 2014
    Publication date: December 11, 2014
    Inventors: Jian SUN, Juan ZENG, Jun CHENG