Gate Recessed FDSOI Transistor with Sandwich of Active and Etch Control Layers
The structure and the fabrication methods herein implement a fully depleted, recessed gate silicon-on-insulator (SOI) transistor with reduced access resistance, reduced on-current variability, and strain-increased performance. This transistor is based on an SOI substrate that has an epitaxially grown sandwich of SiGe and Si layers that are incorporated in the sources and drains of the transistors. Assuming a metal gate last complementary metal-oxide semiconductor (CMOS) technology and using the sidewall spacers as a hard mask, a recess under the sacrificial gate reaching all the way through the SiGe layer is created, and the high-K gate stack and metal gate are formed within that recess. The remaining Si region, having a precisely controlled thickness, is the fully depleted channel.
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This application claims the benefit of U.S. Provisional Patent Application No. 61/676,936 filed Jul. 28, 2012.
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention generally relates to the manufacturing of metal-oxide-semiconductor field effect transistors (MOSFETs), and more particularly to fully depleted channel transistors fabricated in thin silicon films over a buried insulating layer with improved source drain characteristics, excellent electrostatic integrity and reduced statistical variability.
2. Prior Art
MOS transistors have long been troubled by the adverse effects of their underlying substrates, like parasitic capacitance and area-consuming isolation. In the earliest days of integrated circuit technology, the use of a thin film of silicon on a sapphire substrate was proposed as a solution to these problems. RCA Laboratories was an early proponent of this technology, as in Meyer, J. E.; Boleky, E. J.; “High performance, low power CMOS memories using silicon-on-sapphire technology,” Electron Devices Meeting, 1971 International, vol. 17, p. 44, 1971. The basic ideas of this technology have evolved over the years driven by improvements in materials technology, and as less exotic substrates became practical, this technology became known as silicon-on-insulator (SOI). In the earliest implementations, the silicon was simply relatively thin, i.e., less than 1 micron thick, substrate with a conventional level of doping and a depletion layer beneath the transistor's gate thinner than the silicon thickness resulting in ‘partially depleted’ SOI (PD SOI). The un-depleted doped region beneath the gate of a PD SOI transistor proved to have its own disadvantages, largely caused by its tendency to charge and discharge resulting in step changes in the drain current. These problems became known as a “kink” effect, and it was closely tied to impact ionization in the transistor's channel and electron/hole trapping in the un-depleted part of the silicon under the channel.
The next stage in SOI evolution was the use fully-depleted silicon film (FD SOI). This was achieved by making the silicon beneath the gate so thin that there would be no region where there could be mobile carriers. Some of the early work was done at HP Laboratories and reported as Colinge, J.-P.; “Hot-electron effects in Silicon-on-insulator n-channel MOSFET's,” Electron Devices, IEEE Transactions on , vol. 34, no. 10, pp. 2173-2177, October 1987. In this work, the silicon film is thinner by a factor of 10, only 100 nm thick.
The next step in fully depleted SOI technology has been prompted by the emergence of threshold voltage variations that are associated with the uncertainty of the number of discrete doping ions immediately beneath the gate. This uncertainty is similar to shot noise, because it is an irreducible, statistical uncertainty. For large devices, the counting uncertainty, roughly proportional to the square root of the total number of ions, was never a problem. However, in a world where devices have dimensions of the order of 30 nm, the total number of doping ions drops below 100, and the counting uncertainty is about 3%, rising to 10% for smaller devices. These deviations are devastating when billions of transistors are integrated into a single integrated circuit chip. The immediate solution required eliminating all doping from the silicon layer, placing all the responsibility for threshold control on the relative work functions of the gate material, now a metal, and the thickness of the silicon film. This has been done with both planar and FinFET transistor structures. A good review of this work may be found in Kuhn, K. J.; Giles, M. D.; Becher, D.; Kolar, P.; Kornfeld, A.; Kotlyar, R.; Ma, S. T.; Maheshwari, A.; Mudanai, S.; “Process Technology Variation,” Electron Devices, IEEE Transactions on, vol. 58, no. 8, pp. 2197-2208, August 2011.
Planar transistors at 32/28 nm CMOS technology generation made to have good electrostatic integrity and resistance to doping fluctuations have to employ extremely thin silicon layers, of the order of 7 nm or less, and they are fabricated over thin buried oxide layers, roughly 10 nm thick. This is discussed in detail in Maleville, C.; “Extending planar device roadmap beyond node 20 nm through ultra thin body technology,” VLSI Technology, Systems and Applications (VLSI-TSA), 2011 International Symposium on, pp. 1-4, 25-27 April 2011. Layers in the sub-10 nm thickness ranges present manufacturing challenges, and the very thin layers affect performance because the parasitic series resistance in sources and drains cuts down on the transistors' gain figures. The limited number of dopants, particularly in the access regions below the spacer, also introduce access resistance and on current variability, S. Markov, B. Cheng, A. Asenov, “Statistical variability in fully depleted SOI MOSFETs due to random dopant fluctuations in the Source and drain extensions,” IEEE Electron Dev. Let. Vol. 33, pp. 315-317 (March, 2012).
There have been a variety of publications that address the use of an undoped or lightly doped epitaxial channel region to mitigate the fluctuations associated with random doping variations. The publications include Takeuchi, K.; Tatsumi, T.; Furukawa, A.; “Channel engineering for the reduction of random-dopant-placement-induced threshold voltage fluctuation,” Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International, pp. 841-844, 7-10 Dec. 1997; Asenov, A.; Saini, S.; “Suppression of random dopant-induced threshold voltage fluctuations in sub-0.1-μm MOSFET's with epitaxial and δ-doped channels,” Electron Devices, IEEE Transactions on, vol. 46, no. 8, pp. 1718-1724, August 1999; and Thompson; Scott E.; Thummalapally; Damodar R.; “Electronic Devices and Systems, and Methods for Making and Using the Same,” U.S. Patent Application 2011/0074498, Mar. 31, 2011. All these publications address the use of epitaxy in the channels of bulk transistors.
Within the current FDSOI practice there remain problems associated with low and variable access conductance beneath the gate spacers and with thickness control of the active layer. These problems are addressed by the structure and methods described below.
The subject matter that is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention will be apparent from the following detailed description taken in conjunction with the accompanying drawings.
The structure and the fabrication methods herein implement a fully depleted, recessed gate silicon-on-insulator (SOI) transistor with reduced access resistance, reduced on-current variability, and strain-increased performance. This transistor is based on an SOI substrate that has an epitaxially grown sandwich of SiGe and Si layers that are incorporated in the sources and drains of the transistors. Assuming a metal gate last complementary metal-oxide semiconductor (CMOS) technology and using the sidewall spacers as a hard mask, a recess under the sacrificial gate reaching all the way through the SiGe layer is created, and the high-K gate stack and metal gate are formed within that recess. The remaining Si region, having a precisely controlled thickness, is the fully depleted channel.
Embodiments of the invention provide for an improved, fully depleted SOI transistor based on a starting substrate having two thin, single crystal layers, one being silicon and the other silicon-germanium. Within this substrate, the transistor gate is formed in a recess in the upper of the two layers, controlling the conduction of carriers in the lower single crystal layer. The recess is defined laterally by the interior walls of the gate spacer, and its depth is controlled by the thickness of the upper single crystal layer. The processing is compatible with commonly known “Gate Last” technology. The two layers are typically epitaxial silicon adjacent to a buried oxide and beneath an epitaxial layer of SiGe. The completed device realizes fully depleted SOI transistors in the silicon layer, but has added source/drain thickness from the SiGe layer.
Embodiments of the invention that create a fully-depleted silicon on insulator transistors using a “Recessed Gate” process provide benefits that include, but are not limited to: accurate definition of the channel thickness due to epitaxial control of the thickness of the Si channel layer and the high (100:1) selectivity of the SiGe cap etching; reduced access resistance associated with the presence of the relatively thick cap layer containing source/drain doping; strain induced performance enhancement of the p-channel transistors due to compressive strain in the channel inserted by the SiGe cap layer; reduced on current variability due to the larger volume and larger number of dopants in the access regions which reduces the statistical access resistance variations; and, addressing a second source of fluctuations, those associated with the uncertainty of the location of the PN junctions that separate sources and drains from the bodies of their respective transistors.
The new structure differs from the prior art in the physical and electrical structure of the channel region of the thin-film, SOI transistor. This is illustrated in exemplary and non-limiting
In
The new structure utilizes an SOI substrate that is different from the substrate utilized in a conventional fully depleted SOI transistor. This is illustrated in
The ten illustrations identified as
In
At this stage, as shown by
The next step in creating a Recessed Gate structure is shown in
The transistor is completed like any other “Gate Last” transistor as shown in
It is well known that, subsequent to forming the structure shown in
Referring back to
It will be appreciated that there are a variety of approaches to realizing a structure possessing the essential properties of the “Recessed Gate” SOI transistor described in the paragraphs above. Alternative single crystal layers may be used as long as device quality, single crystal semiconductors can realized, particularly for the layer identified variously as 22, 32 or 42. For instance, making layer 32 SiGe and making layer 33 Si, reverses the sequence described in
Further, the recessed gate structure can be realized on a bulk silicon substrate by preparing it with an overlying epitaxial layer of SiGe. In this case, the advantages associated with a fully-depleted, insulated channel region will not be available, but the other virtues of this structure will be preserved.
Claims
1. A metal-oxide-semiconductor field effect transistor (MOSFET) comprising:
- a semiconductor on insulator (SOI) substrate having a first semiconductor layer on a second semiconductor layer that is on an insulator layer, which insulator layer is on an underlying substrate, the two semiconductor layers being a silicon layer and a silicon germanium layer;
- a source region and a drain region formed in the second semiconductor layer;
- a semiconductor channel region in the second semiconductor region separating the source and the drain regions;
- the semiconductor channel region having a thickness for fully depleted operation and extending through the second semiconductor layer to the insulator layer;
- a gate dielectric over the semiconductor channel region; and,
- a conductive gate region over the gate dielectric, the gate dielectric also separating the conductive gate from the first semiconductor layer adjacent the conductive gate.
2. The MOSFET of claim 1 wherein the first semiconductor layer comprises a silicon gel nianium layer and the second semiconductor layer comprises a silicon layer.
3. The MOSFET of claim 1 wherein the source and drain regions extend through the semiconductor layer to the insulator layer.
4. The MOSFET of claim 1, further comprising
- a pair of passive spacers above the first semiconductor layer, each having substantially vertical faces spaced apart and defining a length of the conductive gate region.
5. The MOSFET of claim 4, wherein the gate dielectric and the metal gate fill an etched recess through the first semiconductor layer between the spacers to the semiconductor channel region.
6. The MOSFET of claim 25 wherein the gate dielectric is one or more dielectric layers having an effective dielectric constant greater than 6.
7. The MOSFET of claim 6 wherein the conductive gate region is a metal gate region.
8. The MOSFET of claim 6 wherein the conductive gate region is a silicon gate region.
9. A metal-oxide-semiconductor field effect transistor (MOSFET) comprising:
- a semiconductor on insulator (SOI) substrate having a silicon-germanium semiconductor layer on a silicon semiconductor layer that is on a buried oxide layer, which buried oxide layer is on an underlying substrate;
- a source region and a drain region extending through the silicon semiconductor layer to the buried oxide layer;
- a semiconductor channel region in the silicon semiconductor region separating the source and the drain regions;
- the semiconductor channel region having a thickness for fully depleted operation and extending through the silicon semiconductor layer to the insulator layer;
- a gate dielectric over the semiconductor channel region and edges of the silicon-germanium layer; and,
- a conductive gate region over the gate dielectric, the gate dielectric also separating the conductive gate from the silicon-germanium semiconductor layer adjacent the conductive gate.
10. The MOSFET of claim 9, further comprising a pair of passive spacers above the silicon-germanium semiconductor layer, each having substantially vertical faces spaced apart and defining a length of the conductive gate region.
11. The MOSFET of claim 27, wherein the gate dielectric and silicon semiconductor channel region fill an etched recess through the silicon-germanium layer to the silicon semiconductor layer between the spacers.
12. The MOSFET of claim 9 wherein the gate dielectric is one or more dielectric layers having an effective dielectric constant greater than 6.
13. A method of forming a MOSFET comprising:
- providing a semiconductor on insulator (SOI) substrate having a first semiconductor layer on a second semiconductor layer that is on a buried oxide layer, which buried oxide layer is on an underlying substrate, one of the first and second semiconductor layers being silicon and one of the first and second semiconductor layers being silicon germanium;
- forming a sacrificial gate structure above a region of the second semiconductor layer designated to be a channel region;
- creating sidewall spacers adjacent the sacrificial gate, and implanting source and drain structures in the second semiconductor layer, the source and drain structures being separated by the channel region;
- using a sequence of selective and anisotropic etches to remove the sacrificial gate structure and the portion of the first semiconductor layer between the sidewall spacers to selectively expose the second semiconductor layer defining the channel region between the sidewall spacers;
- depositing a dielectric stack over the semiconductor channel region and exposed edges of the first semiconductor layer; and
- depositing a conductive gate over the dielectric stack.
14. The method of claim 13 wherein the source and drain regions extend through the second semiconductor layer to the buried oxide layer.
15. The method of claim 13 further comprising depositing a conductive gate handle over the metal gate.
16. The method of claim 11 wherein the dielectric stack has an effective dielectric constant of at least 6.
17. The method of claim 13 wherein the metal gate is formulated for specific work functions to set the threshold voltage of the MOSFET.
18. A method of forming a MOSFET comprising:
- providing a semiconductor on insulator (SOI) substrate having a silicon germanium semiconductor layer on a silicon semiconductor layer that is on an oxide layer, which oxide layer is on an underlying substrate and forms a buried oxide layer;
- forming a sacrificial gate structure above a region designated to be the transistor channel;
- creating sidewall spacers adjacent the sacrificial gate, and implanting source and drain structures in the silicon semiconductor layer, the source and drain structures extending through the silicon germanium semiconductor layer to the buried oxide layer being separated by a channel region in the silicon semiconductor layer;
- using a sequence of selective and anisotropic etches to remove the sacrificial gate structure and the portion of the silicon germanium layer between the sidewall spacers to selectively expose the silicon semiconductor layer defining the semiconductor channel region in the region between the sidewall spacers;
- depositing a dielectric stack over the semiconductor channel region and exposed edges of the silicon germanium layer; and
- depositing a conductive gate over the dielectric stack.
19. The method of claim 18 wherein the silicon germanium semiconductor layer is 5-15 nm thick.
20. The method of claim 18 wherein the silicon semiconductor layer is 4-8 nm thick.
21. The method of claim 18 wherein the silicon germanium semiconductor layer is 5-15 nm thick and the silicon semiconductor layer is 4-8 nm thick.
22. The method of claim 18 further comprising depositing a conductive gate handle over the metal gate.
23. The method of claim 18 wherein the dielectric stack has an effective dielectric constant of at least 6.
24. The method of claim 18 wherein the metal gate is formulated for specific work functions to set the threshold voltage of the MOSFET.
25. The MOSFET of claim 4 wherein the semiconductor channel region is in an etched recess through the first semiconductor layer having a lateral dimension defined by the distance between the pair of passive spacers.
26. The MOSFET of claim 1 in which the semiconductor channel region has a thickness between 4 nm and 8 nm.
27. The MOSFET of claim 10, wherein the semiconductor channel region is in an etched recess through the silicon-germanium layer having a lateral dimension defined by the distance between the passive spacers.
28. The MOSFET of claim 9 in which the silicon semiconductor channel region has a thickness between 4 nm and 8 nm.
29. The MOSFET of claim 13 in which the second semiconductor channel region has a thickness between 4 nm and 8 nm.
Type: Application
Filed: Jul 25, 2013
Publication Date: Jan 30, 2014
Patent Grant number: 9269804
Applicant: Gold Standard Simulations Ltd. (Glasgow)
Inventor: Asen Asenov (Glasgow)
Application Number: 13/950,868
International Classification: H01L 29/78 (20060101); H01L 29/66 (20060101);