Field Effect Transistor Patents (Class 257/192)
  • Patent number: 10658362
    Abstract: A FinFET device includes a fin, an epitaxial layer disposed at a side surface of the fin, a contact disposed on the epitaxial layer and on the fin. The contact includes an epitaxial contact portion and a metal contact portion disposed on the epitaxial contact portion. The doping concentration of the epitaxial contact portion is higher than a doping concentration of the epitaxial layer.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 10658513
    Abstract: A finFET structure, and method of forming such structure, in which a germanium enriched nanowire is located in the channel region of the FET, while simultaneously having silicon-germanium fin in the source/drain region of the finFET.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Pouya Hashemi, Ali Khakifirooz, John A. Ott, Alexander Reznicek
  • Patent number: 10644137
    Abstract: An apparatus including a transistor device including a body including a channel region between a source region and a drain region; and a gate stack on the body in the channel region, wherein at least one of the source region and the drain region of the body include a contact surface between opposing sidewalls and the contact surface includes a profile such that a height dimension of the contact surface is greater at the sidewalls than at a point between the sidewalls. A method including forming a transistor device body on a circuit substrate, the transistor device body dimension defining a channel region between a source region and a drain region; forming a groove in the body in at least one of the source region and the drain region; and forming a gate stack on the body in the channel region.
    Type: Grant
    Filed: July 2, 2016
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Matthew V. Metz, Gilbert Dewey, Sean T. Ma, Chandra S. Mohapatra, Sanaz K. Gardner, Jack T. Kavalieros, Anand S. Murthy, Tahir Ghani
  • Patent number: 10644142
    Abstract: A semiconductor device includes a base substrate, a doped region at an upper surface of the base substrate, and a transistor over the upper surface of the base substrate and formed from a plurality of epitaxially-grown semiconductor layers. The doped region includes one or more ion species, and has a lower boundary above a lower surface of the base substrate. The base substrate may be a silicon substrate, and the transistor may be a GaN HEMT formed from a plurality of heteroepitaxial layers that include aluminum nitride and/or aluminum gallium nitride. The doped region may be a diffusion barrier region and/or an enhanced resistivity region. The ion species may be selected from phosphorus, arsenic, antimony, bismuth, argon, helium, nitrogen, and oxygen. When the ion species includes oxygen, the doped region may include a silicon dioxide layer formed from annealing the doped region after introduction of the oxygen.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: May 5, 2020
    Assignee: NXP USA, Inc.
    Inventors: Yuanzheng Yue, David Cobb Burdeaux, Jenn Hwa Huang, Bruce McRae Green, James Allen Teplik
  • Patent number: 10644068
    Abstract: According to one embodiment, a memory device includes first and second electrically conductive portions, a first variable resistance portion, and a first region. A direction from the first electrically conductive portion toward the second electrically conductive portion is aligned with a first direction. The first variable resistance portion is provided between the first and second electrically conductive portions. A second direction from the first variable resistance portion toward the first region crosses the first direction. The first region includes a first layer portion, and a second layer portion provided between the first layer portion and the first variable resistance portion in the second direction. A first distance between the first and second layer portions is longer than first or second lattice length. The first lattice length is a lattice length of the first layer portion. The second lattice length is a lattice length of the second layer portion.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: May 5, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Toshiya Murakami, Akihiro Kajita, Masumi Saitoh
  • Patent number: 10636875
    Abstract: A semiconductor device includes a plurality of base layers. A tunneling layer is disposed on the plurality of base layers. A contact layer is disposed on the tunneling layer. An alloyed metal contact is annealed on to the contact layer. The alloyed metal contact forms a first region and a second region in the contact layer. The first region of the contact layer diffuses into the tunneling layer. The second region of the contact layer resides over the tunneling layer. The tunneling layer facilitates electron mobility of the second region.
    Type: Grant
    Filed: January 21, 2019
    Date of Patent: April 28, 2020
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Yeong-Chang Chou, Hsu-Hwei Chen, Hui Ma, Thomas R. Young, Youngmin Kim, Jansen J. Uyeda
  • Patent number: 10636881
    Abstract: A high electron mobility transistor (HEMT) device with epitaxial layers that include a gallium nitride (GaN) layer and an aluminum (Al) based layer having an interface with the GaN layer is disclosed. The Al based layer includes Al and an alloying element that is selected from Group IIIB transition metals of the periodic table of elements. The epitaxial layers are disposed over the substrate. A gate contact, a drain contact, and a source contact are disposed on a surface of the epitaxial layers such that the source contact and the drain contact are spaced apart from the gate contact and each other. The alloying element relieves lattice stress between the GaN layer and the Al based layer while maintaining a high sheet charge density within the HEMT device.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: April 28, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Edward A. Beam, III, Jinqiao Xie
  • Patent number: 10636884
    Abstract: A nitride semiconductor device includes a silicon substrate. A nitride semiconductor layer is formed over the silicon substrate. A gate electrode is formed over the nitride semiconductor layer so as to have a first ring-shaped portion and a second ring-shaped portion connected to the first ring-shaped portion. A first finger electrode is surrounded by the first ring-shaped portion. A second finger electrode is surrounded by the second ring-shaped portion. A third finger electrode is interposed between the first ring-shaped portion and the second ring-shaped portion.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: April 28, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Taketoshi Tanaka
  • Patent number: 10636907
    Abstract: Embodiments of the invention include a non-planar transistor with a strained channel and methods of forming such a transistor. In an embodiment, the non-planar transistor may include a semiconductor substrate. According to an embodiment, a first source/drain (S/D) region and a second S/D region may be formed over the semiconductor substrate and separated from each other by a channel region. A gate stack may be formed over the channel region. In order to increase the amount of strain that may be induced in the channel region, embodiments may include forming a strain enhancement opening in the semiconductor substrate that removes at least a portion of the semiconductor substrate from below the channel region.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: April 28, 2020
    Assignee: Intel Corporation
    Inventors: Aaron D. Lilak, Stephen M. Cea, Rishabh Mehandru, Patrick Morrow, Patrick H. Keys
  • Patent number: 10629750
    Abstract: The purpose of the invention is to form the TFT of the oxide semiconductor, in which influence of variation in mask alignment is suppressed, thus, manufacturing a display device having a TFT of stable characteristics. The concrete measure is as follows. A display device including plural pixels, each of the plural pixels having a thin film transistor (TFT) of an oxide semiconductor comprising: a width of the oxide semiconductor in the channel width direction is wider than a width of the gate electrode in the channel width direction.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: April 21, 2020
    Assignee: Japan Display Inc.
    Inventors: Takeshi Sakai, Yuichiro Hanyu, Masahiro Watabe
  • Patent number: 10629724
    Abstract: According to one embodiment, a semiconductor device includes first, second and third electrodes, first, second, third, and fourth semiconductor regions, and an insulating portion. The first electrode includes first and second electrode portions. The first semiconductor region includes first, second, and third semiconductor portions. The first semiconductor portion is provided between the first electrode portion and the second electrode. The second semiconductor portion is provided between the second electrode portion and the third electrode. The third semiconductor portion is provided between the first and second semiconductor portions. The second semiconductor region is provided between the first semiconductor portion and the second electrode. The third semiconductor region is positioned between the second semiconductor region and the third electrode. The insulating portion includes first and second insulating regions.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: April 21, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenjiro Uesugi, Shigeya Kimura, Masahiko Kuraguchi
  • Patent number: 10629688
    Abstract: An epitaxial substrate for semiconductor elements suppresses leakage current and has a high breakdown voltage. The epitaxial substrate for semiconductor elements includes: a semi-insulating free-standing substrate formed of GaN doped with Zn; a buffer layer formed of a group 13 nitride adjacent to the free-standing substrate; a channel layer formed of a group 13 nitride adjacent to the buffer layer; and a barrier layer formed of a group 13 nitride on an opposite side of the buffer layer with the channel layer therebetween, wherein part of a first region consisting of the free-standing substrate and the buffer layer is a second region containing Si at a concentration of 1×1017 cm?3 or more, and a minimum value of a concentration of Zn in the second region is 1×1017 cm?3.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: April 21, 2020
    Assignee: NGK INSULATORS, LTD.
    Inventors: Mikiya Ichimura, Sota Maehara, Yoshitaka Kuraoka
  • Patent number: 10629596
    Abstract: A fin-type field effect transistor comprising a substrate, at least one gate stack and epitaxy material portions is described. The substrate has fins and insulators located between the fins, and the fins include channel portions and flank portions beside the channel portions. The at least one gate stack is disposed over the insulators and over the channel portions of the fins. The epitaxy material portions are disposed over the flank portions of the fins and at two opposite sides of the at least one gate stack. The epitaxy material portions disposed on the flank portions of the fins are separate from one another.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun Hsiung Tsai, Ziwei Fang, Tsan-Chun Wang, Kei-Wei Chen
  • Patent number: 10629729
    Abstract: A vFET includes a first impurity region doped with first impurities at an upper portion of the substrate. A first diffusion control pattern is formed on the first impurity region. The first diffusion control pattern is configured to control the diffusion of the first impurities. A channel extends in a vertical direction substantially orthogonal to an upper surface of the substrate. A second impurity region is doped with second impurities on the channel. A second diffusion control pattern is between the channel and the second impurity region. The second diffusion control pattern is configured to control the diffusion of the second impurities. A gate structure is adjacent to the channel.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: April 21, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Gun You, Chang-Hee Kim, Sung-Il Park, Dong-Hun Lee
  • Patent number: 10629716
    Abstract: A semiconductor device has a lateral switching device that includes a channel forming layer, a gate structure portion, a source electrode, a drain electrode, a third semiconductor layer, a fourth semiconductor layer, and a junction gate electrode. The gate structure portion has a gate insulating film provided in a recess portion of the channel forming layer and a MOS gate electrode functioning as a gate electrode of a MOS structure provided on the gate insulating film. The source electrode and the junction gate electrode are coupled through an electrode layer provided on an interlayer insulating film covering the MOS gate electrode. An end of the third semiconductor layer facing the drain electrode protrudes toward the drain electrode from an end of the fourth semiconductor layer facing the drain electrode by a distance in a range of 1 ?m to 5 ?m both inclusive.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: April 21, 2020
    Assignee: DENSO CORPORATION
    Inventors: Hiroyuki Tarumi, Kazuhiro Oyama, Youngshin Eum, Shinichi Hoshi
  • Patent number: 10629735
    Abstract: A semiconductor device and a method for fabricating a semiconductor device involve a semiconductor layer that includes a first material and a second material. The first and second materials can be silicon and germanium. A contact of the device has a portion proximal to the semiconductor layer and a portion distal to the semiconductor layer. The distal portion includes the first material and the second material. A metal layer formed adjacent to the relaxed semiconductor layer and adjacent to the distal portion of the contact is simultaneously reacted with the relaxed semiconductor layer and with the distal portion of the contact to provide metallic contact material.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Matthew T. Currie, Richard Hammond
  • Patent number: 10615098
    Abstract: Devices, systems, and methods for dissipating heat generated from an electrical current carrying device are provided herein. The disclosed concept provides a dielectric heat path device that assists in heat dissipation of an electrical current carrying device by transferring heat from one end of the device to another. The disclosed concept also provides systems that communicate heat generated by an electrical device to a thermally grounded secondary device through a dielectric heat path device to dissipate heat.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: April 7, 2020
    Assignee: EATON INTELLIGENT POWER LIMITED
    Inventors: Tony Ray Benson, Peter J. Fritz
  • Patent number: 10615043
    Abstract: Methods are provided to form pure silicon oxide layers on silicon-germanium (SiGe) layers, as well as an FET device having a pure silicon oxide interfacial layer of a metal gate structure formed on a SiGe channel layer of the FET device. For example, a method comprises growing a first silicon oxide layer on a surface of a SiGe layer using a first oxynitridation process, wherein the first silicon oxide layer comprises nitrogen. The first silicon oxide layer is removed, and a second silicon oxide layer is grown on the surface of the SiGe layer using a second oxynitridation process, which is substantially the same as the first oxynitridation process, wherein the second silicon oxide layer is substantially devoid of germanium oxide and nitrogen. For example, the first silicon oxide layer comprises a SiON layer and the second silicon oxide layer comprises a pure silicon dioxide layer.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: April 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Pouya Hashemi, Hemanth Jagannathan, Choonghyun Lee, Vijay Narayanan
  • Patent number: 10608083
    Abstract: Methods are provided to construct field-effect transistors comprising low-resistance metallic gate structures. A field-effect transistor includes a nanosheet stack and a metal gate which covers a gate region of the nanosheet stack. The nanosheet stack includes nanosheet channel layers and an etch stop layer disposed above an upper nanosheet channel layer. The metal gate includes a work function metal which encapsulates the nanosheet channel layers, and a gate electrode disposed above and in contact with the work function metal. An upper surface of the work function metal is recessed to be substantially coplanar with the etch stop layer. The gate electrode has a resistivity which is less than a resistivity of the work function metal. The etch stop layer protects the portion of the work function metal disposed between the etch stop layer and the upper nanosheet channel layer from being etched when recessing the work function metal.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: March 31, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Chen Zhang, Wenyu Xu, Xin Miao
  • Patent number: 10593666
    Abstract: A cascode switch structure includes a group III-V transistor structure having a first current carrying electrode, a second current carrying electrode and a first control electrode. A semiconductor MOSFET device includes a third current carrying electrode electrically connected to the first current carrying electrode, a fourth current carrying electrode electrically connected to the first control electrode, and a second control electrode. A first diode includes a first cathode electrode electrically connected to the second current carrying electrode and a first anode electrode. A second diode includes a second anode electrode electrically connected to the first anode electrode and a second cathode electrode electrically connected to the fourth current carrying electrode. In one embodiment, the group III-V transistor structure, the first diode, and the second diode are integrated within a common substrate.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: March 17, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Balaji Padmanabhan, Prasad Venkatraman, Zia Hossain, Chun-Li Liu, Jason McDonald, Ali Salih, Alexander Young
  • Patent number: 10593764
    Abstract: A high electron mobility transistor (HEMT) device with epitaxial layers that include a gallium nitride (GaN) layer and an aluminum (Al) based layer having an interface with the GaN layer is disclosed. The Al based layer includes Al and an alloying element that is selected from Group IIIB transition metals of the periodic table of elements. The epitaxial layers are disposed over the substrate. A gate contact, a drain contact, and a source contact are disposed on a surface of the epitaxial layers such that the source contact and the drain contact are spaced apart from the gate contact and each other. The alloying element relieves lattice stress between the GaN layer and the Al based layer while maintaining a high sheet charge density within the HEMT device.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: March 17, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Edward A. Beam, III, Jinqiao Xie
  • Patent number: 10586737
    Abstract: A method for manufacturing a semiconductor device includes forming a fin on a substrate, removing one or more portions of the fin prior to forming a gate structure on the fin, forming the gate structure on the fin, and simultaneously removing one or more additional portions of the fin and one or more portions of the gate structure aligned with the one or more additional portions of the fin to create a fin edge portion aligned with a gate structure edge portion.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: March 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 10585093
    Abstract: The present invention provides a bio-sensing device. The bio-sensing device includes an array of unit cells, each unit cell including: a source electrode and a drain electrode spaced apart from each other; a sensing film which is a channel between the source electrode and the drain electrode; and gate electrodes spaced apart from the sensing film, wherein the gate electrodes include an upper gate electrode and a lower gate electrode that are vertically spaced apart from each other.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: March 10, 2020
    Assignee: NDD, INC.
    Inventors: Sae Young Ahn, Hyun Hwa Kwon
  • Patent number: 10580865
    Abstract: Embodiments of the present disclosure describe a semiconductor multi-gate transistor having a semi-conductor fin extending from a substrate and including a sub-fin region and an active region. The sub-fin region may include a dielectric material region under the gate to provide improved isolation. The dielectric material region may be formed during a replacement gate process by replacing a portion of a sub-fin region under the gate with the dielectric material region, followed by fabrication of a replacement gate structure. The sub-fin region may be comprised of group III-V semiconductor materials in various combinations and concentrations. The active region may be comprised of a different group III-V semiconductor material. The dielectric material region may be comprised of amorphous silicon. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: March 3, 2020
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Matthew V. Metz, Gilbert Dewey, Chandra S. Mohapatra, Nadia M. Rahhal-Orabi, Jack T. Kavalieros, Anand S. Murthy, Tahir Ghani
  • Patent number: 10580881
    Abstract: A method of forming a vertical fin field effect transistor device, including, forming one or more vertical fins with a hardmask cap on each vertical fin on a substrate, forming a fin liner on the one or more vertical fins and hardmask caps, forming a sacrificial liner on the fin liner, and forming a bottom spacer layer on the sacrificial liner.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: March 3, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Hemanth Jagannathan, Paul C. Jamison, ChoongHyun Lee
  • Patent number: 10566449
    Abstract: The present invention is a FET having a p-doped or acceptor-doped layer underneath a FET channel to enable E/D Mode operation. A FET threshold voltage is tunable through a voltage applied to the p-doped layer via a metal contact such as a threshold-control terminal (TCT). The present invention has a dual E/D mode operation of a single FET device, and also a dual E/D mode operation with a single-polarity positive power supply voltage. The FET of the present invention is fabricated to enable dual enhancement-mode/depletion-mode (E-Mode/D-Mode) high electron mobility transistors (HEMTs), to enable dual E/D Mode operation by incorporating a p-doped or acceptor doped region underneath the channel, to achieve a tunable threshold voltage by varying the bias voltage on a fourth terminal called the threshold-control terminal (TCT) that contacts the p-doped layer, and to enable Dual E/D-Mode operation of a HEMT with a single-polarity positive power supply voltage.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: February 18, 2020
    Assignee: Duet Microelectronics, Inc.
    Inventors: John Bayruns, Robert J. Bayruns, Ashok T. Ramu
  • Patent number: 10559565
    Abstract: An integrated circuit (IC) device includes a first and a second fin-type active region protruding from a first region and a second region, respectively, of a substrate, a first and a second gate line, and a first and a second source/drain region. The first fin-type active region has a first top surface and a first recess has a first depth from the first top surface. The first source/drain region fills the first recess and has a first width. The second fin-type active region has a second top surface and a second recess has a second depth from the second top surface. The second depth is greater than the first depth. The second source/drain region fills the second recess and has a second width. The second width is greater than the first width.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: February 11, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-han Lee, Sun-ghil Lee, Myung-il Kang, Jeong-yun Lee, Seung-hun Lee, Hyun-jung Lee, Sun-wook Kim
  • Patent number: 10559690
    Abstract: A shallow trench isolation layer is formed on a structure comprising semiconductor fins. Portions of the fins are recessed to a level below the shallow trench isolation layer. Epitaxial stressor regions are then formed on the recessed fin areas. A bottom portion of the epitaxial stressor regions are contained by the shallow trench isolation layer, which delays formation of the diamond shape as the epitaxial region is grown. Once the epitaxial stressor regions exceed the level of the shallow trench isolation layer, the diamond shape starts to form. The result of delaying the start of the diamond growth pattern is that the epitaxial regions are narrower for a given fin height. This allows for taller fins, which provide more current handling capacity, while the narrower epitaxial stressor regions enable a smaller fin pitch, allowing for increased circuit density.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: February 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz, Henry K. Utomo, Reinaldo Ariel Vega
  • Patent number: 10546936
    Abstract: A structure of a semiconductor device is described. A semiconductor device includes a transistor which further includes a gate structure, a source region and a drain region disposed on a first surface of a substrate. A wiring layer of conductive material is disposed over a second surface of the substrate. The second surface of the substrate is located opposite to the first surface of the substrate. A set of contact studs including a first contact stud which extends completely through the source region and through the substrate to a first respective portion of the wiring layer. The set of contact studs also includes a second contact stud which extends completely through the drain region and through the substrate to a second respective portion of the wiring layer. A gate contact stud electrically couples the gate structure and extends completely through the substrate to a third respective portion of the wiring layer disposed over the second surface of the substrate.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: January 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Carl J Radens, Richard Q Williams
  • Patent number: 10541335
    Abstract: A method for inducing stress in a device channel includes forming a stress adjustment layer on a substrate, the stress adjustment layer including an as deposited stress due to crystal lattice differences with the substrate. A device channel layer is formed on the stress adjustment layer. Cuts are etched through the device channel layer and the stress adjustment layer to release the stress adjustment layer to induce stress in the device channel layer. Source/drain regions are formed adjacent to the device channel layer.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: January 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Nicolas J. Loubet, Xin Miao, Alexander Reznicek
  • Patent number: 10541319
    Abstract: A method of forming first and second fin field effect transistors (finFETs) on a substrate includes forming first and second fin structures of the first and second finFETs, respectively, on the substrate. The first and second fin structures have respective first and second vertical dimensions that are about equal to each other. The method further includes modifying the first fin structure such that the first vertical dimension of the first fin structure is smaller than the second vertical dimension of the second fin structure and depositing a dielectric layer on the modified first fin structure and the second fin structure. The method further includes forming a polysilicon structure on the dielectric layer and selectively forming a spacer on a sidewall of the polysilicon structure.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: January 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Shi Ning Ju
  • Patent number: 10541313
    Abstract: A method of forming a semiconductor device includes providing a heterojunction semiconductor body. The heterojunction semiconductor body includes a first type III-V semiconductor layer and a second type III-V semiconductor layer formed over the first type III-V semiconductor layer. The second type III-V semiconductor layer has a different bandgap as the first type III-V semiconductor layer such that a first two-dimensional charge carrier gas forms at an interface between the first and second type III-V semiconductor layers. The second type III-V semiconductor layer has a thicker section and a thinner section. A first input-output electrode is formed on the thicker section. A gate structure and a second input-output are formed on the thinner section. The gate structure is laterally spaced apart from a transition between the thicker and thinner sections of the second type III-V semiconductor layer.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: January 21, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Gilberto Curatola, Oliver Haeberlen
  • Patent number: 10535735
    Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron-doped germanium-tin alloy layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs and nanowire transistors). The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: January 14, 2020
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Anand S. Murthy
  • Patent number: 10529739
    Abstract: A semiconductor device with one or more fin structures formed from a first material, gate, source, and drain regions formed from a second material, and a contact insulator layer deposited over the substrate, where an etching process applied to the substrate removes the insulator to create a trench over the source region. The device also includes a lower band gap source material that is deposited into the trench, a second contact insulator layer, and a metalizing material that is deposited over the substrate. In some embodiments, the device also includes a higher band gap source material that is deposited into the trench, a second contact insulator layer, and a metalizing material that is deposited over the substrate.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: January 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Effendi Leobandung
  • Patent number: 10529808
    Abstract: An apparatus including a transistor device on a substrate including an intrinsic layer including a channel; a source and a drain on opposite sides of the channel; and a diffusion barrier between the intrinsic layer and each of the source and the drain, the diffusion barrier including a conduction band energy that is less than a conduction band energy of the channel and greater than a material of the source and drain. A method including defining an area of an intrinsic layer on a substrate for a channel of a transistor device; forming a diffusion barrier layer in an area defined for a source and a drain; and forming a source on the diffusion barrier layer in the area defined for the source and forming a drain in the area defined for the drain.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: January 7, 2020
    Assignee: Intel Corporation
    Inventors: Chandra S. Mohapatra, Harold W. Kennel, Glenn A. Glass, Will Rachmady, Gilbert Dewey, Jack T. Kavalieros, Anand S. Murthy, Tahir Ghani, Matthew V. Metz, Sean T. Ma
  • Patent number: 10529841
    Abstract: A field effect transistor having a reduced sheet resistance is provided. A channel layer, a first spacer layer, a second spacer layer, a first electronic barrier layer, and a second electronic barrier layer are sequentially grown on the main surface of a substrate. A gate recess is created, and then an ion implanted section is formed. A third electronic barrier layer and a p-type layer are formed by a metalorganic chemical vapor deposition (MOCVD) method. The p-type layer except a portion at the gate recess is removed. B ions are implanted in the regrown third electronic barrier layer to reform the ion implanted section. A source electrode and a drain electrode are formed on the third electronic barrier layer. Then a gate electrode is formed on the p-type layer.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: January 7, 2020
    Assignee: Panasonic Corporation
    Inventors: Ryo Kajitani, Kenichiro Tanaka, Masahiro Ishida, Tetsuzo Ueda
  • Patent number: 10522681
    Abstract: A method and structure for mitigating strain loss (e.g., in a FinFET channel) includes providing a semiconductor device having a substrate having a substrate fin portion, an active fin region formed over a first part of the substrate fin portion, a pickup region formed over a second part of the substrate fin portion, and an anchor formed over a third part of the substrate fin portion. In some embodiments, the substrate fin portion includes a first material, and the active fin region includes a second material different than the first material. In various examples, the anchor is disposed between and adjacent to each of the active fin region and the pickup region.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Hsiung Wang, Yung Feng Chang, Tung-Heng Hsieh
  • Patent number: 10516041
    Abstract: An HEMT includes a buffer layer, a hole-supply layer on the buffer layer, a heterostructure on the hole-supply layer, and a source electrode. The hole-supply layer is made of P-type doped semiconductor material, the buffer layer is doped with carbon, and the source electrode is in direct electrical contact with the hole-supply layer, such that the hole-supply layer can be biased to facilitate the transport of holes from the hole-supply layer to the buffer layer.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: December 24, 2019
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Ferdinando Iucolano, Alessandro Chini
  • Patent number: 10516042
    Abstract: An III group nitride semiconductor device comprises: a substrate; a nitride semiconductor layer located on the substrate; a passivation layer located on the nitride semiconductor layer, a portion of the passivation layer in a gate region being etched to expose the nitride semiconductor layer so as to form a gate groove; a composite dielectric layer located on the passivation layer and the gate groove, the composite dielectric layer comprising one or more combination structures of two or more of a nitride dielectric layer, an oxynitride dielectric layer and an oxide dielectric layer which are formed sequentially in the direction away from the substrate; and a source electrode and a drain electrode respectively located in a source region and a drain region on the nitride semiconductor layer, and a gate electrode located in a gate region between the source region and the drain region on the composite dielectric layer.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: December 24, 2019
    Assignee: ENKRIS SEMICONDUCTOR, INC.
    Inventor: Kai Cheng
  • Patent number: 10515846
    Abstract: A multilayer semiconductor device structure having different circuit functions on different semiconductor device layers is provided. The semiconductor structure comprises a first semiconductor device layer fabricated on a bulk substrate. The first semiconductor device layer comprises a first semiconductor device for performing a first circuit function. The first semiconductor device layer includes a patterned top surface of different materials. The semiconductor structure further comprises a second semiconductor device layer fabricated on a semiconductor-on-insulator (“SOI”) substrate. The second semiconductor device layer comprises a second semiconductor device for performing a second circuit function. The second circuit function is different from the first circuit function. A bonding surface coupled between the patterned top surface of the first semiconductor device layer and a bottom surface of the SOI substrate is included.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Yi-Tang Lin, Chun Hsiung Tsai, Clement Hsingjen Wann
  • Patent number: 10510829
    Abstract: A method for forming a semiconductor structure is disclosed. The method provides a substrate with an insulator pad overlying at least a top portion of the substrate. The method further includes forming a plurality of dielectric columns overlying the substrate and the dielectric pad. Each dielectric column is separated from another dielectric column to form a corresponding plurality of aspect-ration trapping (ART) trenches. The insulator pad spans a bottom portion of a first ART trench of the plurality of ART trenches. A portion of the substrate spans a bottom portion of a second ART trench of the plurality of ART trenches. The method further includes forming a III-V semiconductor material stack in the second ART trench. The method further includes forming a first resistive region in the first ART trench, wherein the first resistive region is in contact with the insulator pad.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: December 17, 2019
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Chih-Chao Yang, Praneet Adusumilli, Oscar Van Der Straten
  • Patent number: 10510889
    Abstract: In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shahaji B. More, Huai-Tei Yang, Shih-Chieh Chang, Shu Kuan, Cheng-Han Lee
  • Patent number: 10505000
    Abstract: An electronic device can include a transistor structure. In an embodiment, the transistor structure can include a channel region and a drift structure including different semiconductor base materials. In another embodiment, the transistor structure can include a source region and a drain structure including a first region, wherein the source region and the first region include different semiconductor base materials and have the same conductivity type. In another aspect, a process of forming an electronic device can include forming a semiconductor layer; forming a body region; patterning the body region and the semiconductor layer to define a trench having a sidewall; forming a first region of a drain structure along the sidewall of the trench, wherein the first region and body region include different semiconductor base materials and different conductivity types.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: December 10, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Peter Moens, Piet Vanmeerbeek, Gary H. Loechelt, John Michael Parsey, Jr.
  • Patent number: 10497803
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to fully depleted silicon on insulator (SOI) semiconductor structures and methods of manufacture. The structure includes: a gate structure formed over a semiconductor material; a source region adjacent to the gate structure; a drain region remote from the gate structure; and a drift region separating the gate structure from the drain region. The drift region includes an epitaxial material grown on the semiconductor material which increases the thickness of the semiconductor material in the drift region.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: December 3, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ignasi Cortes Mayol, Christian Schippel, Alban Zaka, Tom Herrmann, El Mehdi Bazizi
  • Patent number: 10490743
    Abstract: A crossbar switch comprising: a first interconnect, a second interconnect, and a resistance change element. The resistance change element includes: a first electrode connected to the first interconnect and a second electrode connected to the second interconnect which are embedded in a first insulating film on a substrate having a transistor; a second insulating film covering the first insulating film and the first and second electrodes; first and second opening portions exposing parts of an upper surface including end portions of the first and second electrodes from the second insulating film with translational symmetry; first and second resistance change films covering the first and second opening portions and connecting to the first and second electrodes at the opening portions; third and fourth electrodes connecting to the first and second resistance change films; a fifth electrode connecting to the third and fourth electrodes and to a diffusion layer of the transistor.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: November 26, 2019
    Assignee: NEC CORPORATION
    Inventors: Toshitsugu Sakamoto, Munehiro Tada
  • Patent number: 10490551
    Abstract: A semiconductor device includes: a substrate including a field region that defines an active region; source/drain regions in the active region; a channel region between the source/drain regions; a lightly doped drain (LDD) region between one of the source/drain regions and the channel region; and a gate structure disposed on the channel region. An upper portion of the active region may include an epitaxial growth layer having a larger lattice constant than silicon (Si), and the source/drain regions and the LDD region may be doped with gallium (Ga).
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: November 26, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong-Shik Shin, Tae-Gon Kim, Yuichiro Sasaki
  • Patent number: 10483152
    Abstract: A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, an optionally relaxed semiconductor layer comprising silicon, germanium, or silicon germanium, an optional polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: November 19, 2019
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Igor Peidous, Lu Fei, Jeffrey L. Libbert, Andrew M. Jones, Alex Usenko, Gang Wang, Shawn George Thomas, Srikanth Kommu
  • Patent number: 10483172
    Abstract: A device includes a substrate having an N-active region and a P-active region, a layer of silicon-carbon positioned on an upper surface of the N-active region, a first layer of a first semiconductor material positioned on the layer of silicon-carbon, a second layer of the first semiconductor material positioned on an upper surface of the P-active region, and a layer of a second semiconductor material positioned on the second layer of the first semiconductor material. An N-type transistor is positioned in and above the N-active region and a P-type transistor is positioned in and above the P-active region.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: November 19, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Vara G. Reddy Vakada, Laegu Kang, Michael Ganz, Yi Qi, Puneet Khanna, Srikanth Balaji Samavedam, Sri Charan Vemula, Manfred Eller
  • Patent number: 10475899
    Abstract: A method of forming a GAA FinFET, including: forming a fin on a substrate, the substrate having a STI layer formed thereon and around a portion of a FIN-bottom portion of the fin, the fin having a dummy gate formed thereover, the dummy gate having a gate sidewall spacer on sidewalls thereof; forming a FIN-void and an under-FIN cavity in the STI layer; forming first spacers by filling the under-FIN cavity and FIN-void with a first fill; removing the dummy gate, thereby exposing both FIN-bottom and FIN-top portions of the fin underneath the gate; creating an open area underneath the exposed FIN-top by removing the exposed FIN-bottom; and forming a second spacer by filling the open area with a second fill; wherein a distance separates a top-most surface of the second spacer from a bottom-most surface of the FIN-top portion. A GAA FinFET formed by the method is also disclosed.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: November 12, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Andreas Knorr, Julien Frougier, Hui Zang, Min-hwa Chi
  • Patent number: 10475883
    Abstract: In a semiconductor device, a width of a second epitaxial layer is greater than a width of a first epitaxial layer, and a thickness of an end portion of the second epitaxial layer, which is in contact with an element isolation portion, is smaller than a thickness of an end portion of the first epitaxial layer, which is in contact with the element isolation portion, and a second shortest distance between the element isolation portion and a second plug is greater than a first shortest distance between the element isolation portion and a first plug.
    Type: Grant
    Filed: December 10, 2017
    Date of Patent: November 12, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Masaru Kadoshima, Masahiko Fujisawa