Field Effect Transistor Patents (Class 257/192)
  • Patent number: 10998401
    Abstract: According to one embodiment, a semiconductor device includes a base body including silicon carbide, a first semiconductor region including silicon carbide and a first element, and a second semiconductor region including silicon carbide and the first element. The first semiconductor region includes first and second intermediate regions. A first concentration of the first element in the first intermediate region satisfies a first or a second condition. In the first condition, the first concentration is lower than a second concentration of the first element in the second intermediate region. In the second condition, the first concentration is higher than a third concentration of a second element included in the first intermediate region, the second concentration is higher than a fourth concentration of the second element in the second intermediate region, and a difference between the first and third concentrations is smaller than a difference between the second and fourth concentrations.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: May 4, 2021
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Johji Nishio, Chiharu Ota, Ryosuke Iijima
  • Patent number: 10998425
    Abstract: A device includes a fin structure protruding over a substrate, wherein the fin structure comprises a plurality of portions formed of different materials, a first carbon doped layer formed between two adjacent portions of the plurality of portions, a second carbon doped layer formed underlying a first source/drain region and a third carbon doped layer formed underlying a second source/drain region.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: May 4, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Chiang, Guan-Lin Chen, Chao-Hsiung Wang, Chi-Wen Liu
  • Patent number: 10998442
    Abstract: A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: May 4, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Lin Lee, Chih-Hao Chang, Chih-Hsin Ko, Feng Yuan, Jeff J. Xu
  • Patent number: 10998343
    Abstract: A thin-film transistor (TFT) array substrate is provided. The TFT array substrate includes a base substrate, a semiconductor layer disposed on the base substrate, an insulating layer disposed on the semiconductor layer, and a gate electrode disposed on the insulating layer. A top surface of a portion of the insulating layer overlapping the semiconductor layer in a plan view of the base substrate and a top surface of the gate electrode are placed on the same level.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: May 4, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Byoung Kwon Choo, Joon Hwa Bae, Hyun Jin Cho, Jun Hyuk Cheon, Zi Yeon Yoon, Woo Jin Cho, Sung Hwan Choi, Jeong Hye Choi
  • Patent number: 10991831
    Abstract: A layer according to one embodiment of the present invention may exhibit a first number of electron states in a low-level electron energy range in a conduction band, and exhibit a second number of electron states in a high-level electron energy range higher than the low-level electron energy level in the conduction band, wherein localized states may exist between the low-level electron energy range and the high-level electron energy level.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: April 27, 2021
    Assignee: IUCF-HYU (INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY)
    Inventors: Myung Mo Sung, Jinwon Jung, Hongbum Kim, Jin Seon Park
  • Patent number: 10991687
    Abstract: FinFET varactors having low threshold voltages and methods of making the same are disclosed herein. An exemplary FinFET varactor includes a fin and a gate structure disposed over a portion of the fin, such that the gate structure is disposed between a first source/drain feature and a second source/drain feature that include a first type dopant. The portion of the fin includes the first type dopant and a second type dopant. A dopant concentration of the first type dopant and a dopant concentration of the second type dopant vary from an interface between the fin and the gate structure to a first depth in the fin. The dopant concentration of the first type dopant is greater than the dopant concentration of the second type dopant from a second depth to a third depth in the fin, where the second depth and the third depth are less than the first depth.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: April 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fu-Huan Tsai, Han-Min Tsai, Chia-Chung Chen, Chi-Feng Huang, Victor Chiang Liang
  • Patent number: 10991575
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, and first and second layers. A direction from the first electrode toward the second electrode is aligned with a first direction. A position in the first direction of the third electrode is between positions in the first direction of the first and second electrodes. The first layer includes at least one selected from the group consisting of silicon carbide, silicon, carbon, and germanium. The first layer includes first to sixth partial regions. A concentration of the first impurity in the fourth partial region is higher than a concentration of the first impurity in the fifth partial region and higher than a concentration of the first impurity in the sixth partial region. The second layer includes AlxGa1-xN (0<x?1). The second layer includes a first portion and a second portion.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: April 27, 2021
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisashi Yoshida, Shigeya Kimura
  • Patent number: 10985263
    Abstract: An apparatus is provided which comprises: a semiconductor region on a substrate, a gate stack on the semiconductor region, a source region of doped semiconductor material on the substrate adjacent a first side of the semiconductor region, a cap region on the substrate adjacent a second side of the semiconductor region, wherein the cap region comprises semiconductor material of a higher band gap than the semiconductor region, and a drain region comprising doped semiconductor material on the cap region. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 31, 2016
    Date of Patent: April 20, 2021
    Assignee: Intel Corporation
    Inventors: Seung Hoon Sung, Dipanjan Basu, Ashish Agrawal, Van H. Le, Benjamin Chu-Kung, Harold W. Kennel, Glenn A. Glass, Anand S. Murthy, Jack T. Kavalieros, Tahir Ghani
  • Patent number: 10978349
    Abstract: Semiconductor devices and fabrication methods are provided. An exemplary fabrication method includes forming a first type of fin sidewall spacers and a second type of fin sidewall spacers. The first type of fin sidewall spacers are formed on two sidewall surfaces of a third fin portion group along a width direction of the third fin portions and two sidewall surfaces of a fourth fin portion group along a width direction of the fourth fin portions. The second type of fin sidewall spacers are formed between adjacent third fin portions and sidewall surfaces of the third fin portions and between adjacent fourth fin portions and on sidewall surfaces of the fourth fin portions. Top surfaces of the first type of fin sidewall spacers are higher than top surfaces of the second type of fin sidewall spacers and top surfaces of the third fin portions and the fourth fin portions.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: April 13, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Poren Tang
  • Patent number: 10971617
    Abstract: Some embodiments of this disclosure provide a semiconductor device. The semiconductor device includes: a substrate; a barrier layer, disposed on the substrate; a first channel layer, disposed on the barrier layer; a first gate conductor, disposed on the first channel layer; and a first doped semiconductor layer, disposed between the first gate conductor and the first channel layer, where a forbidden band width of the barrier layer is greater than a forbidden band width of the first channel layer.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: April 6, 2021
    Assignee: INNOSCIENCE (ZHUHAI) TECHNOLOGYCO., LTD.
    Inventor: Ronghui Hao
  • Patent number: 10971391
    Abstract: Generally, examples are provided relating to filling gaps with a dielectric material, such as filling trenches between fins for Shallow Trench Isolations (STIs). In an embodiment, a first dielectric material is conformally deposited in a trench using an atomic layer deposition (ALD) process. After conformally depositing the first dielectric material, the first dielectric material is converted to a second dielectric material. In further examples, the first dielectric material can be conformally deposited in another trench, and a fill dielectric material can be flowed into the other trench and converted.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: April 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Yu-Yun Peng
  • Patent number: 10971625
    Abstract: A semiconductor device is provided, which includes an array of active regions, gate stacks and substantially uniform epitaxial structures. The gate stacks of the array include a first gate stack and a second gate stack over an active region. An active pillar between the first gate stack and the second gate stack, and the active pillar separating two substantially uniform epitaxial structures. A contact structure over the active pillar, positioned equidistant from the first gate stack and the second gate stack.
    Type: Grant
    Filed: June 30, 2019
    Date of Patent: April 6, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Michael V Aquilino, Daniel Jaeger, Man Gu, Bradley Morgenfeld, Haiting Wang, Kavya Sree Duggimpudi, Wang Zheng
  • Patent number: 10971579
    Abstract: The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a doped group III-V layer, a conductor structure, and a metal layer. The doped group III-V layer is disposed on the substrate. The conductor structure is disposed on the doped group III-V layer. The metal layer is disposed between the conductor structure and the doped group III-V layer.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: April 6, 2021
    Assignee: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.
    Inventor: King Yuen Wong
  • Patent number: 10971430
    Abstract: A semiconductor device may include a cooling unit, the cooling unit including a circuit unit, a first flow path member comprised of an insulating material, and a second flow path member comprised of an insulating material. The circuit unit may include a heat sink layer, a wiring layer, and a semiconductor element that is disposed between the heat sink layer and the wiring layer. The circuit unit is disposed between the first flow path member and the second flow path member. The wiring layer may face the first flow path member or the second flow path member.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: April 6, 2021
    Assignee: KYOCERA Corporation
    Inventor: Takeshi Muneishi
  • Patent number: 10964804
    Abstract: A semiconductor structure includes: a channel layer; an active layer over the channel layer, wherein the active layer is configured to form a two-dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer; a gate electrode over a top surface of the active layer; and a source/drain electrode over the top surface of the active layer; wherein the active layer includes a first layer and a second layer sequentially disposed therein from the top surface to a bottom surface of the active layer, and the first layer possesses a higher aluminum (Al) atom concentration compared to the second layer. An HEMT structure and an associated method are also disclosed.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: March 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yao-Chung Chang, Po-Chih Chen, Jiun-Lei Jerry Yu, Chun Lin Tsai
  • Patent number: 10964548
    Abstract: A method includes forming a semiconductor capping layer over a first fin in a first region of a substrate, forming a dielectric layer over the semiconductor capping layer, and forming an insulation material over the dielectric layer, an upper surface of the insulation material extending further away from the substrate than an upper surface of the first fin. The method further includes recessing the insulation material to expose a top portion of the first fin, and forming a gate structure over the top portion of the first fin.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yin Wang, Hung-Ju Chou, Jiun-Ming Kuo, Wei-Ken Lin, Chun Te Li
  • Patent number: 10964803
    Abstract: In some examples, a transistor comprises a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the GaN layer; and a first doped region positioned in a drain access region and extending from the top side into the GaN layer.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: March 30, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Dong Seup Lee, Jungwoo Joh, Pinghai Hao, Sameer Pendharkar
  • Patent number: 10964810
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a source region and a drain region within a substrate. A gate structure is formed over the substrate and between the source region and the drain region. One or more dielectric layers are formed over the gate structure, and a first inter-level dielectric (ILD) layer is formed over the one or more dielectric layers. The first ILD layer laterally surrounds the gate structure. The first ILD layer is etched to define contact openings and a field plate opening. The contact openings and the field plate opening are filled with a conductive material.
    Type: Grant
    Filed: September 21, 2019
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsueh-Liang Chou, Dah-Chuen Ho, Hui-Ting Lu, Po-Chih Su, Pei-Lun Wang, Yu-Chang Jong
  • Patent number: 10945643
    Abstract: In some embodiments, a microelectronic sensor includes an open-gate pseudo-conductive high-electron mobility transistor and used for biometric authentication of a user. The transistor comprises a substrate, on which a multilayer hetero-junction structure is deposited. This hetero-junction structure comprises a buffer layer and a barrier layer, both grown from III-V single-crystalline or polycrystalline semiconductor materials. A two-dimensional electron gas (2DEG) conducting channel is formed at the interface between the buffer and barrier layers and provides electron current in the system between source and drain electrodes. The source and drain contacts, which maybe either ohmic or non-ohmic (capacitively-coupled), are connected to the formed 2DEG channel and to electrical metallizations, the latter are placed on top of the transistor and connect it to the sensor system.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: March 16, 2021
    Assignee: EPITRONIC HOLDINGS PTE. LTD.
    Inventor: Ayal Ram
  • Patent number: 10944005
    Abstract: An embodiment is a semiconductor structure. The semiconductor structure includes a substrate. A fin is on the substrate. The fin includes silicon germanium. An interfacial layer is over the fin. The interfacial layer has a thickness in a range from greater than 0 nm to about 4 nm. A source/drain region is over the interfacial layer. The source/drain region includes silicon germanium.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: March 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Yun Chin, Chii-Horng Li, Chien-Wei Lee, Hsueh-Chang Sung, Heng-Wen Ting, Roger Tai, Pei-Ren Jeng, Tzu-Hsiang Hsu, Yen-Ru Lee, Yan-Ting Lin, Davie Liu
  • Patent number: 10943902
    Abstract: A method for manufacturing a semiconductor device includes growing a first strained semiconductor layer on a substrate, the first strained semiconductor layer having a first type of strain, wherein the substrate comprises a first crystalline orientation at a top surface of the substrate, forming at least one trench in the substrate, wherein exposed sidewalls of the at least one trench have a second crystalline orientation different from the first crystalline orientation, growing a buffer layer in the at least one trench from the exposed sidewalls of the trench, and growing a second strained semiconductor layer on the buffer layer, the second strained semiconductor layer having a second type of strain, wherein the first type of strain is different from the second type of strain.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: March 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: Juntao Li, Kangguo Cheng, John G. Gaudiello
  • Patent number: 10944003
    Abstract: A vFET includes a first impurity region doped with first impurities at an upper portion of the substrate. A first diffusion control pattern is formed on the first impurity region. The first diffusion control pattern is configured to control the diffusion of the first impurities. A channel extends in a vertical direction substantially orthogonal to an upper surface of the substrate. A second impurity region is doped with second impurities on the channel. A second diffusion control pattern is between the channel and the second impurity region. The second diffusion control pattern is configured to control the diffusion of the second impurities. A gate structure is adjacent to the channel.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: March 9, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Gun You, Chang-Hee Kim, Sung-Il Park, Dong-Hun Lee
  • Patent number: 10944270
    Abstract: An electronic circuit is disclosed. The electronic circuit includes a GaN substrate, a first power supply node on the substrate, an output node, a signal node, and an output component on the substrate, where the output component is configured to generate a voltage at the output node based at least in part on a voltage at the signal node. The electronic circuit also includes a capacitor coupled to the signal node, where, the capacitor is configured to selectively cause the voltage at the signal node to be greater than the voltage of the first power supply node, such that the output component causes the voltage at the output node to be substantially equal to the voltage of the first power supply node.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: March 9, 2021
    Assignee: NAVITAS SEMICONDUCTOR LIMITED
    Inventors: Daniel Marvin Kinzer, Santosh Sharma, Ju Zhang
  • Patent number: 10937903
    Abstract: A semiconductor diode including a first conductivity type region on an upper surface of a semiconductor substrate, a fin structure atop the first conductivity type region providing a vertically orientated semiconductor base region, and a second conductivity type region at a second end of the fin structure opposite a first end of the fin structure that is in contact with the first conductivity type region. The semiconductor diode may also include a vertically orientated dual gate that is present around the fin structure. The vertically orientated dual gate including a first gate structure that is present abutting the semiconductor substrate and a second gate structure that is in closer proximity to the second conductivity type region than the first conductivity type region. The first gate structure separated from the second gate structure by a dielectric inter-gate spacer.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: March 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Pouya Hashemi, Bahman Hekmatshoartabari, Alexander Reznicek
  • Patent number: 10937871
    Abstract: A semiconductor device comprises a first layer of a substrate arranged on a second layer of the substrate the second layer of the substrate including a doped III-V semiconductor material barrier layer, a gate stack arranged on a channel region of the first layer of a substrate, a spacer arranged adjacent to the gate stack on the first layer of the substrate, an undoped epitaxially grown III-V semiconductor material region arranged on the second layer of the substrate, and an epitaxially grown source/drain region arranged on the undoped epitaxially grown III-V semiconductor material region, and a portion of the first layer of the substrate.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: March 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng-Wei Cheng, Pranita Kerber, Amlan Majumdar, Yanning Sun
  • Patent number: 10930547
    Abstract: The present disclosure provides a semiconductor structure, including a first semiconductor device having a first surface and a second surface, the second surface being opposite to the first surface, a semiconductor substrate over the first surface of the first semiconductor device, and a III-V etch stop layer in contact with the second surface of the first semiconductor device. The present disclosure also provides a manufacturing method of a semiconductor structure, including providing a temporary substrate having a first surface, forming a III-V etch stop layer over the first surface, forming a first semiconductor device over the III-V etch to stop layer, and removing the temporary substrate by an etching operation and exposing a surface of the III-V etch stop layer.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: February 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Ying Tsai, Yeur-Luen Tu
  • Patent number: 10930507
    Abstract: A method of forming a semiconductor device includes performing a first implantation process on a semiconductor substrate to form a deep p-well region, performing a second implantation process on the semiconductor substrate with a diffusion-retarding element to form a co-implantation region, and performing a third implantation process on the semiconductor substrate to form a shallow p-well region over the deep p-well region. The co-implantation region is spaced apart from a top surface of the semiconductor substrate by a portion of the shallow p-well region, and the dee p-well region and the shallow p-well region are joined with each other. An n-type Fin Field-Effect Transistor (FinFET) is formed, with the deep p-well region and the shallow p-well region acting as a well region of the n-type FinFET.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: February 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sih-Jie Liu, Chun-Feng Nieh, Huicheng Chang
  • Patent number: 10916678
    Abstract: A method of is provided as a process of substrate lift-off. The present invention is mainly used for a group III-V solar cell, which has the highest power generation efficiency. An original sacrificial layer is changed into an AlAs oxide layer, which is transformed into an AlOx sacrificial layer after wet oxidation. The sacrificial layer is then soaked in an oxide-relief solution for etching. Thus, the lift-off process of a GaAs substrate can be harmlessly processed to the complex group III-V solar cell. The GaAs substrate can be recycled to be effectively further reused in photovoltaic devices with reduced cost.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: February 9, 2021
    Assignee: National Central University
    Inventor: Jin-Wei Shi
  • Patent number: 10912474
    Abstract: In some embodiments, the PC-HEMT based microelectronic sensors are used in recording physiological and non-physiological sounds as hypersensitive microphones. Recording the physiological sounds is associated with the S1/S2 heart split phenomena and phonocardiography.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: February 9, 2021
    Assignee: EPITRONIC HOLDINGS PTE LTD.
    Inventors: Ayal Ram, Gideon Kapan
  • Patent number: 10916638
    Abstract: A method of forming a fin field effect device is provided. The method includes forming one or more vertical fins on a substrate and a fin template on each of the vertical fins. The method further includes forming a gate structure on at least one of the vertical fins, and a top spacer layer on the at least one gate structure, wherein at least an upper portion of the at least one of the one or more vertical fins is exposed above the top spacer layer. The method further includes forming a top source/drain layer on the top spacer layer and the exposed upper portion of the at least one vertical fin. The method further includes forming a sacrificial spacer on opposite sides of the fin templates and the top spacer layer, and removing a portion of the top source/drain layer not covered by the sacrificial spacer to form a top source/drain electrically connected to the vertical fins.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: February 9, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Shogo Mochizuki, Choonghyun Lee, Juntao Li
  • Patent number: 10916545
    Abstract: A semiconductor device includes a substrate having a first region and a second region, a first transistor including a single first active fin disposed in the first region, a first gate electrode intersecting the single first active fin, and a single first source/drain layer disposed in the first recess of the single first active fin, and a second transistor including a plurality of second active fins disposed in the second region, a second gate electrode intersecting the plurality of second active fins, and a plurality of second source/drain layers disposed in the second recesses of the plurality of second active fins. The single first active fin and the plurality of second active fins may have a first conductivity type, and a depth of the first recess may be less than a depth of each of the second recesses.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: February 9, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyo Jin Kim, Dae Won Ha, Yoon Moon Park, Keun Hwi Cho
  • Patent number: 10916647
    Abstract: A method of manufacturing a III-V semiconductor circuit; the method comprising: forming a first layer of a III-V material on a growth substrate; forming a second layer of a III-V material on the first layer of III-V material; forming a FET transistor having a source electrode and a drain electrode in contact with a top surface of the second layer of a III-V material; forming a top dielectric layer above the FET transistor; forming a metal layer above the top dielectric layer, wherein said metal layer is connected to said source electrode; attaching a handle substrate to a top surface of the metal layer; removing the growth substrate from the bottom of the first layer of a III-V material; and forming a bottom dielectric layer on the bottom of the first layer of a III-V material.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: February 9, 2021
    Assignee: HRL Laboratories, LLC
    Inventors: Zijian “Ray” Li, Rongming Chu
  • Patent number: 10916424
    Abstract: A method for forming a semiconductor device comprising a graded wurtzite III-nitride alloy layer, including a wurtzite III-nitride alloy, on a second layer. A polarization doping concentration profile is selected for the graded wurtzite III-nitride alloy layer based on an intended function of the semiconductor device. Based on the selected polarization doping concentration profile for the graded wurtzite III-nitride alloy layer, a composition-polarization change rate of the graded wurtzite III-nitride alloy layer and a grading speed of the graded wurtzite III-nitride alloy layer are determined. The composition-polarization change rate and grading speed are based on a composition of first and second elements of the wurtzite III-nitride alloy.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: February 9, 2021
    Assignee: KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Xiaohang Li, Kaikai Liu
  • Patent number: 10903350
    Abstract: A semiconductor device includes a first composite III-V group compound semiconductor layer disposed on a composite substrate, and a second III-V group compound semiconductor layer disposed on the first composite III-V group compound semiconductor layer. The semiconductor device also includes a gate structure disposed on the second III-V group compound semiconductor layer, and a source electrode and a drain electrode disposed on the second III-V group compound semiconductor layer and at opposite sides of the gate structure. The semiconductor device further includes a field plate disposed between the gate structure and the drain electrode, and a conductive structure penetrating through the second III-V group compound semiconductor layer and the first composite III-V group compound semiconductor layer, wherein the field plate is electrically connected to the composite substrate through the conductive structure.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: January 26, 2021
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Cheng-Wei Chou, Hsin-Chih Lin, Yu-Chieh Chou
  • Patent number: 10903073
    Abstract: A method of manufacturing a semiconductor device includes forming a first epitaxial layer on a first substrate. The first substrate includes a first semiconductor material having a first lattice constant and the first epitaxial layer includes a second semiconductor material having a second lattice constant different from the first lattice constant. The method also includes disposing a graphene layer on the first epitaxial layer and forming a second epitaxial layer comprising the second semiconductor material on the graphene layer. This method can increase the substrate reusability, increase the release rate of functional layers, and realize precise control of release thickness.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: January 26, 2021
    Assignee: Massachusetts Institute of Technology
    Inventors: Jeehwan Kim, Kyusang Lee
  • Patent number: 10896976
    Abstract: A shallow trench isolation layer is formed on a structure comprising semiconductor fins. Portions of the fins are recessed to a level below the shallow trench isolation layer. Epitaxial stressor regions are then formed on the recessed fin areas. A bottom portion of the epitaxial stressor regions are contained by the shallow trench isolation layer, which delays formation of the diamond shape as the epitaxial region is grown. Once the epitaxial stressor regions exceed the level of the shallow trench isolation layer, the diamond shape starts to form. The result of delaying the start of the diamond growth pattern is that the epitaxial regions are narrower for a given fin height. This allows for taller fins, which provide more current handling capacity, while the narrower epitaxial stressor regions enable a smaller fin pitch, allowing for increased circuit density.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: January 19, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz, Henry K. Utomo, Reinaldo Ariel Vega
  • Patent number: 10896863
    Abstract: A semiconductor substrate (1) has a front surface and a rear surface facing each other. A gate wiring (2) and first and second front surface electrodes (3,4) are provided on the front surface of the semiconductor substrate (1). The first and second front surface electrodes (3,4) are separated from each other by the gate wiring (2). An insulating film (7) covers the gate wiring (2). An electrode layer (8) is provided on the insulating film (7) and the first and second front surface electrodes (3,4) across the gate wiring (2). A rear surface electrode (9) is provided on the rear surface of the semiconductor substrate (1). A first plated electrode (10) is provided on the electrode layer (8). A second plated electrode (11) is provided on the rear surface electrode (9).
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: January 19, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yosuke Nakata, Shinya Akao, Kenji Harada
  • Patent number: 10892401
    Abstract: This spin current magnetization rotational element includes a second ferromagnetic metal layer 1 having a variable magnetization orientation, and spin-orbit torque wiring 2, which extends in a direction that intersects a direction perpendicular to the surface of the second ferromagnetic metal layer 1, and is connected to the second ferromagnetic metal layer 1, wherein the spin resistance of a connection portion of the spin-orbit torque wiring layer 2 that is connected to the second ferromagnetic metal layer 1 is larger than the spin resistance of the second ferromagnetic metal layer 1.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: January 12, 2021
    Assignee: TDK CORPORATION
    Inventors: Tomoyuki Sasaki, Tohru Oikawa
  • Patent number: 10892327
    Abstract: A rectifying junction (15) is formed in a conduction path provided in a material (1). A size of the material (1) is smaller than a threshold size in a first dimension, the threshold size being the size required for the material (1) to exhibit sufficient quantum confinement such that it forms a semiconductor. A surface of a first region (17) of the material (1) is arranged to decrease the bandgap of the material such that the first region is conducting. A surface of a second region (19) of the material (1) is arranged to preserve a bandgap such that the second region is semiconducting. The second region (19) is contiguous to the first region (17), such that a rectifying junction (15) is formed at a boundary (21) between the first region and the second region.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: January 12, 2021
    Assignee: University College Cork
    Inventors: Alfonso Sanchez Soares, James Greer
  • Patent number: 10886290
    Abstract: A method of etching a substrate includes providing an etching solution in a tank of an etch processing system, where the etch processing system is configured to control temperature of the etching solution, a concentration of the etching solution, and flow of the etching solution within the tank. The substrate contains micro-fabricated structures that have alternating layers of a first material and a second material, and the etching solution including an acid that etches the first material and results in an etch product to be moved from the substrate. The method further includes monitoring a concentration of the etch product within the etching solution, and maintaining the concentration of the etch product within the etching solution below a predetermined value to prevent deposition of the etch product on the second material in an amount that blocks etching of the first material by the etching solution.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: January 5, 2021
    Assignee: Tokyo Electron Limited
    Inventors: Derek Bassett, Antonio Rotondaro, Ihsan Simms, Trace Hurd
  • Patent number: 10886408
    Abstract: Techniques are disclosed for forming group III-V material transistors employing nitride-based dopant diffusion barrier layers. The techniques can include growing the dilute nitride-based barrier layer as a relatively thin layer of III-V material in the sub-channel (or sub-fin) region of a transistor, near the substrate/III-V material interface, for example. Such a nitride-based barrier layer can be used to trap atoms from the substrate at vacancy sites within the III-V material. Therefore, the barrier layer can arrest substrate atoms from diffusing in an undesired manner by protecting the sub-channel layer from being unintentionally doped due to subsequent processing in the transistor fabrication. In addition, by forming the barrier layer pseudomorphically, the lattice mismatch of the barrier layer with the sub-channel layer in the heterojunction stack becomes insignificant. In some embodiments, the group III-V alloyed with nitrogen (N) material may include an N concentration of less than 5, 2, or 1.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: January 5, 2021
    Assignee: INTEL CORPORATION
    Inventors: Chandra S. Mohapatra, Harold W. Kennel, Glenn A. Glass, Willy Rachmady, Anand S. Murthy, Gilbert Dewey, Jack T. Kavalieros, Tahir Ghani, Matthew V. Metz, Sean T. Ma
  • Patent number: 10886391
    Abstract: Transistors and methods of forming the same include forming a fin that has an active layer between two sacrificial layers. Material is etched away from the two sacrificial layers in a region of the fin. A gate stack is formed around the active layer in the region. The active layer is etched after forming the gate stack to form a quantum dot.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: January 5, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 10886381
    Abstract: The present invention provides an epitaxial structure of N-face group III nitride, its active device, and the method for fabricating the same. By using a fluorine-ion structure in device design, a 2DEG in the epitaxial structure of N-face group III nitride below the fluorine-ion structure will be depleted. Then the 2DEG is located at a junction between a i-GaN channel layer and a i-AlyGaN layer, and thus fabricating GaN enhancement-mode AlGaN/GaN high electron mobility transistors (HEMTs), hybrid Schottky barrier diodes (SBDs), or hybrid devices. After the fabrication step for polarity inversion, namely, generating stress in a passivation dielectric layer, the 2DEG will be raised from the junction between the i-GaN channel layer and the i-AlyGaN layer to the junction between the i-GaN channel layer and the i-AlxGaN layer.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: January 5, 2021
    Inventor: Chih-Shu Huang
  • Patent number: 10879376
    Abstract: To form p-type semiconductor regions in a gallium nitride (GaN)-based semiconductor by ion implantation. A method for manufacturing a semiconductor device comprises forming first grooves, depositing, and ion-implanting. At the step of forming the first grooves, the first grooves are formed in a stacked body including a gallium nitride (GaN)-based first semiconductor layer containing an n-type impurity and a gallium nitride (GaN)-based second semiconductor layer stacked on the first semiconductor layer and containing a p-type impurity. The first grooves each have a bottom portion located in the first semiconductor layer. At the depositing step, the p-type impurity is deposited on side portions and the bottom portions of the first grooves. At the ion-implanting step, the p-type impurity is ion-implanted into the first semiconductor layer through the first grooves.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: December 29, 2020
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Takaki Niwa, Takahiro Fujii, Masayoshi Kosaki
  • Patent number: 10879131
    Abstract: The present disclosure provides a method for method for forming a semiconductor structure, including providing a substrate with a first well region of a first conductivity type, forming a silicon layer over the first well region, forming a first silicon fin over the first well region, and applying a silicon-free gas source upon the first silicon fin.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tsungyu Hung, Pei-Wei Lee, Pang-Yen Tsai
  • Patent number: 10868194
    Abstract: A transistor comprises a pair of source/drain regions having a channel region there-between. A transistor gate construction is operatively proximate the channel region. The channel region comprises a direction of current flow there-through between the pair of source/drain regions. The channel region comprises at least one of GaP, GaN, and GaAs extending all along the current-flow direction. Each of the source/drain regions comprises at least one of GaP, GaN, and GaAs extending completely through the respective source/drain region orthogonal to the current-flow direction. The at least one of the GaP, the GaN, and the GaAs of the respective source/drain region is directly against the at least one of the GaP, the GaN, and the GaAs of the channel region. Each of the source/drain regions comprises at least one of elemental silicon and metal material extending completely through the respective source/drain region orthogonal to the current-flow direction. Other embodiments are disclosed.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: December 15, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Durai Vishak Nirmal Ramaswamy
  • Patent number: 10867792
    Abstract: A high electron mobility transistor (HEMT) includes a substrate, and a channel layer over the substrate, wherein and at least one of the channel layer or the active layer comprises indium. The HEMT further includes an active layer over the channel layer. The active layer has a band gap discontinuity with the channel layer.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Chun Liu, Chi-Ming Chen, Min-Chang Ching, Chen-Hao Chiang, Chung-Yi Yu, Chung-Chieh Hsu
  • Patent number: 10861939
    Abstract: Semiconductor devices, computing devices, and related methods are disclosed herein. A semiconductor device includes a seed material, an epitaxial material in contact with the seed material, and at least one quantum region including an elastic stiffness that is greater than an elastic stiffness of the epitaxial material. The epitaxial material has lattice parameters that are different from lattice parameters of the seed material by at least a threshold amount. Lattice parameters of the quantum region are within the threshold amount of the lattice parameters of the epitaxial material. A method includes disposing an epitaxial material on a seed material, disposing a quantum region on the epitaxial material, and disposing the epitaxial material on the quantum region.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: December 8, 2020
    Assignee: Intel Corporation
    Inventors: Matthew Metz, Gilbert Dewey, Harold W. Kennel, Cheng-Ying Huang, Sean T. Ma, Willy Rachmady
  • Patent number: 10861944
    Abstract: According to one embodiment, a semiconductor device includes a first layer, a first electrode, and a first nitride region. The first layer includes a first material and a first partial region. The first material includes at least one selected from the group consisting of silicon carbide, silicon, carbon, and germanium. The first partial region is of a first conductivity type. The first conductivity type is one of an n-type or a p-type. A direction from the first partial region toward the first electrode is aligned with a first direction. The first nitride region includes Alx1Ga1-x1N (0?x1<1), is provided between the first partial region and the first electrode, is of the first conductivity type, and includes a first protrusion protruding in the first direction.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: December 8, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeya Kimura, Hisashi Yoshida, Tatsuo Shimizu, Ryosuke Iijima
  • Patent number: 10854444
    Abstract: In some aspects, methods of forming a metal sulfide thin film are provided. According to some methods, a metal sulfide thin film is deposited on a substrate in a reaction space in a cyclical process where at least one cycle includes alternately and sequentially contacting the substrate with a first vapor-phase metal reactant and a second vapor-phase sulfur reactant. In some aspects, methods of forming a three-dimensional architecture on a substrate surface are provided. In some embodiments, the method includes forming a metal sulfide thin film on the substrate surface and forming a capping layer over the metal sulfide thin film. The substrate surface may comprise a high-mobility channel.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: December 1, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Suvi P. Haukka, Fu Tang, Michael E. Givens, Jan Willem Maes, Qi Xie