Field Effect Transistor Patents (Class 257/192)
  • Patent number: 11545586
    Abstract: A Group III-Nitride (III-N) device structure is provided which comprises: a heterostructure having three or more layers comprising III-N material, an anode within a recess that extends through two or more of the layers, wherein the anode is in electrical contact with the first layer, a cathode comprising donor dopants, wherein the cathode is on the first layer of the heterostructure; and a conducting region in the first layer in direct contact to the cathode and conductively connected to the anode. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: January 3, 2023
    Assignee: Intel Corporation
    Inventors: Harald Gossner, Peter Baumgartner, Uwe Hodel, Domagoj Siprak, Stephan Leuschner, Richard Geiger, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta
  • Patent number: 11538908
    Abstract: A semiconductor device (100, 100?, 100?) and a method for manufacturing a semiconductor device (100, 100?, 100?). The semiconductor device (100, 100?, 100?) includes a substrate (104, 106), a GaN layer (112), and an AlGaN layer (114). The GaN layer (112) is located between the substrate (104, 106) and the AlGaN layer (114). The device further includes at least one contact (130, 132, 134), comprising a central portion (150) and an edge portion (152), and a passivation layer (160) located at least between the edge portion (152) of the contact (130, 132, 134) and the AlGaN layer (114). The edge portion (152) is spaced apart from an upper surface of the passivation layer (160). The edge portion (152) may be spaced apart from the passivation layer (160) by a further layer (170) or by an air gap (172).
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: December 27, 2022
    Assignee: Nexperia B.V.
    Inventors: Johannes Josephus Theodorus Marinus Donkers, Hans Broekman
  • Patent number: 11532740
    Abstract: A semiconductor structure includes: a channel layer; an active layer over the channel layer, wherein the active layer is configured to form a two-dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer; a gate electrode over a top surface of the active layer; and a source/drain electrode over the top surface of the active layer; wherein the active layer includes a first layer and a second layer sequentially disposed therein from the top surface to a bottom surface of the active layer, and the first layer possesses a higher aluminum (Al) atom concentration compared to the second layer. An HEMT structure and an associated method are also disclosed.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yao-Chung Chang, Po-Chih Chen, Jiun-Lei Jerry Yu, Chun Lin Tsai
  • Patent number: 11527606
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate; a buffer layer on the substrate; a channel layer on the buffer layer; a barrier layer on the channel layer; a doped compound semiconductor layer on a portion of the barrier layer; an un-doped first capping layer on the doped compound semiconductor layer; a gate structure on the un-doped first capping layer; and source/drain structures on opposite sides of the gate structure. There is a channel region in the channel layer that is adjacent to the interface between the channel layer and the barrier layer.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: December 13, 2022
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Yu-Chieh Chou, Tsung-Hsiang Lin
  • Patent number: 11527532
    Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistor-based cascode arrangements that may simultaneously realize enhancement mode transistor operation and high voltage capability. In one aspect, an IC structure includes a source region, a drain region, an enhancement mode III-N transistor, and a depletion mode III-N transistor, where each of the transistors includes a first and a second source or drain (S/D) terminals. The transistors are arranged in a cascode arrangement in that the first S/D terminal of the enhancement mode III-N transistor is coupled to the source region, the second S/D terminal of the enhancement mode III-N transistor is coupled to the first S/D terminal of the depletion mode III-N transistor, and the second S/D terminal of the depletion mode III-N transistor is coupled to the drain region.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: December 13, 2022
    Assignee: Intel Corporation
    Inventors: Nidhi Nidhi, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta, Paul B. Fischer, Rahul Ramaswamy, Walid M. Hafez, Johann Christian Rode
  • Patent number: 11527535
    Abstract: An embodiment of the invention may include a forkFET semiconductor structure, and the method of forming said structure. The structure may include a first FET device and a second FET device separated by a vertical dielectric pillar. The first FET device may include a first plurality of horizontal sheet channels. The second FET device may include a second plurality of horizontal sheet channels. The first plurality of horizontal sheet channels contains more horizontal sheets than the second plurality of horizontal sheet channels. This may enable adjustment of Weff for different devices on different sides of the pillar or different thicknesses of dielectrics used for the device.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: December 13, 2022
    Assignee: International Business Machines Corporation
    Inventors: Julien Frougier, Ruilong Xie, Kangguo Cheng, Chanro Park
  • Patent number: 11515304
    Abstract: An integrated circuit device with a substrate and a plurality of fins is provided where fin width is less than 11 nanometers, fin height is greater than 155 nanometers and spacing between any two neighboring fins is less than 30 nanometers and each fin is in non-collapsed state. An integrated circuit device with a substrate and a plurality of fins is provided where fin width is less than 15 nanometers, fin height is greater than 190 nanometers and spacing between any two neighboring fins is less than 30 nanometers and each fin is in non-collapsed state. A method for forming a fin-based transistor structure is provided where a plurality of fins on a substrate are pre-treated with at least one of a self-assembled monolayer, a non-polar solvent, and a surfactant. One or more of these treatments is to reduce adhesion and/or cohesive forces to prevent occurrence of fin collapse.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: November 29, 2022
    Assignee: Tahoe Research, Ltd.
    Inventors: Nabil G. Mistkawi, Glenn A. Glass
  • Patent number: 11489068
    Abstract: An HEMT device, comprising: a semiconductor body including a heterojunction structure; a dielectric layer on the semiconductor body; a gate electrode; a drain electrode, facing a first side of the gate electrode; and a source electrode, facing a second side opposite to the first side of the gate electrode; an auxiliary channel layer, which extends over the heterojunction structure between the gate electrode and the drain electrode, in electrical contact with the drain electrode and at a distance from the gate electrode, and forming an additional conductive path for charge carriers that flow between the source electrode and the drain electrode.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: November 1, 2022
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Ferdinando Iucolano, Alessandro Chini
  • Patent number: 11489078
    Abstract: A semiconductor structure and a method of forming the same are provided. A semiconductor structure according to the present disclosure includes a first channel member and a second channel member disposed over the first channel member, a first channel extension feature coupled to the first channel member, a second channel extension feature coupled to the second channel member, and an inner spacer feature disposed between the first channel extension feature and the second channel extension feature.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: November 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Jen Lai, Wei-Yuan Lu, Chih-Hao Yu, Chia-Pin Lin
  • Patent number: 11489075
    Abstract: In a method of manufacturing a semiconductor device, first and second fin structures are formed over a substrate, an isolation insulating layer is formed over the substrate, a gate structure is formed over channel regions of the first and second fin structures, source/drain regions of the first and second fin structure are recessed, and an epitaxial source/drain structure is formed over the recessed first and second fin structures. The epitaxial source/drain structure is a merged structure having a merger point, and a height of a bottom of the merger point from an upper surface of the isolation insulating layer is 50% or more of a height of the channel regions of the first and second fin structures from the upper surface of the isolation insulating layer.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: November 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shahaji B. More, Chandrashekhar Prakash Savant
  • Patent number: 11476359
    Abstract: A device includes a substrate; a buffer layer on the substrate; a barrier layer on the buffer layer, a source electrically coupled to the barrier layer; a gate electrically coupled to the barrier layer; and a drain electrically coupled to the barrier layer. The device further includes an electron concentration reduction structure arranged with at least one of the following: in the barrier layer and on the barrier layer. The electron concentration reduction structure is configured to at least one of the following: reduce electron concentration around the gate, reduce electron concentration around an edge of the gate, reduce electron concentration, increase power gain, increase efficiency, decouple the gate from the drain, decouple the gate from the source, and reduce capacitance.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: October 18, 2022
    Assignee: WOLFSPEED, INC.
    Inventors: Jia Guo, Scott Sheppard, Saptharishi Sriram
  • Patent number: 11469332
    Abstract: A semiconductor device includes a substrate, a plurality of nanowires, a gate structure, a source/drain epitaxy structure, and a semiconductor layer. The substrate has a protrusion portion. The nanowires extend in a first direction above the protrusion portion of the substrate, the nanowires being arranged in a second direction substantially perpendicular to the first direction. The gate structure wraps around each of the nanowires. The source/drain epitaxy structure is in contact with an end surface of each of the nanowires, in which a bottom surface of the source/drain epitaxy structure is lower than a top surface of the protrusion portion of the substrate. The semiconductor layer is in contact with the bottom surface of the epitaxy structure, in which the semiconductor layer is spaced from the protrusion portion of the substrate.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: October 11, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Ju Lee, Chun-Fu Cheng, Chung-Wei Wu, Zhiqiang Wu
  • Patent number: 11469228
    Abstract: Disclosed is a semiconductor device comprising a substrate including PMOSFET and NMOSFET regions, first active fins at the PMOSFET region, second active fins at the NMOSFET region, a gate electrode extending in a first direction and running across the first and second active fins, a first source/drain pattern on the first active fins and connecting the first active fins to each other, a second source/drain pattern on the second active fins and connecting the second active fins to each other, a first active contact electrically connected to the first source/drain pattern, and a second active contact electrically connected to the second source/drain pattern. A maximum width of the first active contact in the first direction is less than a maximum width of the second active in the first direction.
    Type: Grant
    Filed: January 12, 2021
    Date of Patent: October 11, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chanwook Lee, Seungkwon Kim, Jaechul Kim, Younggun Ko, Yuri Masuoka
  • Patent number: 11456318
    Abstract: A nonvolatile memory device according to an embodiment includes a substrate having an upper surface, and a gate structure disposed over the substrate. The gate structure includes at least one gate electrode layer pattern and at least one gate insulation layer pattern, which are alternately stacked along a first direction perpendicular to the upper surface. The gate structure extends in a second direction perpendicular to the first direction. The nonvolatile memory device includes a ferroelectric layer disposed on at least a portion of one sidewall surface of the gate structure. The one sidewall surface of the gate structure forms a plane substantially parallel to the first and second directions. The nonvolatile memory device includes a channel layer disposed on the ferroelectric layer, and a source electrode structure and a drain electrode structure disposed to contact the channel layer and spaced apart from each other in the second direction.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: September 27, 2022
    Assignee: SK hynix Inc.
    Inventors: Jae Hyun Han, Jae Gil Lee, Hyangkeun Yoo, Se Ho Lee
  • Patent number: 11444159
    Abstract: An electronic device comprises a channel layer on a buffer layer on a substrate. The channel layer has a first portion and a second portion adjacent to the first portion. The first portion comprises a first semiconductor. The second portion comprises a second semiconductor that has a bandgap greater than a bandgap of the first semiconductor.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: September 13, 2022
    Assignee: Intel Corporation
    Inventors: Sean T. Ma, Gilbert Dewey, Willy Rachmady, Matthew V. Metz, Cheng-Ying Huang, Harold W. Kennel, Jack T. Kavalieros, Anand S. Murthy, Tahir Ghani
  • Patent number: 11437469
    Abstract: A semiconductor structure includes semiconductor layers disposed over a substrate and oriented lengthwise in a first direction, a metal gate stack disposed over the semiconductor layers and oriented lengthwise in a second direction perpendicular to the first direction, where the metal gate stack includes a top portion and a bottom portion that is interleaved with the semiconductor layers, source/drain features disposed in the semiconductor layers and adjacent to the metal gate stack, and an isolation structure protruding from the substrate, where the isolation structure is oriented lengthwise along the second direction and spaced from the metal gate stack along the first direction, and where the isolation structure includes a dielectric layer and an air gap.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: September 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chia-Ta Yu, Hsiao-Chiu Hsu, Feng-Cheng Yang
  • Patent number: 11437497
    Abstract: In an embodiment, a device includes: a substrate; a first semiconductor region extending from the substrate, the first semiconductor region including silicon; a second semiconductor region on the first semiconductor region, the second semiconductor region including silicon germanium, edge portions of the second semiconductor region having a first germanium concentration, a center portion of the second semiconductor region having a second germanium concentration less than the first germanium concentration; a gate stack on the second semiconductor region; and source and drain regions in the second semiconductor region, the source and drain regions being adjacent the gate stack.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: September 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ji-Yin Tsai, Jung-Jen Chen, Pei-Ren Jeng, Chii-Horng Li, Kei-Wei Chen, Yee-Chia Yeo
  • Patent number: 11430882
    Abstract: A high-electron mobility transistor includes a substrate layer, a first buffer layer provided on the substrate layer, a barrier layer provided on the first buffer layer, a source provided on the barrier layer, a drain provided on the barrier layer, and a gate provided on the barrier layer. The transistor further includes a p-type material layer having a length parallel to a surface of the substrate layer over which the first buffer layer is provided, the length of the p-type material layer being less than an entire length of the substrate layer. The p-type material layer is provided in one of the following: the substrate layer, or the first buffer layer. A process of making the high-electron mobility transistor is disclosed as well.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: August 30, 2022
    Assignee: WOLFSPEED, INC.
    Inventor: Saptharishi Sriram
  • Patent number: 11430868
    Abstract: Integrated circuit structures including a buried etch-stop layer to help control transistor source/drain depth are provided herein. The buried etch-stop layer addresses the issue of the source/drain etch (or epi-undercut (EUC) etch) going below the bottom of the active height of the channel region, as such an issue can result in un-controlled sub-fin leakage that causes power consumption degradation and other undesired performance issues. The buried etch-stop layer is formed below the channel material, such as in the epitaxial stack that includes the channel material, and acts to slow the removal of material after the channel material has been removed when etching to form the source/drain trenches. In other words, the buried etch-stop layer includes different material from the channel material that can be etched, for at least one given etchant, at a relatively slower rate than the channel material to help control the source/drain trench depth.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: August 30, 2022
    Assignee: Intel Corporation
    Inventors: Rishabh Mehandru, Biswajeet Guha, Anupama Bowonder, Anand S. Murthy, Tahir Ghani, Stephen M. Cea
  • Patent number: 11424330
    Abstract: A gate electrode (3), a source electrode (4), and a drain electrode (5) is provided on a surface of the semiconductor substrate (1,2). An insulating film (6) covers the surface of the semiconductor substrate (1,2) in a region between the gate electrode (3) and the drain electrode (5). A source field plate (7) is provided on the insulating film (6) and not connected with the drain electrode (5). A diode (8) has a cathode connected with the source field plate (7) and an anode having a constant potential.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: August 23, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventor: Shinsuke Watanabe
  • Patent number: 11417646
    Abstract: An integrated circuit formed on a silicon substrate includes an NMOS transistor with n-channel raised source and drain (NRSD) layers adjacent to a gate of the NMOS transistor, a PMOS transistor with SiGe stressors in the substrate adjacent to a gate of the PMOS transistor, and an NPN heterojunction bipolar transistor (NHBT) with a p-type SiGe base formed in the substrate and an n-type silicon emitter formed on the SiGe base. The SiGe stressors and the SiGe base are formed by silicon-germanium epitaxy. The NRSD layers and the silicon emitter are formed by silicon epitaxy.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: August 16, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Manoj Mehrotra, Terry J. Bordelon, Deborah J. Riley
  • Patent number: 11404274
    Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a fin structure over the substrate, a gate structure over a first portion of the fin structure, and an epitaxial region formed in a second portion of the fin structure. The epitaxial region can include a first semiconductor layer and an n-type second semiconductor layer formed over the first semiconductor layer. A lattice constant of the first semiconductor layer can be greater than that of the second semiconductor layer.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiao-Chun Chang, Guan-Jie Shen
  • Patent number: 11404558
    Abstract: A semiconductor device includes a first field effect transistor (FET) including a first gate dielectric layer and a first gate electrode. The first gate electrode includes a first lower metal layer and a first upper metal layer. The first lower metal layer includes a first underlying metal layer in contact with the first gate dielectric layer and a first bulk metal layer. A bottom of the first upper metal layer is in contact with an upper surface of the first underlying metal layer and an upper surface of the first bulk metal layer.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: August 2, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yao-De Chiou, Hui-Chi Chen, Jeng-Ya Yeh
  • Patent number: 11393980
    Abstract: A variable resistance memory device includes a first electrode on a substrate, a variable resistance pattern on the first electrode, a second electrode on the variable resistance pattern, a selection pattern structure on the second electrode, and a third electrode on the selection pattern structure. The selection pattern structure may include a first leakage current prevention pattern and a selection pattern sequentially stacked, and the first leakage current pattern may include a two-dimensional transition metal dichalcogenide (TMDC) material.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: July 19, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hideki Horii, Jungmoo Lee
  • Patent number: 11393923
    Abstract: A Drain Extended Tunnel FET (DeTFET) device is disclosed that outperforms state of art devices and can meet the requirements of High voltage/high power devices operating in the range of 5V-20V for System on Chip (SoC). The device comprises a P+ SiGe source with an N-type Si Epilayer sandwiched between SiGe source and the gate stack, which enables vertical tunneling of minority carriers from SiGe P+ source into N-Epi region under the influence of gate field. The area tunneling between SiGe source and Si Epi region breaks the barrier imposed by thermionic injection based carrier transport from source to channel, which exists in DeMOS devices known in the art. The disclosed device results in improved performance in respect of ON current, leakage, sub-threshold slope, breakdown voltage and RF characteristics making it attractive for SoC applications as compared to its state of the art counterparts.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: July 19, 2022
    Assignee: Indian Institute of Science
    Inventor: Mayank Shrivastava
  • Patent number: 11380786
    Abstract: An insulating structure of a high electron mobility transistor (HEMT) is provided, which comprises a gallium nitride layer, an aluminum gallium nitride layer disposed on the gallium nitride layer, a groove disposed in the gallium nitride layer and the aluminum gallium nitride layer, an insulating layer disposed in the groove, wherein a top surface of the insulating layer is aligned with a top surface of the aluminum gallium nitride layer, and a passivation layer, disposed on the aluminum gallium nitride layer and the insulating layer.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: July 5, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Ming Chang, Wen-Jung Liao
  • Patent number: 11374115
    Abstract: A method includes forming a first semiconductor layer over a substrate; forming a second semiconductor layer over the first semiconductor layer; forming a dummy gate structure over the second semiconductor layer; performing an etching process to form a recess in the first and second semiconductor layers; forming a epitaxy structure over in the recess, wherein the epitaxy structure is in contact with the first and second semiconductor layers; performing a solid phase diffusion process to form a doped region in the epitaxy structure, in which the doped region is in contact with the second semiconductor layer and is separated from the first semiconductor layer; and replacing the dummy gate structure with a metal gate structure.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: June 28, 2022
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chung-En Tsai, Fang-Liang Lu, Pin-Shiang Chen, Chee-Wee Liu
  • Patent number: 11373995
    Abstract: A Group III-Nitride (III-N) device structure is presented comprising: a heterostructure having three or more layers comprising III-N material, a cathode comprising donor dopants, wherein the cathode is on a first layer of the heterostructure, an anode within a recess that extends through two or more of the layers of the heterostructure, wherein the anode comprises a first region wherein the anode is separated from the heterostructure by a high k dielectric material, and a second region wherein the anode is in direct contact with the heterostructure, and a conducting region in the first layer in direct contact to the cathode and conductively connected to the anode. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: June 28, 2022
    Assignee: Intel Corporation
    Inventors: Harald Gossner, Peter Baumgartner, Uwe Hodel, Domagoj Siprak, Stephan Leuschner, Richard Geiger, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta
  • Patent number: 11374098
    Abstract: A semiconductor device and a process of forming the semiconductor device are disclosed. The semiconductor device type of a high electron mobility transistor (HEMT) has double SiN films on a semiconductor layer, where the first SiN film is formed by the lower pressure chemical vapor deposition (LPCVD) technique, while, the second SiN film is deposited by the plasma assisted CVD (p-CVD) technique. Moreover, the gate electrode has an arrangement of double metals, one of which contains nickel (Ni) as a Schottky metal, while the other is free from Ni and covers the former metal. A feature of the invention is that the first metal is in contact with the semiconductor layer but apart from the second SiN film.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: June 28, 2022
    Assignees: SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventors: Kenta Sugawara, Yukinori Nose
  • Patent number: 11367615
    Abstract: A method of fabricating transistors with short gate length by two-step photolithography is provided. This method utilizes the two-step photolithography by a stepper as well as controlling a first exposed position and a second exposed position to change the gate length.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: June 21, 2022
    Assignee: National Chiao Tung University
    Inventors: Yi Chang, Yueh-Chin Lin, Po-Sheng Chang
  • Patent number: 11355518
    Abstract: An integrated circuit includes a bias pad within a buried oxide layer. A layer of semiconductor material is over the buried oxide layer. The layer of semiconductor material includes a doped regions for a transistor. An inter layer dielectric (ILD) material covers the layer of semiconductor material and a gate electrode for the transistor. The integrated circuit includes one or more bias contacts extending through the ILD material within an isolation region in the layer of semiconductor material. Bias contacts electrically connect to the first bias pad. The isolation structure insulates the one or more bias contacts from the doped regions of the transistor within the layer of semiconductor material. The one or more bias contacts are electrically connected to an interconnection structure of the integrated circuit which is configured to connect a voltage source to the bias pad.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: June 7, 2022
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY, LIMIIED
    Inventors: Jian Wu, Feng Han, Shuai Zhang
  • Patent number: 11355493
    Abstract: Various embodiments of the present disclosure are directed towards a method to embed planar field-effect transistor (FETs) with fin field-effect transistors (finFETs). A semiconductor substrate is patterned to define a mesa and a fin. A trench isolation structure is formed overlying the semiconductor substrate and surrounding the mesa and the fin. A first gate dielectric layer is formed on the mesa, but not the fin. The trench isolation structure recessed around the fin, but not the mesa, after the forming the first gate dielectric layer. A second gate dielectric layer is deposited overlying the first gate dielectric layer at the mesa and further overlying the fin. A first gate electrode is formed overlying the first and second gate dielectric layers at the mesa and partially defining a planar FET. A second gate electrode is formed overlying the second gate dielectric layer at the fin and partially defining a finFET.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: June 7, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Li-Feng Teng, Li-Jung Liu
  • Patent number: 11349023
    Abstract: In some embodiments, the present disclosure relates to an integrated transistor device, including a first barrier layer arranged over a substrate. Further, an undoped layer may be arranged over the first barrier layer and have a n-channel device region laterally next to a p-channel device region. The n-channel device region of the undoped layer has a topmost surface that is above a topmost surface of the p-channel device region of the undoped layer. The integrated transistor device may further comprise a second barrier layer over the n-channel device region of the undoped layer. A first gate electrode is arranged over the second barrier layer, and a second gate electrode is arranged over the p-channel device region of the undoped layer.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: May 31, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Man-Ho Kwan, Fu-Wei Yao, Chun Lin Tsai, Jiun-Lei Jerry Yu, Ting-Fu Chang
  • Patent number: 11348921
    Abstract: A semiconductor structure comprises a substrate and a fin extruding from the substrate along a first direction, wherein the fin comprises a first conductive type semiconductive layer over the substrate, a second conductive type semiconductive layer stacking over the first conductive type semiconductive layer along the first direction, and a dielectric layer sandwiched by the first conductive type semiconductive layer and the second conductive type semiconductive layer providing electrical isolation along the first direction between the first conductive type semiconductive layer and the second conductive type semiconductive layer.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: May 31, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Wei-Lun Chen
  • Patent number: 11349003
    Abstract: A new transistor structure is disclosed. This new structure has a dielectric stress layer in a three-dimensional structure outside of the gate region for modulation or the characteristics of the transistor. Additionally, trenches are created in the region between the source electrode and the drain electrode in such a manner so as to create ridges that traverse the gate region.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: May 31, 2022
    Assignee: Cambridge Electronics, Inc.
    Inventor: Bin Lu
  • Patent number: 11342440
    Abstract: A transistor is provided that comprises a source region overlying a base structure, a drain region overlying the base structure, and a block of semiconducting material overlying the base structure and being disposed between the source region and the drain region. The block of semiconducting material comprises a gate controlled region adjacent the source region, and a drain access region disposed between the gate controlled region and the drain region. The drain access region is formed of a plurality of semiconducting material ridges spaced apart from one another by non-channel trench openings, wherein at least a portion of the non-channel trench openings being filled with a doped material to provide a depletion region to improve breakdown voltage of the transistor.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: May 24, 2022
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Ishan Wathuthanthri, Ken Alfred Nagamatsu, William J. Sweet, James T. Kelliher, John S. Mason, Jr., Jonah Paul Sengupta
  • Patent number: 11322589
    Abstract: Provided is a semiconductor device comprising an active region on a substrate and including first and second sidewalls extending in a first direction and an epitaxial pattern on the active region, wherein the epitaxial pattern includes first and second epitaxial sidewalls extending from the first and second sidewalls, respectively, the first epitaxial sidewall includes a first epitaxial lower sidewall, a first epitaxial upper sidewall, and a first epitaxial connecting sidewall connecting the first epitaxial lower sidewall and the first epitaxial upper sidewall, the second epitaxial sidewall includes a second epitaxial lower sidewall, a second epitaxial upper sidewall, and a second epitaxial connecting sidewall connecting the second epitaxial lower sidewall and the second epitaxial upper sidewall, a distance between the first and second epitaxial upper sidewalls decreases away from the active region, and the first and second epitaxial lower sidewalls extend in parallel to a top surface of the substrate.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: May 3, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung Gil Yang, Seung Min Song, Soo Jin Jeong, Dong Il Bae, Bong Seok Suh
  • Patent number: 11322615
    Abstract: A semiconductor structure includes a layer arrangement consisting of, in sequence, a semiconductor-on-insulator layer (SOI) over a buried oxide (BOX) layer over a buried stressor (BS) layer with a silicon bonding layer (BL) intervening between the BOX and the BS layers. The semiconductor structure may be created by forming the BS layer on a substrate of a first wafer; growing the BL layer at the surface of the BS layer; wafer bonding the first wafer to a second wafer having a silicon oxide layer formed on a silicon substrate such that the silicon oxide layer of the second wafer is bonded to the BL layer of the first wafer, and thereafter removing a portion of the silicon substrate of the second wafer.
    Type: Grant
    Filed: November 4, 2020
    Date of Patent: May 3, 2022
    Assignee: Acorn Semi, LLC
    Inventors: Paul A. Clifton, Andreas Goebel
  • Patent number: 11316009
    Abstract: An integrated electronic device includes a first terminal and a second terminal, a Schottky diode having a first threshold voltage and coupled between the first terminal and the second terminal, a derivation component having a second threshold voltage greater than the first threshold voltage and coupled between the first terminal and the second terminal. The derivation component comprises a super-junction.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: April 26, 2022
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Julien Buckley, Jérôme Biscarrat
  • Patent number: 11316040
    Abstract: A high electron mobility transistor includes a channel layer, a barrier layer, a first compound semiconductor layer, and a second compound semiconductor layer. The channel layer is disposed on the substrate, and the barrier layer is disposed on the channel layer. The first compound semiconductor layer is disposed on the barrier layer. The second compound semiconductor layer is disposed between the barrier layer and the first compound semiconductor layer, where the first compound semiconductor layer and the second compound semiconductor layer include a concentration distribution of metal dopant, and the concentration distribution of metal dopant includes a first peak in the first compound semiconductor layer and a second peak in the second compound semiconductor layer.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: April 26, 2022
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Franky Juanda Lumbantoruan, Chia-Ching Huang, Chih-Yen Chen
  • Patent number: 11316038
    Abstract: An HEMT includes: a heterostructure; a dielectric layer on the heterostructure; a gate electrode, which extends throughout the thickness of the dielectric layer; a source electrode; and a drain electrode. The dielectric layer extends between the gate electrode and the drain electrode and is absent between the gate electrode and the source electrode. In this way, the distance between the gate electrode and the source electrode can be designed in the absence of constraints due to a field plate that extends towards the source electrode.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: April 26, 2022
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Ferdinando Iucolano
  • Patent number: 11302778
    Abstract: The present disclosure provides a high electron mobility transistor (HEMT). The HEMT includes a substrate, a buffer layer, a channel layer, a barrier layer, a source, a drain, and a gate. The substrate, the buffer layer, the channel layer, the barrier layer, the source, the drain, and the gate are stacked in sequence in a thickness direction of the HEMT. The channel layer includes a doped semiconductor structure. The present disclosure further provides a method for manufacturing an HEMT. The HEMT has good performance and has features such as low drain electric field intensity, a high breakdown voltage, high stability, and low costs.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: April 12, 2022
    Assignee: Innoscience (Zhuhai) Technology Co., Ltd.
    Inventors: King Yuen Wong, Ronghui Hao, Jinhan Zhang
  • Patent number: 11283021
    Abstract: A semiconductor layer (2,3) is provided on a substrate (1). A gate electrode (4), a source electrode (5) and a drain electrode (6) are provided on the semiconductor layer (3). A strongly correlated electron system material (12) is connected between the gate electrode (4) and the source electrode (5).
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: March 22, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventor: Hajime Sasaki
  • Patent number: 11276653
    Abstract: An electronic device includes a substrate, a transistor, and a ring resonator. The transistor is over the substrate. The transistor is configured to generate a quantum dot. The ring resonator is over the substrate and includes a conductive loop and an impedance matching element. The conductive loop overlaps with the transistor. The impedance matching element is on the conductive loop and is configured to determine a resonance frequency of the ring resonator.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: March 15, 2022
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Shih-Yuan Chen, Jiun-Yun Li, Rui-Fu Xu, Chiung-Yu Chen, Ting-I Yeh, Yu-Jui Wu, Yao-Chun Chang
  • Patent number: 11264379
    Abstract: A monolithic integration of enhancement mode (E-mode) and depletion mode (D-mode) field effect transistors (FETs) comprises a compound semiconductor substrate overlaid by an epitaxial structure overlaid by source and drain electrodes. The epitaxial structure includes from bottom to top sequentially a buffer layer, a channel layer, a Schottky barrier layer, a first etch stop layer, and a first cap layer. The respective first gate metal layers of the D-mode and E-mode FET are in contact with the first etch stop layer. The D-mode and E-mode gate-sinking regions are beneath the respective first gate metal layers of the D-mode and E-mode gate electrode at least within the first etch stop layer. The first gate metal layer material of the D-mode is the same as that of the E-mode, where the first gate metal layer thickness of the E-mode is greater than that of the D-mode.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: March 1, 2022
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Chia-Ming Chang, Jung-Tao Chung, Yan-Cheng Lin, Lung-Yi Tseng
  • Patent number: 11264418
    Abstract: A device for sensing light includes a first semiconductor region doped with a dopant of a first type and a second semiconductor region doped with a dopant of a second type. The second semiconductor region is positioned above the first semiconductor region. The device includes a gate insulation layer; a gate, a source, and a drain. The second semiconductor region has a top surface that is positioned toward the gate insulation layer and a bottom surface that is positioned opposite to the top surface of the second semiconductor region. The second semiconductor region has an upper portion that includes the top surface of the second semiconductor region and a lower portion that includes the bottom surface of the second semiconductor region and is mutually exclusive with the upper portion. The first semiconductor region is in contact with both the upper portion and the lower portion of the second semiconductor region.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: March 1, 2022
    Assignee: Stratio Inc.
    Inventors: Jae Hyung Lee, Yeul Na, Youngsik Kim, Woo-Shik Jung
  • Patent number: 11257938
    Abstract: A semiconductor device is provided with, a group-III nitride semiconductor layered structure that includes a heterojunction, an insulating layer which has a gate opening that reaches the group-III nitride semiconductor layered structure and which is disposed on the group-III nitride semiconductor layered structure, a gate insulating film that covers the bottom and the side of the gate opening, a gate electrode defined on the gate insulating film inside the gate opening, a source electrode and a drain electrode which are disposed to be spaced apart from the gate electrode so as to sandwich the gate electrode, a first conductive layer embedded in the insulating layer between the gate electrode and the drain electrode, and a second conductive layer that is embedded in the insulating layer above the first conductive layer in a region closer to the drain electrode side than the first conductive layer.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: February 22, 2022
    Assignee: ROHM CO., LTD.
    Inventor: Kentaro Chikamatsu
  • Patent number: 11257942
    Abstract: A resistive element that includes: a substrate; a first nitride semiconductor layer; a second nitride semiconductor layer; a two-dimensional electron gas layer on the first nitride semiconductor layer side at an interface between the first nitride semiconductor layer and the second nitride semiconductor layer; a first electrode ohmically connected to the two-dimensional electron gas layer; a second electrode ohmically connected to the two-dimensional electron gas layer; and an insulating layer between the first electrode and the second electrode in plan view. The two-dimensional electron gas layer functions as an electric resistance element. A conductive layer is not provided above the insulating layer between the first electrode and the second electrode in the plan view. The resistive element has a resistance-value stabilization structure that functions to keep a resistance value of the electric resistance element constant.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: February 22, 2022
    Assignee: NUVOTON TECHNOLOGY CORPORATION JAPAN
    Inventors: Kenichi Miyajima, Yoshiaki Katou, Akihiko Nishio, Kaname Motoyoshi
  • Patent number: 11251183
    Abstract: A semiconductor arrangement includes: a substrate; fins formed on the substrate and extending in a first direction; gate stacks formed on the substrate and each extending in a second direction crossing the first direction to intersect at least one of the fins, and dummy gates composed of a dielectric and extending in the second direction; spacers formed on sidewalls of the gate stacks and the dummy gates; and dielectric disposed between first and second ones of the gate stacks in the second direction to electrically isolate the first and second gate stacks. The dielectric is disposed in a space surrounded by respective spacers of the first and second gate stacks which extend integrally. At least a portion of an interval between the first and second gate stacks in the second direction is less than a line interval achievable by lithography in a process of manufacturing the semiconductor arrangement.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: February 15, 2022
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Huilong Zhu, Yanbo Zhang, Huicai Zhong
  • Patent number: 11251274
    Abstract: A semiconductor device includes a substrate; a semiconductor structure arranged on the substrate, the semiconductor structure including at least one first semiconductor layer; an insulator layer arranged on the semiconductor structure; a field plate covering a part of the insulator layer, wherein the insulator layer includes a non-linear dielectric material having a permittivity that decreases as an electric field traversing the dielectric material increases.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: February 15, 2022
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Romain Gwoziecki, Gwenaël Le Rhun