Vertical Channel Patents (Class 438/156)
  • Patent number: 10490654
    Abstract: Tunneling field-effect transistors (TFETs) and associated methods of fabrication are disclosed herein. An exemplary TFET includes a protrusion that extends vertically from a substrate. A drain region is in a bottommost portion of the protrusion. A source region is in a topmost portion of the protrusion. A gate stack that wraps a middle portion of the protrusion. The gate stack further wraps around a portion of the source region and a portion of the drain region. Spacers are along a portion of the topmost portion of the protrusion. The TFET further includes a drain contact coupled to the drain region, a gate contact coupled to the gate stack, and a source contact coupled to the source region. The source contact has a width that is greater than a width of the source region. The source contact is disposed on the source region and a portion of the spacers.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: November 26, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Harry-Hak-Lay Chuang, Cheng-Cheng Kuo, Chi-Wen Liu, Ming Zhu
  • Patent number: 10297692
    Abstract: The invention provides a manufacturing method of TFT substrate and a TFT substrate. The method provides a dual-gate structure symmetrically disposed on both sides of active layer, which prevents TFT threshold voltage from changing and improve TFT conduction state switching; by first manufacturing the active layer before the gate insulating layer to make the insulating layer directly grow on active layer, the contact interface between the gate insulating layer and active layer is improved, leading to further improving TFT conduction state switching. The TFT substrate makes the gate located between the source and the pixel electrode in vertical direction, and the dual-gate is symmetrically disposed on both sides of active layer to prevent TFT threshold voltage from changing and improve TFT conduction state switching, as well as improve the contact interface between the gate insulating layer and active layer, leading to further improving TFT conduction state switching.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: May 21, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Zhichao Zhou, Hui Xia
  • Patent number: 10269825
    Abstract: According to one embodiment, a stacked body includes a plurality of metal layers stacked with an insulator interposed. A semiconductor body extends in a stacking direction through the stacked body. A charge storage portion is provided between the semiconductor body and one of the metal layers. A metal nitride film has a first portion and a second portion. The first portion is provided between the charge storage portion and one of the metal layers. The second portion is thicker than the first portion and is provided between one of the metal layers and the insulator.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: April 23, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Satoshi Wakatsuki, Atsuko Sakata, Daisuke Ikeno
  • Patent number: 10269908
    Abstract: A FinFET device and a method of forming the same are provided. A method includes forming a patterned mask stack over a substrate, features of the patterned mask stack protecting the substrate having a uniform width. Unprotected portions of the substrate exposed by the patterned mask stack are removed to form a plurality of recesses in the substrate, unremoved portions of the substrate interposed between adjacent recesses forming a plurality of fins. Portions of the plurality of fins are removed, a width of a first fin of the plurality of fins being less than a width of a second fin of the plurality of fins.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 10199498
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a pillar structure, at least one charge storage film, and a first electrode. The stacked body includes electrode films stacked separately from each other. The pillar structure is provided in the stacked body and includes a semiconductor layer extending in stacking direction of the stacked body. The charge storage film is provided between the semiconductor layer and the electrode films. The first electrode is provided in the stacked body, spreads in the stacking direction and a first direction along a surface of the substrate, and contacting the substrate. The first electrode includes a first portion containing a material having conductivity and a second portion containing a material that a linear expansion coefficient is lower than a linear expansion coefficient of silicon, and positioned at a substrate side than the first portion in the stacking direction.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: February 5, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Osamu Matsuura, Hideki Inokuma, Masanari Fujita
  • Patent number: 10164076
    Abstract: A method for forming a tunneling field-effect transistor (TFET) is disclosed. The method includes etching a semiconductor substrate to form a semiconductor protrusion that protrudes out from a top surface of the semiconductor substrate, forming a drain region in lower portion of the semiconductor protrusion, and patterning a gate stack layer to form a gate stack. The gate stack has a gating surface that directly contacts and wraps around a middle portion of the semiconductor protrusion. The method further includes forming a source region in an upper portion of the semiconductor protrusion and forming a source contact over the source region, the source contact have a first width that is larger than a width of the source region.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Harry-Hak-Lay Chuang, Cheng-Cheng Kuo, Chi-Wen Liu, Ming Zhu
  • Patent number: 10157845
    Abstract: A semiconductor device includes a first transistor having a first gate, a first source and a first drain, a second transistor having a second gate, a second source and a second drain, an isolation region separating the first transistor from the second transistor, and a local interconnect connecting at least one of the first source and the first drain to at least the second source and the second drain. The local interconnect is in contact with a surface of the at least one of the first source and the first drain, a surface of the at least the second source and the second drain and a surface of a part of the isolation region.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jui-Yao Lai, Sai-Hooi Yeong, Ying-Yan Chen
  • Patent number: 10109720
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a patterned conductive layer and an epitaxial layer. The substrate includes a first fin structure and a second fin structure respectively protruding from a top surface of the substrate, and the second fin structure has a recess. The patterned conductive layer is disposed on the substrate and covers a first end of the first fin structure. The epitaxial layer is disposed in the recess. The first end of the first fin structure and a second end of the epitaxial layer face a first direction.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: October 23, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tan-Ya Yin, Chia-Wei Huang
  • Patent number: 10083980
    Abstract: The semiconductor memory device includes a stacked structure including conductive patterns and interlayer insulating patterns which are alternately stacked, a through-hole configured to pass through the stacked structure; a channel pattern formed inside the through-hole, a first capping conductive pattern formed on the channel pattern, a second capping conductive pattern formed on a sidewall of the first capping conductive pattern and surrounding the first capping conductive pattern, and a contact plug formed on the first capping conductive pattern and the second capping conductive pattern.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: September 25, 2018
    Assignee: SK hynix Inc.
    Inventor: Hyun Ho Lee
  • Patent number: 10032877
    Abstract: A FinFET device and a method of forming the same are provided. A method includes forming a patterned mask stack over a substrate, features of the patterned mask stack protecting the substrate having a uniform width. Unprotected portions of the substrate exposed by the patterned mask stack are removed to form a plurality of recesses in the substrate, unremoved portions of the substrate interposed between adjacent recesses forming a plurality of fins. Portions of the plurality of fins are removed, a width of a first fin of the plurality of fins being less than a width of a second fin of the plurality of fins.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: July 24, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 10026737
    Abstract: In a method of manufacturing a semiconductor device, a separation wall made of a dielectric material is formed between two fin structures. A dummy gate structure is formed over the separation wall and the two fin structures. An interlayer dielectric (ILD) layer is formed over the dummy gate structure. An upper portion of the ILD layer is removed, thereby exposing the dummy gate structure. The dummy gate structure is replaced with a metal gate structure. A planarization operation is performed to expose the separation wall, thereby dividing the metal gate structure into a first gate structure and a second gate structure. The first gate structure and the second gate structure are separated by the separation wall.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: July 17, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Chih-Liang Chen, Shi Ning Ju
  • Patent number: 9997597
    Abstract: A method for forming a vertical single electron transistor includes forming a heterostructured nanowire having a SiGe region centrally disposed between an upper portion and a lower portion in the nanowire. An oxide is deposited to cover the SiGe region, and a condensation process is performed to convert the SiGe to oxide and condense Ge to form an island between the upper portion and the lower portion of the nanowire. A bottom contact is formed about the lower portion, a first dielectric layer is formed on the bottom contact and a gate structure is formed about the island on the first dielectric layer. A second dielectric layer is formed on the gate structure, and a top contact is formed on the second dielectric layer.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: June 12, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 9997407
    Abstract: Voidless contact metal structures are provided. In one embodiment, a voidless contact metal structure is provided by first providing a first contact metal that contains a void within a contact opening. The void is then opened to provide a divot in the first contact metal. After forming a dielectric spacer atop a portion of first contact metal, a second contact metal is then formed that lacks any void. The second contact metal fills the entirety of the divot within the first contact metal. In another embodiment, two diffusion barrier structures are provided within a contact opening, followed by the formation of a contact metal structure that lacks any void.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: June 12, 2018
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Nicolas L. Breil, Oleg Gluschenkov, Shogo Mochizuki, Alexander Reznicek
  • Patent number: 9905700
    Abstract: A highly integrated semiconductor device that holds data and includes a first semiconductor layer, a first gate insulating film over the first semiconductor layer, a first gate electrode over the first gate insulating film, a second semiconductor layer over the first gate electrode, a conductive layer over the second semiconductor layer, a second gate insulating film covering the second semiconductor layer and the conductive layer, and a second gate electrode covering at least part of a side surface of the second semiconductor layer with the second gate insulating film interposed therebetween. An end portion of the second semiconductor layer is substantially aligned with an end portion of the conductive layer.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: February 27, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshinobu Asami
  • Patent number: 9899400
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device may be provided. The semiconductor device may include first channel layers arranged in a first direction. The semiconductor device may include second channel layers adjacent to the first channel layers in a second direction crossing the first direction and arranged in the first direction. The semiconductor device may include insulating layers stacked while surrounding side walls of the first and second channel layers. The semiconductor device may include conductive layers interposed between the insulating layers, and including first metal patterns extended in the first direction and second metal patterns extended in the first direction while surrounding the side walls of the first channel layers.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: February 20, 2018
    Assignee: SK hynix Inc.
    Inventor: Do Youn Kim
  • Patent number: 9859440
    Abstract: A thin film transistor can include a substrate, a gate electrode on the substrate, a first electrode located on the substrate and surrounded by the gate electrode, a second electrode located on the first electrode and surrounded by the gate electrode, and a channel layer located between the first electrode and the second electrode. The gate electrode can include a first margin metal layer on the substrate and a second metal layer located on the first margin metal layer. A method for manufacturing the thin film transistor is also provided.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: January 2, 2018
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Hsin-Hua Lin, Yi-Chun Kao, Chih-Lung Lee, Po-Li Shih, Kuo-Lung Fang
  • Patent number: 9716136
    Abstract: A method of forming an embedded polysilicon resistor body contact. According to the method, a transistor is formed in and above a crystalline active region that is positioned in a semiconductor layer of a multilayer semiconductor device. A resistor region is defined in single crystal semiconductor material of the semiconductor layer formed on a buried insulating layer. The resistor region is adjacent the transistor. An amorphized semiconductor material is formed in the resistor region. A barrier is formed in the amorphized semiconductor material. The barrier is between the transistor and an electrical body contact for the transistor. The amorphized semiconductor material is annealed, forming a polysilicon semiconductor. The barrier prevents the amorphized region from recrystallizing back to single crystal silicon.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: July 25, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Michel J. Abou-Khalil, Steven M. Shank, Anthony K. Stamper
  • Patent number: 9711531
    Abstract: A method of fabricating a semiconductor device can include forming a channel hole in a vertical stack of alternating insulating and sacrificial layers to form a recess in a substrate. A selectively epitaxial growth can be performed to provide a lower semiconductor pattern in the recess using material of the substrate as a seed and a recess can be formed to penetrate an upper surface of the lower semiconductor pattern via the channel hole.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: July 18, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woong-Seop Lee, Jongyoon Choi, Jinhyun Shin, Dong-Sik Lee
  • Patent number: 9660089
    Abstract: A thin film transistor substrate includes a substrate, a data line disposed on the substrate and which extends substantially in a predetermined direction, a light blocking layer disposed on the substrate and including a metal oxide including zinc manganese oxide, zinc cadmium oxide, zinc phosphorus oxide or zinc tin oxide, a gate electrode disposed on the light blocking layer, a signal electrode including a source electrode and a drain electrode spaced apart from the source electrode, where the source electrode is connected to the data line, and a semiconductor pattern disposed between the source electrode and the drain electrode.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: May 23, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD
    Inventors: Byung-Du Ahn, Ji-Hun Lim, Jin-Hyun Park, Hyun-Jae Kim
  • Patent number: 9640390
    Abstract: Doped semiconductor ink formulations, methods of making doped semiconductor ink formulations, methods of coating or printing thin films, methods of forming electronic devices and/or structures from the thin films, and methods for modifying and controlling the threshold voltage of a thin film transistor using the films are disclosed. A desired dopant may be added to an ink formulation comprising a Group IVA compound and a solvent, and then the ink may be printed on a substrate to form thin films and conductive structures/devices, such as thin film transistors. By adding a customized amount of the dopant to the ink prior to printing, the threshold voltage of a thin film transistor made from the doped semiconductor ink may be independently controlled upon activation of the dopant.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: May 2, 2017
    Assignee: Thin Film Electronics ASA
    Inventors: Wenzhuo Guo, Fabio Zurcher, Arvind Kamath, Joerg Rockenberger
  • Patent number: 9583439
    Abstract: A memory device and a method for fabricating the same are provided. The memory device includes a substrate, a ground layer disposed on the substrate, a stacking structure having a plurality of conductive layers and a plurality of insulating layers alternatively stacked on the ground layer and a plurality of memory strings penetrating through the stacking structure. The ground layer includes a metal layer. The memory strings electrically contact with the metal layer.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: February 28, 2017
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Shih-Hung Chen
  • Patent number: 9406786
    Abstract: In a transistor including an oxide semiconductor film, a metal oxide film for preventing electrification which is in contact with the oxide semiconductor film and covers a source electrode and a drain electrode is formed. Then, oxygen is introduced (added) to the oxide semiconductor film through the metal oxide film and heat treatment is performed. Through these steps of oxygen introduction and heat treatment, impurities such as hydrogen, moisture, a hydroxyl group, or hydride are intentionally removed from the oxide semiconductor film, so that the oxide semiconductor film is highly purified. Further, by providing the metal oxide film, generation of a parasitic channel on a back channel side of the oxide semiconductor film can be prevented in the transistor.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: August 2, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9391168
    Abstract: A manufacturing method of an electronic device simplifies the process by performing a patterning process by using an imprinting technology. An electronic device manufactured by the manufacturing method is also disclosed. In one embodiment, the electronic device includes a substrate provided to have a dented portion and a non-dented portion, a gate electrode located at and in direct contact with the dented portion of the substrate, a source electrode and a drain electrode located at the non-dented portion of the substrate, and a semiconductor layer located on the gate electrode and in contact with the source electrode and the drain electrode. The gate electrode, the source electrode, and the drain electrode are formed of at least one of molybdenum, tungsten, copper, aluminum, titanium, an alloy thereof, nanowire, graphene, carbon nanotube, indium tin oxide, indium zinc oxide and combinations thereof.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: July 12, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventor: Jung-Hun Lee
  • Patent number: 9368626
    Abstract: A semiconductor device and method of fabricating thereof is described that includes a substrate including at least one fin, at least one gate stack formed on a top surface of the at least one fin, a first inter-layer dielectric (ILD) layer formed on the top surface of the at least one fin, and a strained layer formed at least on a top surface of the at least one gate stack, wherein the strained layer is configured to provide a strain force to the at least one gate stack.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: June 14, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lun-Wei Chang, Yun-Ju Sun, Tomonari Yamamoto
  • Patent number: 9368646
    Abstract: A vertical memory device includes a channel array, a charge storage layer structure, multiple gate electrodes and a dummy pattern array. The channel array includes multiple channels, each of which is formed on a first region of a substrate and is formed to extend in a first direction substantially perpendicular to a top surface of the substrate. The charge storage layer structure includes a tunnel insulation layer pattern, a charge storage layer pattern and a blocking layer pattern, which are sequentially formed on a sidewall of each channel in the second direction substantially parallel to the top surface of the substrate. The gate electrodes arranged on a sidewall of the charge storage layer structure and spaced apart from each other in the first direction. The dummy pattern array includes multiple dummy patterns, each of which is formed on a second region adjacent the first region of the substrate and is formed to extend in the first direction.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: June 14, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Gyun Kim, Jae-Young Ahn, Ki-Hyun Hwang
  • Patent number: 9355844
    Abstract: Electrical characteristics of transistors using an oxide semiconductor are greatly varied in a substrate, between substrates, and between lots, and the electrical characteristics are changed due to heat, bias, light, or the like in some cases. In view of the above, a semiconductor device using an oxide semiconductor with high reliability and small variation in electrical characteristics is manufactured. In a method for manufacturing a semiconductor device, hydrogen in a film and at an interface between films is removed in a transistor using an oxide semiconductor. In order to remove hydrogen at the interface between the films, the substrate is transferred under a vacuum between film formations. Further, as for a substrate having a surface exposed to the air, hydrogen on the surface of the substrate may be removed by heat treatment or plasma treatment.
    Type: Grant
    Filed: May 6, 2014
    Date of Patent: May 31, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9147616
    Abstract: One illustrative method disclosed herein includes, among other things, oxidizing a lower portion of an initial fin structure to thereby define an isolation region that vertically separates an upper portion of the initial fin structure from a semiconducting substrate, performing a recess etching process to remove a portion of the upper portion of the initial fin structure so as to define a recessed fin portion, forming a replacement fin on the recessed fin portion so as to define a final fin structure comprised of the replacement fin and the recessed fin portion, and forming a gate structure around at least a portion of the replacement fin.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: September 29, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ajey Poovannummoottil Jacob, Murat Kerem Akarvardar
  • Patent number: 9142405
    Abstract: A thin film transistor including a first polycrystalline semiconductor layer disposed on a substrate, a second polycrystalline semiconductor layer disposed on the first polycrystalline semiconductor layer, and metal catalysts configured to adjoin the first polycrystalline semiconductor layer and spaced apart from one another at specific intervals.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: September 22, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yong-Duck Son, Ki-Yong Lee, Jin-Wook Seo, Min-Jae Jeong, Byung-Soo So, Seung-Kyu Park, Kil-Won Lee, Yun-Mo Chung, Byoung-Keon Park, Dong-Hyun Lee, Jong-Ryuk Park, Tak-Young Lee, Jae-Wan Jung
  • Patent number: 9093402
    Abstract: A manufacturing method of an active matrix light emitting device in which the active matrix light emitting device can be manufactured in a shorter time with high yield at low cost compared with conventional ones will be provided. It is a feature of the present invention that a layered structure is employed for a metal electrode which is formed in contact with or is electrically connected to a semiconductor layer of each TFT arranged in a pixel area of an active matrix light emitting device. Further, the metal electrode is partially etched and used as a first electrode of a light emitting element. A buffer layer, a layer containing an organic compound, and a second electrode layer are stacked over the first electrode.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: July 28, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masayuki Sakakura, Takeshi Noda, Hideaki Kuwabara, Shunpei Yamazaki
  • Patent number: 9059309
    Abstract: The object to provide a semiconductor device comprising a highly-integrated SGT-based CMOS inverter circuit is achieved by forming an inverter which comprises: a first transistor including; an first island-shaped semiconductor layer; a first gate insulating film; a gate electrode; a first first-conductive-type high-concentration semiconductor layer arranged above the first island-shaped semiconductor layer; and a second first-conductive-type high-concentration semiconductor layer arranged below the first island-shaped semiconductor layer, and a second transistor including; a second gate insulating film surrounding a part of the periphery of the gate electrode; a second semiconductor layer in contact with a part of the periphery of the second gate insulating film; a first second-conductive-type high-concentration semiconductor layer arranged above the second semiconductor layer; and a second second-conductive-type high-concentration semiconductor layer arranged below the second semiconductor layer.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: June 16, 2015
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Publication number: 20150137224
    Abstract: A semiconductor device comprises a transistor formed in a semiconductor body having a first main surface. The transistor comprises a source region, a drain region, a channel region, a drift zone, a source contact electrically connected to the source region, a drain contact electrically connected to the drain region, and a gate electrode at the channel region. The channel region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The channel region has a shape of a first ridge extending along the first direction. One of the source contact and the drain contact is adjacent to the first main surface, the other one of the source contact and the drain contact is adjacent to a second main surface that is opposite to the first main surface.
    Type: Application
    Filed: November 18, 2013
    Publication date: May 21, 2015
    Inventors: Andreas Meiser, Rolf Weis, Franz Hirler, Martin Vielemeyer, Markus Zundel, Peter Irsigler
  • Patent number: 9018638
    Abstract: A MOSFET device is provided. An N-type epitaxial layer is disposed on an N-type substrate. An insulating trench is disposed in the epitaxial layer. A P-type well region is disposed in the epitaxial layer at one side of the insulating trench. An N-type heavily doped region is disposed in the well region. A gate structure is disposed on the epitaxial layer and partially overlaps with the heavily doped region. At least two P-type first doped regions are disposed in the epitaxial layer below the well region. At least one P-type second doped region is disposed in the epitaxial layer and located between the first doped regions. Besides, the first and second doped regions are separated from each other. The first doped regions extend along a first direction, and the second doped region extends along a second direction different from the first direction.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: April 28, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Chee-Wee Liu, Hui-Hsuan Wang
  • Patent number: 9013884
    Abstract: There are provided a display and an electronic unit that realize excellent operability when display content is switched based on a user operation associated with a variation in a physical form, and a supporting substrate employed in such a display. The display includes: a supporting substrate having flexibility; and a display section provided on the supporting substrate. The flexibility of the supporting substrate gradually increases toward an edge in a first region provided at at least a portion on a side of the edge in a plane thereof.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: April 21, 2015
    Assignee: Sony Corporation
    Inventors: Yohei Fukuma, Masahiro Kinoshita, Mitsuhiro Nakamura
  • Patent number: 9006077
    Abstract: Methods for fabricating integrated circuits and FinFET transistors on bulk substrates with active channel regions isolated from the substrate with an insulator are provided. In accordance with an exemplary embodiment, a method for fabricating an integrated circuit includes forming fin structures overlying a semiconductor substrate, wherein each fin structure includes a channel material and extends in a longitudinal direction from a first end to a second end. The method deposits an anchoring material over the fin structures. The method includes recessing the anchoring material to form trenches adjacent the fin structures, wherein the anchoring material remains in contact with the first end and the second end of each fin structure. Further, the method forms a void between the semiconductor substrate and the channel material of each fin structure with a gate length independent etching process, wherein the channel material of each fin structure is suspended over the semiconductor substrate.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: April 14, 2015
    Assignee: GlobalFoundries, Inc.
    Inventors: Murat Kerem Akarvardar, Ajey Poovannummoottil Jacob
  • Publication number: 20150069320
    Abstract: A 3D memory array having a vertically oriented thin film transistor (TFT) selection device that has a body formed from a wide energy band gap semiconductor is disclosed. The wide energy band gap semiconductor may be an oxide semiconductor, such as a metal oxide semiconductor. As examples, this could be an InGaZnO, InZnO, HfInZnO, or ZnInSnO body. The source and drains can also be formed from the wide energy band gap semiconductor, although these may be doped for better conduction. The vertically oriented TFT selection device serves as a vertical bit line selection device in the 3D memory array. A vertical TFT select device has a high drive current, a high breakdown voltage and low leakage current.
    Type: Application
    Filed: September 6, 2013
    Publication date: March 12, 2015
    Applicant: SanDisk 3D LLC
    Inventors: Peter Rabkin, Masaaki Higashitani
  • Patent number: 8975124
    Abstract: One or more embodiments of the disclosed technology provide a thin film transistor, an array substrate and a method for preparing the same. The thin film transistor comprises a base substrate, and a gate electrode, a gate insulating layer, an active layer, an ohmic contact layer, a source electrode, a drain electrode and a passivation layer prepared on the base substrate in this order. The active layer is formed of microcrystalline silicon, and the active layer comprises an active layer lower portion and an active layer upper portion, and the active layer lower portion is microcrystalline silicon obtained by using hydrogen plasma to treat at least two layers of amorphous silicon thin film prepared in a layer-by-layer manner.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: March 10, 2015
    Assignees: Boe Technology Group Co., Ltd., Beijing Asahi Glass Electronics Co., Ltd.
    Inventors: Xueyan Tian, Chunping Long, Jiangfeng Yao
  • Publication number: 20150060997
    Abstract: A semiconductor fin including a vertical stack, from bottom to top, of a second semiconductor material and a first semiconductor material is formed on a substrate. A disposable gate structure straddling the semiconductor fin is formed. A source region and a drain region are formed employing the disposable gate structure as an implantation mask, At least one semiconductor shell layer or a semiconductor cap layer can be formed as an etch stop structure. A planarization dielectric layer is subsequently formed. A gate cavity is formed by removing the disposable gate structure. A portion of the second semiconductor material is removed selective to the first semiconductor material within the gate cavity so that a middle portion of the semiconductor fin becomes suspended over the substrate. A gate dielectric layer and a gate electrode are sequentially formed. The gate electrode laterally surrounds a body region of a fin field effect transistor.
    Type: Application
    Filed: August 27, 2013
    Publication date: March 5, 2015
    Applicant: International Business Machines Corporation
    Inventors: Anirban Basu, Guy Cohen, Amlan Majumdar, Jeffrey W. Sleight
  • Patent number: 8969145
    Abstract: In one aspect, a method of fabricating a nanowire FET device includes the following steps. A layer of III-V semiconductor material is formed on an SOI layer of an SOI wafer. Fins are etched into the III-V material and SOI layer. One or more dummy gates are formed over a portion of the fins that serves as a channel region of the device. A gap filler material is deposited onto the wafer. The dummy gates are removed selective to the gap filler material, forming trenches in the gap filler material. The SOI layer is removed from portions of the fins within the trenches thereby forming suspended nanowire channels in the channel regions of the device. The trenches are filled with at least one gate material to form one or more replacement gates surrounding the nanowire channels in a gate-all-around configuration.
    Type: Grant
    Filed: January 19, 2013
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Isaac Lauer, Jeffrey W. Sleight, Amlan Majumdar
  • Patent number: 8961733
    Abstract: A method of improving an impact-protective property of a conformable substrate is provided. The method includes positioning a central core adjacent the conformable substrate. The central core includes a plurality of rigid plates. A first of the plates is joined by at least one hinge to a second of the plates.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: February 24, 2015
    Assignee: Pinwrest Development Group, LLC
    Inventor: Mark D. Dodd
  • Patent number: 8946070
    Abstract: Producing a transistor includes providing a substrate including in order a first electrically conductive material layer positioned on the substrate and a first electrically insulating material layer positioned on the first electrically conductive material layer. A gate including a reentrant profile is formed from an electrically conductive material layer stack provided on the first electrically insulating material layer in which a first portion of the gate is sized and positioned to extend beyond a second portion of the gate. The gate including the reentrant profile and at least a portion of the first electrically insulating material layer are conformally coated with a second electrically insulating material layer. The second electrically insulating material layer is conformally coated the with a semiconductor material layer. A source and drain electrodes are formed simultaneously by directionally depositing a second electrically conductive material layer on portions of the semiconductor material layer.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: February 3, 2015
    Assignee: Eastman Kodak Company
    Inventors: Lee W. Tutt, Shelby F. Nelson
  • Patent number: 8928093
    Abstract: A semiconductor device may include body contacts on a finFET device for ESD protection. The semiconductor device comprises a semiconductor fin, a source/drain region and a body contact. The source/drain region and the body contact are in the semiconductor fin. A portion of the fin is laterally between the source/drain region and the body contact. The semiconductor fin is on a substrate.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: January 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Hsiung Lo, Jam-Wem Lee, Wun-Jie Lin, Jen-Chou Tseng
  • Patent number: 8927353
    Abstract: A fin field effect transistor and method of forming the same. The fin field effect transistor includes a semiconductor substrate having a fin structure and between two trenches with top portions and bottom portions. The fin field effect transistor further includes shallow trench isolations formed in the bottom portions of the trenches and a gate electrode over the fin structure and the shallow trench isolation, wherein the gate electrode is substantially perpendicular to the fin structure. The fin field effect transistor further includes a gate dielectric layer along sidewalls of the fin structure and source/drain electrode formed in the fin structure.
    Type: Grant
    Filed: May 7, 2007
    Date of Patent: January 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ju-Wang Hsu, Chih-Yuan Ting, Tang-Xuan Zhong, Yi-Nien Su, Jang-Shiang Tsai
  • Patent number: 8912053
    Abstract: A method for fabricating a non-volatile memory device includes forming a stacked structure where a plurality of inter-layer dielectric layers and a plurality of second sacrificial layers are alternately stacked over a substrate, forming a channel layer that is coupled with a portion of the substrate by penetrating through the stacked structure, forming a slit that penetrates through the second sacrificial layers by selectively etching the stacked structure, removing the second sacrificial layers that are exposed through the slit, forming an epitaxial layer over the channel layer exposed as a result of the removal of the second sacrificial layers, and forming a gate electrode layer filling a space from which the second sacrificial layers are removed, and a memory layer interposed between the gate electrode layer and the epitaxial layer.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: December 16, 2014
    Assignee: SK Hynix Inc.
    Inventor: Hyun-Seung Yoo
  • Patent number: 8912612
    Abstract: A FinFET structure which includes: silicon fins on a semiconductor substrate, each silicon fin having two sides and a horizontal surface; a gate wrapping around at least one of the silicon fins, the gate having a first surface and an opposing second surface facing the at least one of the silicon fins; a hard mask on a top surface of the gate; a silicon nitride layer formed in each of the first and second surfaces so as to be below and in direct contact with the hard mask on the top surface of the gate; spacers on the gate and in contact with the silicon nitride layer; and epitaxially deposited silicon on the at least one of the silicon fins so as to form a raised source/drain.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Sanjay Mehta, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 8907406
    Abstract: A semiconductor device according to embodiments includes a semiconductor substrate, a buried insulating layer which is formed on the semiconductor substrate, a semiconductor layer which is formed on the buried insulating layer and includes a narrow portion and two wide portions which are larger than the narrow portion in width and are respectively connected to one end and the other end of the narrow portion, a gate insulating film which is formed on a side surface of the narrow portion, and a gate electrode formed on the gate insulating film. The impurity concentration of the semiconductor substrate directly below the narrow portion is higher than the impurity concentration of the narrow portion, and the impurity concentration of the semiconductor substrate directly below the narrow portion is higher than the impurity concentration of the semiconductor substrate directly below the wide portion.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: December 9, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kensuke Ota, Toshinori Numata, Masumi Saitoh, Chika Tanaka, Yusuke Higashi
  • Patent number: 8906759
    Abstract: A method of forming a FinFET structure which includes forming fins on a semiconductor substrate; forming a gate wrapping around at least one of the fins, the gate having a first surface and an opposing second surface facing the fins; depositing a hard mask on a top of the gate; angle implanting nitrogen into the first and second surfaces of the gate so as to form a nitrogen-containing layer in the gate that is below and in direct contact with the hard mask on top of the gate; forming spacers on the gate and in contact with the nitrogen-containing layer; and epitaxially depositing silicon on the at least one fin so as to form a raised source/drain. Also disclosed is a FinFET structure.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: December 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Sanjay Mehta, Tenko Yamashita, Chun-Chen Yeh
  • Publication number: 20140353746
    Abstract: A semiconductor device of the present invention includes a semiconductor layer, a source region and a drain region formed in a surface of the semiconductor layer, both having a first conductivity type, a plurality of gate trenches each formed so as to extend across the source region and the drain region, in a plan view observed in a direction of a normal to the surface of the semiconductor layer, a channel region of a first conductivity type made of the semiconductor layer sandwiched by the gate trenches adjacent to each other, having a channel length along a direction extending from the drain region to the source region, and a gate electrode buried in the gate trench via a gate insulating film, and the channel region has a thickness in the plan view not more than two times a width of a depletion layer to be generated due to a built-in potential between the channel region and the gate electrode.
    Type: Application
    Filed: May 30, 2014
    Publication date: December 4, 2014
    Applicant: ROHM CO., LTD.
    Inventor: Yasushi HAMAZAWA
  • Patent number: 8901619
    Abstract: Asymmetric FET devices, and a method for fabricating such asymmetric devices on a fin structure is disclosed. The fabrication method includes disposing over the fin a high-k dielectric layer followed by a threshold-modifying layer, performing an ion bombardment at a tilted angle which removes the threshold-modifying layer over one of the fin's side-surfaces. The completed FET devices will be asymmetric due to the threshold-modifying layer being present only in one of two devices on the side of the fin. In an alternate embodiment further asymmetries are introduced, again using tilted ion implantation, resulting in differing gate-conductor materials for the two FinFET devices on each side of the fin.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ying Zhang
  • Patent number: 8901644
    Abstract: Disclosed herein is a field effect transistor with a vertical channel and a fabrication method thereof. A channel region of the field effect transistor is a circular ring-shaped Si platform, which is formed over a substrate and perpendicular to the substrate; a source, which is made of polysilicon, is located at an upper end of the Si platform; a drain is disposed at an outside of a lower end of the circular ring-shaped Si platform; a gate is placed on an outer side surface of the circular ring-shaped Si platform; and an inside of the circular ring-shaped Si platform is filled with a dielectric material. In comparison with the conventional vertical structure MOSFET with a Si platform, the circular ring-shaped structure field effect transistor according to the invention can effectively suppress the short channel effect and improve the device performance.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: December 2, 2014
    Assignee: Peking University
    Inventors: Ru Huang, Yujie Ai, Zhihua Hao, Shuangshuang Pu, Jiewen Fan, Shuai Sun, Runsheng Wang, Xiaoyan Xu
  • Patent number: 8896067
    Abstract: Embodiments of present invention provide a method of forming a first and a second group of fins on a substrate; covering a top first portion of the first and second groups of fins with a first dielectric material; covering a bottom second portion of the first and second groups of fins with a second dielectric material, the bottom second portion of the first group and the second group of fins having a same height; exposing a middle third portion of the first and second groups of fins to an oxidizing environment to create an oxide section that separates the top first portion from the bottom second portion of the first and second groups of fins; and forming one or more fin-type field-effect-transistors (FinFETs) using the top first portion of the first and second groups of fins as fins under gates of the one or more FinFETs.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: November 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Marc Adam Bergendahl, David Vaclav Horak, Shom Ponoth, Chih-Chao Yang, Charles William Koburger, III