Methods for Operating SRAM Cells
A circuit includes a Static Random Access Memory (SRAM) array. An SRAM cell is in the SRAM array and includes a p-well region, a first and a second n-well region on opposite sides of the p-well region, and a first and a second pass-gate FinFET. The first pass-gate FinFET and the second pass-gate FinFET are p-type FinFETs. A CVss line is over the p-well region, wherein the CVss line is parallel to an interface between the p-well region and the first n-well region. A bit-line and a bit-line bar are on opposite sides of the CVss line. A CVdd line crosses over the SRAM cell. A CVss control circuit is connected to the CVss line. The CVss control circuit is configured to provide a first CVss voltage and a second CVss voltage to the CVss line, with the first and the second CVss voltage being different from each other.
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This application is a continuation-in-part application of commonly-assigned U.S. patent application Ser. No. 13/691,373, filed Nov. 30, 2012, and entitled “SRAM Cell Comprising FinFETs,” which application is hereby incorporated herein by reference.
BACKGROUNDStatic Random Access Memory (SRAM) is commonly used in integrated circuits. SRAM cells have the advantageous feature of holding data without a need for refreshing. With the increasing demanding requirement to the speed of integrated circuits, the read speed and write speed of SRAM cells also become more important. Furthermore, enough read margin and write margins are required to achieve reliable read and write operations, respectively. With the increasingly scaling down of the already very small SRAM cells, however, such request becomes increasingly demanding.
For a more complete understanding of the embodiments, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
The making and using of the embodiments of the disclosure are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are illustrative, and do not limit the scope of the disclosure.
A Static Random Access Memory (SRAM) cell is provided in accordance with various exemplary embodiments. The variations of the embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.
The sources of pull-up transistors PU-1 and PU-2 are connected to CVdd-node1 and CVdd-node2, respectively, which are further connected to power supply voltage Vdd. Power supply voltage Vdd may be carried by metal lines CVdd-line, CVdd-line-1, and CVdd-line-2, as shown in
In some embodiments, drain region 113 and source regions 116 of p-type FinFETs PG-1, PG-2, PU-1, and PU-2 are formed by implanting end portions of the semiconductor fin with a p-type impurity such as boron, indium, or the like. In alternative embodiments, drain region 113 and source regions 116 are formed by etching end portions of original fin (such as fins 14 and 34 in
SRAM cell 10 includes a P-well region and two N-well regions N-well-1 and N-well-2 on opposite sides of the P-well region. A first butted contact plug Butt-CO is used to electrically connect gate electrode 36 of transistors PU-2 and PD-2 to the drain region of transistor PD-1, and a second butted contact plug Butt-CO is used to electrically connect gate electrode 16 of transistors PU-1 and PD-1 to the drain region of transistor PD-2. Butted contacts Butt-CO are formed in the contact level and the OD level in
In some embodiments, length L3 of SRAM cell 10 is greater than width W3 of SRAM cell 10, wherein length L3 is measured in the direction perpendicular to the lengthwise directions of the fins 14, 20, 34, and 40 (refer to
Metal line CVss-line, which carries voltage VSS for SRAM cell 10, is located in a same metal layer as metal lines Bit-line and Bit-line bar (also see
Metal lines Word-line and metal lines CVdd-line-1 and CVdd-line-2 are parallel to each other and are in the same metal layer. Metal lines CVdd-line-1 and CVdd-line-2 carry power supply voltage Vdd. The word-line is between lines CVdd-line-1 and CVdd-line-2, which may overlap the opposite long boundaries of SRAM cell 10. The CVdd-line and lines CVdd-line-1 and CVdd-line-2 are perpendicular to, and cross over, the shorter cell boundaries 10C and 10D. The length of the portion of CVdd-line within SRAM cell may be equal to L3. In some embodiments, the word-line and lines Vdd-line-1 and CVdd-line-2 may be in metal layer M2 (
In accordance with some embodiments, laying out CVss-line in the width direction of SRAM cell 10 provides more space for allocating the CVss-line since length L3 is greater than width W3. Accordingly, width W4 of CVs s-line may be increased. This provides a good grounding ability for SRAM cell 10 and the respective SRAM array.
Similarly,
The layout in
The SRAM cells in accordance with the embodiments of the present disclosure may be written into or read from using modified voltages that are different from the Vdd and Vss voltages. The modified voltages may be applied on word-lines, bit-lines, CVss-lines, CVdd-lines, and the like. Tables 1 through 4 illustrate some exemplary voltages for read and write operations and the standby mode of an SRAM array. In Tables 1 through 4, the operations that may be performed on SRAM cells and the exemplary voltages applied on the respective voltage lines are listed. The voltage lines listed in Tables 1 through 4 include power lines (CVdd-line and CVss-line) and signal/control lines (Bit-line, Bit-line Bar, and Word-line) that are connected to an SRAM array, wherein the SRAM array is schematically illustrated in
The operations shown in Table 1 through 3 include write data “1,” write data “0,” and “read data out.” The operation “Write data ‘1’” means writing a logic high data (“1”) into the respective SRAM cell, and the operation “Write data ‘0’” means writing a logic low data (“0”) into the respective SRAM cell. The symbol “Vdd(1)” means applying a voltage equal to positive power supply voltage Vdd to the respective voltage line. The symbol “Vss(0)” means applying a voltage equal to power supply voltage Vss to the respective voltage line. Throughout the description, the voltages that are applied with either Vdd(1) or Vss(0) are not discussed in detail, and the respective voltages may be found referring to Tables 1 through 4.
Table 1 lists the operations that may be performed on a single-port SRAM cell, and the exemplary voltages applied on the voltage lines that are connected to the single-port SRAM cell. An exemplary circuit diagram of the single-port SRAM cell is shown in
Table 1 illustrates write operation 1 and write operation 2, which are different approaches for performing write operations. As shown in Table 1, in write operation 1 for writing data “1” or data “0” into an SRAM cell, the respective CVss-line is applied with a voltage equal to Vss+ΔV1, which is a voltage higher than power supply voltage Vss (for example, en electrical ground voltage), and lower than power supply voltage Vdd. In some embodiments, voltage difference ΔV1 is greater than about 30 mV, although it may have a different value. The remaining voltages applied on other voltage lines as shown in Table 1 may be regular Vdd(1) voltage or Vss(0) voltage.
In write operation 2 for writing data “1” into an SRAM cell, the respective Bit-line is applied with a voltage equal to Vdd+ΔV2, which is a voltage higher than power supply voltage Vdd. The respective Bit-line Bar is applied with a voltage equal to Vss. In some embodiments, voltage difference ΔV2 is greater than about 30 mV, although it may have a different value. The remaining voltages applied on other voltage lines may be regular Vdd(1) voltage or Vss(0) voltage. In write operation 2 for writing data “0” into the SRAM cell, the respective Bit-line Bar is applied with a voltage equal to Vdd+ΔV2. The respective Bit-line is applied with a voltage equal to Vss. The remaining voltages applied on other voltage lines may be regular Vdd(1) voltage or Vss(0) voltage.
In the write operations 1 and 2 for writing into the sing-port SRAM cell, by increase the voltages on the CVss-line, Bit-line, or Bit-line Bar, the write margin may be improved, and hence the write speed and reliability are improved.
Table 1 also illustrates read operation 1 and read operation 2, which are different approaches for performing read operations. In read operation 1 for reading data out of an SRAM cell, the respective Word-line is applied with a voltage equal to Vss+ΔV3, which is a voltage higher than power supply voltage Vss, and lower than power supply voltage Vdd. In some embodiments, voltage difference ΔV3 is greater than about 30 mV, although it may have a different value. The remaining voltages applied on other voltage lines in read operation 1 may be regular Vdd(1) voltage or Vss(0) voltage.
In read operation 2 for reading data out of an SRAM cell, the respective CVss-line is applied with a voltage equal to Vss-ΔV4, which is a voltage lower than power supply voltage Vss (for example, en electrical ground voltage). Voltage Vss-ΔV4 may also be a negative voltage. In some embodiments, voltage difference ΔV4 is greater than about 30 mV, although it may have a different value. The remaining voltages applied on other voltage lines in read operation 2 may be regular Vdd(1) voltage or Vss(0) voltage. With either the increased word-line voltage in read operation 1, or the decreased CVss-line voltage in read operation 2, not only reading data from the SRAM cell is easier, the data stored in the DRAM cell is less unlikely to be flipped by the read operation.
Table 2 lists the operations that may be performed on two-port SRAM cells and dual port SRAM cells, and the exemplary voltages applied on the voltage lines that are connected to the two-port or dual-port SRAM cells. An exemplary circuit diagram of the two-port SRAM cell is shown in
An exemplary circuit diagram of the dual-port SRAM cell is shown in
As shown in Table 2, in a write operation for writing data “1” into a two-port or dual-port SRAM cell, the respective Bit-line in Table 2 is applied with a voltage equal to Vdd+ΔV2, which is a voltage higher than power supply voltage Vdd. The respective Bit-line Bar is applied with a voltage equal to Vss. In some embodiments, voltage difference ΔV2 is greater than about 30 mV, although it may have a different value. The remaining voltages applied on other voltage lines in the write operation may be regular Vdd(1) voltage or Vss(0) voltage. When writing data “0” into the two-port or dual-port SRAM cell, the respective Bit-line Bar is applied with a voltage equal to Vdd+ΔV2. The respective Bit-line is applied with a voltage equal to Vss. The remaining voltages applied on other voltage lines as shown in Table 2 may be regular Vdd(1) voltage or Vss(0) voltage.
In a read operation for reading data out of the dual-port or two-port SRAM cell, the respective Write Word-line is applied with a voltage equal to Vss+ΔV3, which is a voltage high than power supply voltage Vss. In some embodiments, voltage difference ΔV3 is greater than about 30 mV, although it may have a different value. The remaining voltages applied on other voltage lines in the read operation may be regular Vdd(1) voltage or Vss(0) voltage.
In the operations shown in Table 2, when data is written into some SRAM cells that are connected to a word line, the remaining SRAM cells connected to the same word line experience dummy read. With the increased voltages on the Bit-line and Bit-Line bar, the data in the SRAM cells experiencing dummy read are protected from being changed by the dummy read operation.
Table 3 lists the operations that may be performed on two-port SRAM cells, and the exemplary voltages applied on the voltage lines that are connected to the two-port SRAM cells. The respective operations are performed so that all SRAM cells connected to a same word-line are written into or read from at the same time. Therefore, no dummy read occurs to any of the SRAM cells. An exemplary circuit diagram of the two-port SRAM cell is shown in
As shown in Table 3, in a write operation for writing data “1” or data “0” into the two-port SRAM cell, the respective “Write/Read Word-line” (which will be word-line W-WL in
In a read operation for reading data out of the two-port SRAM cell, the respective “Write/Read Word-line” (which will be word-line R-WL in
Table 4 lists the exemplary voltages applied on the voltage lines that are connected to single-port, two-port, or dual-port SRAM cells in a standby mode. Accordingly, the voltages listed in Table 4 correspond to FIGS. 1 and 11-21. The correspondence between the voltage lines in Table 4 and the voltage lines in
As shown in Table 4, in approach 1 for the standby mode, the voltage on CVdd-line is reduced to Vdd-ΔV6, which is a voltage lower than power supply voltage Vdd. In some embodiments, voltage difference ΔV6 is greater than about 30 mV, or greater than about 200 mV, although it may have a different value. Alternatively or simultaneously, as shown in approach 2, the voltage on CVss-line is increased to Vss+ΔV7, which is a voltage higher than power supply voltage Vss and lower than voltage Vdd. In some embodiments, voltage difference ΔV7 is greater than about 50 mV, although it may have a different value. The remaining voltages applied on other voltage lines may be regular Vdd(1) voltage or Vss(0) voltage. By increasing the voltage on CVdd-line or reducing the voltage on CVss-line, the power consumption may be reduced.
In accordance with some embodiments, the CVss-lines for different SRAM cells in a same SRAM cells array may need to have different voltages. Accordingly, in accordance with some embodiments, the CVss-lines as shown in
The circuit in
The circuit in
In accordance with the exemplary embodiments of the present disclosure, by adopting p-type pass-gate FinFETs, strong drive currents Ion can be obtained, and the speed of the respective SRAM cell is improved. The embodiments have good resistance to alpha-particle induced errors. The raised SiGe epitaxy regions for the source and drain regions of the FinFETs in the SRAM cells may result in a low contact resistance, and hence the drive currents Ion are further boosted. The landing margin for the contact plugs to land on the source and drain regions is also improved by using raised SiGe epitaxy regions. By adjusting the voltages on Bit-line, Bit-line Bar, Word-line, and the CVss-line voltage, the read and write speed may be increased, and the read and write reliability may be improved. The power consumption of the SRAM cells may also be reduced by increasing the voltage on CVss-line, or reducing the voltage on CVdd-line.
In accordance with some embodiments, a circuit includes an SRAM array. An SRAM cell is in the SRAM array and includes a p-well region, a first and a second n-well region on opposite sides of the p-well region, and a first and a second pass-gate FinFET. The first pass-gate FinFET and the second pass-gate FinFET are p-type FinFETs. A CVss line is over the p-well region, wherein the CVss line is parallel to an interface between the p-well region and the first n-well region. A bit-line and a bit-line bar are on opposite sides of the CVss line. A CVdd line crosses over the SRAM cell. A CVss control circuit is connected to the CVss line. The CVss control circuit is configured to provide a first CVss voltage and a second CVss voltage to the CVss line, with the first and the second CVss voltage are different from each other.
In accordance with other embodiments, a circuit includes an SRAM array having a plurality of rows and columns of SRAM cells. Each of the SRAM cells includes a p-well region, a first and a second n-well region on opposite sides of the p-well region, and a first pass-gate FinFET and a second pass-gate FinFET. The first pass-gate FinFET and the second pass-gate FinFET are p-type FinFETs. A CVss line is over the p-well region. A bit-line and a bit-line bar are on opposite sides of the CVss line. A CVdd line crosses over the SRAM cell. A CVdd control circuit is connected to the CVdd line. The CVdd control circuit is configured to provide a first CVdd voltage and a second CVdd voltage to the CVdd line. With the first CVdd voltage and the second CVdd voltage being different from each other.
In accordance with yet other embodiments, a method includes performing a first operation on as SRAM array by supplying a Vss voltage to a CVss line of the SRAM array. The SRAM array has a plurality of rows and a plurality of columns of SRAM cells. Each of the SRAM cells includes a p-well region, a first and a second n-well region on opposite sides of the p-well region, and a first pass-gate FinFET and a second pass-gate FinFET in the first n-well region and the second n-well region, respectively. The first pass-gate FinFET and a second pass-gate FinFET are p-type FinFETs. The method further includes performing a second operation on the SRAM array by supplying a modified Vss voltage to the CVss line, wherein the Vss voltage and the modified Vss voltage are different from each other.
Although the embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the embodiments as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the disclosure.
Claims
1. A circuit comprising:
- a Static Random Access Memory (SRAM) array;
- an SRAM cell in the SRAM array, wherein the SRAM cell comprises: a p-well region; a first and a second n-well region on opposite sides of the p-well region; and a first pass-gate FinFET and a second pass-gate FinFET, wherein the first pass-gate FinFET and the second pass-gate FinFET are p-type FinFETs;
- a CVss line over the p-well region, wherein the CVss line is parallel to an interface between the p-well region and the first n-well region;
- a bit-line and a bit-line bar on opposite sides of the CVss line;
- a CVdd line crossing over the SRAM cell; and
- a CVss control circuit connected to the CVss line, wherein the CVss control circuit is configured to provide a first CVss voltage and a second CVss voltage to the CVss line, and wherein the first CVss voltage and the second CVss voltage are different from each other.
2. The circuit of claim 1, wherein the CVss line and the p-well region are electrically decoupled from each other, and are configured to be capable of having different voltages.
3. The circuit of claim 1, wherein the SRAM cell further comprises:
- a first pull-up Fin Field-Effect Transistor (FinFET) and a second pull-up FinFET in the first n-well region and the second n-well region, respectively; and
- a first pull-down FinFET and a second pull-down FinFET in the p-well region.
4. The circuit of claim 1 further comprising:
- a plurality of CVss lines, each connected to one column of the SRAM array; and
- a plurality of CVss control circuits, each coupled to one of the plurality of CVss lines, wherein each of the plurality of CVss control circuits is configured to supply at least two different voltages to a respective one of the plurality of CVss lines.
5. The circuit of claim 1 further comprising a CVdd control circuit connected to the CVdd line, wherein the CVdd control circuit is configured to provide a first CVdd voltage and a second CVdd voltage to the CVdd line, and wherein the first CVdd voltage and the second CVdd voltage are different from each other.
6. The circuit of claim 5, wherein the CVdd control circuit is shared by all columns of the SRAM array.
7. The circuit of claim 1 further comprising a bit-line voltage control circuit connected to the bit-line and the bit-line bar, wherein the bit-line voltage control circuit is configured to provide a bit-line voltage different from power supply voltages Vdd and Vss.
8. A circuit comprising:
- a Static Random Access Memory (SRAM) array comprising a plurality of rows and columns of SRAM cells, wherein each of the SRAM cells comprises: a p-well region; a first and a second n-well region on opposite sides of the p-well region; and a first pass-gate FinFET and a second pass-gate FinFET, wherein the first pass-gate FinFET and the second pass-gate FinFET are p-type FinFETs;
- a CVss line over the p-well region;
- a bit-line and a bit-line bar on opposite sides of the CVss line;
- a CVdd line crossing over the SRAM cell; and
- a CVdd control circuit connected to the CVdd line, wherein the CVdd control circuit is configured to provide a first CVdd voltage and a second CVdd voltage to the CVdd line, and wherein the first CVdd voltage and the second CVdd voltage are different from each other.
9. The circuit of claim 8 further comprising an enable control circuit coupled to the CVdd control circuit, wherein the enable control circuit is configured to generate different enable control signals in response to different operation modes of the SRAM array.
10. The circuit of claim 9, wherein the CVdd control circuit is connected to, and is configured to provide voltages to, all columns of the SRAM array.
11. The circuit of claim 9, wherein the CVdd control circuit is configured to provide a reduced voltage during a standby mode of the SRAM array, wherein the reduced voltage is lower than a voltage provided to the CVdd line during a non-standby mode of the SRAM array.
12. The circuit of claim 8 further comprising a bit-line voltage control circuit connected to the bit-line and the bit-line bar, wherein the bit-line voltage control circuit is configured to provide a bit-line voltage different from power supply voltages Vdd and Vss provided to the SRAM array.
13. The circuit of claim 12, wherein the bit-line voltage is higher than the power supply voltages Vdd.
14. The circuit of claim 8, wherein the SRAM cell further comprising:
- a first pull-up Fin Field-Effect Transistor (FinFET) and a second pull-up FinFET in the first n-well region and the second n-well region, respectively; and
- a first pull-down FinFET and a second pull-down FinFET in the p-well region.
15. The circuit of claim 8 further comprising a CVss control circuit connected to the CVss line, wherein the CVss control circuit is configured to provide a first CVss voltage and a second CVss voltage to the CVss line, and wherein the first CVss voltage and the second CVss voltage are different from each other.
16. A method comprising:
- performing a first operation on a Static Random Access Memory (SRAM) array by supplying a Vss voltage to a CVss line of the SRAM array, wherein the SRAM array comprises a plurality of rows and a plurality of columns of SRAM cells, each comprising: a p-well region; a first and a second n-well region on opposite sides of the p-well region; and a first pass-gate FinFET and a second pass-gate FinFET in the first n-well region and the second n-well region, respectively, wherein the first pass-gate FinFET and the second pass-gate FinFET are p-type FinFETs; and
- performing a second operation on the SRAM array by supplying a modified Vss voltage to the CVss line, wherein the Vss voltage and the modified Vss voltage are different from each other.
17. The method of claim 16, wherein during the first operation and the second operation, voltages of the p-well region are different from the Vss voltage and the modified Vss voltage, respectively.
18. The method of claim 16, wherein the first operation is a read operation, and the second operation is a write operation, and wherein the Vss voltage is lower than the modified Vss voltage.
19. The method of claim 18, wherein the Vss voltage is lower than the modified Vss voltage by more than about 30 mV.
20. The method of claim 16 further comprising, during a standby mode of the SRAM array, increasing a voltage on the CVss line to a third voltage greater than the Vss voltage.
Type: Application
Filed: Jan 25, 2013
Publication Date: Jun 5, 2014
Patent Grant number: 8964457
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Hsin-Chu)
Inventor: Taiwan Semiconductor Manufacturing Company, Ltd.
Application Number: 13/750,864
International Classification: G11C 11/419 (20060101); G11C 11/412 (20060101);