Abstract: A dual-port static random access memory (SRAM) cell is provided. The dual-port SRAM cell includes: P-type active patterns that are spaced apart from one another along a first direction, each of the P-type active patterns extending in a second direction perpendicular to the first direction and including at least one transistor. The P-type active patterns include first through sixth P-type active patterns which are sequentially arranged along the first direction. A first cutting area is provided between the second P-type active pattern and a first boundary of the dual-port SRAM cell that extends along the first direction, and a second cutting area is provided between the fifth P-type active pattern and a second boundary that is opposite to the first boundary and extends along the first direction.

Abstract: Disclosed is a physical unclonable function generator circuit and method.

Abstract: A semiconductor structure is provided. A logic cell with a logic function includes a plurality of first transistors in an active region over a semiconductor substrate, a second transistor in the active region, a third transistor in the active region, and first and second isolation structures on opposite edges of the active region and extending along the first direction. Each first transistor includes a first gate electrode extending along the first direction. The second transistor includes a second gate electrode extending along the first direction. The third transistor includes a third gate electrode extending along the first direction. The first gate electrodes are disposed between the first and second isolation structures. The second gate electrode is disposed between the first gate electrodes and the first isolation structure. The third gate electrode is disposed between the first gate electrodes and the second isolation structure.

Abstract: A memory circuit includes a NAND logic gate configured to receive a first bit line signal and a second bit line signal, and to generate a first signal. The memory circuit further includes a first P-type transistor coupled to the NAND logic gate, and configured to receive a first clock signal. The memory circuit further includes a first N-type transistor coupled to the NAND logic gate, and configured to receive a first pre-charge signal. The memory circuit further includes a first latch coupled to the NAND logic gate, and configured to latch the first signal in response to at least the first clock signal or the first pre-charge signal.

Abstract: A static random access memory includes a first and second memory cell array, a first word line, a bit line, a bit line bar, a primary driver circuit, and a first and second supplementary driver circuit. The first supplementary driver circuit is configured to pull a voltage of a first signal of the bit line or a second signal of the bit line bar to a first voltage level during a write operation in response to a supplementary driver circuit enable signal. The second supplementary driver circuit is configured to sense the voltage of the first or second signal. The second supplementary driver circuit includes a first pass-gate transistor. A first terminal of the first pass-gate transistor is coupled to a reference voltage supply. A second terminal of the first pass-gate transistor is electrically floating. A third terminal of the first pass-gate transistor is coupled to a first node.

Abstract: In a memory device including a ternary memory cell, the ternary memory cell may include: a first inverter and a second inverter cross-coupled in a first node and a second node and including a pull-up device and a pull-down device configured to have a constant current pass therethrough upon turn-off; a first read transistor and a first write transistor which are connected to each other in parallel between the first node and a first bit line; and a second read transistor and a second write transistor which are connected to each other in parallel between the second node and a second bit line, wherein the first read transistor and the second read transistor may have a read access current, which is less than or equal to the constant current, pass therethrough in response to an activated read word line.

Abstract: Embodiments provide a control circuit and a semiconductor memory. The control circuit includes a bias switching circuit and a first logic gate circuit. The first logic gate circuit includes at least one target transistor. A substrate of one of the at least one target transistor is connected to an output terminal of the bias switching circuit. The first logic gate circuit has a first speed mode and a second speed mode. A transmission speed of the first speed mode is less than a transmission speed of the second speed mode. The bias switching circuit is configured to: receive a target signal, and output a target bias voltage, to increase a threshold voltage of the target threshold. The enabled state of the target signal represents that the first logic gate circuit is in the first speed mode.

Abstract: An array of memory cells is arranged into a plurality of columns and rows. A first signal line extends through a first column of the plurality of columns. The first signal line is electrically coupled to the memory cells in the first column. A first end portion of the first signal line is configured to receive a logic high signal from a first circuit during a first operational state of the memory device and a logic low signal from the first circuit during a second operational state of the memory device. A second circuit includes a plurality of transistors. The transistors are configured to be turned on or off to electrically couple a second end portion of the first signal line to a logic low source when the first end portion of the first signal line is configured to receive the logic low signal from the first circuit.

Abstract: SRAM cells are connected in columns by bit lines and connected in rows by first and second word lines coupled to first and second data storage sides of the SRAM cells. First the first word lines are actuated in parallel and then next the second word lines are actuated in parallel in first and second phases, respectively, of an in-memory compute operation. Bit line voltages in the first and second phases are processed to generate an in-memory compute operation decision. A low supply node reference voltage for the SRAM cells is selectively modulated between a ground voltage and a negative voltage. The first data storage side receives the negative voltage and the second data storage side receives the ground voltage during the second phase. Conversely, the second data storage side receives the negative voltage and the first data storage side receives the ground voltage during the first phase.

Abstract: Methods, systems, and devices for configurable input for an amplifier are described. In some examples, a circuit may be configured to operate based on a signal having a first voltage profile or a second voltage profile. For example, the first voltage profile may be associated with a range of voltages that are based on a temperature of an associated memory chip, and the second voltage profile may be associated with a voltage (or voltages) that are not associated with the temperature of the memory chip. The circuit may include one or more transistors and switches that are activated based on the voltage profile and a switch receiving a particular control signal. In some instances, the control signal may be received based on a value stored to one or more non-volatile memory elements.

Abstract: A memory cell includes a flip-flop circuit that includes a first CMOS inverter circuit including a 1Ath transistor TR1 and a 1Bth transistor TR2 and a second inverter circuit including a 2Ath transistor TR3 and a 2Bth transistor TR4 and two transfer transistors TR5 and TR6. The 1Ath transistor TR1 and the 2Ath transistor TR2 are connected to a common first power supply line, and the 1Bth transistor TR3 and the 2Bth transistor TR4 are connected to a common second power supply line.

Abstract: Various implementations described herein are related to a device having a memory cell with logic that is configured to store data and passgates that are configured to access the data stored in the logic. The device may include a first number of input-output ports that are time-multiplexed with the passgates so as to increase the first number of input-output ports to a second number of input-output ports that is greater than the first number of input-output ports.

Abstract: A memory architecture for optimizing leakage currents in standby mode and a method thereof is disclosed. The memory architecture includes a plurality of memory segments configured to operate in one or more modes of operations. The plurality of memory segments includes a plurality of decoder slices. Each of the plurality of decoder slice includes a plurality of wordlines running in the row direction; at least one array power header configured for controlling leakage currents within each of the plurality of decoder slice in the row direction; and a retention header. Each of the plurality of power supply rails running in the column direction are segmented within one or more decoder slice to form one or more segmented power supply node.

Abstract: A memory device includes a memory cell array having a plurality of memory cells arranged in rows and columns, each row of memory cells being associated with a word line, each column of memory cells being associated with a bit line and a source line. Each memory cell includes: a storage device coupled to the bit line, the storage device being selectable between a first resistance state and a second resistance state in response to a bit line signal at the bit line; and a selection device connected in series with the storage device and coupled to the source line, the selection device being configured to provide access to the storage device in response to a word line signal at the word line. The memory device further includes a word-line driver and a bit-line driver. A first number of the source lines are connected in parallel.

Abstract: An IC structure comprises a substrate, a first SRAM cell, and a second SRAM cell. The first SRAM cell is formed over the substrate and comprises a first N-type transistor. The second SRAM cell is formed over the substrate and comprises a second N-type transistor. A gate structure of first N-type transistor of the first SRAM cell has a different work function metal composition than a gate structure of the second N-type transistor of the second SRAM cell.

Abstract: Disclosed is a physical unclonable function generator circuit and method.

Abstract: Methods of operating a memory, and apparatus configured to perform similar methods, include determining a voltage level of a stepped sense operation that activates a memory cell of the memory during a programming operation for the memory cell, and determining a voltage level of a ramped sense operation that activates the memory cell during a read operation for the memory cell.

Abstract: Disclosed herein is a memory-type camouflaged logic gate using transistors having different threshold voltages. The camouflaged logic gate may include two or more candidate logic gates, memory, the output signal of which is adjusted based on two or more transistors having different threshold voltages, and a multiplexer for selectively outputting the output of one of the two or more candidate logic gates depending on the output signal of the memory.

Abstract: A memory cell includes a write port and a read port. The write port includes two cross-coupled inverters that form a storage unit. The cross-coupled inverters are connected between a first power source signal line and a second power source signal line. The write port also includes a first local interconnect line in an interconnect layer that is connected to the second power source signal line. The read port includes a transistor that is connected to the storage unit in the write port and to the second power source signal line, and a second local interconnect line in the interconnect layer that is connected to the second power source signal line. The second local interconnect line in the read port is separate from the first local interconnect line in the write port.

Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, and a third semiconductor element. A first terminal of the first semiconductor element is coupled to a first computing bit-line. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to the memory cell circuit. A first terminal of the second semiconductor element is coupled to a second terminal of the first semiconductor element. A first terminal of the third semiconductor element is coupled to a second terminal of the second semiconductor element. A second terminal of the third semiconductor element is coupled to a second computing bit-line. A control terminal of the third semiconductor element receives a bias voltage.

Abstract: A memory device is provided. The memory device includes a bit cell having a first invertor connected between a first node and a second node and a second invertor connected between the first node and the second node. The first invertor and the second invertor are cross coupled at a first data node and a second data node. The memory device further includes a pull down circuit connected to the second node. The pull down circuit is operative to pull down a voltage of the second node below a ground voltage in response to an enable signal.

Abstract: An integrated circuit memory device includes a static random access memory (SRAM) cell, and a charge storing circuit electrically coupled to the SRAM cell. A switching controller is provided, which is electrically coupled to the charge storing circuit. The switching controller and the charge storing circuit are collectively configured to save power by recycling charge associated with a bit line electrically coupled to the SRAM cell by: (i) transferring charge from the bit line to a charge storage node electrically coupled to source terminals of a pair of NMOS pull-down transistors within the SRAM cell upon commencement of a SRAM cell write operation, and then (ii) returning at least a portion of the charge to the bit line upon completion of the SRAM cell write operation.

Abstract: A layout pattern of static random access memory at least includes a substrate, a plurality of fin structures on the substrate, a plurality of gate structures on the substrate and spanning the fin structures to form a plurality of transistors distributed on the substrate, the plurality of transistors include, a first pull-up transistor PU1, a first pull-down transistor PD1, a second pull-up transistor PU2, a second pull-down transistor PD2, a first pass gate transistor PG1, a second pass gate transistor PG2, a first read transistor RPD and a second read transistor RPG, and an additional fin structure, the additional fin structure is located between the fin structure of the first pass gate transistor PG1 and the fin structure of the second read transistor RPG.

Abstract: A memory is provided that is configured to practice both a normal read operation and also a burst mode read operation. A column multiplexer selects from a plurality of columns using a pair of pass transistor for each column. The column multiplexer drives a true input node and a complement input node of an output data latch.

Abstract: An optimization device includes: a memory; and a processor configured to: calculate, as bit operations, when any bit in a bit string representing a state of an Ising model is inverted, an energy change value of the Ising model based on a coefficient indicating magnitude of an interaction between an own bit and the inverted bit in the bit string; output a first signal indicating inversion availability of the own bit according to the energy change value and a second signal indicating the energy change value; select the bit to be inverted in the bit string and the energy change value corresponding to the bit based on the first signal and the second signal; output a fourth signal indicating the selected energy change value; and calculate energy of the Ising model based on the energy change value indicated by the fourth signal.

Abstract: A memory array includes a first memory cell and a second memory cell, each including a data storage element having a first terminal and a second terminal, a first access transistor coupled to the first terminal of the data storage element, and a second access transistor coupled to the second terminal of the data storage element. The memory device also includes a first bit line coupled to the first access transistor of the first memory cell, a second bit line coupled to the second access transistor of the first memory cell, a third bit line coupled to the first access transistor of the second memory cell and a fourth bit line coupled to the second access transistor of the second memory cell.

Abstract: A circuit includes a memory array, a write circuit configured to store data in memory cells of the memory array, a read circuit configured to retrieve the stored data from the memory cells of the memory array, and a computation circuit configured to perform one or more logic operations on the retrieved stored data. The memory array is positioned between the write circuit and the read circuit.

Abstract: A semiconductor device capable of reducing electric power consumption while suppressing deterioration in reliability is provided. The semiconductor device includes a flash memory, a SRAM formed on a SOI substrate, oscillation circuits generating a signal of a first frequency and a signal of a second frequency lower than the first frequency, and a processor operating in synchronization with a system clock. The processor performs steps of turning on a power supply of the flash memory, lowering a threshold voltage of the SRAM, transferring a program from the flash memory to the SRAM by using the signal of the first frequency as the system clock, turning off the power supply of the flash memory, heightening the threshold voltage of the SRAM, and executing the program stored in the SRAM by using the signal of the second frequency as the system clock.

Abstract: A method of generating a layout diagram of an IC cell includes defining a boundary recess in a boundary of the cell by extending a first portion of the boundary along a first gate track, extending a second portion of the boundary from the first gate track to a second gate track, the second portion being contiguous with the first portion, and extending a third portion of the boundary from the first gate track to the second gate track, the third portion being contiguous with the first portion. An active region is positioned in the cell by extending the active region across a third gate track, wherein the first gate track is between the second gate track and the third gate track. The layout diagram is stored on a non-transitory computer-readable medium.

Abstract: The present application provides a dual-port SRAM cell and a layout structure thereof, comprises a first and a second NMOS transistors, a first and a second PMOS transistors; the gates of the first and second NMOS transistors and the drains of the first and second PMOS transistors are connected to a word line; the source of the first NMOS transistor is connected to a first bit line; the source of the first PMOS transistor is connected to a second bit line; the source of the second NMOS transistor is connected to a third bit line; the source of the second PMOS transistor is connected to a fourth bit line; the drain of the first NMOS transistor and the gate of the first PMOS transistor are connected to a common input node of a latch.

Abstract: An SRAM write assist device includes: a power circuit supplying power to an SRAM-cells column and then stopping supplying power to make the voltage of a power-receiving terminal of the SRAM-cells column floating; a write driving circuit coupling a bit line of the SRAM-cells column with a ground terminal according to a data signal in a write drive phase; a charge sharing circuit coupling the power-receiving terminal with the first terminal of a capacitor to lower this terminal's floating voltage by charge sharing in a charge sharing phase; a charging circuit including a switch turned on to charge the capacitor with an operating voltage in a charge phase; and a negative-voltage coupling circuit including the capacitor whose first and second terminals are coupled to a ground terminal and the bit line respectively to lower the voltage of the bit line by charge sharing in a negative-voltage generation phase.

Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storage systems selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storage systems selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to minimize power consumption. Moreover, the configurable memory storage systems selectively provide the maximum operational voltage signal to bulk (B) terminals of some of their transistors to prevent latch-up of these transistors.

Abstract: A memory cell includes a write port and a read port. The write port includes two cross-coupled inverters that form a storage unit. The cross-coupled inverters are connected between a first power source signal line and a second power source signal line. The write port also includes a first local interconnect line in an interconnect layer that is connected to the second power source signal line. The read port includes a transistor that is connected to the storage unit in the write port and to the second power source signal line, and a second local interconnect line in the interconnect layer that is connected to the second power source signal line. The second local interconnect line in the read port is separate from the first local interconnect line in the write port.

Abstract: A semiconductor circuit of the present disclosure includes: a volatile first storage section; a volatile second storage section that stores data stored in the first storage section on the basis of a first control signal; a non-volatile third storage section that stores data according to data stored in the second storage section on the basis of a second control signal, and causes the first storage section to store data stored in itself on the basis of a third control signal; and a control section that generates the first control signal and the third control signal, and compares the data stored in the first storage section and the data stored in the second storage section with each other to generate the second control signal on the basis of a result of the comparison.

Abstract: An SRAM device and method of forming include pass gate (PG), pull-down (PD), and pull-up (PU) transistors. A first gate line of the PG and a second gate line of the PD and the PU extend in a first direction. A common source/drain of the PG, PD, and PU transistors interposes the first and second gate lines and another source/drain of the PG transistor. A first contact extends from the common source/drain and a second contact extends from the another source/drain. A third contact is disposed above the second contact with a first width in the first direction and a first length in a second direction, first length being greater than the first width.

Abstract: In some examples, an inactive word line voltage control (IWVC) circuit may be configured to provide a respective subword driver associated with a memory bank of a plurality of memory banks a non-active potential from a default off-state word line voltage (VNWL) to a reduced voltage VNWL lower than the default VNWL following a time duration after activating the memory bank. The IWVC circuit may also be configured to provide the respective subword driver with the default VNWL responsive to precharging the memory bank. The IWVC circuit may include a multiplexer coupled to the subword driver and configured to provide the default VNWL or the reduced voltage VNWL to the respective subword driver responsive to a VNWL control signal. The IWVC circuit may also include a time control circuit configured to provide the VNWL control signal responsive to a clock signal and a time control signal.

Abstract: An ultra low VDD memory cell has a ratioless write port. In some embodiments, the VDD operation level can be as low as the threshold voltage of NMOS and PMOS transistors of the cell.

Abstract: A semiconductor storage circuit has: a plurality of first memory cells and a first precharge transistor connected to a first local read bit line; and a plurality of second memory cells and a second precharge transistor connected to a second local read bit line. A signal responsive to signals output to the first and second local read bit lines is output to a global read bit line via a gate circuit and an output circuit. A first transistor having a gate connected to the output of the gate circuit is provided between the first and second local read bit lines.

Abstract: The present disclosure discloses a circuit structure. The circuit structure comprises: a redundant memory device for simulating a read operation of the memory cell in response to the driving of the test word line voltage; a decision device connected to the internal node of the redundant memory device for determining whether the test word line voltage causes the internal node of the redundant memory device to reverse during the read operation in response to the read operation. In response to the reversal, the redundant memory device simulates the read operation with the adjusted test word line voltage until the determination device determines that the internal node does not reverse during the read operation. The circuit structure also comprises: a statistics device for counting and outputting the number of reversals, which is used to characterize the critical word line voltage in conjunction with each adjustment of the test word line voltage.

Abstract: An SRAM cell with dynamic split ground (GND) and split wordline (WL) for extreme scaling is disclosed. The memory cell includes a first access transistor enabled by a first wordline to control access to cross coupled inverters by a first bitline. The memory cell further includes a second access transistor enabled by a second wordline to control access to the cross coupled inverters by a second bitline. The memory cell further includes a split ground line comprising a first ground line (GNDL) separated from a second ground line (GNDR). The GNDL is connected to a transistor of a first inverter of the cross coupled inverters and the GNDR is connected to a first transistor of a second inverter of the cross coupled inverters.

Abstract: A power gating system including: a first power line coupled to a first pad; a second power line coupled to a second pad; a third power line coupled to a plurality of logic gates in common; a first power gating switch coupled between the first and third power lines; and a second power gating switch coupled between the second and third power lines. When a double power mode is set, the first and second power gating switches may be turned on to couple the first and second power lines to the third power line at the same time.

Abstract: A method for storing information in SRAM bit cell arrays provides for lowering voltage supplied to the SRAM bit cell arrays, with voltage lowering controlled by a connected voltage control circuit. Writing, reading, and correcting information storable in the SRAM bit cell arrays is accomplished using an error correcting code (ECC) block connected to at least some of the SRAM bit cell arrays. The ECC block is configurable to repair stored information.

Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storage systems selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storage systems selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to minimize power consumption. Moreover, the configurable memory storage systems selectively provide the maximum operational voltage signal to bulk (B) terminals of some of their transistors to prevent latch-up of these transistors.

Abstract: An electromechanical power switch device and methods thereof. At least some of the illustrative embodiments are devices including a semiconductor substrate, at least one integrated circuit device on a front surface of the semiconductor substrate, an insulating layer on the at least one integrated circuit device, and an electromechanical power switch on the insulating layer. By way of example, the electromechanical power switch may include a source and a drain, a body region disposed between the source and the drain, and a gate including a switching metal layer. In some embodiments, the body region includes a first body portion and a second body portion spaced a distance from the first body portion and defining a body discontinuity therebetween. Additionally, in various examples, the switching metal layer may be disposed over the body discontinuity.

Abstract: Various implementations described herein may refer to an integrated circuit using discharging circuitries for bit lines. In one implementation, an integrated circuit may include a memory array having memory cells, where the memory cells are arranged into columns and configured to be accessed using bit line pairs. The integrated circuit may also include discharging circuitries to selectively discharge the bit line pairs, where a respective discharging circuitry is coupled to a negative supply voltage node of a respective column of memory cells. The respective discharging circuitry may discharge a bit line pair of the respective column to a first voltage when the bit line pair is selected for a memory operation, and may discharge the bit line pair of the respective column to a second voltage when the bit line pair is not selected for a memory operation, where the second voltage is greater than the first voltage.

Abstract: A semiconductor structure includes a first transistor including a first gate structure over a first active region in a substrate, a second transistor including a second gate structure over a second active region in the substrate, and a butted contact electrically connecting the second active region of the second transistor to the first gate structure of the first transistor. The butted contact includes a first portion extending along a first direction and overlapping at least the second active region, and a second portion extending along a second direction different from the first direction and intersecting the first portion. The second portion extends over the first gate structure.

Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.

Abstract: A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.

Abstract: In one embodiment, a graphics processor includes a register file having a plurality of storage segments to store information and output a plurality of segment outputs via a plurality of segmented bitlines to a static logic circuit to receive the plurality of segment outputs from the plurality of storage segments and to output read data based on the plurality of segment outputs. The register file may output the read data with a same amount of power without regard to a logic state of the read data. Other embodiments are described and claimed.

Abstract: A semiconductor device is provided. The semiconductor device comprises a first active region, a second active region and a third active region, a first poly region, a second poly region, a third poly region, a first doped region and a second doped region. The first active region, the second active region and the third active region are separated and parallel with each other. The first poly region is arranged over the first and second active regions. The second poly region is arranged over the first and second active regions. The third poly region is arranged over the second and third active regions. The first doped region is in the second active region and between the first poly region and the second poly region. The second doped region is in the second active region and between the second poly region and the third poly region.