Complementary Patents (Class 365/156)
  • Patent number: 11910723
    Abstract: A memory device includes a memory cell array having a plurality of memory cells arranged in rows and columns, each row of memory cells being associated with a word line, each column of memory cells being associated with a bit line and a source line. Each memory cell includes: a storage device coupled to the bit line, the storage device being selectable between a first resistance state and a second resistance state in response to a bit line signal at the bit line; and a selection device connected in series with the storage device and coupled to the source line, the selection device being configured to provide access to the storage device in response to a word line signal at the word line. The memory device further includes a word-line driver and a bit-line driver. A first number of the source lines are connected in parallel.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Ku-Feng Lin
  • Patent number: 11910586
    Abstract: An IC structure comprises a substrate, a first SRAM cell, and a second SRAM cell. The first SRAM cell is formed over the substrate and comprises a first N-type transistor. The second SRAM cell is formed over the substrate and comprises a second N-type transistor. A gate structure of first N-type transistor of the first SRAM cell has a different work function metal composition than a gate structure of the second N-type transistor of the second SRAM cell.
    Type: Grant
    Filed: October 28, 2022
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 11902455
    Abstract: Disclosed is a physical unclonable function generator circuit and method.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Lien Linus Lu, Cheng-En Lee
  • Patent number: 11776633
    Abstract: Methods of operating a memory, and apparatus configured to perform similar methods, include determining a voltage level of a stepped sense operation that activates a memory cell of the memory during a programming operation for the memory cell, and determining a voltage level of a ramped sense operation that activates the memory cell during a read operation for the memory cell.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: October 3, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Ugo Russo, Violante Moschiano, William C. Filipiak, Andrea D'Alessandro
  • Patent number: 11671101
    Abstract: Disclosed herein is a memory-type camouflaged logic gate using transistors having different threshold voltages. The camouflaged logic gate may include two or more candidate logic gates, memory, the output signal of which is adjusted based on two or more transistors having different threshold voltages, and a multiplexer for selectively outputting the output of one of the two or more candidate logic gates depending on the output signal of the memory.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: June 6, 2023
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jae-Mun Oh, Byung-Do Yang, Jung-Ho Kim
  • Patent number: 11657870
    Abstract: A memory cell includes a write port and a read port. The write port includes two cross-coupled inverters that form a storage unit. The cross-coupled inverters are connected between a first power source signal line and a second power source signal line. The write port also includes a first local interconnect line in an interconnect layer that is connected to the second power source signal line. The read port includes a transistor that is connected to the storage unit in the write port and to the second power source signal line, and a second local interconnect line in the interconnect layer that is connected to the second power source signal line. The second local interconnect line in the read port is separate from the first local interconnect line in the write port.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: May 23, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hidehiro Fujiwara, Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen, Wei-Chang Zhao
  • Patent number: 11599600
    Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, and a third semiconductor element. A first terminal of the first semiconductor element is coupled to a first computing bit-line. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to the memory cell circuit. A first terminal of the second semiconductor element is coupled to a second terminal of the first semiconductor element. A first terminal of the third semiconductor element is coupled to a second terminal of the second semiconductor element. A second terminal of the third semiconductor element is coupled to a second computing bit-line. A control terminal of the third semiconductor element receives a bias voltage.
    Type: Grant
    Filed: September 6, 2020
    Date of Patent: March 7, 2023
    Assignee: Industrial Technology Research Institute
    Inventors: Chih-Sheng Lin, Jian-Wei Su, Tuo-Hung Hou, Sih-Han Li, Fu-Cheng Tsai, Yu-Hui Lin
  • Patent number: 11600317
    Abstract: A memory device is provided. The memory device includes a bit cell having a first invertor connected between a first node and a second node and a second invertor connected between the first node and the second node. The first invertor and the second invertor are cross coupled at a first data node and a second data node. The memory device further includes a pull down circuit connected to the second node. The pull down circuit is operative to pull down a voltage of the second node below a ground voltage in response to an enable signal.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: March 7, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shigeki Shimomura, Jonathan Tsung-Yung Chang
  • Patent number: 11568924
    Abstract: An integrated circuit memory device includes a static random access memory (SRAM) cell, and a charge storing circuit electrically coupled to the SRAM cell. A switching controller is provided, which is electrically coupled to the charge storing circuit. The switching controller and the charge storing circuit are collectively configured to save power by recycling charge associated with a bit line electrically coupled to the SRAM cell by: (i) transferring charge from the bit line to a charge storage node electrically coupled to source terminals of a pair of NMOS pull-down transistors within the SRAM cell upon commencement of a SRAM cell write operation, and then (ii) returning at least a portion of the charge to the bit line upon completion of the SRAM cell write operation.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: January 31, 2023
    Inventors: Taemin Choi, Seongook Jung, Keonhee Cho
  • Patent number: 11502088
    Abstract: A layout pattern of static random access memory at least includes a substrate, a plurality of fin structures on the substrate, a plurality of gate structures on the substrate and spanning the fin structures to form a plurality of transistors distributed on the substrate, the plurality of transistors include, a first pull-up transistor PU1, a first pull-down transistor PD1, a second pull-up transistor PU2, a second pull-down transistor PD2, a first pass gate transistor PG1, a second pass gate transistor PG2, a first read transistor RPD and a second read transistor RPG, and an additional fin structure, the additional fin structure is located between the fin structure of the first pass gate transistor PG1 and the fin structure of the second read transistor RPG.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: November 15, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Chi Lee, Shu-Wei Yeh, Chang-Hung Chen
  • Patent number: 11462263
    Abstract: A memory is provided that is configured to practice both a normal read operation and also a burst mode read operation. A column multiplexer selects from a plurality of columns using a pair of pass transistor for each column. The column multiplexer drives a true input node and a complement input node of an output data latch.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: October 4, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Changho Jung, Arun Babu Pallerla, Chulmin Jung
  • Patent number: 11443090
    Abstract: An optimization device includes: a memory; and a processor configured to: calculate, as bit operations, when any bit in a bit string representing a state of an Ising model is inverted, an energy change value of the Ising model based on a coefficient indicating magnitude of an interaction between an own bit and the inverted bit in the bit string; output a first signal indicating inversion availability of the own bit according to the energy change value and a second signal indicating the energy change value; select the bit to be inverted in the bit string and the energy change value corresponding to the bit based on the first signal and the second signal; output a fourth signal indicating the selected energy change value; and calculate energy of the Ising model based on the energy change value indicated by the fourth signal.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: September 13, 2022
    Assignee: FUJITSU LIMITED
    Inventors: Takeshi Mishina, Satoshi Matsuura
  • Patent number: 11430507
    Abstract: A memory array includes a first memory cell and a second memory cell, each including a data storage element having a first terminal and a second terminal, a first access transistor coupled to the first terminal of the data storage element, and a second access transistor coupled to the second terminal of the data storage element. The memory device also includes a first bit line coupled to the first access transistor of the first memory cell, a second bit line coupled to the second access transistor of the first memory cell, a third bit line coupled to the first access transistor of the second memory cell and a fourth bit line coupled to the second access transistor of the second memory cell.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: August 30, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Shih-Lien Linus Lu
  • Patent number: 11398275
    Abstract: A circuit includes a memory array, a write circuit configured to store data in memory cells of the memory array, a read circuit configured to retrieve the stored data from the memory cells of the memory array, and a computation circuit configured to perform one or more logic operations on the retrieved stored data. The memory array is positioned between the write circuit and the read circuit.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: July 26, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Huei Chen, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Hidehiro Fujiwara
  • Patent number: 11392192
    Abstract: A semiconductor device capable of reducing electric power consumption while suppressing deterioration in reliability is provided. The semiconductor device includes a flash memory, a SRAM formed on a SOI substrate, oscillation circuits generating a signal of a first frequency and a signal of a second frequency lower than the first frequency, and a processor operating in synchronization with a system clock. The processor performs steps of turning on a power supply of the flash memory, lowering a threshold voltage of the SRAM, transferring a program from the flash memory to the SRAM by using the signal of the first frequency as the system clock, turning off the power supply of the flash memory, heightening the threshold voltage of the SRAM, and executing the program stored in the SRAM by using the signal of the second frequency as the system clock.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: July 19, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Kazuya Uejima
  • Patent number: 11355488
    Abstract: A method of generating a layout diagram of an IC cell includes defining a boundary recess in a boundary of the cell by extending a first portion of the boundary along a first gate track, extending a second portion of the boundary from the first gate track to a second gate track, the second portion being contiguous with the first portion, and extending a third portion of the boundary from the first gate track to the second gate track, the third portion being contiguous with the first portion. An active region is positioned in the cell by extending the active region across a third gate track, wherein the first gate track is between the second gate track and the third gate track. The layout diagram is stored on a non-transitory computer-readable medium.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: June 7, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Ying Chen, Lee-Chung Lu, Li-Chun Tien, Ta-Pen Guo
  • Patent number: 11315629
    Abstract: The present application provides a dual-port SRAM cell and a layout structure thereof, comprises a first and a second NMOS transistors, a first and a second PMOS transistors; the gates of the first and second NMOS transistors and the drains of the first and second PMOS transistors are connected to a word line; the source of the first NMOS transistor is connected to a first bit line; the source of the first PMOS transistor is connected to a second bit line; the source of the second NMOS transistor is connected to a third bit line; the source of the second PMOS transistor is connected to a fourth bit line; the drain of the first NMOS transistor and the gate of the first PMOS transistor are connected to a common input node of a latch.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: April 26, 2022
    Assignee: SHANGHAI HUALI INTEGRATED CIRCUIT CORPORATION
    Inventor: Xiaojun Zhou
  • Patent number: 11170840
    Abstract: An SRAM write assist device includes: a power circuit supplying power to an SRAM-cells column and then stopping supplying power to make the voltage of a power-receiving terminal of the SRAM-cells column floating; a write driving circuit coupling a bit line of the SRAM-cells column with a ground terminal according to a data signal in a write drive phase; a charge sharing circuit coupling the power-receiving terminal with the first terminal of a capacitor to lower this terminal's floating voltage by charge sharing in a charge sharing phase; a charging circuit including a switch turned on to charge the capacitor with an operating voltage in a charge phase; and a negative-voltage coupling circuit including the capacitor whose first and second terminals are coupled to a ground terminal and the bit line respectively to lower the voltage of the bit line by charge sharing in a negative-voltage generation phase.
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: November 9, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Hung-Yu Lee
  • Patent number: 11145335
    Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storage systems selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storage systems selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to minimize power consumption. Moreover, the configurable memory storage systems selectively provide the maximum operational voltage signal to bulk (B) terminals of some of their transistors to prevent latch-up of these transistors.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: October 12, 2021
    Inventors: Sungchieh Lin, Kuoyuan (Peter) Hsu
  • Patent number: 11074966
    Abstract: A memory cell includes a write port and a read port. The write port includes two cross-coupled inverters that form a storage unit. The cross-coupled inverters are connected between a first power source signal line and a second power source signal line. The write port also includes a first local interconnect line in an interconnect layer that is connected to the second power source signal line. The read port includes a transistor that is connected to the storage unit in the write port and to the second power source signal line, and a second local interconnect line in the interconnect layer that is connected to the second power source signal line. The second local interconnect line in the read port is separate from the first local interconnect line in the write port.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: July 27, 2021
    Inventors: Hidehiro Fujiwara, Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen, Wei-Chang Zhao
  • Patent number: 11038494
    Abstract: A semiconductor circuit of the present disclosure includes: a volatile first storage section; a volatile second storage section that stores data stored in the first storage section on the basis of a first control signal; a non-volatile third storage section that stores data according to data stored in the second storage section on the basis of a second control signal, and causes the first storage section to store data stored in itself on the basis of a third control signal; and a control section that generates the first control signal and the third control signal, and compares the data stored in the first storage section and the data stored in the second storage section with each other to generate the second control signal on the basis of a result of the comparison.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: June 15, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Keizo Hiraga
  • Patent number: 11031336
    Abstract: An SRAM device and method of forming include pass gate (PG), pull-down (PD), and pull-up (PU) transistors. A first gate line of the PG and a second gate line of the PD and the PU extend in a first direction. A common source/drain of the PG, PD, and PU transistors interposes the first and second gate lines and another source/drain of the PG transistor. A first contact extends from the common source/drain and a second contact extends from the another source/drain. A third contact is disposed above the second contact with a first width in the first direction and a first length in a second direction, first length being greater than the first width.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: June 8, 2021
    Inventors: Chao-Yuan Chang, Jui-Lin Chen, Kian-Long Lim, Feng-Ming Chang
  • Patent number: 10998022
    Abstract: In some examples, an inactive word line voltage control (IWVC) circuit may be configured to provide a respective subword driver associated with a memory bank of a plurality of memory banks a non-active potential from a default off-state word line voltage (VNWL) to a reduced voltage VNWL lower than the default VNWL following a time duration after activating the memory bank. The IWVC circuit may also be configured to provide the respective subword driver with the default VNWL responsive to precharging the memory bank. The IWVC circuit may include a multiplexer coupled to the subword driver and configured to provide the default VNWL or the reduced voltage VNWL to the respective subword driver responsive to a VNWL control signal. The IWVC circuit may also include a time control circuit configured to provide the VNWL control signal responsive to a clock signal and a time control signal.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: May 4, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Boon Hor Lam, Shawn M. Hilde, Karl L. Major, Travis Marley
  • Patent number: 10943648
    Abstract: An ultra low VDD memory cell has a ratioless write port. In some embodiments, the VDD operation level can be as low as the threshold voltage of NMOS and PMOS transistors of the cell.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: March 9, 2021
    Assignee: GSI Technology, Inc.
    Inventors: Lee-Lean Shu, Patrick Chuang, Chao-Hung Chang
  • Patent number: 10930340
    Abstract: A semiconductor storage circuit has: a plurality of first memory cells and a first precharge transistor connected to a first local read bit line; and a plurality of second memory cells and a second precharge transistor connected to a second local read bit line. A signal responsive to signals output to the first and second local read bit lines is output to a global read bit line via a gate circuit and an output circuit. A first transistor having a gate connected to the output of the gate circuit is provided between the first and second local read bit lines.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: February 23, 2021
    Assignee: SOCIONEXT INC.
    Inventor: Yoshinobu Yamagami
  • Patent number: 10910042
    Abstract: The present disclosure discloses a circuit structure. The circuit structure comprises: a redundant memory device for simulating a read operation of the memory cell in response to the driving of the test word line voltage; a decision device connected to the internal node of the redundant memory device for determining whether the test word line voltage causes the internal node of the redundant memory device to reverse during the read operation in response to the read operation. In response to the reversal, the redundant memory device simulates the read operation with the adjusted test word line voltage until the determination device determines that the internal node does not reverse during the read operation. The circuit structure also comprises: a statistics device for counting and outputting the number of reversals, which is used to characterize the critical word line voltage in conjunction with each adjustment of the test word line voltage.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: February 2, 2021
    Inventors: Wen Liu, Hongjin He
  • Patent number: 10910041
    Abstract: An SRAM cell with dynamic split ground (GND) and split wordline (WL) for extreme scaling is disclosed. The memory cell includes a first access transistor enabled by a first wordline to control access to cross coupled inverters by a first bitline. The memory cell further includes a second access transistor enabled by a second wordline to control access to the cross coupled inverters by a second bitline. The memory cell further includes a split ground line comprising a first ground line (GNDL) separated from a second ground line (GNDR). The GNDL is connected to a transistor of a first inverter of the cross coupled inverters and the GNDR is connected to a first transistor of a second inverter of the cross coupled inverters.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: February 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Robert C. Wong
  • Patent number: 10885947
    Abstract: A power gating system including: a first power line coupled to a first pad; a second power line coupled to a second pad; a third power line coupled to a plurality of logic gates in common; a first power gating switch coupled between the first and third power lines; and a second power gating switch coupled between the second and third power lines. When a double power mode is set, the first and second power gating switches may be turned on to couple the first and second power lines to the third power line at the same time.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: January 5, 2021
    Assignee: SK hynix Inc.
    Inventor: Woongrae Kim
  • Patent number: 10885972
    Abstract: A method for storing information in SRAM bit cell arrays provides for lowering voltage supplied to the SRAM bit cell arrays, with voltage lowering controlled by a connected voltage control circuit. Writing, reading, and correcting information storable in the SRAM bit cell arrays is accomplished using an error correcting code (ECC) block connected to at least some of the SRAM bit cell arrays. The ECC block is configurable to repair stored information.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: January 5, 2021
    Assignee: AMBIQ MICRO, INC.
    Inventors: Christophe J. Chevallier, Stephen James Sheafor
  • Patent number: 10879025
    Abstract: An electromechanical power switch device and methods thereof. At least some of the illustrative embodiments are devices including a semiconductor substrate, at least one integrated circuit device on a front surface of the semiconductor substrate, an insulating layer on the at least one integrated circuit device, and an electromechanical power switch on the insulating layer. By way of example, the electromechanical power switch may include a source and a drain, a body region disposed between the source and the drain, and a gate including a switching metal layer. In some embodiments, the body region includes a first body portion and a second body portion spaced a distance from the first body portion and defining a body discontinuity therebetween. Additionally, in various examples, the switching metal layer may be disposed over the body discontinuity.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: December 29, 2020
    Assignee: INOSO, LLC
    Inventors: Kiyoshi Mori, Ziep Tran, Giang Trung Dao, Michael Edward Ramon
  • Patent number: 10878852
    Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storage systems selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storage systems selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to minimize power consumption. Moreover, the configurable memory storage systems selectively provide the maximum operational voltage signal to bulk (B) terminals of some of their transistors to prevent latch-up of these transistors.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: December 29, 2020
    Inventors: Sungchieh Lin, Kuoyuan (Peter) Hsu
  • Patent number: 10878892
    Abstract: Various implementations described herein may refer to an integrated circuit using discharging circuitries for bit lines. In one implementation, an integrated circuit may include a memory array having memory cells, where the memory cells are arranged into columns and configured to be accessed using bit line pairs. The integrated circuit may also include discharging circuitries to selectively discharge the bit line pairs, where a respective discharging circuitry is coupled to a negative supply voltage node of a respective column of memory cells. The respective discharging circuitry may discharge a bit line pair of the respective column to a first voltage when the bit line pair is selected for a memory operation, and may discharge the bit line pair of the respective column to a second voltage when the bit line pair is not selected for a memory operation, where the second voltage is greater than the first voltage.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: December 29, 2020
    Assignee: Arm Limited
    Inventors: Lalit Gupta, Jitendra Dasani, Vivek Nautiyal, Shri Sagar Dwivedi, Fakhruddin Ali Bohra
  • Patent number: 10861859
    Abstract: A semiconductor structure includes a first transistor including a first gate structure over a first active region in a substrate, a second transistor including a second gate structure over a second active region in the substrate, and a butted contact electrically connecting the second active region of the second transistor to the first gate structure of the first transistor. The butted contact includes a first portion extending along a first direction and overlapping at least the second active region, and a second portion extending along a second direction different from the first direction and intersecting the first portion. The second portion extends over the first gate structure.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: You Che Chuang, Chih-Ming Lee, Hsin-Chi Chen, Hsun-Ying Huang
  • Patent number: 10840181
    Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: November 17, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Hsin Hu, Yu-Chiun Lin, Yi-Hsuan Chung, Chung-Peng Hsieh, Chung-Chieh Yang, Po-Nien Chen
  • Patent number: 10803928
    Abstract: A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mahmut Sinangil, Yen-Huei Chen, Yen-Ting Lin, Hung-Jen Liao, Jonathan Tsung-Yung Chang
  • Patent number: 10790010
    Abstract: In one embodiment, a graphics processor includes a register file having a plurality of storage segments to store information and output a plurality of segment outputs via a plurality of segmented bitlines to a static logic circuit to receive the plurality of segment outputs from the plurality of storage segments and to output read data based on the plurality of segment outputs. The register file may output the read data with a same amount of power without regard to a logic state of the read data. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: September 29, 2020
    Assignee: Intel Corporation
    Inventors: Bhushan M. Borole, Iqbal R. Rajwani, Anupama A. Thaploo, Sunil Nekkanti, Altug Koker, Abhisek R. Appu
  • Patent number: 10784276
    Abstract: A semiconductor device is provided. The semiconductor device comprises a first active region, a second active region and a third active region, a first poly region, a second poly region, a third poly region, a first doped region and a second doped region. The first active region, the second active region and the third active region are separated and parallel with each other. The first poly region is arranged over the first and second active regions. The second poly region is arranged over the first and second active regions. The third poly region is arranged over the second and third active regions. The first doped region is in the second active region and between the first poly region and the second poly region. The second doped region is in the second active region and between the second poly region and the third poly region.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: September 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hau-Yan Lu, Shih-Hsien Chen, Chun-Yao Ko, Felix Ying-Kit Tsui
  • Patent number: 10777259
    Abstract: Certain aspects of the present disclosure are directed to methods and apparatus for convolution computation. One example apparatus generally includes a static random-access memory (SRAM) having a plurality of memory cells. Each of the plurality of memory cells may include a flip-flop (FF) having an output node and a complementary output node; a first switch coupled between the output node and a bit line (BL) of the SRAM, the first switch having a control input coupled to a word line (WL) of the SRAM; and a second switch coupled between the complementary output node and a complementary bit line (BLB) of the SRAM, the second switch having another control input coupled to a complementary word line (WLB) of the SRAM.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: September 15, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Zhongze Wang, Xiaochun Zhu
  • Patent number: 10762951
    Abstract: An SRAM device includes a memory cell and a keeper circuit. The memory cell is formed in an active area and coupled to a first bit line and a second bit line. The keeper circuit is formed in the active area and configured to charge the second bit line when the first bit line is at a first voltage level and the second bit line is at a second voltage level or charge the first bit line when the second bit line is at the first voltage level and the first bit line is at the second voltage level, wherein the second voltage level is higher than the first voltage level.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: September 1, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Wei Tsai, Tsan-Tang Chen, Chung-Cheng Tsai, Yen-Hsueh Huang, Chang-Ting Lo, Chun-Yen Tseng, Yu-Tse Kuo
  • Patent number: 10755769
    Abstract: A carbon nanotube ternary SRAM cell with an improved stability and low standby power comprises a write bit line, a read bit line, a column select bit line, an inverted column select bit line, a write word line, an inverted write word line, a read word line, an inverted read word line, a first P-type CNFET, a second P-type CNFET, a third P-type CNFET, a fourth P-type CNFET, a fifth P-type CNFET, a sixth P-type CNFET, a seventh P-type CNFET, an eighth P-type CNFET, a ninth P-type CNFET, a first N-type CNFET, a second N-type CNFET, a third N-type CNFET, a fourth N-type CNFET, a fifth N-type CNFET, a sixth N-type CNFET, a seventh CNFET, an eighth N-type CNFET and a ninth N-type CNFET. The carbon nanotube ternary SRAM cell has the advantages of being lower in power consumption, capable of solving the half-select problem and the read-disturb problem and high in static noise margin.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: August 25, 2020
    Assignee: Wenzhou University
    Inventors: Gang Li, Pengjun Wang, Yuejun Zhang, Bo Chen
  • Patent number: 10691861
    Abstract: Disclosed herein is an apparatus that includes a first pair of signal lines and a second pair of signal lines. Each pair of signal lines comprises a first line and a second line that collectively signal any one of: a logical zero, a logical one, and nothing. A first cell occupies a first layer of the apparatus to receive the first line of the first pair of signal lines and the first line of the second pair of signal lines; and a second cell occupies a second layer of the apparatus to receive the second line of the first pair of signal lines and the second line of the second pair of signal lines. The first cell is a dual of the second cell and at least partially overlaps the second cell.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: June 23, 2020
    Assignee: Arm Limited
    Inventors: Adrian Reece Wheeldon, John Philip Biggs, Jedrzej Kufel
  • Patent number: 10629257
    Abstract: A method for storing information in SRAM bit cell arrays provides for lowering voltage supplied to the SRAM bit cell arrays, with voltage lowering controlled by a connected voltage control circuit. Writing, reading, and correcting information storable in the SRAM bit cell arrays is accomplished using an error correcting code (ECC) block connected to at least some of the SRAM bit cell arrays. The ECC block is configurable to repair stored information.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: April 21, 2020
    Assignee: Ambiq Micro, Inc.
    Inventors: Christophe J. Chevallier, Stephen James Sheafor
  • Patent number: 10600600
    Abstract: An electromechanical power switch device and methods thereof. At least some of the illustrative embodiments are devices including a semiconductor substrate, at least one integrated circuit device on a front surface of the semiconductor substrate, an insulating layer on the at least one integrated circuit device, and an electromechanical power switch on the insulating layer. By way of example, the electromechanical power switch may include a source and a drain, a body region disposed between the source and the drain, and a gate including a switching metal layer. In some embodiments, the body region includes a first body portion and a second body portion spaced a distance from the first body portion and defining a body discontinuity therebetween. Additionally, in various examples, the switching metal layer may be disposed over the body discontinuity.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: March 24, 2020
    Assignee: INOSO, LLC
    Inventors: Kiyoshi Mori, Ziep Tran, Giang Trung Dao, Michael Edward Ramon
  • Patent number: 10600474
    Abstract: A circuit includes a core having a memory array. The memory array includes memory cells and bitlines, and is arranged in columns. The core includes a metallization layer having connections to the memory array, which is devoid of memory cells. Digit lines are connected to the bitlines of a column of the memory array. A write driver is connected to the digit lines. A write assist circuit is connected to the write driver. The write assist circuit maintains a voltage on the digit lines prior to write operations and provides a boost voltage to the digit lines during write operations. A wire bridge located in the metallization layer of the core connects the write assist circuit to the write driver.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: March 24, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sreenivasula Reddy Dhani Reddy, Sreejith Chidambaran, Binu Jose, Venkatraghavan Bringivijayaraghavan
  • Patent number: 10593395
    Abstract: There is provided a multiple data rate memory configured to implement first and second memory accesses within a single cycle of an external clock signal. The memory comprises a plurality of memory cell groups, each memory cell group comprising a plurality of memory cells that are each operatively connected to at least one local bit line, the at least one local bit line of each memory cell group being connected to a local-to-global interface circuit. The local-to-global interface circuit is configured to control the state of at least one first global bit line in dependence upon the state of the at least one local bit line during the first memory access and to control the state of at least one second global bitline in dependence upon the state of the at least one local bit line during the second memory access.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: March 17, 2020
    Assignee: SURECORE LIMITED
    Inventors: Stefan Cosemans, Bram Rooseleer
  • Patent number: 10553588
    Abstract: Memory cells are formed with vertical thyristors to create a volatile memory array. Power consumption in such arrays is reduced or controlled with various techniques including encoding the data stored in the arrays.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: February 4, 2020
    Assignee: TC Lab, Inc.
    Inventors: Harry Luan, Bruce L. Bateman, Valery Axelrad, Charlie Cheng
  • Patent number: 10535400
    Abstract: Systems, apparatuses, and methods for efficiently driving level shifted write data are described. In various embodiments, a level-shifting write driver combines a write data bit and a write mask bit that each use a first supply voltage to indicate a logic high level. During a write operation, the driver generates complementary values on two output nodes based on the write data bit. The output nodes use a second supply voltage greater than the first supply voltage. Before a write operation, the driver precharges each of the two output nodes to the second supply voltage. When the write clock enables a write operation and the write mask bit disables the write operation, the level-shifting write driver puts the two output nodes in a tri-state.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: January 14, 2020
    Assignee: Apple Inc.
    Inventors: William R. Weier, Steven Frederick Schicht
  • Patent number: 10535665
    Abstract: Some embodiments include an integrated assembly having a first transistor adjacent to a second transistor. The first transistor has a first conductive gate material over a first insulative region, and the second transistor has a second conductive gate material over a second insulative region. A continuous high-k dielectric film extends across both of the first and second insulative regions. In some embodiments, the transistors may be incorporated into a sense amplifier.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: January 14, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Takuya Imamoto, Takeshi Nagai, Yoichi Fukushima
  • Patent number: 10522217
    Abstract: Disclosed is a chip with a memory array and at least one positive voltage boost circuit, which provides positive voltage boost pulses to the sources of pull-up transistors in the memory cells of the array during write operations to store data values in those memory cells and, more specifically, provides positive voltage boost pulses substantially concurrently with wordline deactivation during the write operations to ensure that the data is stored. Application of such pulses to different columns can be performed using different positive voltage boost circuits to minimize power consumption. Also disclosed are a memory array operating method that employs a positive voltage boost circuit and a chip manufacturing method, wherein post-manufacture testing is performed to identify chips having memory arrays that would benefit from positive voltage boost pulses and positive voltage boost circuits are attached to those identified chips and operably connected to the memory arrays.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: December 31, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Venkatraghavan Bringivijayaraghavan, Eswararao Potladhurthi, George M. Braceras
  • Patent number: 10497432
    Abstract: A memory array includes a first memory cell and a second memory cell, each including a data storage element, a first access transistor coupled to the data storage element, and a second access transistor coupled to the data storage element. The memory array further includes two word lines configured to selectively enable access to the data storage element of the first memory cell through the two access transistors of the first memory cell respectively, two bit lines coupled to the two access transistors of the first memory cell respectively, two another word lines configured to selectively enable access to the data storage element of the second memory cell through the two access transistors of the second memory cell respectively, a third bit line coupled to the first access transistor of the second memory cell, and a first sense amplifier coupled to the first bit line and the third bit line.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: December 3, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Shih-Lien Linus Lu