Complementary Patents (Class 365/156)
  • Patent number: 10998022
    Abstract: In some examples, an inactive word line voltage control (IWVC) circuit may be configured to provide a respective subword driver associated with a memory bank of a plurality of memory banks a non-active potential from a default off-state word line voltage (VNWL) to a reduced voltage VNWL lower than the default VNWL following a time duration after activating the memory bank. The IWVC circuit may also be configured to provide the respective subword driver with the default VNWL responsive to precharging the memory bank. The IWVC circuit may include a multiplexer coupled to the subword driver and configured to provide the default VNWL or the reduced voltage VNWL to the respective subword driver responsive to a VNWL control signal. The IWVC circuit may also include a time control circuit configured to provide the VNWL control signal responsive to a clock signal and a time control signal.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: May 4, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Boon Hor Lam, Shawn M. Hilde, Karl L. Major, Travis Marley
  • Patent number: 10943648
    Abstract: An ultra low VDD memory cell has a ratioless write port. In some embodiments, the VDD operation level can be as low as the threshold voltage of NMOS and PMOS transistors of the cell.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: March 9, 2021
    Assignee: GSI Technology, Inc.
    Inventors: Lee-Lean Shu, Patrick Chuang, Chao-Hung Chang
  • Patent number: 10930340
    Abstract: A semiconductor storage circuit has: a plurality of first memory cells and a first precharge transistor connected to a first local read bit line; and a plurality of second memory cells and a second precharge transistor connected to a second local read bit line. A signal responsive to signals output to the first and second local read bit lines is output to a global read bit line via a gate circuit and an output circuit. A first transistor having a gate connected to the output of the gate circuit is provided between the first and second local read bit lines.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: February 23, 2021
    Assignee: SOCIONEXT INC.
    Inventor: Yoshinobu Yamagami
  • Patent number: 10910042
    Abstract: The present disclosure discloses a circuit structure. The circuit structure comprises: a redundant memory device for simulating a read operation of the memory cell in response to the driving of the test word line voltage; a decision device connected to the internal node of the redundant memory device for determining whether the test word line voltage causes the internal node of the redundant memory device to reverse during the read operation in response to the read operation. In response to the reversal, the redundant memory device simulates the read operation with the adjusted test word line voltage until the determination device determines that the internal node does not reverse during the read operation. The circuit structure also comprises: a statistics device for counting and outputting the number of reversals, which is used to characterize the critical word line voltage in conjunction with each adjustment of the test word line voltage.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: February 2, 2021
    Inventors: Wen Liu, Hongjin He
  • Patent number: 10910041
    Abstract: An SRAM cell with dynamic split ground (GND) and split wordline (WL) for extreme scaling is disclosed. The memory cell includes a first access transistor enabled by a first wordline to control access to cross coupled inverters by a first bitline. The memory cell further includes a second access transistor enabled by a second wordline to control access to the cross coupled inverters by a second bitline. The memory cell further includes a split ground line comprising a first ground line (GNDL) separated from a second ground line (GNDR). The GNDL is connected to a transistor of a first inverter of the cross coupled inverters and the GNDR is connected to a first transistor of a second inverter of the cross coupled inverters.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: February 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Robert C. Wong
  • Patent number: 10885947
    Abstract: A power gating system including: a first power line coupled to a first pad; a second power line coupled to a second pad; a third power line coupled to a plurality of logic gates in common; a first power gating switch coupled between the first and third power lines; and a second power gating switch coupled between the second and third power lines. When a double power mode is set, the first and second power gating switches may be turned on to couple the first and second power lines to the third power line at the same time.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: January 5, 2021
    Assignee: SK hynix Inc.
    Inventor: Woongrae Kim
  • Patent number: 10885972
    Abstract: A method for storing information in SRAM bit cell arrays provides for lowering voltage supplied to the SRAM bit cell arrays, with voltage lowering controlled by a connected voltage control circuit. Writing, reading, and correcting information storable in the SRAM bit cell arrays is accomplished using an error correcting code (ECC) block connected to at least some of the SRAM bit cell arrays. The ECC block is configurable to repair stored information.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: January 5, 2021
    Assignee: AMBIQ MICRO, INC.
    Inventors: Christophe J. Chevallier, Stephen James Sheafor
  • Patent number: 10879025
    Abstract: An electromechanical power switch device and methods thereof. At least some of the illustrative embodiments are devices including a semiconductor substrate, at least one integrated circuit device on a front surface of the semiconductor substrate, an insulating layer on the at least one integrated circuit device, and an electromechanical power switch on the insulating layer. By way of example, the electromechanical power switch may include a source and a drain, a body region disposed between the source and the drain, and a gate including a switching metal layer. In some embodiments, the body region includes a first body portion and a second body portion spaced a distance from the first body portion and defining a body discontinuity therebetween. Additionally, in various examples, the switching metal layer may be disposed over the body discontinuity.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: December 29, 2020
    Assignee: INOSO, LLC
    Inventors: Kiyoshi Mori, Ziep Tran, Giang Trung Dao, Michael Edward Ramon
  • Patent number: 10878852
    Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storage systems selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storage systems selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to minimize power consumption. Moreover, the configurable memory storage systems selectively provide the maximum operational voltage signal to bulk (B) terminals of some of their transistors to prevent latch-up of these transistors.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: December 29, 2020
    Inventors: Sungchieh Lin, Kuoyuan (Peter) Hsu
  • Patent number: 10878892
    Abstract: Various implementations described herein may refer to an integrated circuit using discharging circuitries for bit lines. In one implementation, an integrated circuit may include a memory array having memory cells, where the memory cells are arranged into columns and configured to be accessed using bit line pairs. The integrated circuit may also include discharging circuitries to selectively discharge the bit line pairs, where a respective discharging circuitry is coupled to a negative supply voltage node of a respective column of memory cells. The respective discharging circuitry may discharge a bit line pair of the respective column to a first voltage when the bit line pair is selected for a memory operation, and may discharge the bit line pair of the respective column to a second voltage when the bit line pair is not selected for a memory operation, where the second voltage is greater than the first voltage.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: December 29, 2020
    Assignee: Arm Limited
    Inventors: Lalit Gupta, Jitendra Dasani, Vivek Nautiyal, Shri Sagar Dwivedi, Fakhruddin Ali Bohra
  • Patent number: 10861859
    Abstract: A semiconductor structure includes a first transistor including a first gate structure over a first active region in a substrate, a second transistor including a second gate structure over a second active region in the substrate, and a butted contact electrically connecting the second active region of the second transistor to the first gate structure of the first transistor. The butted contact includes a first portion extending along a first direction and overlapping at least the second active region, and a second portion extending along a second direction different from the first direction and intersecting the first portion. The second portion extends over the first gate structure.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: You Che Chuang, Chih-Ming Lee, Hsin-Chi Chen, Hsun-Ying Huang
  • Patent number: 10840181
    Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: November 17, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Hsin Hu, Yu-Chiun Lin, Yi-Hsuan Chung, Chung-Peng Hsieh, Chung-Chieh Yang, Po-Nien Chen
  • Patent number: 10803928
    Abstract: A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mahmut Sinangil, Yen-Huei Chen, Yen-Ting Lin, Hung-Jen Liao, Jonathan Tsung-Yung Chang
  • Patent number: 10790010
    Abstract: In one embodiment, a graphics processor includes a register file having a plurality of storage segments to store information and output a plurality of segment outputs via a plurality of segmented bitlines to a static logic circuit to receive the plurality of segment outputs from the plurality of storage segments and to output read data based on the plurality of segment outputs. The register file may output the read data with a same amount of power without regard to a logic state of the read data. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: September 29, 2020
    Assignee: Intel Corporation
    Inventors: Bhushan M. Borole, Iqbal R. Rajwani, Anupama A. Thaploo, Sunil Nekkanti, Altug Koker, Abhisek R. Appu
  • Patent number: 10784276
    Abstract: A semiconductor device is provided. The semiconductor device comprises a first active region, a second active region and a third active region, a first poly region, a second poly region, a third poly region, a first doped region and a second doped region. The first active region, the second active region and the third active region are separated and parallel with each other. The first poly region is arranged over the first and second active regions. The second poly region is arranged over the first and second active regions. The third poly region is arranged over the second and third active regions. The first doped region is in the second active region and between the first poly region and the second poly region. The second doped region is in the second active region and between the second poly region and the third poly region.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: September 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hau-Yan Lu, Shih-Hsien Chen, Chun-Yao Ko, Felix Ying-Kit Tsui
  • Patent number: 10777259
    Abstract: Certain aspects of the present disclosure are directed to methods and apparatus for convolution computation. One example apparatus generally includes a static random-access memory (SRAM) having a plurality of memory cells. Each of the plurality of memory cells may include a flip-flop (FF) having an output node and a complementary output node; a first switch coupled between the output node and a bit line (BL) of the SRAM, the first switch having a control input coupled to a word line (WL) of the SRAM; and a second switch coupled between the complementary output node and a complementary bit line (BLB) of the SRAM, the second switch having another control input coupled to a complementary word line (WLB) of the SRAM.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: September 15, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Zhongze Wang, Xiaochun Zhu
  • Patent number: 10762951
    Abstract: An SRAM device includes a memory cell and a keeper circuit. The memory cell is formed in an active area and coupled to a first bit line and a second bit line. The keeper circuit is formed in the active area and configured to charge the second bit line when the first bit line is at a first voltage level and the second bit line is at a second voltage level or charge the first bit line when the second bit line is at the first voltage level and the first bit line is at the second voltage level, wherein the second voltage level is higher than the first voltage level.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: September 1, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Wei Tsai, Tsan-Tang Chen, Chung-Cheng Tsai, Yen-Hsueh Huang, Chang-Ting Lo, Chun-Yen Tseng, Yu-Tse Kuo
  • Patent number: 10755769
    Abstract: A carbon nanotube ternary SRAM cell with an improved stability and low standby power comprises a write bit line, a read bit line, a column select bit line, an inverted column select bit line, a write word line, an inverted write word line, a read word line, an inverted read word line, a first P-type CNFET, a second P-type CNFET, a third P-type CNFET, a fourth P-type CNFET, a fifth P-type CNFET, a sixth P-type CNFET, a seventh P-type CNFET, an eighth P-type CNFET, a ninth P-type CNFET, a first N-type CNFET, a second N-type CNFET, a third N-type CNFET, a fourth N-type CNFET, a fifth N-type CNFET, a sixth N-type CNFET, a seventh CNFET, an eighth N-type CNFET and a ninth N-type CNFET. The carbon nanotube ternary SRAM cell has the advantages of being lower in power consumption, capable of solving the half-select problem and the read-disturb problem and high in static noise margin.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: August 25, 2020
    Assignee: Wenzhou University
    Inventors: Gang Li, Pengjun Wang, Yuejun Zhang, Bo Chen
  • Patent number: 10691861
    Abstract: Disclosed herein is an apparatus that includes a first pair of signal lines and a second pair of signal lines. Each pair of signal lines comprises a first line and a second line that collectively signal any one of: a logical zero, a logical one, and nothing. A first cell occupies a first layer of the apparatus to receive the first line of the first pair of signal lines and the first line of the second pair of signal lines; and a second cell occupies a second layer of the apparatus to receive the second line of the first pair of signal lines and the second line of the second pair of signal lines. The first cell is a dual of the second cell and at least partially overlaps the second cell.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: June 23, 2020
    Assignee: Arm Limited
    Inventors: Adrian Reece Wheeldon, John Philip Biggs, Jedrzej Kufel
  • Patent number: 10629257
    Abstract: A method for storing information in SRAM bit cell arrays provides for lowering voltage supplied to the SRAM bit cell arrays, with voltage lowering controlled by a connected voltage control circuit. Writing, reading, and correcting information storable in the SRAM bit cell arrays is accomplished using an error correcting code (ECC) block connected to at least some of the SRAM bit cell arrays. The ECC block is configurable to repair stored information.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: April 21, 2020
    Assignee: Ambiq Micro, Inc.
    Inventors: Christophe J. Chevallier, Stephen James Sheafor
  • Patent number: 10600600
    Abstract: An electromechanical power switch device and methods thereof. At least some of the illustrative embodiments are devices including a semiconductor substrate, at least one integrated circuit device on a front surface of the semiconductor substrate, an insulating layer on the at least one integrated circuit device, and an electromechanical power switch on the insulating layer. By way of example, the electromechanical power switch may include a source and a drain, a body region disposed between the source and the drain, and a gate including a switching metal layer. In some embodiments, the body region includes a first body portion and a second body portion spaced a distance from the first body portion and defining a body discontinuity therebetween. Additionally, in various examples, the switching metal layer may be disposed over the body discontinuity.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: March 24, 2020
    Assignee: INOSO, LLC
    Inventors: Kiyoshi Mori, Ziep Tran, Giang Trung Dao, Michael Edward Ramon
  • Patent number: 10600474
    Abstract: A circuit includes a core having a memory array. The memory array includes memory cells and bitlines, and is arranged in columns. The core includes a metallization layer having connections to the memory array, which is devoid of memory cells. Digit lines are connected to the bitlines of a column of the memory array. A write driver is connected to the digit lines. A write assist circuit is connected to the write driver. The write assist circuit maintains a voltage on the digit lines prior to write operations and provides a boost voltage to the digit lines during write operations. A wire bridge located in the metallization layer of the core connects the write assist circuit to the write driver.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: March 24, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sreenivasula Reddy Dhani Reddy, Sreejith Chidambaran, Binu Jose, Venkatraghavan Bringivijayaraghavan
  • Patent number: 10593395
    Abstract: There is provided a multiple data rate memory configured to implement first and second memory accesses within a single cycle of an external clock signal. The memory comprises a plurality of memory cell groups, each memory cell group comprising a plurality of memory cells that are each operatively connected to at least one local bit line, the at least one local bit line of each memory cell group being connected to a local-to-global interface circuit. The local-to-global interface circuit is configured to control the state of at least one first global bit line in dependence upon the state of the at least one local bit line during the first memory access and to control the state of at least one second global bitline in dependence upon the state of the at least one local bit line during the second memory access.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: March 17, 2020
    Assignee: SURECORE LIMITED
    Inventors: Stefan Cosemans, Bram Rooseleer
  • Patent number: 10553588
    Abstract: Memory cells are formed with vertical thyristors to create a volatile memory array. Power consumption in such arrays is reduced or controlled with various techniques including encoding the data stored in the arrays.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: February 4, 2020
    Assignee: TC Lab, Inc.
    Inventors: Harry Luan, Bruce L. Bateman, Valery Axelrad, Charlie Cheng
  • Patent number: 10535400
    Abstract: Systems, apparatuses, and methods for efficiently driving level shifted write data are described. In various embodiments, a level-shifting write driver combines a write data bit and a write mask bit that each use a first supply voltage to indicate a logic high level. During a write operation, the driver generates complementary values on two output nodes based on the write data bit. The output nodes use a second supply voltage greater than the first supply voltage. Before a write operation, the driver precharges each of the two output nodes to the second supply voltage. When the write clock enables a write operation and the write mask bit disables the write operation, the level-shifting write driver puts the two output nodes in a tri-state.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: January 14, 2020
    Assignee: Apple Inc.
    Inventors: William R. Weier, Steven Frederick Schicht
  • Patent number: 10535665
    Abstract: Some embodiments include an integrated assembly having a first transistor adjacent to a second transistor. The first transistor has a first conductive gate material over a first insulative region, and the second transistor has a second conductive gate material over a second insulative region. A continuous high-k dielectric film extends across both of the first and second insulative regions. In some embodiments, the transistors may be incorporated into a sense amplifier.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: January 14, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Takuya Imamoto, Takeshi Nagai, Yoichi Fukushima
  • Patent number: 10522217
    Abstract: Disclosed is a chip with a memory array and at least one positive voltage boost circuit, which provides positive voltage boost pulses to the sources of pull-up transistors in the memory cells of the array during write operations to store data values in those memory cells and, more specifically, provides positive voltage boost pulses substantially concurrently with wordline deactivation during the write operations to ensure that the data is stored. Application of such pulses to different columns can be performed using different positive voltage boost circuits to minimize power consumption. Also disclosed are a memory array operating method that employs a positive voltage boost circuit and a chip manufacturing method, wherein post-manufacture testing is performed to identify chips having memory arrays that would benefit from positive voltage boost pulses and positive voltage boost circuits are attached to those identified chips and operably connected to the memory arrays.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: December 31, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Venkatraghavan Bringivijayaraghavan, Eswararao Potladhurthi, George M. Braceras
  • Patent number: 10497432
    Abstract: A memory array includes a first memory cell and a second memory cell, each including a data storage element, a first access transistor coupled to the data storage element, and a second access transistor coupled to the data storage element. The memory array further includes two word lines configured to selectively enable access to the data storage element of the first memory cell through the two access transistors of the first memory cell respectively, two bit lines coupled to the two access transistors of the first memory cell respectively, two another word lines configured to selectively enable access to the data storage element of the second memory cell through the two access transistors of the second memory cell respectively, a third bit line coupled to the first access transistor of the second memory cell, and a first sense amplifier coupled to the first bit line and the third bit line.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: December 3, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Shih-Lien Linus Lu
  • Patent number: 10490545
    Abstract: An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: November 26, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Okagaki, Koji Shibutani, Makoto Yabuuchi, Nobuhiro Tsuda
  • Patent number: 10483951
    Abstract: A circuit may include a ring oscillator circuit and monitoring circuitry. The ring oscillator circuit has a group of inverters in a loop, whereby the group of inverters includes first, second, and third output nodes. The monitoring circuitry may monitor for error events in a signal that has passed through the inverters from any one of the first, second, or third output nodes, and may generate first and second monitoring circuitry outputs. The circuit may further include an error correction circuit that produces an error correction output based on the first and second monitoring circuitry outputs. Accordingly, the monitoring circuitry may generate first and second updated monitoring circuitry outputs based on the error correction output. The first and second updated monitoring circuitry outputs may be logically combined using a logic circuit to reset the signal that has passed through the loop.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: November 19, 2019
    Assignee: Altera Corporation
    Inventors: Nelson Gaspard, Yanzhong Xu
  • Patent number: 10460794
    Abstract: SRAM arrays are provided. In each SRAM cell arranged in the same column of cell array, first pull-down transistor and first pass-gate transistor are formed in first P-type well region. First and second pull-up transistors are formed in N-type well region. Second pull-down transistor and second pass-gate transistor are formed in second P-type well region. Each well strap cell includes an N-well strap structure formed on the N-type well region and a P-well strap structure formed on the first or second P-type well region. In the same column of cell array, a first distance between an active region of the P-well strap structure and the N-type well region is greater than a second distance from an active region of the first pull-down transistor and the first pass-gate transistor or an active region of the second pull-down transistor and the second pass-gate transistor to the N-type well region.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: October 29, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 10381069
    Abstract: A circuit includes a core having a memory array. The memory array includes memory cells and bitlines, and is arranged in columns. The core includes a metallization layer having connections to the memory array, which is devoid of memory cells. Digit lines are connected to the bitlines of a column of the memory array. A write driver is connected to the digit lines. A write assist circuit is connected to the write driver. The write assist circuit maintains a voltage on the digit lines prior to write operations and provides a boost voltage to the digit lines during write operations. A wire bridge located in the metallization layer of the core connects the write assist circuit to the write driver.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: August 13, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sreenivasula Reddy Dhani Reddy, Sreejith Chidambaran, Binu Jose, Venkatraghavan Bringivijayaraghavan
  • Patent number: 10366989
    Abstract: A semiconductor device includes a first fin field effect transistor (FinFET) and a contact bar (source/drain (S/D) contact layer). The first FinFET includes a first fin structure extending in a first direction, a first gate structure extending in a second direction crossing the first direction, and a first S/D structure. The contact bar is disposed over the first S/D structure and extends in the second direction crossing the first S/D structure in plan view. The contact bar includes a first portion disposed over the first S/D structure and a second portion. The second portion overlaps no fin structure and no S/D structure. A width of the second portion in the first direction is smaller than a width of the first portion in the first direction in plan view.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: July 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hao Chang, Wen-Huei Guo, Yi-Shien Mor
  • Patent number: 10319429
    Abstract: A method for storing information in SRAM bit cell arrays provides for lowering voltage supplied to the SRAM bit cell arrays, with voltage lowering controlled by a connected voltage control circuit. Writing, reading, and correcting information storable in the SRAM bit cell arrays is accomplished using an error correcting code (ECC) block connected to at least some of the SRAM bit cell arrays. The ECC block is configurable to repair stored information.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: June 11, 2019
    Assignee: AMBIQ MICRO, INC.
    Inventors: Christophe J. Chevallier, Stephen James Sheafor
  • Patent number: 10283190
    Abstract: Transpose non-volatile (NV) memory (NVM) bit cells and related data arrays configured for both memory row and column, transpose access operations. A plurality of transpose NVM bit cells can be arranged in memory rows and columns in a transpose NVM data array. To facilitate a row read operation, the transpose NVM bit cell includes a first access transistor coupled to a word line. An activation voltage is applied to the word line to activate the first access transistor to read a memory state stored in the NVM cell circuit in a row read operation. To facilitate a column, transpose read operation, the transpose NVM bit cell includes a second access transistor coupled to a transpose word line. An activation voltage is applied to the transpose word line to activate the second access transistor to read the memory state stored in the NVM cell circuit in a column, transpose read operation.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: May 7, 2019
    Assignee: QUALCOMM Incorporated
    Inventor: Xia Li
  • Patent number: 10277441
    Abstract: Methods, systems, and devices for improving uniformity between levels of a multi-level signal are described. Techniques are provided herein to unify peak-to-peak voltage differences between the amplitudes of data transmitted using multi-level signaling. Such multi-level signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: April 30, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Timothy M. Hollis
  • Patent number: 10224403
    Abstract: A semiconductor device including a base region present within a fin semiconductor structure that is present atop a dielectric substrate. An epitaxial emitter region and epitaxial collector region are present on opposing sides and in direct contact with the fin semiconductor structure. An epitaxial extrinsic base region is present on a surface of the fin semiconductor substrate that is opposite the surface of the fin semiconductor structure that is in contact with the dielectric base.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: March 5, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Bahman Hekmatshoartabari, Alexander Reznicek, Jeng-Bang Yau
  • Patent number: 10204672
    Abstract: A magnetic memory device includes a memory cell array, a counter circuit and a control circuit. The memory cell array includes a memory cell including a magneto resistive element in which writing is performed by current in a first direction or current in a second direction which is an opposite direction to the first direction. The memory cell array includes a first word line and a first bit line, both connected with the memory cell. The counter circuit counts the number of writing times in the first direction while the counter circuit is in electrical connection with the magneto resistive element. The control circuit performs writing in the second direction in the memory cell when the number of consecutive writing times in the first direction reaches a threshold number of times while the control circuit is in connection with the memory cell array.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: February 12, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Shinya Kobayashi
  • Patent number: 10177760
    Abstract: A method to generate a circuit instance to include a plurality of pMOSFET instances, where each pMOSFET instance has a source terminal instance connected to one or more supply rail instances. The circuit instance includes impedance element instances, where each impedance element instance is connected to a source terminal instance and a drain terminal instance of a corresponding pMOSFET instance. Depending upon a set of requirements, one or more of the impedance element instances are in a high impedance state or a low impedance state.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: January 8, 2019
    Assignee: ARM Limited
    Inventors: Andy Wangkun Chen, Yew Keong Chong, Yicong Li, Hsin-Yu Chen, Sriram Thyagarajan
  • Patent number: 10153034
    Abstract: A static random access memory unit structure and layout structure includes two pull-up transistors, two pull-down transistors, two slot contact plugs, and two metal-zero interconnects. Each metal-zero interconnect is disposed on each slot contact plug and a gate of each pull-up transistor, in which, each slot contact plug crosses a drain of each pull-down transistor and a drain of each pull-up transistor and extends to cross an end of each metal-zero interconnect. A gap between the slot contact plugs is smaller than a gap between the metal-zero interconnects.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: December 11, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tan-Ya Yin, Ming-Jui Chen, Chia-Wei Huang, Yu-Cheng Tung, Chin-Sheng Yang
  • Patent number: 10141323
    Abstract: A semiconductor device is provided. The semiconductor device comprises a first active region, a second active region and a third active region, a first poly region, a second poly region, a third poly region, a first doped region and a second doped region. The first active region, the second active region and the third active region are separated and parallel with each other. The first poly region is arranged over the first and second active regions. The second poly region is arranged over the first and second active regions. The third poly region is arranged over the second and third active regions. The first doped region is in the second active region and between the first poly region and the second poly region. The second doped region is in the second active region and between the second poly region and the third poly region.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: November 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hau-Yan Lu, Shih-Hsien Chen, Chun-Yao Ko, Felix Ying-Kit Tsui
  • Patent number: 10038050
    Abstract: A method includes providing a semiconductor substrate having a plurality of linear semiconductor fin structures spaced apart from one another on a surface of the substrate; siliciding sidewalls of the semiconductor fin structures; removing an unsilicided central portion of each semiconductor fin structure leaving, for a given one of the semiconductor fin structures, a pair of silicide fin structures that are parallel to one another and spaced apart from one another by a distance about equal to a width of the removed unsilicided central portion of the semiconductor fin structure; and forming contacts to conductively connect together a plurality of the silicide fin structures to form a resistor. A resistance value of the resistor is related at least to a type of silicide, a number of contacted adjacent silicide fin structures and a length between two contacts.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: July 31, 2018
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Keith E. Fogel, Alexander Reznicek, Oscar van der Straten
  • Patent number: 10008257
    Abstract: Embodiments include systems and methods for improving column selection functionality of memory circuits. Embodiments operate in context of memory bitcells having additional series pass gates (e.g., junction sharing transistors) coupled with a column select signal to form an integrated column select port. Such a column select port can provide each bitcell with column select functionality in a manner that has improved area and power performance over some conventional (added NOR or other logic) approaches. However, the added column select port can still tend to add area, add column select load, and degrade writability (e.g., due to certain charge-sharing effects). Some embodiments are described herein for addressing the area and column select load by sharing certain intermediate nodes among multiple, adjacent bitcells. Other embodiments can include additional ground-connected transistors in a manner that improves writability (e.g., and read noise margin) of the bitcell.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: June 26, 2018
    Assignee: Oracle International Corporation
    Inventors: Jinho Kwack, Hoyeol Cho, Heechoul Park, Myung Gyoo Won, Peter Labrecque, Jungyong Lee
  • Patent number: 10008258
    Abstract: A circuit can be used, for example, with a multi-supply memory device. The circuit includes a first conductor and a second conductor. A first transistor has a current path coupled between the first conductor and the second conductor. A second transistor also has a current path coupled between the first conductor and the second conductor. A pulse generator circuit has an input coupled to a control terminal of the first transistor and an output coupled to a control terminal of the second transistor.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: June 26, 2018
    Assignee: STMicroelectronics International N.V.
    Inventors: Piyush Jain, Vivek Asthana, Naveen Batra
  • Patent number: 9997590
    Abstract: A method includes providing a semiconductor substrate having a plurality of linear semiconductor fin structures spaced apart from one another on a surface of the substrate; siliciding sidewalls of the semiconductor fin structures; removing an unsilicided central portion of each semiconductor fin structure leaving, for a given one of the semiconductor fin structures, a pair of silicide fin structures that are parallel to one another and spaced apart from one another by a distance about equal to a width of the removed unsilicided central portion of the semiconductor fin structure; and forming contacts to conductively connect together a plurality of the silicide fin structures to form a resistor. A resistance value of the resistor is related at least to a type of silicide, a number of contacted adjacent silicide fin structures and a length between two contacts.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: June 12, 2018
    Assignee: International B├╝siness Machines Corporation
    Inventors: Praneet Adusumilli, Keith E. Fogel, Alexander Reznicek, Oscar van der Straten
  • Patent number: 9990986
    Abstract: A static random access memory device includes a plurality of memory cells arranged in rows and columns, a write driver configured to apply a bit line voltage corresponding to write data to a bit line extending in a column direction of the plurality of memory cells in a write operation, and a sub power line configured to transmit a cell driving voltage to the plurality of memory cells in the write operation and to extend in a direction parallel to the bit line, and includes a first node and a second node. The cell driving voltage is applied to the first node of the sub power line and the first node of the sub power line is aligned with an output node of the write driver in a row direction of the plurality of memory cells.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: June 5, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ingyu Park, Inhak Lee, Chanho Lee, Jaeseung Choi
  • Patent number: 9973179
    Abstract: A method and device for input offset cancellation utilizing a latched comparator that is configurable as a linear amplifier capable of sampling and cancelling offset in the inputs to the latched comparator. The latched comparator is configured according to three control signals for operation in three operating intervals. During a first operating interval, the latched comparator is configured as a linear amplifier that samples the offset at the inputs to the latched comparator. Based on the sampled offset, the linear amplifier cancels the offset in the inputs to the latched comparator. During a second operating interval, the latched comparator reverts to operation as comparator and the inputs to the latch are reset. During a third interval, the latch resolves the inputs to the comparator and generates an output signal indicating.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: May 15, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Kannan Krishna
  • Patent number: 9940994
    Abstract: A circuit and method performs a write assist for a memory cell (e.g., a static random access memory cell (SRAM)). The method includes providing a lower supply voltage signal to a voltage supply node of the memory cell using a capacitor. The lower supply voltage signal is lower in voltage level than a supply voltage signal. The method further includes lowering a common signal provided to a write driver using the capacitor.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: April 10, 2018
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Yifei Zhang, Mark J. Winter
  • Patent number: 9928900
    Abstract: A semiconductor device having static memory cells is designed to reduce leakage current and power consumption. The static memory cells are coupled to word lines and bit lines, and the word lines are coupled to word drivers. A first P channel MOS transistor (MOS power switch) has a gate coupled to receive a first control signal, and a second P channel MOS transistor (MOS power switch) has a gate coupled to receive a second control signal different from the first control signal. Source-drain paths of the first and second P channel MOS transistors (MOS power switches) are coupled to respective voltage supply points for different parts of the semiconductor device, such as voltage supply points for the memory cells and the word drivers, or voltage supply points for a logic circuit and the word drivers.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: March 27, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Masanao Yamaoka, Koichiro Ishibashi, Shigezumi Matsui, Kenichi Osada
  • Patent number: 9922688
    Abstract: A bit line sensing latch circuit is disclosed. In one embodiment, a latch circuit includes a keeper and a precharge circuit. The keeper may be implemented using a single pair of transistors that are cross-coupled between first and second differential signal nodes. A gate terminal of a first one of the pair of transistors is coupled to the first differential signal node, while the drain terminal of the same transistor is coupled to the second differential signal node. The gate terminal of a second one of the pair of transistors is coupled to the second differential signal node, while its drain terminal is coupled to the first differential signal node. The bitline sensing latch also includes a precharge circuit, and may operates in two phases, a precharge phase and an enable phase.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: March 20, 2018
    Assignee: Apple Inc.
    Inventor: William R. Weier