Complementary Patents (Class 365/156)
  • Patent number: 10497432
    Abstract: A memory array includes a first memory cell and a second memory cell, each including a data storage element, a first access transistor coupled to the data storage element, and a second access transistor coupled to the data storage element. The memory array further includes two word lines configured to selectively enable access to the data storage element of the first memory cell through the two access transistors of the first memory cell respectively, two bit lines coupled to the two access transistors of the first memory cell respectively, two another word lines configured to selectively enable access to the data storage element of the second memory cell through the two access transistors of the second memory cell respectively, a third bit line coupled to the first access transistor of the second memory cell, and a first sense amplifier coupled to the first bit line and the third bit line.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: December 3, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Shih-Lien Linus Lu
  • Patent number: 10490545
    Abstract: An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: November 26, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Okagaki, Koji Shibutani, Makoto Yabuuchi, Nobuhiro Tsuda
  • Patent number: 10483951
    Abstract: A circuit may include a ring oscillator circuit and monitoring circuitry. The ring oscillator circuit has a group of inverters in a loop, whereby the group of inverters includes first, second, and third output nodes. The monitoring circuitry may monitor for error events in a signal that has passed through the inverters from any one of the first, second, or third output nodes, and may generate first and second monitoring circuitry outputs. The circuit may further include an error correction circuit that produces an error correction output based on the first and second monitoring circuitry outputs. Accordingly, the monitoring circuitry may generate first and second updated monitoring circuitry outputs based on the error correction output. The first and second updated monitoring circuitry outputs may be logically combined using a logic circuit to reset the signal that has passed through the loop.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: November 19, 2019
    Assignee: Altera Corporation
    Inventors: Nelson Gaspard, Yanzhong Xu
  • Patent number: 10460794
    Abstract: SRAM arrays are provided. In each SRAM cell arranged in the same column of cell array, first pull-down transistor and first pass-gate transistor are formed in first P-type well region. First and second pull-up transistors are formed in N-type well region. Second pull-down transistor and second pass-gate transistor are formed in second P-type well region. Each well strap cell includes an N-well strap structure formed on the N-type well region and a P-well strap structure formed on the first or second P-type well region. In the same column of cell array, a first distance between an active region of the P-well strap structure and the N-type well region is greater than a second distance from an active region of the first pull-down transistor and the first pass-gate transistor or an active region of the second pull-down transistor and the second pass-gate transistor to the N-type well region.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: October 29, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 10381069
    Abstract: A circuit includes a core having a memory array. The memory array includes memory cells and bitlines, and is arranged in columns. The core includes a metallization layer having connections to the memory array, which is devoid of memory cells. Digit lines are connected to the bitlines of a column of the memory array. A write driver is connected to the digit lines. A write assist circuit is connected to the write driver. The write assist circuit maintains a voltage on the digit lines prior to write operations and provides a boost voltage to the digit lines during write operations. A wire bridge located in the metallization layer of the core connects the write assist circuit to the write driver.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: August 13, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sreenivasula Reddy Dhani Reddy, Sreejith Chidambaran, Binu Jose, Venkatraghavan Bringivijayaraghavan
  • Patent number: 10366989
    Abstract: A semiconductor device includes a first fin field effect transistor (FinFET) and a contact bar (source/drain (S/D) contact layer). The first FinFET includes a first fin structure extending in a first direction, a first gate structure extending in a second direction crossing the first direction, and a first S/D structure. The contact bar is disposed over the first S/D structure and extends in the second direction crossing the first S/D structure in plan view. The contact bar includes a first portion disposed over the first S/D structure and a second portion. The second portion overlaps no fin structure and no S/D structure. A width of the second portion in the first direction is smaller than a width of the first portion in the first direction in plan view.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: July 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hao Chang, Wen-Huei Guo, Yi-Shien Mor
  • Patent number: 10319429
    Abstract: A method for storing information in SRAM bit cell arrays provides for lowering voltage supplied to the SRAM bit cell arrays, with voltage lowering controlled by a connected voltage control circuit. Writing, reading, and correcting information storable in the SRAM bit cell arrays is accomplished using an error correcting code (ECC) block connected to at least some of the SRAM bit cell arrays. The ECC block is configurable to repair stored information.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: June 11, 2019
    Assignee: AMBIQ MICRO, INC.
    Inventors: Christophe J. Chevallier, Stephen James Sheafor
  • Patent number: 10283190
    Abstract: Transpose non-volatile (NV) memory (NVM) bit cells and related data arrays configured for both memory row and column, transpose access operations. A plurality of transpose NVM bit cells can be arranged in memory rows and columns in a transpose NVM data array. To facilitate a row read operation, the transpose NVM bit cell includes a first access transistor coupled to a word line. An activation voltage is applied to the word line to activate the first access transistor to read a memory state stored in the NVM cell circuit in a row read operation. To facilitate a column, transpose read operation, the transpose NVM bit cell includes a second access transistor coupled to a transpose word line. An activation voltage is applied to the transpose word line to activate the second access transistor to read the memory state stored in the NVM cell circuit in a column, transpose read operation.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: May 7, 2019
    Assignee: QUALCOMM Incorporated
    Inventor: Xia Li
  • Patent number: 10277441
    Abstract: Methods, systems, and devices for improving uniformity between levels of a multi-level signal are described. Techniques are provided herein to unify peak-to-peak voltage differences between the amplitudes of data transmitted using multi-level signaling. Such multi-level signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: April 30, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Timothy M. Hollis
  • Patent number: 10224403
    Abstract: A semiconductor device including a base region present within a fin semiconductor structure that is present atop a dielectric substrate. An epitaxial emitter region and epitaxial collector region are present on opposing sides and in direct contact with the fin semiconductor structure. An epitaxial extrinsic base region is present on a surface of the fin semiconductor substrate that is opposite the surface of the fin semiconductor structure that is in contact with the dielectric base.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: March 5, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Bahman Hekmatshoartabari, Alexander Reznicek, Jeng-Bang Yau
  • Patent number: 10204672
    Abstract: A magnetic memory device includes a memory cell array, a counter circuit and a control circuit. The memory cell array includes a memory cell including a magneto resistive element in which writing is performed by current in a first direction or current in a second direction which is an opposite direction to the first direction. The memory cell array includes a first word line and a first bit line, both connected with the memory cell. The counter circuit counts the number of writing times in the first direction while the counter circuit is in electrical connection with the magneto resistive element. The control circuit performs writing in the second direction in the memory cell when the number of consecutive writing times in the first direction reaches a threshold number of times while the control circuit is in connection with the memory cell array.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: February 12, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Shinya Kobayashi
  • Patent number: 10177760
    Abstract: A method to generate a circuit instance to include a plurality of pMOSFET instances, where each pMOSFET instance has a source terminal instance connected to one or more supply rail instances. The circuit instance includes impedance element instances, where each impedance element instance is connected to a source terminal instance and a drain terminal instance of a corresponding pMOSFET instance. Depending upon a set of requirements, one or more of the impedance element instances are in a high impedance state or a low impedance state.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: January 8, 2019
    Assignee: ARM Limited
    Inventors: Andy Wangkun Chen, Yew Keong Chong, Yicong Li, Hsin-Yu Chen, Sriram Thyagarajan
  • Patent number: 10153034
    Abstract: A static random access memory unit structure and layout structure includes two pull-up transistors, two pull-down transistors, two slot contact plugs, and two metal-zero interconnects. Each metal-zero interconnect is disposed on each slot contact plug and a gate of each pull-up transistor, in which, each slot contact plug crosses a drain of each pull-down transistor and a drain of each pull-up transistor and extends to cross an end of each metal-zero interconnect. A gap between the slot contact plugs is smaller than a gap between the metal-zero interconnects.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: December 11, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tan-Ya Yin, Ming-Jui Chen, Chia-Wei Huang, Yu-Cheng Tung, Chin-Sheng Yang
  • Patent number: 10141323
    Abstract: A semiconductor device is provided. The semiconductor device comprises a first active region, a second active region and a third active region, a first poly region, a second poly region, a third poly region, a first doped region and a second doped region. The first active region, the second active region and the third active region are separated and parallel with each other. The first poly region is arranged over the first and second active regions. The second poly region is arranged over the first and second active regions. The third poly region is arranged over the second and third active regions. The first doped region is in the second active region and between the first poly region and the second poly region. The second doped region is in the second active region and between the second poly region and the third poly region.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: November 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hau-Yan Lu, Shih-Hsien Chen, Chun-Yao Ko, Felix Ying-Kit Tsui
  • Patent number: 10038050
    Abstract: A method includes providing a semiconductor substrate having a plurality of linear semiconductor fin structures spaced apart from one another on a surface of the substrate; siliciding sidewalls of the semiconductor fin structures; removing an unsilicided central portion of each semiconductor fin structure leaving, for a given one of the semiconductor fin structures, a pair of silicide fin structures that are parallel to one another and spaced apart from one another by a distance about equal to a width of the removed unsilicided central portion of the semiconductor fin structure; and forming contacts to conductively connect together a plurality of the silicide fin structures to form a resistor. A resistance value of the resistor is related at least to a type of silicide, a number of contacted adjacent silicide fin structures and a length between two contacts.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: July 31, 2018
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Keith E. Fogel, Alexander Reznicek, Oscar van der Straten
  • Patent number: 10008257
    Abstract: Embodiments include systems and methods for improving column selection functionality of memory circuits. Embodiments operate in context of memory bitcells having additional series pass gates (e.g., junction sharing transistors) coupled with a column select signal to form an integrated column select port. Such a column select port can provide each bitcell with column select functionality in a manner that has improved area and power performance over some conventional (added NOR or other logic) approaches. However, the added column select port can still tend to add area, add column select load, and degrade writability (e.g., due to certain charge-sharing effects). Some embodiments are described herein for addressing the area and column select load by sharing certain intermediate nodes among multiple, adjacent bitcells. Other embodiments can include additional ground-connected transistors in a manner that improves writability (e.g., and read noise margin) of the bitcell.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: June 26, 2018
    Assignee: Oracle International Corporation
    Inventors: Jinho Kwack, Hoyeol Cho, Heechoul Park, Myung Gyoo Won, Peter Labrecque, Jungyong Lee
  • Patent number: 10008258
    Abstract: A circuit can be used, for example, with a multi-supply memory device. The circuit includes a first conductor and a second conductor. A first transistor has a current path coupled between the first conductor and the second conductor. A second transistor also has a current path coupled between the first conductor and the second conductor. A pulse generator circuit has an input coupled to a control terminal of the first transistor and an output coupled to a control terminal of the second transistor.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: June 26, 2018
    Assignee: STMicroelectronics International N.V.
    Inventors: Piyush Jain, Vivek Asthana, Naveen Batra
  • Patent number: 9997590
    Abstract: A method includes providing a semiconductor substrate having a plurality of linear semiconductor fin structures spaced apart from one another on a surface of the substrate; siliciding sidewalls of the semiconductor fin structures; removing an unsilicided central portion of each semiconductor fin structure leaving, for a given one of the semiconductor fin structures, a pair of silicide fin structures that are parallel to one another and spaced apart from one another by a distance about equal to a width of the removed unsilicided central portion of the semiconductor fin structure; and forming contacts to conductively connect together a plurality of the silicide fin structures to form a resistor. A resistance value of the resistor is related at least to a type of silicide, a number of contacted adjacent silicide fin structures and a length between two contacts.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: June 12, 2018
    Assignee: International B├╝siness Machines Corporation
    Inventors: Praneet Adusumilli, Keith E. Fogel, Alexander Reznicek, Oscar van der Straten
  • Patent number: 9990986
    Abstract: A static random access memory device includes a plurality of memory cells arranged in rows and columns, a write driver configured to apply a bit line voltage corresponding to write data to a bit line extending in a column direction of the plurality of memory cells in a write operation, and a sub power line configured to transmit a cell driving voltage to the plurality of memory cells in the write operation and to extend in a direction parallel to the bit line, and includes a first node and a second node. The cell driving voltage is applied to the first node of the sub power line and the first node of the sub power line is aligned with an output node of the write driver in a row direction of the plurality of memory cells.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: June 5, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ingyu Park, Inhak Lee, Chanho Lee, Jaeseung Choi
  • Patent number: 9973179
    Abstract: A method and device for input offset cancellation utilizing a latched comparator that is configurable as a linear amplifier capable of sampling and cancelling offset in the inputs to the latched comparator. The latched comparator is configured according to three control signals for operation in three operating intervals. During a first operating interval, the latched comparator is configured as a linear amplifier that samples the offset at the inputs to the latched comparator. Based on the sampled offset, the linear amplifier cancels the offset in the inputs to the latched comparator. During a second operating interval, the latched comparator reverts to operation as comparator and the inputs to the latch are reset. During a third interval, the latch resolves the inputs to the comparator and generates an output signal indicating.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: May 15, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Kannan Krishna
  • Patent number: 9940994
    Abstract: A circuit and method performs a write assist for a memory cell (e.g., a static random access memory cell (SRAM)). The method includes providing a lower supply voltage signal to a voltage supply node of the memory cell using a capacitor. The lower supply voltage signal is lower in voltage level than a supply voltage signal. The method further includes lowering a common signal provided to a write driver using the capacitor.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: April 10, 2018
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Yifei Zhang, Mark J. Winter
  • Patent number: 9928900
    Abstract: A semiconductor device having static memory cells is designed to reduce leakage current and power consumption. The static memory cells are coupled to word lines and bit lines, and the word lines are coupled to word drivers. A first P channel MOS transistor (MOS power switch) has a gate coupled to receive a first control signal, and a second P channel MOS transistor (MOS power switch) has a gate coupled to receive a second control signal different from the first control signal. Source-drain paths of the first and second P channel MOS transistors (MOS power switches) are coupled to respective voltage supply points for different parts of the semiconductor device, such as voltage supply points for the memory cells and the word drivers, or voltage supply points for a logic circuit and the word drivers.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: March 27, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Masanao Yamaoka, Koichiro Ishibashi, Shigezumi Matsui, Kenichi Osada
  • Patent number: 9922688
    Abstract: A bit line sensing latch circuit is disclosed. In one embodiment, a latch circuit includes a keeper and a precharge circuit. The keeper may be implemented using a single pair of transistors that are cross-coupled between first and second differential signal nodes. A gate terminal of a first one of the pair of transistors is coupled to the first differential signal node, while the drain terminal of the same transistor is coupled to the second differential signal node. The gate terminal of a second one of the pair of transistors is coupled to the second differential signal node, while its drain terminal is coupled to the first differential signal node. The bitline sensing latch also includes a precharge circuit, and may operates in two phases, a precharge phase and an enable phase.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: March 20, 2018
    Assignee: Apple Inc.
    Inventor: William R. Weier
  • Patent number: 9916893
    Abstract: The present disclosure provides a static random access memory (SRAM) cell. The SRAM cell includes first and second inverters cross-coupled for data storage, each inverter including at least one pull-up device and at least two pull-down devices; at least four pass gate devices configured with the two cross-coupled inverters; at least two ports coupled with the at least four pass-gate devices for reading and writing; a first contact feature contacting first two pull-down devices (PD-11 and PD-12) of the first inverter; and a second contact feature contacting second two pull-down devices (PD-21 and PD-22) of the second inerter.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: March 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 9871049
    Abstract: A static random access memory device includes two body contacts and two resistive-switching devices. The body contacts are disposed in a wafer and are exposed from a back side of the wafer, wherein the body contacts electrically connect a static random access memory cell through a metal interconnect in the wafer. The resistive-switching devices connect the two body contacts respectively from the back side of the wafer. A method of forming a static random access memory device is also provided in the following. A wafer having two body contacts exposed from a back side of the wafer and a metal interconnect electrically connecting a static random access memory cell to the body contacts is provided. Two resistive-switching devices are formed to connect the two body contacts respectively from the back side of the wafer.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: January 16, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wanxun He, Su Xing
  • Patent number: 9786358
    Abstract: A 6T bitcell for single port SRAM that performs single ended read and single ended write is described. The presently described bitcell gives huge advantage in terms of area, dynamic power, leakage power and performance over the prior art in the industry. The bitcell and architecture does not have either a write bitline pair or a read bitline for each bitcell. It has only one read bitline per mux.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: October 10, 2017
    Inventor: Sudhir S. Moharir
  • Patent number: 9786360
    Abstract: A memory bank of a semiconductor memory device includes: a plurality of memory cells; first and second local bit lines; a differential amplifier configured to amplify a potential difference between the first and second local bit lines; a connector to which a global data line is connected; a first output circuit configured to selectively output, according to a potential level of the first local bit line, a first potential to the connector; and a second output circuit configured to selectively prevent, according to a potential level of the second local bit line, a potential of the connector from being affected by an output of the first output circuit and being equal to the first potential.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: October 10, 2017
    Assignee: SOCIONEXT INC.
    Inventor: Tsuyoshi Koike
  • Patent number: 9773545
    Abstract: The present disclosure provides a static random access memory (SRAM) cell. The SRAM cell includes first and second inverters cross-coupled for data storage, each inverter including at least one pull-up device and at least two pull-down devices; at least four pass gate devices configured with the two cross-coupled inverters; at least two ports coupled with the at least four pass-gate devices for reading and writing; a first contact feature contacting first two pull-down devices (PD-11 and PD-12) of the first inverter; and a second contact feature contacting second two pull-down devices (PD-21 and PD-22) of the second inverter.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: September 26, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 9728237
    Abstract: A determination circuit of one embodiment includes first and second inverter circuits, a first transistor which turns on when receiving an asserted first signal, and a first capacity component including a first end which receives an inversion signal of the first signal. The second inverter circuit includes an input coupled to an output of the first inverter circuit, and includes an output coupled to an input of the first inverter circuit. The first node is coupled to a first potential node, the first transistor is coupled between the second node and a second potential node having a lower potential than a potential of the first potential node, and a second end of the first capacity component is coupled to the second node.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: August 8, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toshiaki Dozaka
  • Patent number: 9697888
    Abstract: The present patent application describes 9T, 8T, and 7T versions of bitcells used with 1R1W memories. It also describes 9T, 8T, and 7T versions of bitcells used with single port SRAM memories. Different circuits are discussed to support different bitcells and architectures mentioned above. Our 1R1W and single port bitcells and architectures give significant advantages over the conventional bitcells and architectures.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: July 4, 2017
    Assignee: SKAN TECHNOLOGIES CORPORATION
    Inventor: Sudhir S. Moharir
  • Patent number: 9691495
    Abstract: A memory array with RAM and embedded ROM including multiple RAM cells, a ROM cell, and a ROM enable circuit. Each RAM cell has a RAM cell structure with a first and second power terminals and configured to operate as a RAM cell when the memory array is in a RAM mode. The ROM cell has the same RAM cell structure in which at least one transistor is modified to cause the ROM cell to have a predetermined logic state. The ROM enable circuit enables bit lines of the ROM cell to control supply voltages provided to the power terminals of the RAM cells so that they settle to predetermined logic states in a ROM mode. The modified transistor has a pseudo transistor structure having a modified substrate that operates as a resistance, such as a doping region in the substrate having the same polarity type as the substrate.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: June 27, 2017
    Assignee: NXP USA, INC.
    Inventors: Jianan Yang, Scott I. Remington, Shayan Zhang
  • Patent number: 9672904
    Abstract: A 6T bitcell for single port SRAM that performs single ended read and single ended write is described. The presently described bitcell gives huge advantage in terms of area, dynamic power, leakage power and performance over the prior art in the industry. The bitcell and architecture does not have either a write bitline pair or a read bitline for each bitcell. It has only one read bitline per mux.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: June 6, 2017
    Assignee: SKAN TECHNOLOGIES CORPORATION
    Inventor: Sudhir S. Moharir
  • Patent number: 9666253
    Abstract: A dual rail memory operable at a first voltage and a second voltage, the dual rail memory includes: a memory array operates at the first voltage; a word line driver circuit configured to drive a word line of the memory array to the first voltage; a data path configured to transmit an input data signal or an output data signal; and a control circuit configured to generate control signals to the memory array, the word line driver circuit and the data path; wherein the data path and the control circuit are configured to operate at both the first and second voltages. Associated memory macro and method are also disclosed.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: May 30, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jonathan Tsung-Yung Chang, Chiting Cheng, Cheng Hung Lee, Hung-Jen Liao, Michael Clinton
  • Patent number: 9627043
    Abstract: The present patent application describes 9T, 8T, and 7T versions of bitcells used with 1R1W memories. It also describes 9T, 8T, and 7T versions of bitcells used with single port SRAM memories. Different circuits are discussed to support different bitcells and architectures mentioned above. Our 1R1W and single port bitcells and architectures give significant advantages over the conventional bitcells and architectures.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: April 18, 2017
    Assignee: SKAN TECHNOLOGIES CORPORATION
    Inventor: Sudhir S. Moharir
  • Patent number: 9601162
    Abstract: A device includes a memory array, a first data line, and a second data line. The memory array includes a first strap cell, a first sub-bank, and a second sub-bank, in which the first strap cell is disposed between the first sub-bank and the second sub-bank. The first data line has a first portion and a second portion, in which the first portion of the first data line is disconnected from the second portion of the first data line, and the second portion of the first data line is configured to couple the first sub-bank to a first input/output (I/O) circuit. The second data line and the first portion of the first data line are configured to couple the second sub-bank to the first I/O circuit.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: March 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jonathan Tsung-Yung Chang, Cheng-Hung Lee, Chi-Ting Cheng, Hung-Jen Liao, Jhon-Jhy Liaw, Yen-Huei Chen
  • Patent number: 9595348
    Abstract: A memory circuit includes: a control part configured to output a control signal; a fuse circuit which is driven by the control signal and is configured to output a fuse signal whose signal level is determined based on a state of a first fuse element; and a holding circuit configured to update and hold a signal based on the fuse signal in response to the control signal output from the control part and output the held signal as an output signal.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: March 14, 2017
    Assignee: Rohm Co., Ltd.
    Inventor: Yoshihiro Teno
  • Patent number: 9583178
    Abstract: Methods and apparatuses for static memory cells. A static memory cell may include a first pass gate transistor including a first back gate node and a second pass gate transistor including a second back gate node. The static memory cell may include a first pull down transistor including a third back gate node and a second pull down transistor including a fourth back gate node. The source node of the first pull down transistor, source node of the second pull down transistor, and first, second, third, and fourth back gate nodes are electrically coupled to each other to form a common node.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: February 28, 2017
    Assignees: QUALCOMM Incorporated, Industry-Academic Cooperation Foundation Yonsei University
    Inventors: Seong-Ook Jung, Younghwi Yang, Bin Yang, Choh Fei Yeap
  • Patent number: 9564441
    Abstract: A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: February 7, 2017
    Assignee: Kilopass Technology, Inc.
    Inventors: Harry Luan, Bruce L. Bateman, Valery Axelrad, Charlie Cheng, Christophe J. Chevallier
  • Patent number: 9509255
    Abstract: A sense amplifier includes a first transistor having a first gate, a second transistor having a second gate in series with the first transistor, a third transistor having a third gate, and a fourth transistor having a fourth gate in series with the third transistor. A first input node is coupled to the third gate and the fourth gate, a second input node is coupled to the first gate and the second gate, and a first compensation transistor is in series with the first and second transistors or the third and fourth transistors, the first compensation transistor having a first compensation bulk. The first compensation bulk receives a first compensation voltage to modify the first compensation threshold, the first compensation voltage having a value calculated to compensate for an offset associated with the first and second input nodes.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: November 29, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Bharath Upputuri, Shreekanth Sampigethaya
  • Patent number: 9502541
    Abstract: A fin structure for a fin field effect transistor (FinFET) device is provided. The device includes a substrate, a first semiconductor material disposed on the substrate, a shallow trench isolation (STI) region disposed over the substrate and formed on opposing sides of the first semiconductor material, and a second semiconductor material forming a first fin and a second fin disposed on the STI region, the first fin spaced apart from the second fin by a width of the first semiconductor material. The fin structure may be used to generate the FinFET device by forming a gate layer formed over the first fin, a top surface of the first semiconductor material disposed between the first and second fins, and the second fin.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: November 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Georgios Vellianitis, Mark van Dal, Blandine Duriez, Richard Kenneth Oxland
  • Patent number: 9490008
    Abstract: The present patent application describes 9T, 8T, and 7T versions of bitcells used with 1R1W memories. It also describes 9T, 8T, and 7T versions of bitcells used with single port SRAM memories. Different circuits are discussed to support different bitcells and architectures mentioned above. Our 1R1W and single port bitcells and architectures give significant advantages over the conventional bitcells and architectures.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: November 8, 2016
    Assignee: SKAN TECHNOLOGIES CORPORATION
    Inventor: Sudhir S. Moharir
  • Patent number: 9490007
    Abstract: A device including a plurality of static random-access memory (SRAM) bitcells arranged in rows and columns, wherein the SRAM bitcells comprise fully depleted silicon-on-insulator field effect transistors (FDSOI-FETs). The FDSOI-FETs comprise P-channel-pull-up-transistors, wherein each P-channel-pull-up-transistor comprises a back gate. The device further includes a plurality of bitlines, wherein each bitline is electrically connected to the SRAM bitcells of one of the columns and a plurality of wordlines, wherein each wordline is electrically connected to the SRAM bitcells of one of the rows. The device further includes a bitline control circuit configured to select at least one column for writing, wherein during a write operation a first control signal is applied to the back gates of the P-channel-pull-up-transistors of the at least one column selected for writing and a second control signal to the back gates of the P-channel-pull-up-transistors of the columns not selected for writing.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: November 8, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Nigel Chan, Germain Bossu, Michael Otto
  • Patent number: 9485447
    Abstract: An image pickup apparatus for photographing an image, includes: a photoelectric converter to convert incident light an electric charge and accumulate the electric charge, a transfer element to transfer the electric charge accumulated in the photoelectric converter, a converter to convert the electric charge in the photoelectric converter transferred via the transfer element into a voltage, a reset element to reset potentials of the converter, and an amplifier to amplify a voltage converted by the converter to generate a pixel signal and output the pixel signal to a read signal line for reading the pixel signal. A plurality of the photoelectric converter and the transfer element are disposed at least in a horizontal direction share the amplifier and the read signal line.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: November 1, 2016
    Assignee: Sony Corporation
    Inventors: Koji Mishina, Yoshikazu Nitta
  • Patent number: 9424222
    Abstract: Apparatuses and methods for charge sharing across data buses based on respective levels of the data buses are disclosed herein. An example apparatus may include a first bus, a second bus, and a charge sharing circuit coupled to each of the first bus and the second bus. The charge sharing circuit may be configured to couple the first bus to the second bus based on logic levels of the first bus and the second bus. For example, the charge sharing circuit may couple the first bus to the second bus responsive to the first bus and the second bus having inverted logic levels.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: August 23, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Kyoichi Nagata
  • Patent number: 9406616
    Abstract: A method of forming a semiconductor device with uniform regular shaped gate contacts and the resulting device are disclosed. Embodiments include forming first and second gate electrodes adjacent one another on a substrate; forming at least one trench silicide (TS) on the substrate between the first and second gate electrodes; forming a gate contact on the first gate electrode, the gate contact having a regular shape; forming a source/drain contact on a trench silicide between the first and second gate electrodes, wherein an upper portion of the source/drain contact overlaps an upper portion of the gate contact.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: August 2, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Youngtag Woo, Ryan Ryoung-han Kim
  • Patent number: 9401199
    Abstract: A storage cell is provided with improved robustness to soft errors. The storage cell comprises complementary core storage nodes and complementary outer storage nodes. The outer storage nodes act to limit feedback between the core storage nodes and are capable of restoring the logical state of the core storage nodes in the event of a soft error. Similarly the core storage nodes act to limit feedback between the outer storage nodes with the same effect. This cell has advantages compared with other robust storage cells in that there are only two paths between the supply voltage and ground which limits the leakage power. An SRAM cell utilizing the proposed storage cell can be realized with two access transistors configured to selectively couple complementary storage nodes to a corresponding bitline. A flip-flop can be realized with a variety of transfer gates which selectively couple data into the proposed storage cell.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: July 26, 2016
    Assignee: Tiraboschi Services, LLC
    Inventors: David Rennie, Manoj Sachdev
  • Patent number: 9336861
    Abstract: A bit cell and memory architecture wherein a write bitline is not required is presented. The bitcell and the memory architecture bring a huge improvement in the performance, dynamic power, leakage power, area, and the yield of the memory.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: May 10, 2016
    Assignee: SKAN TECHNOLOGIES CORPORATION
    Inventor: Sudhir S. Moharir
  • Patent number: 9322859
    Abstract: A method of re-offsetting a plurality of amplifier is provided. The method includes testing the plurality of amplifiers based on a re-offset value at bulks of compensation transistors of the plurality of amplifiers; identifying a first group of first amplifiers of the plurality of amplifiers favoring reading a first logic level and/or a second group of second amplifiers of the plurality of amplifiers favoring reading a second logic level different from the first logic level, based on results of the testing step; changing the re-offset value to a new re-offset value; re-offsetting the first group of first amplifiers and/or the second group of second amplifiers based on the new re-offset value; and re-testing the first group of first amplifiers and the second group of second amplifiers.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: April 26, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Bharath Upputuri, Shreekanth Sampigethaya
  • Patent number: 9299396
    Abstract: Integrated circuits may include partial reconfiguration (PR) circuitry for reconfiguring only a portion of a memory array. In some applications, partial reconfiguration may be performed during user mode. During partial reconfiguration, write assist techniques such as varying the power supply voltage may be applied to help increase write margin, but doing so can potentially affect the performance of in-operation pass gates that are being controlled by the memory array during user mode. In one suitable arrangement, ground power supply voltage write assist techniques may be implemented on memory cells that include p-channel access transistors and that are used to control n-channel pass transistors. In another suitable arrangement, positive power supply voltage write assist techniques may be implemented on memory cells that include n-channel access transistors and that are used to control p-channel pass transistors.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: March 29, 2016
    Assignee: Altera Corporation
    Inventors: Andy L. Lee, Shankar Sinha, Ning Cheng
  • Patent number: 9287370
    Abstract: A memory device consumes low power, has high capacity, and is shared by a plurality of processors. A data write transistor of a memory device is manufactured with a material capable of achieving a sufficiently low off-state current of a transistor (e.g., an oxide semiconductor material that is a wide band gap semiconductor). The memory device has a memory cell including at least one data write transistor, at least one data storage transistor, and at least two data read transistors.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: March 15, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiyuki Kurokawa