PACKAGE-LEVEL INTEGRATED CIRCUIT CONNECTION WITHOUT TOP METAL PADS OR BONDING WIRE
An integrated circuit method is provided with package-level connectivity, between internal electronic circuitry thereof and contact points on a package substrate thereof, without requiring top metal pads or bonding wires.
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This application is a division of U.S. patent application Ser. No. 12/701,122, filed on Feb. 5, 2010, now U.S. Pat. No. 8,664,748, which claims priority under 35 USC 119 to U.S. Provisional Application No. 61/234,473, filed on Aug. 17, 2009, all of which are incorporated herein by reference.
FIELDThis work relates generally to integrated circuits and, more particularly, to package-level connection to the internal circuitry of an integrated circuit.
BACKGROUNDMoore's law has affected the microchip world where many system applications have demanded more functionality and high performance in ever-smaller form factors. The manufacturing cost also has increased since the first process technology of the late 1950's. As shown in
These kinds of factors require chip area to be sacrificed for bond pads. Along with the bond pad area, some space is provided between the pad and the chip edge to avoid cracks near the pad.
Wire bonding requires electrical connection to the pad, and thus a large enough metal pad area to permit safely connecting the bonding wire to the pad. This results in relatively large capacitive and inductive loading from the metal pad area and the bonding wire itself. Although internal transistor sizes have been steadily reduced by innovations in process technology, the pad size and bonding wire diameter have not kept pace with the shrink ratio of the transistors. Due to this unbalanced trend, the relative influence of the capacitive and inductive loading effect of the pad and bonding wire is increasing seriously. This is generally detrimental, and particularly so for high-speed applications.
It is therefore desirable to provide for reducing the capacitive and inductive loading, and the chip area sacrifices, associated with prior art integrated circuit chip connections at the package level.
Example embodiments of the present work provide lateral pads that replace the conventional wire bonding pads of
Table I summarizes characteristics comparisons between lateral pad structure according to the present work and conventional wire bonding pad structure.
As shown in Table 1 and explained below, lateral pads do not require conventional bonding wires, and thus eliminate the inductive loading associated with bonding wires. Moreover, as also shown in Table 1 and explained below, the physical size of the lateral pads is determined by the metal layer thicknesses provided by the process, which results in much less capacitive loading than is imposed by conventional wire bonding pads, whose physical size is determined by the minimum metal area requirements of the process and/or the minimum bonding wire diameter. These load reductions provided by lateral pads are particularly advantageous in terms of operating speed and power consumption.
As seen from Table 1, in various embodiments, any of the lateral pads 101 and 102 of
It is common to use a back-grinding process to reduce wafer thickness in order to facilitate stacking multiple chips. However, because the size of the lateral pads depends only on the dimensions of the metal layers in the fabrication process technology, the use of lateral pads does not present technical issues in this environment.
Referring to
External circuitry may be connected to the packaged integrated circuit apparatus according to the present work in any manner that would be suitable for connecting the external circuitry to a conventional packaged integrated circuit apparatus.
Although example embodiments of the invention have been described above in detail, this does not limit the scope of the invention, which can be practiced in a variety of embodiments.
Claims
1. A method of producing an integrated circuit apparatus, comprising:
- providing electronic circuitry within a wafer;
- sawing the wafer to produce an integrated circuit apparatus that contains said electronic circuitry and has an edge produced by said sawing; and
- providing within the wafer a plurality of conductors connected to said electronic circuitry and positioned to be exposed on said edge by said sawing to make said conductors physically accessible on said edge.
2. The method of claim 1, wherein said sawing includes sawing with a laser.
3. The method of claim 1, including using physical vapor deposition to provide respective conductive connections between respective ones of said conductors and respective conductive contacts on a package substrate.
4. The method of claim 1, wherein said providing conductors includes providing one of said conductors in one metal layer of the integrated circuit apparatus, and providing another of said conductors in another metal layer of the integrated circuit apparatus.
5. The method of claim 4, wherein said providing conductors includes providing one of said conductors with a different cross-sectional area than another of said conductors.
6. The method of claim 1, wherein said providing conductors includes providing one of said conductors with a different cross-sectional area than another of said conductors.
7. A method of producing an integrated circuit apparatus, comprising:
- providing electronic circuitry and a plurality of conductors connected to said electronic circuitry;
- providing a package substrate including a plurality of conductive contacts; and
- connecting respective ones of said conductors to respective ones of said contacts by respective vias that are physically attached to the associated conductors and contacts.
Type: Application
Filed: Feb 28, 2014
Publication Date: Jun 26, 2014
Applicant: MOSAID Technologies Incorporated (Ottawa)
Inventor: Hong Beom PYEON (Kanata)
Application Number: 14/193,436
International Classification: H01L 21/82 (20060101); H01L 23/00 (20060101);