By Electromagnetic Irradiation (e.g., Electron, Laser, Etc.) Patents (Class 438/463)
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Patent number: 12062544Abstract: A laser annealing method for a semiconductor device, includes: a first step of adding an impurity to a semiconductor substrate; and a second step of irradiating a region to which the impurity is added with a pulsed laser beam a plurality of times to anneal the semiconductor substrate. In the second step, a first region of a portion of the region to which the impurity is added is irradiated with the pulsed laser beam, and after a predetermined time interval, a second region adjacent to the first region is irradiated with the pulsed laser beam. The predetermined time interval is larger than a pulse interval of the pulsed laser beam.Type: GrantFiled: December 21, 2020Date of Patent: August 13, 2024Assignees: SUMITOMO HEAVY INDUSTRIES, LTD., FUJI ELECTRIC CO., LTD.Inventors: Takeshi Aiba, Hiroshi Takishita, Takashi Yoshimura
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Patent number: 11996331Abstract: A method for separating a solid body includes: providing a first solid body having opposite first and second surfaces and a crystal lattice, and that is at least partially transparent to a laser beam emitted by a laser; modifying a portion of the crystal lattice by the laser beam, the laser beam penetrating through the first surface, the modified portion of the crystal lattice extending in a plane parallel to the first surface, as a result of the modification, subcritical cracks are formed arranged in a plane parallel to the first surface, a plurality of the subcritical cracks forming a detachment region in the first solid body, the plurality of the subcritical cracks passing at least in some sections through the modified portion of the crystal lattice; and separating the first solid body along the detachment region to form a wafer and a second solid body.Type: GrantFiled: December 9, 2022Date of Patent: May 28, 2024Assignee: Siltectra GmbHInventors: Christian Beyer, Jan Richter
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Patent number: 11935788Abstract: A manufacturing method of a semiconductor device includes the following steps. A singulation process is performed to a semiconductor wafer for forming semiconductor dies and includes a first cutting step, a thinning step, and a second cutting step. The first cutting step is configured to form first openings in the semiconductor wafer by etching. A portion of the semiconductor wafer is located between each first opening and a back surface and removed by the thinning step. Each first opening penetrates through the semiconductor wafer after the thinning step. The second cutting step is configured to form second openings. Each second opening penetrates through the semiconductor wafer for separating the semiconductor dies. A semiconductor die includes two first side surfaces opposite to each other and two second side surfaces opposite to each other. A roughness of each first side surface is different from a roughness of each second side surface.Type: GrantFiled: December 29, 2020Date of Patent: March 19, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventor: Po-Yu Yang
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Patent number: 11881407Abstract: A method of manufacturing a chip formation wafer includes: forming an epitaxial film on a first main surface of a silicon carbide wafer to provide a processed wafer having one side adjacent to the epitaxial film and the other side; irradiating a laser beam into the processed wafer from the other side of the processed wafer so as to form an altered layer along a surface direction of the processed wafer; and separating the processed wafer with the altered layer as a boundary into a chip formation wafer having the one side of the processed wafer and a recycle wafer having the other side of the processed wafer. The processed wafer has a beveling portion at an outer edge portion of the processed wafer, and an area of the other side is larger than an area of the one side in the beveling portion.Type: GrantFiled: August 31, 2021Date of Patent: January 23, 2024Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA, MIRISE Technologies Corporation, DISCO CorporationInventors: Masatake Nagaya, Teruaki Kumazawa, Yuji Nagumo, Kazuya Hirata, Asahi Nomoto
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Patent number: 11817304Abstract: A system and method for stealth dicing a semiconductor wafer. The method may include implanting dopant ions to a first depth in the semiconductor wafer through a back side of the semiconductor wafer. The method may further include focusing a laser beam at an inside portion of the wafer through the back surface of the wafer to form a modified layer in material of the semiconductor wafer proximate the first depth. The method may also include fracturing the semiconductor wafer along boundaries defined by the modified layer.Type: GrantFiled: May 11, 2020Date of Patent: November 14, 2023Assignee: Micron Technology, Inc.Inventor: Chih Kai Wang
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Patent number: 11637040Abstract: A method for mitigating crack propagation during manufacture of semiconductor dies, and associated systems and methods are disclosed herein. The method includes forming holes into a first side of a wafer substrate opposite a second side. The wafer substrate has active components at the second side. Each hole extends from the first side towards the second side an extend to an intermediate depth within the wafer substrate such that a bottom of the holes is spaced vertically apart from the active components on the second side. The holes are configured to inhibit cracks in the wafer substrate from propagating longitudinally across the wafer substrate. The method also includes backgrinding the first side of the wafer substrate to thin the wafer substrate after forming the holes. The method also includes dicing the wafer substrate after backgrinding to separate individual semiconductor dies from each other.Type: GrantFiled: December 29, 2020Date of Patent: April 25, 2023Assignee: Micron Technology, Inc.Inventors: Wei Yeeng Ng, Rajesh Balachandran, Frank Speetjens, Andrew L. Li, Sukhdeep Kaur, Sangeetha P. Komanduri
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Patent number: 11456260Abstract: A wafer processing method for forming a modified layer within a wafer along planned dividing lines forms the modified layer within the wafer, positions a condensing point within the wafer or at a top surface of the wafer and applies a second laser beam while moving the condensing point, images reflected light, and determines a processed state of the wafer on the basis of an imaged image. The second laser beam is formed such that a sectional shape of the second laser beam in a plane perpendicular to a traveling direction of the second laser beam is not axisymmetric with respect to an axis along the planned dividing lines.Type: GrantFiled: February 9, 2021Date of Patent: September 27, 2022Assignee: DISCO CORPORATIONInventors: Shunsuke Teranishi, Shigefumi Okada, Shuichiro Tsukiji, Yuki Ikku
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Patent number: 11413708Abstract: An object cutting method includes: a first step of preparing an object to be processed including a single crystal silicon substrate and a functional device layer provided on a first main surface side and forming an etching protection layer on a second main surface of the object; a second step of irradiating the object with laser light to form at least one row of modified regions in the single crystal silicon substrate and to form a fracture in the object so as to extend between the at least one row of modified regions and a surface of the etching protection layer; and a third step of performing dry etching on the object from the second main surface side, in a state in which the etching protection layer is formed on the second main surface, to form a groove opening to the second main surface.Type: GrantFiled: April 12, 2018Date of Patent: August 16, 2022Assignee: HAMAMATSU PHOTONICS K.K.Inventors: Takeshi Sakamoto, Tomoya Taguchi
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Patent number: 11380586Abstract: A cutting method includes: forming a reformed region in a workpiece; and after forming the reformed region in the workpiece, forming a groove in the workpiece along an intended cut line. In the forming a groove, a first dry etching process is performed from a front surface toward a rear surface of the workpiece. After the first dry etching process, a first pressure-reducing process is performed in which the workpiece is placed under an atmosphere of reduced pressure as compared to pressure during the first dry etching process. After the first pressure-reducing process, a second dry etching process is performed from the front surface toward the rear surface of the workpiece.Type: GrantFiled: July 18, 2018Date of Patent: July 5, 2022Assignees: IWATANI CORPORATION, HAMAMATSU PHOTONICS K.K.Inventors: Toshiki Manabe, Takehiko Senoo, Koichi Izumi, Tadashi Shojo, Takafumi Ogiwara, Takeshi Sakamoto
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Patent number: 11282746Abstract: A method of manufacturing a microelectronic device may include forming a wiring layer on a first surface of a wafer. The method may also include forming a modified layer along separation regions for each microelectronic device of the wafer by focusing a laser on an inside portion of the wafer. The method may also include removing material from the second surface of the wafer. The wafer may be cooled to a temperature where a low dielectric constant layer extending across the separation regions is brittle while the material is removed from the second surface of the wafer. The method may further include separating the wafer along the separation region to form separate microelectronic devices.Type: GrantFiled: December 27, 2019Date of Patent: March 22, 2022Assignee: Micron Technology, Inc.Inventors: Suresh K. Upadhyayula, Thiam Chye Lim
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Patent number: 11239206Abstract: Semiconductor devices including a dual-sided redistribution structure and having low-warpage across all temperatures and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die electrically coupled to a first side of a redistribution structure and a second semiconductor die electrically coupled to a second side of the redistribution structure opposite the first side. The semiconductor device also includes a first molded material on the first side, a second molded material on the second side, and conductive columns electrically coupled to the first side and extending through the first molded material. The first and second molded materials can have the same volume and/or coefficients of thermal expansion to inhibit warpage of the semiconductor device.Type: GrantFiled: June 18, 2020Date of Patent: February 1, 2022Assignee: Micron Technology, Inc.Inventors: Chan H. Yoo, Mark E. Tuttle
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Patent number: 11189480Abstract: An element chip manufacturing method including: a preparing step of preparing a substrate including a plurality of element regions and a dicing region defining the element regions, the substrate having a first surface and a second surface opposite the first surface; a laser scribing step of applying a laser beam to the dicing region from a side of the first surface, to form a groove corresponding to the dicing region and being shallower than a thickness of the substrate; a cleaning step of exposing the first surface of the substrate to a first plasma, to remove debris on the groove; and a dicing step of exposing the substrate at a bottom of the groove to a second plasma after the cleaning step, to dice the substrate into element chips including the element regions. The first plasma is generated from a process gas containing a carbon oxide gas.Type: GrantFiled: March 5, 2020Date of Patent: November 30, 2021Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Shogo Okita, Atsushi Harikai, Akihiro Itou
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Patent number: 11114342Abstract: A wafer processing method is a method of dividing a wafer in which a functional layer is laminated to a top surface of a substrate and a plurality of devices are formed, along streets dividing the plurality of devices. The wafer processing method includes: a protective member disposing step of disposing an adhesive tape on the functional layer side of a top surface of the wafer; a cutting step of forming, along the streets, a cut groove having a depth exceeding a finished thickness of the wafer by making a cutting blade cut into an undersurface of the wafer; and a plasma etching step of extending the cut groove toward the top surface of the wafer and dividing the substrate along the streets by plasma-etching, from an undersurface side, the wafer whose adhesive tape side is held by a chuck table.Type: GrantFiled: October 22, 2018Date of Patent: September 7, 2021Assignee: DISCO CORPORATIONInventor: Ryuji Norimoto
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Patent number: 11101162Abstract: A chuck table includes a main part having a holding surface for holding thereon a workpiece through a dicing tape, and a frame holder disposed around the main part for holding the annular frame. The main part has a flat surface that functions as the holding surface, an outer circumferential suction groove defined in a region of the holding surface that underlies an annular region of the adhesive tape between the workpiece and the frame of the frame unit, for holding the annular region of the adhesive tape under suction, and a suction channel held in fluid communication with the outer circumferential suction groove and a suction source. The frame holder pulls down the frame to a position lower than the holding surface to hold the dicing tape in close contact with the holding surface.Type: GrantFiled: March 5, 2019Date of Patent: August 24, 2021Assignee: DISCO CORPORATIONInventors: Setsuo Yamamoto, Kazuma Sekiya
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Patent number: 11053156Abstract: A method for machining and releasing closed forms from a transparent, brittle substrate includes using a burst of ultrafast laser pulses to drill patterns of orifices in the substrate. Orifices are formed by photoacoustic compression and they extend completely or partially in the transparent substrate. A scribed line of spaced apart orifices in the transparent substrate comprise a closed form pattern in the substrate. A heat source is applied in a region about said scribed line of spaced apart orifices until the closed form pattern releases from the transparent substrate.Type: GrantFiled: November 11, 2014Date of Patent: July 6, 2021Assignee: ROFIN-SINAR TECHNOLOGIES LLCInventor: S. Abbas Hosseini
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Patent number: 10985065Abstract: A wafer processing method includes a protective member laying step of placing a protective member on a face side of a wafer, a reverse side grinding step of grinding a reverse side of the wafer to thin the wafer, a cut groove forming step of positioning a cutting blade in alignment with projected dicing lines one at a time on the reverse side of the wafer, cutting the wafer with the cutting blade to form cut grooves in the wafer which terminate short of the face side thereof, and a cutting step of applying a laser beam to the wafer from the reverse side thereof along the cut grooves to completely sever the wafer along the projected dicing lines into individual device chips.Type: GrantFiled: October 31, 2017Date of Patent: April 20, 2021Assignee: DISCO CORPORATIONInventors: Yohei Yamashita, Tsubasa Obata, Yuki Ogawa
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Patent number: 10872758Abstract: A SiC wafer is produced from a single crystal SiC ingot. A focal point of a pulsed laser beam having a transmission wavelength to the ingot is set inside the ingot at a predetermined depth from a flat surface of the ingot, the predetermined depth corresponding to the thickness of the wafer to be produced. The pulsed laser beam is applied to the ingot to thereby form a separation layer for separating the wafer from the ingot. The wafer is separated from the ingot along the separation layer, and a flat surface is formed by grinding an upper surface of the ingot as a rough separation surface left after separating the wafer, thereby removing the roughness of the upper surface of the ingot to flatten the upper surface of the ingot.Type: GrantFiled: April 25, 2018Date of Patent: December 22, 2020Assignee: DISCO CORPORATIONInventor: Kazuya Hirata
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Patent number: 10852644Abstract: An optical proximity correction (OPC) method may include providing a design layout including conductive patterns, determining line end void (LEV)-risk patterns among the conductive patterns, the LEV-risk patterns each having a risk of suffering from poor contact due to an LEV, setting markers including portions of the LEV-risk patterns and portions of the conductive patterns adjacent to the LEV-risk patterns, performing a first OPC on first patterns included in the markers and performing a second OPC on second patterns outside the markers, the second OPC being different from the first OPC, and each of the first OPC and the second OPC being performed a plurality of times, and calculating a cost function of each of the markers. The determining may include comparing risks of occurrence of poor contact in each of the conductive patterns based on a scoring function, and the scoring function may be inversely proportional to a width of each of the conductive patterns.Type: GrantFiled: April 16, 2019Date of Patent: December 1, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Byung-je Jung, No-young Chung
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Patent number: 10854562Abstract: A semiconductor device includes a semiconductor substrate having a chip region and an edge region, a plurality of connection structures provided in a lower insulating layer of the edge region and arranged at first intervals in a first direction, an upper insulating layer covering the connection structures, and a plurality of redistribution pads disposed on the upper insulating layer and connected to the connection structures, respectively. Each of the redistribution pads includes a pad portion provided on the chip region. The pad portions of the redistribution pads are spaced apart from the connection structures by a first distance in a second direction intersecting the first direction when viewed in a plan view.Type: GrantFiled: May 6, 2020Date of Patent: December 1, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Seok-Ho Shin, Bonhwi Gu, Hyekyeong Kweon, Sungjin Kim, Joodong Kim, Jaepil Lee, Dongwon Lim
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Patent number: 10818554Abstract: A laser processing method for a wafer that is segmented by plural planned dividing lines set on a surface in a lattice manner uses a laser processing apparatus including a laser beam irradiation unit that irradiates, through a collecting lens, the wafer held by a chuck table, with plural laser beams formed by being oscillated by a laser beam oscillator and being split by a laser beam splitting unit. The method includes a processed groove forming step of irradiating the wafer with the plural laser beams along the planned dividing lines and forming a processed groove along the planned dividing lines. The plural laser beams split by the laser beam splitting unit are arranged in a line manner along a direction that is non-parallel to an extension direction of the planned dividing line irradiated with the plural laser beams.Type: GrantFiled: April 3, 2018Date of Patent: October 27, 2020Assignee: DISCO CORPORATIONInventor: Yuri Ban
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Patent number: 10818552Abstract: The present invention provides a method for plasma dicing a substrate. The substrate is provided with a top surface and a bottom surface, the top surface of the substrate having a plurality of street areas and at least one device structure. The substrate is placed onto a support film on a frame to form a work piece. A process chamber having a plasma source is provided. A work piece support is provided within the plasma process chamber. The work piece is placed onto the work piece support. A plasma is generated from the plasma source in the plasma process chamber. The work piece is processed using the generated plasma and a byproduct generated from the support film while the support film is exposed to the generated plasma.Type: GrantFiled: February 19, 2019Date of Patent: October 27, 2020Assignee: Plasma-Therm LLCInventors: Tsu-Wu Chiang, Russell Westerman
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Patent number: 10807198Abstract: A laser processing apparatus includes: a chuck table that holds a packaged wafer by a holding surface; a laser processing unit that applies a laser beam to the packaged wafer to form a through-groove along each division line; an X-axis moving unit that moves the chuck table in an X-axis direction; and an examination unit. The chuck table includes: a holding member that forms the holding surface; and a light emitting body. The examination unit includes: a line sensor that extends in a Y-axis direction; and a control unit that determines the result of processing through reception by the line sensor of light from the light emitting body through the through-groove. The line sensor images the whole surface of the packaged wafer being held by the chuck table.Type: GrantFiled: January 26, 2018Date of Patent: October 20, 2020Assignee: DISCO CORPORATIONInventors: Yuri Ban, Yuta Yoshida, Kentaro Odanaka
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Patent number: 10758999Abstract: The object to be processed cutting method includes: a crystal orientation identifying step of identifying a crystal orientation of the substrate; a line to cut setting step of setting, for the object to be processed, a line to cut passing through a street region formed between adjacent functional devices, after the crystal orientation identifying step; and a cutting step of cutting the object to be processed along the line to cut, after the line to cut setting step. In the line to cut setting step, in a case where an extending direction of the street region does not match the crystal orientation, the line to cut parallel to the crystal orientation and inclined with respect to the extending direction of the street region, is set for the object to be processed.Type: GrantFiled: August 8, 2016Date of Patent: September 1, 2020Assignee: HAMAMATSU PHOTONICS K.K.Inventors: Junji Okuma, Yo Sugimoto
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Patent number: 10763172Abstract: A method of processing a wafer having a face side where devices are formed in respective areas demarcated by a grid of projected dicing lines includes a groove forming step, a protective film sticking step, a protective-member-combined wafer forming step, a grinding step, a tape bonding step, a holding step, a peeling step, and a die-attach film dividing step.Type: GrantFiled: December 27, 2018Date of Patent: September 1, 2020Assignee: DISCO CORPORATIONInventor: Kazuma Sekiya
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Patent number: 10702952Abstract: The present application describes a method for laser scribing first and second transparent electrically conductive layers (14, 14?) deposited on respective opposing first and second surfaces (12, 13) of a transparent substrate (11), the method comprising: directing a first laser beam (21) through one or more lenses (22) to a focal spot on or closely adjacent to the first surface (12) of the substrate (11), such that the focusing laser beam (21) passes through the second electrically conductive layer (14?) and the second surface (13) of the substrate (11); initiating relative movement between the first laser beam (21) and the substrate (11) in two axes in a plane orthogonal to the axis of the first laser beam (21) to scribe a first pattern in the first electrically conductive layer (14); directing a second laser beam (21?) through one or more lenses (22?) to a focal spot on or closely adjacent to the second surface (13) of the substrate (11), such that the focusing laser beam (21?) passes through the first eleType: GrantFiled: July 21, 2015Date of Patent: July 7, 2020Assignee: M-SOLV LITD.Inventor: David Charles Milne
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Patent number: 10682728Abstract: The invention relates to a method of processing a substrate. The substrate has on a first surface a device area with a plurality of devices partitioned by a plurality of division lines. A pulsed laser beam is applied to the substrate at least in a plurality of positions along each of the division lines, with a focal point located at a distance from the first surface in the direction from the first surface towards a second, opposite surface, so as to form a plurality of modified regions in the substrate along each of the division lines. The second surface of the substrate is then ground to adjust the substrate thickness. After forming modified regions and/or hole regions in the substrate, a plasma can be applied to the substrate so as to form a plurality of grooves extending along the division lines.Type: GrantFiled: July 25, 2018Date of Patent: June 16, 2020Assignee: DISCO CORPORATIONInventors: Karl Heinz Priewasser, Hitoshi Hoshino, Kenji Furuta
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Patent number: 10679910Abstract: A packaged wafer processing method includes a processing step of processing each division line formed on a packaged wafer by using a laser beam applying unit and a feeding mechanism, and indexing the wafer by a preset index amount “a” corresponding to the pitch of the division lines by using an indexing mechanism, thereby forming a laser processed groove along each division line. A correcting step images the next division line to be processed in an exposed peripheral portion of the wafer and the laser processed groove just formed along the present division line, at any arbitrary time during the processing step. The distance “b” between the next division line and the laser processed groove just formed is determined, and then a correction index amount “c” is calculated by using the deviation corresponding to the difference (a?b) between the preset index amount “a” and the distance “b”.Type: GrantFiled: January 27, 2017Date of Patent: June 9, 2020Assignee: DISCO CORPORATIONInventors: Makoto Tanaka, Xin Lu
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Patent number: 10679865Abstract: The method of dicing a wiring substrate that includes a core substrate having a front surface and a rear surface at least one of which is provided with an adhesive layer and a rim pattern thereon. The adhesive layer is provided with a laminate that has wiring layers and insulating layers, laminating. The rim pattern is provided with the insulating layers laminated thereon. The method includes steps of forming separation grooves by removing portions of the insulating layers laminated on the rim pattern to expose the rim pattern; exposing at least one of the front and rear surfaces of the core substrate by dissolving and removing the rim pattern of the groove bottoms; and dicing the core substrate exposed at groove bottoms, along cutting margins each being smaller than a groove width of each of the groove bottoms.Type: GrantFiled: June 19, 2019Date of Patent: June 9, 2020Assignee: TOPPAN PRINTING CO., LTD.Inventors: Koji Imayoshi, Yuki Nitta
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Patent number: 10672660Abstract: A method of manufacturing a semiconductor element includes: providing a wafer having a semiconductor layered body on a sapphire substrate; irradiating a laser light in an interior region of the sapphire substrate to create cracks in the sapphire substrate by performing a first scan to irradiate the laser light at a first depth with a first pulse energy to create a first modified region, and a second scan following the first scan to irradiate the laser light at a second depth with a second pulse energy greater than the first pulse energy along and within the first modified region; and dividing the wafer by extending the cracks to obtain a semiconductor element.Type: GrantFiled: February 22, 2018Date of Patent: June 2, 2020Assignee: NICHIA CORPORATIONInventors: Naoto Inoue, Sho Kusaka, Minoru Yamamoto, Masayuki Ibaraki, Hiroaki Tamemoto
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Patent number: 10658171Abstract: A laser processing apparatus including a condenser having a function of spherical aberration. Since the condenser has a function of spherical aberration, the focal point of a laser beam to be focused by the condenser and applied to a wafer can be continuously changed in position along the thickness of the wafer. Accordingly, a uniform shield tunnel composed of a fine hole and an amorphous region surrounding the fine hole can be formed so as to extend from the front side of the wafer to the back side thereof, by one shot of the laser beam.Type: GrantFiled: April 23, 2019Date of Patent: May 19, 2020Assignee: DISCO CORPORATIONInventor: Naotoshi Kirihara
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Patent number: 10639747Abstract: A method of manufacturing a light emitting element includes: providing a wafer that includes a substrate having a first principal face and a second principal face, a dielectric multilayer film disposed on the first principal face, and a semiconductor structure disposed on the second principal face; forming modified regions in the substrate by focusing a laser beam inside the substrate via the dielectric multilayer film, and allowing cracks to form from the modified regions to the dielectric multilayer film; subsequent to forming the modified regions in the substrate, removing regions of the dielectric multilayer film that contain cracks; and cleaving the wafer along regions where cracks were formed in the substrate.Type: GrantFiled: January 24, 2018Date of Patent: May 5, 2020Assignee: NICHIA CORPORATIONInventors: Naoto Inoue, Yoshitaka Sumitomo
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Patent number: 10610975Abstract: A method of removing material from an opposite side of workpiece includes directing a laser beam at a first side of the workpiece to remove the material from an opposite second side of the workpiece.Type: GrantFiled: February 15, 2018Date of Patent: April 7, 2020Assignee: GENTEX CORPORATIONInventors: Henry A. Luten, Kurtis L. Geerlings, Donald L. Bareman
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Patent number: 10576585Abstract: A method for processing a crystalline substrate to form multiple patterns of subsurface laser damage facilitates subsequent fracture of the substrate to yield first and second substrate portions of reduced thickness. Multiple (e.g., two, three, or more) groups of parallel lines of multiple subsurface laser damage patterns may be sequentially interspersed with one another, with at least some lines of different groups not crossing one another. Certain implementations include formation of multiple subsurface laser damage patterns including groups of parallel lines that are non-parallel to one another, but with each line remaining within ±5 degrees of perpendicular to the <1120> direction of a hexagonal crystal structure of a material of the substrate.Type: GrantFiled: February 12, 2019Date of Patent: March 3, 2020Assignee: CREE, INC.Inventors: Matthew Donofrio, John Edmond, Harshad Golakia
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Patent number: 10580700Abstract: A method for avoiding crack formation during a laser lift-off process is provided. The method includes: forming a composite glue layer on a carrier substrate in which the composite glue layer includes an ultraviolet glue and fillers therein and a Young's modulus of the fillers is greater than a Young's modulus of the ultraviolet glue; placing a semiconductor structure onto the composite glue layer in which the semiconductor structure includes a growth substrate, an epitaxial layer present on the growth substrate, and a metal layer present on the epitaxial layer, wherein placing the semiconductor structure makes the metal layer be in contact with and attached to the composite glue layer; and performing the laser lift-off process to separate the growth substrate from the epitaxial layer.Type: GrantFiled: February 15, 2019Date of Patent: March 3, 2020Assignee: MIKRO MESA TECHNOLOGY CO., LTD.Inventors: Yi-Ching Lin, Li-Yi Chen
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Patent number: 10573505Abstract: A method for producing a wafer from an ingot of single crystal SiC includes an end surface planarizing step of planarizing an end surface of the ingot, a separation layer forming step of setting a focal point of a laser beam having a transmission wavelength to single crystal SiC inside the ingot at a predetermined depth from the end surface of the ingot, the predetermined depth corresponding to the thickness of the wafer to be produced, and next applying the laser beam to the ingot to thereby form a separation layer for separating the wafer from the ingot, a hard plate providing step of providing a hard plate through an adhesive on the end surface of the ingot in which the separation layer has been formed, and a separating step of separating the wafer with the hard plate from the ingot along the separation layer.Type: GrantFiled: January 30, 2018Date of Patent: February 25, 2020Assignee: DISCO CORPORATIONInventor: Kazuya Hirata
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Patent number: 10515854Abstract: The present invention relates to a laser lift-off method of wafer. The method includes the steps as follows: focusing laser in an inside for a wafer (10) to form a plurality of cracking points (19), the plurality of cracking points (19) are located on a separating surface (20); and exerting, under a temperature of ?400K to 0K, forces with opposite directions to opposite sides of the wafer (10), thereby dividing the wafer (10) into two pieces along the separating surface (20).Type: GrantFiled: August 30, 2016Date of Patent: December 24, 2019Assignee: Han's Laser Technology Industry Group Co., Ltd.Inventors: Yanhua Wang, Changhui Zhuang, Fuhai Li, Wei Zeng, Wei Zhu, Jiangang Yin, Yunfeng Gao
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Patent number: 10510605Abstract: An embodiment method includes providing a wafer including a first integrated circuit die, a second integrated circuit die, and a scribe line region between the first integrated circuit die and the second integrated circuit die. The method further includes forming a kerf in the scribe line region and after forming the kerf, using a mechanical sawing process to fully separate the first integrated circuit die from the second integrated circuit die. The kerf extends through a plurality of dielectric layers into a semiconductor substrate.Type: GrantFiled: July 24, 2018Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fu-Chen Chang, Cheng-Lin Huang, Wen-Ming Chen
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Patent number: 10438898Abstract: A wafer processing method for processing a wafer has a front side and a back side, the front side of the wafer being formed with a plurality of crossing streets for defining a plurality of separate regions where a plurality of devices are individually formed. The wafer processing method includes the steps of first attaching a protective tape to the front side of the wafer, next heating the protective tape and the wafer, next applying a laser beam having a transmission wavelength to the wafer to the back side of the wafer along the streets, thereby forming a modified layer inside the wafer along each street, and next grinding the back side of the wafer, thereby reducing a thickness of the wafer to a predetermined thickness and also dividing the wafer into individual chips along each street where the modified layer is formed as a division start point.Type: GrantFiled: November 21, 2017Date of Patent: October 8, 2019Assignee: Disco CorporationInventors: Masaru Nakamura, Masamitsu Agari
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Patent number: 10421158Abstract: A method for processing a crystalline substrate to form multiple patterns of subsurface laser damage facilitates subsequent fracture of the substrate to yield first and second substrate portions of reduced thickness. Multiple (e.g., two, three, or more) groups of parallel lines of multiple subsurface laser damage patterns may be sequentially interspersed with one another, with at least some lines of different groups not crossing one another. Certain implementations include formation of multiple subsurface laser damage patterns including groups of parallel lines that are non-parallel to one another, but with each line remaining within ±5 degrees of perpendicular to the <1120> direction of a hexagonal crystal structure of a material of the substrate.Type: GrantFiled: February 12, 2019Date of Patent: September 24, 2019Assignee: CREE, INC.Inventors: Matthew Donofrio, John Edmond, Harshad Golakia
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Patent number: 10410924Abstract: Provided is a manufacturing process of an element chip, which comprises a preparation step for preparing a substrate including a semiconductor layer having first and second sides and a wiring layer on the first side thereof, the substrate having a plurality of dicing regions and element regions defined by the dicing regions, a scribing step for radiating a laser beam towards the first side of the wiring layer onto the dicing regions to form apertures exposing the semiconductor layer along the dicing regions, and a dicing step for dicing the substrate along the apertures into a plurality of the element chips, wherein the laser beam has a beam profile having a M-shaped distribution whose peripheral intensity is greater than a central intensity in a width direction of the laser beam along the dicing regions.Type: GrantFiled: January 3, 2018Date of Patent: September 10, 2019Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Hidehiko Karasaki, Hidefumi Saeki, Atsushi Harikai
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Patent number: 10410923Abstract: A method of processing a wafer includes forming a mask on portions of a face side of the wafer which correspond to devices; performing plasma etching on the face side of the wafer through the mask to etch areas of streets other than areas thereof corresponding to metal components, thereby forming grooves in the areas of the streets to a depth corresponding to a finished thickness of device chips; bonding a protective member for protecting the face side of the wafer, holding the face side of the wafer on a chuck table through the protective member and grinding a reverse side of the wafer until bottoms of the grooves are exposed, to fragmentize the wafer into the device chips; and picking up the device chips from the protective member, leaving remaining regions of the substrate which correspond to the metal components on the protective member.Type: GrantFiled: September 15, 2017Date of Patent: September 10, 2019Assignee: DISCO CORPORATIONInventor: Hideyuki Sandoh
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Patent number: 10396237Abstract: A light-emitting diode substrate and a manufacturing method thereof, and a display device are provided. The manufacturing method of a light-emitting diode (LED) substrate, including: disposing a supporting substrate supporting a plurality of LED units to be opposed to a receiving substrate so that a side of the supporting substrate facing the receiving substrate supports the plurality of LED units; and irradiating a side of the supporting substrate away from the receiving substrate with laser, stripping the LED units from the supporting substrate, and transferring the LED units onto the receiving substrate. The manufacturing method of the LED substrate can better transfer LED units from the supporting substrate onto the receiving substrate.Type: GrantFiled: January 6, 2017Date of Patent: August 27, 2019Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventors: Long Wang, Yanzhao Li, Chieh Hsing Chung, Jie Sun
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Patent number: 10381292Abstract: A lead frame includes a plate portion provided with a first surface and a second surface, the second surface being opposite to the first surface; a protruding portion integrally formed with the plate portion to be protruded from the first surface of the plate portion, wherein a surface of the lead frame includes a work affected layer existing region at which a work affected layer is formed, and a work affected layer non-existing region at which a work affected layer is not formed, wherein a front end surface of the protruding portion is the work affected layer existing region, wherein a region of the first surface at which the protruding portion is not formed is the work affected layer non-existing region, and wherein the second surface of the plate portion includes the work affected layer non-existing region.Type: GrantFiled: August 21, 2018Date of Patent: August 13, 2019Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Koji Watanabe, Kentaro Kaneko
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Patent number: 10363629Abstract: Methods of dicing semiconductor wafers are described. In an example, a method of dicing a wafer having a plurality of integrated circuits thereon involves dicing the wafer into a plurality of singulated dies disposed above a dicing tape. The method also involves forming a material layer over and between the plurality of singulated dies above the dicing tape. The method also includes expanding the dicing tape, wherein a plurality of particles is collected on the material layer during the expanding.Type: GrantFiled: June 1, 2017Date of Patent: July 30, 2019Assignee: Applied Materials, Inc.Inventors: Wei-Sheng Lei, Jungrae Park, Ajay Kumar, Brad Eaton
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Patent number: 10347534Abstract: Embodiments are provided herein for separating integrated circuit (IC) device die of a wafer, the wafer having a front side with an active device region and a back side, the active device region having a plurality of active devices arranged in rows and columns and separated by cutting lanes, the method including: attaching the front side of the wafer onto a first dicing tape; forming a modification zone within each cutting lane through the back side of the wafer, wherein each modification zone has a first thickness near a corner of each active device and a second thickness near a center point of each active device, wherein the second thickness is less than the first thickness; and propagating cracks through each cutting lane to separate the plurality of active devices.Type: GrantFiled: September 12, 2017Date of Patent: July 9, 2019Assignee: NXP B.V.Inventors: Martin Lapke, Hartmut Buenning, Sascha Moeller, Guido Albermann, Michael Zernack, Leo M. Higgins, III
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Patent number: 10328529Abstract: Employing laser scanning directions (20) that are oblique to and against a predominant gas flow direction (25) equalize the quality and waviness characteristics of orthogonal scribe lines (26) made by the laser scans. Positioning and sequence of multiple scan passes to form a feature wider than the width of a scribe line (26) can be controlled to enhance quality and waviness characteristics of the edges of the feature.Type: GrantFiled: August 10, 2016Date of Patent: June 25, 2019Assignee: ELECTRO SCIENTIFIC INDUSTRIES, INCInventors: Daragh Finn, Robert A. Ferguson
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Patent number: 10293433Abstract: A laser processing method which can efficiently perform laser processing while minimizing the deviation of the converging point of a laser beam in end parts of an object to be processed is provided.Type: GrantFiled: September 2, 2016Date of Patent: May 21, 2019Assignee: HAMAMATSU PHOTONICS K.K.Inventors: Kazuhiro Atsumi, Koji Kuno, Masayoshi Kusunoki, Tatsuya Suzuki, Kenshi Fukumitsu, Fumitsugu Fukuyo
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Patent number: 10269641Abstract: The present invention provides a method for plasma dicing a substrate. The substrate is provided with a top surface and a bottom surface, the top surface of the substrate having a plurality of street areas and at least one device structure. The substrate is placed onto a support film on a frame to form a work piece. A process chamber having a plasma source is provided. A work piece support is provided within the plasma process chamber. The work piece is placed onto the work piece support. A plasma is generated from the plasma source in the plasma process chamber. The work piece is processed using the generated plasma and a byproduct generated from the support film while the support film is exposed to the generated plasma.Type: GrantFiled: November 28, 2017Date of Patent: April 23, 2019Assignee: Plasma-Therm LLCInventors: Tsu-Wu Chiang, Russell Westerman
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Patent number: 10236402Abstract: In various embodiments, photovoltaic modules are hermetically sealed by providing a first glass sheet, a photovoltaic device disposed on the first glass sheet, and a second glass sheet, a gap being defined between the first and second glass sheets, disposing a glass powder within the gap, and heating the powder to seal the glass sheets.Type: GrantFiled: February 14, 2018Date of Patent: March 19, 2019Assignee: SIVA POWER, INC.Inventor: Markus Eberhard Beck
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Patent number: 10147646Abstract: A manufacturing process of an element chip comprises a preparation step for preparing a substrate, the substrate including first and second streets crossing each other to define a plurality of element regions. Also, it comprises a first shallow-groove formation step for radiating a laser beam along the first streets to form a plurality of first shallow grooves being shallower than a thickness of the substrate, a second shallow-groove formation step for radiating the laser beam along the second streets to form a plurality of second shallow grooves being shallower than a thickness of the substrate, a first groove formation step for radiating the laser beam along the first shallow grooves to form a plurality of first grooves, and a plasma dicing step for etching the substrate along the first grooves and the second shallow grooves by a plasma exposure to dice the substrate into a plurality of element chips.Type: GrantFiled: November 14, 2017Date of Patent: December 4, 2018Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Hidehiko Karasaki, Hidefumi Saeki, Atsushi Harikai