POWER DEVICE INTEGRATION ON A COMMON SUBSTRATE
A MOSFET includes an active region formed on an SOI substrate. A buried well is formed in the active region. A drain region having the first conductivity type is formed in the active region and spaced laterally from a source region and the buried well. A body region is formed in the active region between the source and drain regions on the buried well, and a drift region is formed in the active region between the drain and body regions on at least a portion of the buried well. A shielding structure is formed proximate the upper surface of the active region, overlapping a gate. During conduction, the buried well forms a PN junction with the drift region which, in conjunction with the shielding structure, depletes the drift region. The MOSFET is configured to sustain a linear mode of operation of an inversion channel formed under the gate.
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This patent application is a continuation-in-part of U.S. application Ser. No. 13/887,704 filed on May 6, 2013, entitled “Power Device Integration on a Common Substrate,” which claims the benefit of U.S. Provisional Patent Application Ser. No. 61/677,660 filed on Jul. 31, 2012, the disclosures of which are incorporated herein by reference in their entireties for all purposes.
FIELD OF THE INVENTIONThe present invention relates generally to electronic circuits, and more particularly relates to power device integration.
BACKGROUND OF THE INVENTIONModern portable electronic devices, including, but not limited to, smart phones, laptop and tablet computing devices, netbooks, etc., are battery operated and generally require power supply components for stabilizing the supply voltage applied to subsystems in the devices, such as, for example, microprocessors, graphic displays, memory chips, etc. The required power range is often between about 1 watt (W) and about 50 W.
Power supply/management components are usually partitioned into functional blocks; namely, control circuitry, driver stage and power switches. From the standpoint of device miniaturization, which is a desired objective of many portable electronic devices, it is advantageous to integrate the power supply/management components into a single integrated circuit (IC) chip. This solution is particularly dominant in very low power consumption products, where supply current is limited to a few hundreds of milliamperes (mA).
Typically, metal-oxide-semiconductor field-effect transistor (MOSFET) devices are used to implement the power switches. A MOSFET requires relatively few mask steps to be manufactured (e.g., less than about ten mask levels), whereas control circuitry in the IC usually requires a relatively large number of mask steps (e.g., about 26 to 36 mask levels) in comparison to MOSFET devices. Consequently, an allocation of a large die area to the power switch leads to a high product cost, which is undesirable.
SUMMARY OF THE INVENTIONEmbodiments of the invention provide novel semiconductor structure and techniques for facilitating the integration of circuits and/or components (e.g., drivers and power switches) on the same silicon substrate as corresponding control circuitry for implementing a power control device. To accomplish this, embodiments of the invention exploit features of a BiCMOS IC fabrication technology implemented on silicon-on-insulator (SOI) substrates with dielectric lateral isolation.
In accordance with an embodiment of the invention, a semiconductor structure includes at least one radio frequency (RF) MOSFET, the MOSFET comprising a first insulating layer formed on a substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A buried well having a second conductivity type is formed in the active region. A source region having the first conductivity type is formed in the active region proximate an upper surface of the active region, the source region being electrically connected with the buried well. A drain region having the first conductivity type is formed in the active region proximate the upper surface of the active region and spaced laterally from the source region and the buried well. The MOSFET further includes a body region having the second conductivity type formed in the active region between the source and drain regions on at least a portion of the buried well, at least a portion of the source region extending laterally into the body region, and a drift region having the first conductivity type formed in the active region between the drain and body regions on at least a portion of the buried well. A gate is formed above the active region of the MOSFET proximate the upper surface of the active region and at least partially between the source and drain regions. A shielding structure is formed proximate the upper surface of the active region, the shielding structure being spaced laterally from the gate and overlapping at least a portion of the gate, the shielding structure being electrically connected at one end to the source region. During conduction of the MOSFET under a potential applied to the drain region, the MOSFET is configured such that the buried well forms a PN junction with the drift region which, in conjunction with the shielding structure, depletes at least a portion of the drift region between the shielding structure and the buried well. The MOSFET is configured to induce a velocity saturation mode of operation in the depleted drift region when the potential applied to the drain region is larger than an applied gate bias to thereby sustain a linear mode of operation of an inversion channel formed under the gate for all operating conditions of the transistor.
In accordance with another embodiment of the invention, a method of forming an RF MOS transistor adaptable for integration with one or more other components on a common substrate includes: forming a first insulating layer on a substrate; forming an active region having a first conductivity type on at least a portion of the first insulating layer; forming a buried well having a second conductivity type in the active region; forming a source region having the first conductivity type in the active region proximate an upper surface of the active region, the source region being electrically connected with the buried well; forming a drain region having the first conductivity type in the active region proximate the upper surface of the active region and spaced laterally from the source region and the buried well; forming a body region having the second conductivity type in the active region between the source and drain regions on at least a portion of the buried well, at least a portion of the source region extending laterally into the body region; forming a drift region having the first conductivity type in the active region between the drain and body regions on at least a portion of the buried well; forming a gate above the active region proximate the upper surface of the active region and at least partially between the source and drain regions; forming a shielding structure formed proximate the upper surface of the active region, the shielding structure being spaced laterally from the gate and overlapping at least a portion of the gate, the shielding structure being electrically connected at one end to the source region; and configuring the RF MOS transistor such that during conduction under a potential applied to the drain region, the buried well forms a PN junction with the drift region which, in conjunction with the shielding structure, depletes at least a portion of the drift region between the shielding structure and the buried well, wherein the transistor is configured to induce a velocity saturation mode of operation in the depleted drift region when the potential applied to the drain region is larger than an applied gate bias to thereby sustain a linear mode of operation of an inversion channel formed under the gate for all operating conditions of the transistor.
Embodiments of the invention will become apparent from the following detailed description thereof, which is to be read in connection with the accompanying drawings.
The following drawings are presented by way of example only and without limitation, wherein like reference numerals (when used) indicate corresponding elements throughout the several views, and wherein:
It is to be appreciated that elements in the figures are illustrated for simplicity and clarity. Common but well-understood elements that may be useful or necessary in a commercially feasible embodiment may not be shown in order to facilitate a less hindered view of the illustrated embodiments.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTSEmbodiments of the invention will be described herein in the context of illustrative power management circuits and semiconductor fabrication methods for forming one or more components suitable for use in the illustrative power management circuits. It should be understood, however, that embodiments of the invention are not limited to the particular circuits and/or methods shown and described herein. Rather, embodiments of the invention are more broadly related to techniques for fabricating an integrated circuit in a manner which achieves high-frequency performance for a variety applications, such as, for example, radio frequency (RF) signal amplification, and advantageously reduces the physical size and cost of external components which may be used in conjunction with embodiments of the invention, such as, for example, a DC-DC power supply, an output filter, among other benefits. Moreover, it will become apparent to those skilled in the art given the teachings herein that numerous modifications can be made to the embodiments shown that are within the scope of the claimed invention. That is, no limitations with respect to the embodiments shown and described herein are intended or should be inferred.
For the purpose of describing and claiming aspects of the invention, the term MOSFET as used herein is intended to be construed broadly so as to encompass any type of metal-insulator-semiconductor field-effect transistor (MISFET). The term MOSFET is, for example, intended to encompass semiconductor field-effect transistors that utilize an oxide material as their gate dielectric, as well as those that do not. In addition, despite a reference to the term “metal” in the acronyms MOSFET and MISFET, a MOSFET and/or MISFET according to embodiments of the invention are also intended to encompass semiconductor field-effect transistors having a gate formed from a non-metal, such as, for instance, polysilicon.
Although implementations of the present invention described herein may be implemented using P-channel MISFETs (hereinafter called “PMOS” or “PFET” devices) and N-channel MISFETs (hereinafter called “NMOS” or “NFET” devices), as may be formed using a BiCMOS (bipolar complementary metal-oxide-semiconductor) fabrication process, it is to be appreciated that the invention is not limited to such transistor devices and/or such a fabrication process, and that other suitable devices, such as, for example, laterally diffused metal-oxide-semiconductor (LDMOS) devices, bipolar junction transistors (BJTs), etc., and/or fabrication processes (e.g., bipolar, complementary metal-oxide-semiconductor (CMOS), etc.), may be similarly employed, as will be understood by those skilled in the art given the teachings herein. Moreover, although embodiments of the invention are fabricated in a silicon wafer, embodiments of the invention can alternatively be fabricated on wafers comprising other materials, including but not limited to gallium arsenide (GaAs), gallium nitride (GaN), indium phosphide (InP), cadmium selenide (CdSe), cadmium telluride (CdTe), zinc sulfide (ZnS), etc.
As previously stated, when device current is limited to a few hundreds of milliamperes (i.e., device power consumption less than about two watts), the illustrative power stage can be monolithically integrated in a power management circuit architecture as shown in
For example,
The MCM approach of
Typically, a digital/analog process, such as, for example, a BiCMOS technology, is developed with an aim to maximize integration density and speed of signal processing. Optional power switches which can be designed using existing doping profiles and process steps generally cannot achieve sufficient performance in a power management application. The reduction of transistor on-resistance and the reduction of switching power loss require a dedicated optimization of the doping structure and use of a tailored sequence of process steps. This is usually done in the design of discrete power switches only. On the other hand, the processing of discrete power switches does not allow a monolithic integration of different electronic components, including NFETs, PFETs, bipolar junction transistors, P-N junction and Schottky diodes, etc.
Power management systems (e.g., DC-DC converters) typically use power switches to perform a high-frequency chopping of the input power and use an output filter comprising inductors and capacitors to stabilize the output voltage under variable load conditions. The higher the switching frequency, the better the power conversion performance, and smaller volume and cost of the required output filter. An increase in the switching frequency from about 1 megahertz (MHz) available today to about 5 MHz is desired but has not been achievable due to associated switching power losses in the power transistors used to implement the power switches which are attributable, at least in part, to device parasitic impedances (e.g., internal capacitance, inductance, and resistance).
It is known that the switching performance of power MOSFETs can be drastically improved by reducing internal capacitances and the charge stored in an internal body diode (see, e.g., U.S. Pat. Nos. 7,420,247 and 7,842,568).
Despite at least these technical advantages of the use of SOI substrates, the proposed transistors have not been widely adapted for manufacturing of discrete and/or integrated power MOSFETs due, at least in part, to an increased cost of the product. Moreover, acceptance of this approach is impeded by problems with long term reliability of the gate oxide, particularly at side corners of the gate, due primarily to hot carrier injection (HCI) under avalanche condition.
Thus, there is a need to develop an analog integration process focused on optimal switching performance of lateral power devices, which allows a monolithic integration of different types of power switches along with the associated driving stages and, optionally, some monitoring and protection functions. Power stages manufactured in accordance with aspects of the invention provide an enhanced power management solution for an input voltage range between about one volt and about ten volts (V), and an output current between about one ampere and about five amperes. Accordingly, the delivered power will cover a range roughly between three watts and 30 watts, although embodiments of the invention are not limited to this or any specific power range.
As will be explained in further detail below, embodiments of the invention described herein are based on a 20-volt BiCMOS technology implemented on SOI substrates with dielectric lateral isolation. The system partitioning presented in
The configuration of structure 800 beneficially allows integration of a variety of components, such as, for example, FETs, BJTs, PN diodes, Schottky diodes, resistors and capacitors. Each of the trenches 806 extends substantially vertically from a top surface 812 of the structure 800, through the active layer 804, and at least partially into the buried well 802. In alternative embodiments, the trenches 806 may extend through the buried well 802, into the buried oxide layer 818. The oxide lining 808 covering the sidewalls and bottom walls of the trenches 806 prevents direct electrical connection between the polysilicon material 810 filling the trenches and the buried well 802. Polysilicon fill 810 is preferably used as a gate terminal which can be biased as in, for example, FET and Schottky diode embodiments.
The buried well 802 has an important function in devices operative to sustain an applied blocking voltage, such as transistors or diodes. More particularly, a doping level, doping type and/or a location of the buried well 802 are configured in a manner which substantially pins (i.e., clamps) a breakdown voltage at the PN junction created between an upper right side (i.e., tip) of the buried well and an N− background doping of the active layer 804. By selectively controlling one or more characteristics of the buried well 802, an electric field distribution in the device is controlled.
The trench stripes 806 having walls (i.e., sidewalls and bottom walls) lined with gate oxide 808 are placed between main terminals of the power devices formed therein. The term “main terminals” as used herein is intended to broadly refer to external connections to the device, such as, for example, source and drain terminals, in the case of an MOS device, or anode and cathode terminals, in the case of a diode. The trench gates stripes 806 are formed (e.g., etched) substantially in parallel to a current path in the illustrative embodiment shown in
Doped polysilicon material 810 filling the trenches is used to create a gate bus connecting the gate regions to a gate terminal in a third dimension (not explicitly shown). For an NFET device formed according to an embodiment of the invention, the polysilicon material 810 is preferably doped with phosphorous, with a doping concentration of greater than about 1019/cm3, while for a PFET device, the polysilicon material is preferably doped with boron having a doping concentration of about 1019/cm3. The top surface of polysilicon gate layer 810 is shown optionally covered by a layer of silicide material 814 (e.g., titanium silicide (TiSi) or tungsten silicide (WSi)) with low resistivity, which can be deposited thereon using a known silicide deposition process (e.g., chemical vapor deposition (CVD), sputter deposition, etc.). The silicide layer 814, which forms a polycide electrode in the device 800, reduces a gate resistance of the device.
In a preferred embodiment, narrow gate trenches 806 are formed underneath the polycide electrode 814 along a path of current flow in the body region 804. In this manner, the trenches 806 increase an effective gate width in the MOSFET structure 800, among other advantages.
Another trench structure 816, formed deeper than trenches 806, is preferably used to create a lateral isolation region between integrated components. The deep trench structure 816, also referred to herein as a lateral isolation trench, can be formed, for example, by etching from the top surface 812 of the structure, through the active layer 804, to a buried oxide layer 818 formed on the substrate 801. The lateral isolation trench 816 can be filled with oxide, or a combination of oxide and polysilicon. An optional deep trench cut (i.e., etch), not explicitly shown, through the buried oxide layer 818 to the substrate 801 can be used as a substrate contact. This optional trench is preferably filled with doped polysilicon, or an alternative conductive material, to ensure good ohmic (i.e., low resistance) contact to the substrate 801.
A variety of electronic components can be created using an illustrative BiCMOS process flow, according to embodiments of the invention. Examples of some components which can be formed which incorporate aspects of the invention are described herein below with reference to
It is to be appreciated that, in the case of a simple MOS device, because the MOS device is symmetrical in nature, and thus bidirectional, the assignment of source and drain designations in the MOS device is essentially arbitrary. Therefore, the source and drain regions may be referred to generally as first and second source/drain regions, respectively, where “source/drain” in this context denotes a source region or a drain region. In an LDMOS device, which is generally not bidirectional, such source and drain designations may not be arbitrarily assigned.
The buried well 902, like the buried well 802 shown in
When the illustrative SOI LDMOS devices 600 and 700 shown in
With continued reference to
The shield 912 functions primarily as a field plate, distributing (e.g., stretching) an electric field distribution along a top oxide interface away from an edge (e.g., bottom right corner) of the gate 914 nearest the drain, and helps to reduce gate-to-drain capacitance, Cgd (a component of Miller capacitance seen at a gate terminal of a transistor which affects the switching speed of the transistor), at a positive bias of the drain. As a result of the shield 912, the peak electric field present at the drain side corner of the gate 914 will be split between the gate corner and the end of the field plate, thereby reducing the peak electric field value and inhibiting early injection of hot carriers into the gate oxide. Drain and source contacts 910 and 916, respectively, are formed as metal-filled vias reaching a patterned top metal layer (not explicitly shown, but implied) and form drain (D) and source (S) terminals, respectively, of the LDMOS device 900. Depleting the LDD extension region 908, with a positive bias applied to the drain contact 910, also helps reduce the gate-to-drain capacitance Cgd. A silicide layer 918 formed on the polysilicon gate structure 914, thereby forming a polycide layer (also referred to as silicided polysilicon), is used to create a gate bus leading to a gate terminal (G) located in a third dimension (not explicitly shown, but implied). The silicide layer 918 is preferably formed using a known deposition process (e.g., CVD, sputtering, etc.).
It is to be understood that by careful design of one or more of the gate, the shield/field plate 912 and the deep P well 902, the electric field in the vicinity of the gate and drain regions of the device can be effectively controlled as desired. This is particularly beneficial for forming a device (e.g., a radio frequency (RF) power transistor) suitable for use, for example, in a power amplifier application. In one or more embodiments of the invention, the LDD doping and thickness, the width of a spacer at the gate side wall (the oxide along the gate wall is thicker than underneath the field plate), the thickness of the oxide underneath the field plate, and/or the extension of the deep P region 902, among other parameters, are configured so that an effective pinching of the electric field in the LDD region adjacent to the gate is achieved. Pinching of the electric field is considered “effective,” according to one or more embodiments, when an electric potential of the drain does not affect the long-channel behavior of the MOS structure under the gate; i.e., the electric field within the inversion MOS channel is effectively decoupled from the electric field in the drift region LDD. As will be known by those skilled in the art, in a long-channel MOS device, there is no drain voltage dependence of the current once the drain voltage exceeds a prescribed threshold voltage, VT, of the device (i.e., VDS>>VT), but as channel length is reduced, drain-induced barrier lowering introduces drain voltage dependence that depends in a complex way upon the device geometry (e.g., channel doping, junction doping, etc.).
By way of example only and without limitation, in one or more embodiments, values of the device structure parameters, for an exemplary RF LDMOS transistor in a voltage range of about 12 to 60 volts, are as follows:
-
- maximum doping concentration in the LDD drift region is between about 1e17 atoms/cm3 and 4e17 atoms/cm3
- depth of LDD drift region is between about 0.2 μm and 0.4 μm
- spacer width at the gate side wall is between about 600 Å and 800 Å
- thickness of the oxide underneath the field plate over at least a portion of the drift region is between about 800 Å and 1200 Å
- extension of the deep P well beyond the gate edge on the drain side of the mask layout is between about 0.1 μm and 0.2 μm, where a sheet charge in the deep P well has a value larger than a sheet charge in the drift region. Here, sheet charge can be determined as mean doping concentration of the region multiplied by a thickness of the region; sheet charge is also referred to as charge density. Due to lateral diffusion, this extension will grow further under the drift region.
- design of a stack comprising the deep P well, N-LDD drift region, and a contour of the field plate structure is configured to satisfy a prescribed charge balance design rule requiring the charge in the deep P well to be sufficient to compensate a charge in the drift region (see, e.g., Fairchild Semiconductor Corporation Application Note AN-5232, entitled “New Generation Super-Junction MOSFETs, SuperFET® II and SuperFET® II Easy Drive MOSFETs for High Efficiency and Lower Switching Noise,” the disclosure of which is incorporated herein by reference in its entirety for all purposes). That is, the buried well, drift region, and the contour of the field plate structure are configured such that a net charge associated with the drift region is substantially balanced with a net charge associated with the deep P well (i.e., charge balancing). As a result, the drift region will be depleted by the PN junction formed by the deep well, in conjunction with the electrostatic impact of the field plate, even under a small positive drain bias. At a drain bias larger than the gate bias, the current flow through the depleted drift region is governed by a velocity saturation of the carriers.
In certain embodiments of the MOSFET described above in connection with
With reference now to
The connection of the deep P well 1408 and the polycide structure 1406 with the anode contact 1402 can be formed in a manner consistent with the connection 1252 shown in
The initial high-voltage capability and the avalanche ruggedness of the MOSFET structure are preserved, as the blocking voltage is sustained by the device structure on the cathode (former drain) side of the top polycide electrode, and the avalanche breakdown is clamped by the PN junction at the upper right corner (i.e., tip) of the deep P well 1408. The deep well 1408 is preferably an implanted well with a maximum doping concentration close to the Si/buried oxide interface. In a preferred embodiment, the maximum doping concentration is in the range of about 5e16 atoms/cm3 and 5e17 atoms/cm3, and the doping profile is configured to slope down towards the surface. It is to be appreciated, however, that the invention is not limited to a specific doping concentration or profile of the deep well 1408. The PN junction, in this embodiment, is formed by the deep P well 1408, N− active layer 1404, N region 1410 and N+ region 1412 toward the cathode terminal.
As described herein above in conjunction with the exemplary structures depicted in
With reference now to
The exemplary electronic components depicted in
With reference now to
Form a lateral dielectric isolation, also referred to as lateral trench isolation (LTI), by etching a trench through an active layer 2002, and filling the trench with oxide or a combination of oxide and polysilicon using a first mask step (LTI mask), as shown in
Deposit a thick field oxide and pattern it with an active area mask (active mask);
Deep implantation of boron, or an alternative dopant, to form a local deep well 2004, or alternatively an N+ well as a function of the dopant employed, with a concentration peak close to an interface between the P well (buried layer (BL)) 2004 and a buried oxide 2006 using a second mask step (deep well mask), as shown in
Pattern a mask to define a position of one or more gate trenches 2008 through the active layer 2002 into the buried well 2004 using a third mask step (trench gate mask), as shown in
Dope the polysilicon 2010 by phosphor implantation, or an alternative dopant, and anneal, and deposit a silicide layer 2012 on the top to reduce gate parasitic resistance, as shown in
Pattern the polycide layer 2012 to form a gate structure using a fourth mask level (polysilicon mask), as shown in
Implant boron to create a body region 2014 self-aligned to the edge of the polycide layer 2012 using a fifth mask step (body mask). Perform body diffusion, for example with a dedicated thermal anneal, as shown in
Implant phosphor or arsenic, or an alternative dopant, to create a lightly doped drain (LDD) extension 2016 at the other edge of the polycide layer 2012, opposite the edge used to form the body region 2014, using a sixth mask step (LDD mask), as shown in
Create highly doped source region 218 and drain region 220 in the body region 2014 and LDD extension 2016, respectively, by shallow arsenic implantation using a seventh mask step (source/drain mask), as shown in
Deposit field oxide 2022 over a top surface of the structure to assure a pre-defined spacing of a field plate 2024 from the surface of the drain extension region 2016 as shown in
Etch a shallow source contact trench 2026 using an eighth mask step (trench contact mask), and implant BF2 through the trench bottom (plug implant) to assure a good ohmic contact to the body and deep P regions, as shown in
Deposit and sinter a silicide film 2028 (e.g., Ti/WSix or Ti/TiN) lining the trench contact walls to create an electric short between source and body regions, as shown in
Pattern the contact silicide layer allowing a lateral extension to overlap the gate structure and create a field plate in the proximity of the LDD/oxide interface using a ninth mask step (field plate (FPL) mask), as shown in
Deposit an interlayer dielectric film (ILD) 2030 and apply a chemical-mechanical polishing step (CMP), or an alternative planarization process, to achieve a substantially planar top surface, as shown in
Etch via openings to access source, drain and gate contact areas using a tenth mask step (via mask). Fill vias with tungsten plugs (Ti/TiN/W), or an alternative conductive material, and apply a CMP step to planarize the top surface again, as shown in
Deposit and pattern a thick aluminum layer 2032 to create top electrodes with source, drain, and gate bus structures using an eleventh mask step (metal mask), as shown in
As discussed above, the processing of an N-channel LDMOS (NFET) transistor, in this embodiment, requires eleven mask levels (i.e., steps). The number of mask levels can be reduced to ten if the gate trench processing is omitted, as noted above. An optional mask can be used to create an electrical contact to the substrate by etching a deep trench through the active layer and the buried oxide, and filling it with oxide and doped polysilicon.
In order to create a P-channel MOSFET (PFET) using the same process flow, an additional mask subset is required. According to an illustrative embodiment of the invention, dedicated additional implants are made using the following mask levels: P-BL, P-POLYDOP, P-BODY, P-LDD, P-S/D, and P-CONT, where P-BL refers to a P-type doping of the buried layer, and P-POLYDOP refers to a mask level enabling P doping of Polysilicon for the PFET devices. In this case an additional N-POLYDOP mask level is used for the N+ doping of polysilicon for NFET devices.
Thus, the complete mask set in the exemplary BiCMOS process, according to embodiments of the invention, includes a maximum of 18 to 20 levels. This process flow allows a design of all the exemplary electronic components shown in
Processing details are well known to those skilled in the art and will therefore not be presented in further detail herein. By way of example only and without limitation, illustrative values for certain technological process parameters are listed below for the case of fabricating an exemplary 20-volt N-channel MOSFET:
-
- SOI substrate: lightly doped handle wafer (e.g., <5e14 cm−3), 0.3-μm buried oxide, and 0.6-μm active film with a doping of around 1e16 cm−3.
- Buried P well: Boron implant with a dose of 2e13 cm−2 and energy of 180 keV.
- Gate trench: 0.3 μm wide, 0.3 μm deep, and 0.3 μm long.
- Polycide layer: 0.3-μm polysilicon and 0.1-μm WSi2. Polycide stripe width 0.45 μm covering gate trench, or 0.35 μm for the case of the NFET without gate trenches
- Body region: Boron implant with a dose of 3e13 cm−2 and energy of 30 keV, followed by a second boron implant with a dose of 4e13 cm−2 and energy of 90 keV, and a 60 minutes anneal at 1000° C.
- LDD region: Phosphor implant with a dose of 6e12 cm−2 and energy of 60 keV.
- S/D regions: Arsenic implant with a dose of 5e15 cm−2 and energy of 30 keV.
- Contact trench: 0.4 μm wide and 0.25 μm deep.
- Silicide film: Ti (300 Angstroms (Å))/TiN (800 Å) annealed at 800° C.
- Plug implant: BF2 implant with a dose of 7e14 cm−2 and energy of 30 keV.
- Top metal: AlSiCu (1.5 μm thickness) patterned with 0.5 μm metal-to-metal spacing.
Features and advantages achieved according to embodiments of the invention include, but are not limited to, one or more of the following, although a given embodiment may not necessarily include all of these features or only these features:
-
- Exploits unique aspects of the BiCMOS process, like manufacturing of all integrated power devices with the same set of process steps;
- Doping and placement of the deep buried well defines the breakdown voltage and the location of avalanche impact ionization within all SOI power devices; i.e., a clamping diode is effectively integrated in the device, thereby assuring high avalanche ruggedness;
- BiCMOS process flow is defined with an aim to minimize SOI-LDMOS power losses in SMPS applications. Other power devices like PN diodes Schottky diodes, and BJTs are obtained by modification of the SOI-LDMOS structure;
- PN diode is obtained by removing N+ source region from N-channel LDMOS structure;
- Schottky diode is obtained by removing P body region from the PN diode structure;
- Bipolar transistor is obtained by removing the electrical short between source and body regions. Gate stack is connected to the body region and builds a current bus structure used as a base terminal;
- Chip scale package (CSP) or wafer level packaging (WLP) is adopted to create current terminals on the top surface of the finished die.
As previously stated, an important benefit of embodiments of the invention is the ability to easily facilitate the integration of power circuits and/or components (e.g., drivers and power switches) on the same silicon substrate as corresponding control circuitry for implementing a power control device. By way of example only and without limitation,
With reference to
In
With reference to
A semiconductor structure in accordance with one or more embodiments of the invention described herein is particularly well-suited for use in RF power amplifier applications, including, but not limited to, a power amplifier (PA) stage in an RF transceiver system. As is well known, in an RF power amplifier stage, the high-frequency transmit signal is amplified to a prescribed output power level and this amplified transmit signal is then radiated by an antenna where it is picked up by a receiver.
At low signal frequencies, power amplifiers may have relatively high levels of power gain, G, where G=Pout/Pin. Consequently, the direct contribution of the input signal power to the output signal power is significant and, therefore, is not included in the overall efficiency calculations of the PA. The basic efficiency, η, of the PA 2202 can be expressed as:
Linearity and efficiency are often considered two of the most important performance parameters of a PA system. Although linearity and efficiency are affected by one another, and are therefore not mutually exclusive parameters, there is at least one important conceptual difference between the two: linearity is typically dictated by specification whereas efficiency is typically unspecified. Stated another way, linearity is a parameter which must meet prescribed specifications while efficiency is merely a figure of merit of the PA system.
Linearity is often discussed in the context of power transfer characteristics, which defines the output power Pout of the PA 2202 as a function of the applied input power Pin. With reference to
The nonlinear relationship between output power and input power of the PA leads to distortion of the signal, as shown conceptually in
As is known by those skilled in the art, IMD occurs as two or more signals pass through a two-port network having a nonlinear transfer function. The spectrum at the output of the PA is comprised of the original signals and any additional spurious signals. These additional spurious signals can cause interference within the original system or in other systems. When the spurious signals are of sufficient amplitude, they can overpower the signal of interest, resulting in loss of transmitted information.
When operating at near-peak efficiency, the RF power amplifiers commonly used in wireless base stations distort the signals they amplify. These signal distortions not only affect signal clarity, they also make it difficult to keep the signal within its assigned frequency band, thus resulting in spurious emissions. Base station operators risk violating Federal Communications Commission (FCC) and international regulatory agency standards if they cannot keep spurious amplifier emissions from interfering with adjacent frequencies. Modern wideband code division multiple access (WCDMA) and long term evolution (LTE) carriers utilize wider bandwidths than their predecessors, thereby increasing the likelihood of interference from spurious emissions. To reduce spurious emissions and increase amplifier output linearity, base station operators can reduce the power output of the amplifier, but this practice also reduces efficiency. Amplifiers operating below their peak efficiency dissipate more energy, generally in the form of heat, sometimes requiring costly cooling equipment to prevent overheating.
These power amplifiers require a very high gain and ideally should add no or little distortion to the signal. But this is not practically possible, since increasing the power efficiency of the signal would increase the distortion added to the signal and drives the device into nonlinearity. For an efficient communication system, the power efficiency of the system should be increased without making the system nonlinear. This linearity is conventionally achieved with the help of various predistortion techniques implemented in conjunction with the power amplifiers to linearize both the gain and phase response of the system. Some known predistortion techniques include, for example, feedforward, feedback and digital predistortion.
Feedforward linearization is a commonly used technique where the spurious, distorted PA output spectrum is modified via two complementary circuits: (i) an input signal cancellation circuit; and (ii) a distortion or error cancellation circuit. Unfortunately, however, feedforward linearization generally provides only moderate power efficiency and suffers from limited bandwidth. Contemporary analog RF techniques such as diode predistortion that are primarily operated in an open-loop configuration are also only moderately effective, but relatively simple to implement. Currently, digital baseband adaptive predistortion is a popular method, as it permits application of a variety of corrective algorithms and ensures reasonable bandwidths for common cellular phone standards such as, for example, code division multiple access (CDMA) and Global System for Mobile Communications (GSM). For third generation (3G) cellular systems, spectrum-efficient techniques are employed, including WCDMA and orthogonal frequency division multiplexing (OFDM), having higher spectrum efficiency; however, instantaneous input power changes continuously leading to nonlinearity. This is due, at least in part, to the fact that an envelope of the signal continuously varies in WCDMA and OFDM systems, and hence the instantaneous input power also changes.
Feedforward linearization is not only moderately effective, but it almost doubles the cost and power dissipation of the PA. A combination of digital signal processing (DSP) and microprocessor control allows widespread use of complicated feedback and pre-distortion techniques to help improve efficiency and linearity, but this approach significantly increases the complexity and cost of the system, making it prohibitive for mobile commercial applications. Accordingly, the most straightforward way of improving performance in the context of an RF power amplifier application is to develop RF transistors with truly linear characteristics. However, conventional vertical MOSFETs previously used for base station applications are not capable of achieving this objective.
More recently, LDMOS transistors have essentially displaced silicon bipolar transistors in the cellular base station market, due primarily to improvements in efficiency and linearity and cost-performance benefits that LDMOS transistors provide. However, drift of the threshold voltage of a standard LDMOS transistor during operation at its quiescent operating point continue to plague the technology. In spite of several generations of technology improvements, manufacturers could only guarantee a change in threshold voltage of less than ten percent over a 20 year time period, despite using costly burn-in to stabilize the devices. The undesirable drift in device threshold voltage over time arises from an injection of hot carriers (e.g., hot electrons) into a gate oxide of the device, creating a reliability issue and barrier to obtaining stable performance.
Discrete LDMOS transistors, such as the LDMOS transistor 500 shown in
In a power amplifier application, an RF MOSFET formed in accordance with aspects of the invention is preferably configured to be easily integrated into an IC and to satisfy one or more of the following design features:
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- sustain maximum prescribed drain and gate voltage corresponding to the DC supply voltage used in the power amplifier. Table 1 below presents certain DC supply voltage levels (VDS) used in modern mobile WiFi systems.
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- produce high power gain allowing operation at popular carrier frequency bands, such as, for example, 900 MHz and 2 GHz. By way of illustration only and without limitation, an RF FET according to one or more embodiments exceeds 15 dB at 2 GHz.
- exhibit truly linear transfer characteristics
- provide high-efficiency power amplification
- enable monolithic integration of passive matching filters and/or other circuits for on-chip signal processing
- provide a layout and package assembly which facilitates heat dissipation
It is to be understood that the above features represent a non-limiting illustration of at least a portion of the benefits achievable according to aspects of the invention, and that other and/or additional features are similarly contemplated, as may become apparent to those skilled in the art given the teachings herein.
Relative to the layout of a power MOSFET, the layout of an RF FET formed in accordance with one or more embodiments of the invention is governed by a different set of design specifications. Table 2 below provides a comparison of illustrative layout rules which may be used in fabricating a power MOSFET and an RF FET for optimizing certain device parameters, including maximum drain current, ID,max, gate width, and die area.
The power MOSFET has a compact layout, with the active area determined by the target on-resistance RDS,on. In the case of a chip scale package (CSP), the maximum allowed current is limited by the current density along a perimeter of the solder bumps collecting current flowing through the source and drain terminals. In contrast, RF FETs do not necessarily target a minimal RDS,on. Rather, an objective of an RF FET is to achieve a target maximum output current without infringement of the electromigration limit of the current density in the source and drain fingers. To this end, the RF FET, according to one or more embodiments, is comprised of a larger number of shorter interdigitated fingers. By way of example only and without limitation,
With regard to gate width, as presented in Table 2 above, the gate width of a power MOSFET is generally maximized to reduce on-resistance RDS,on. By contrast, the gate width of an RF transistor should be minimized to reduce parasitic capacitances, primarily gate capacitances, as imposed by a prescribed maximum output current requirement.
The total die area of a power MOSFET is typically kept to a minimum in order to reduce manufacturing cost associated therewith. An RF transistor, on the other hand, is not as sensitive to cost. Consequently, the total die area of an RF transistor is not necessarily minimized, but rather die size is determined by heat dissipation constraints, which is dictated primarily by power dissipation in the device.
The exemplary layout of the RF MOSFET cell 2500 shown in
As previously explained in conjunction with
As is well known by those skilled in the art, when a strong enough electric field is applied to a semiconductor device, the carrier velocity in the device reaches a maximum value referred to as saturation velocity. When this occurs, the device is said to be in a state of velocity saturation. As the applied electric field increases from this point, the carrier velocity no longer increases because the carriers lose energy through increased levels of interaction with the crystal lattice. Charge carriers normally move at an average drift speed proportional to the electric field strength they experience temporally. The proportionality constant is known as mobility of the carrier, which is a property of the material forming the device. Velocity saturation in the LDD region 908 results in linear IDS (VGS) behavior, where IDS does not depend on drain voltage even for VDS values much higher than VGS. This behavior can be observed in
Comparing the two exemplary LDMOS transistor embodiments shown in
Specifically,
Calculated power and current gain for the exemplary LDMOS transistor 1050 according to one or more embodiments of the invention are shown in
To evidence further advantages associated with aspects of the invention, power amplifier efficiency has been calculated under the following operating conditions: drain-to-source voltage VDS=12.5 volts, output power POUT=3W at 500 MHz and gate-to-source voltage VGS adjusted to keep the same output power at different frequencies. This calculation has been performed for the exemplary LDMOS transistor 1050 shown in
A process flow for fabricating an N-channel RF LDMOS transistor having sufficient linearity to be used in a power amplifier application utilizes essentially the same fabrication steps as those illustrative process steps previously described in conjunction with
With regard to doping of the LDD and deep well regions in the vicinity of the drain side corner of the gate, a preferred LDD doping is achieved, according to one or more embodiments, by a double phosphor implant with a first dose of about 1e12 atoms/cm2 to about 3e12 atoms/cm2 and an energy of about 50 keV, and a second dose of about 3e12 atoms/cm2 to about 6e12 atoms/cm2 and an energy of about 170 keV; in a combination where the total charge density remains between about 4e12 and 8e12 atoms/cm2. The deep P-well is preferably created by a boron implant with a dose of about 2e13 atoms/cm2 and an energy of about 180 keV. With regard to the spacer along the sidewall of the gate, a thickness of the spacer is configured to be between about 600 Å and 800 Å. The field plate oxide is preferably configured having a thickness of between about 800 Å and 1200 Å.
Taking advantage of the BiCMOS technology used to form an RF transistor (e.g., RF switch, PA, etc.) according to one or more embodiments of the invention described herein, a silicon die comprising the novel RF transistor can be configured to integrate related circuitry, such as, for example, passive components to connect matching filters, etc., to the terminals of the RF transistor. Moreover, some circuitry can be monolithically integrated to perform signal processing prior to amplification. By way of example only and without limitation, the ability of the BiCMOS technology according to aspects of the invention to integrate a high-efficiency DC-DC converter, among other circuitry, provide an opportunity to fabricate a complete power amplifier module on one die.
More particularly,
With reference to
Thus, in accordance with one or more embodiments of the invention, an LDMOS transistor is configured for use in an RF power application. Among certain benefits achieved by the novel RF transistor include one or more of the following:
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- The RF MOSFET has the lateral LDMOS structure formed in accordance with the teachings herein fabricated within a thin silicon active layer on an upper surface of a buried oxide layer in an SOI substrate. The device structure comprises a deep P-well located along the interface with he buried oxide which is used to pin (i.e., control) a location of the avalanche breakdown between the tip of the P-well and the drain contact, as previously described. By uniquely configuring the transition region between the MOS channel and the lightly doped drift (LDD) region in a manner which prevents a drain potential from penetrating the MOS channel region. This solution effectively decouples the electric field within the inversion MOS channel from the electric field in the drift region LDD, thereby providing an LDMOS transistor which exhibits enhanced linearity, and is therefore well-suited for use in an RF amplifier application.
- A careful design of the transition region between the MOSFET channel and the LDD region assures depletion and pinch-off of the LDD region in the vicinity of the drain side corner of the gate as the applied increasing drain bias reaches gate voltage. This is achieved, according to one or more embodiments of the invention, by the electrostatic impact of the deep P-well and the field plate structure above the LDD region on the electric field distribution with the LDD region.
- During conduction under high positive drain bias, the inversion MOS channel operates in a linear mode whereas current flow through the depleted LDD region is limited by velocity saturation of charge carriers (e.g., electrons).
- Preservation of the linear mode of operation of the inversion MOS channel under all operating conditions (i.e., essentially all combinations of applied gate and drain voltages, VGS and VDS, respectively) results in linear, or near-linear, power transfer characteristics.
- Design of the RF MOSFET in a BiCMOS technology facilitates an integration of passive (and other) components to realize, for example, matching filters or other circuitry, monolithic integration of signal processing circuitry, and integration of a high-efficiency switching DC-DC converter on the same chip. Accordingly, aspects of the invention provide an opportunity to design fully integrated PA modules on a single silicon die.
- Having all electric terminals on the top surface of the die, it is possible to flip the die and exploit advantages of CSP assembly technology.
At least a portion of the embodiments of the invention may be implemented in an integrated circuit. In forming integrated circuits, identical die are typically fabricated in a repeated pattern on a surface of a semiconductor wafer. Each die includes at least one device described herein, and may include other structures and/or circuits. The individual die are cut or diced from the wafer, then packaged as an integrated circuit. One skilled in the art would know how to dice wafers and package die to produce integrated circuits. Integrated circuits so manufactured are considered part of this invention.
An integrated circuit in accordance with embodiments of the invention can be employed in essentially any application and/or electronic system in which power management techniques may be employed. Suitable applications and systems for implementing techniques according to embodiments of the invention may include, but are not limited to, portable devices, including smart phones, laptop and tablet computing devices, netbooks, etc. Systems incorporating such integrated circuits are considered part of embodiments of the invention. Given the teachings of embodiments of the invention provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of the techniques of embodiments of the invention.
The illustrations of embodiments of the invention described herein are intended to provide a general understanding of the structure of various embodiments, and they are not intended to serve as a complete description of all the elements and features of apparatus and systems that might make use of the structures described herein. Many other embodiments will become apparent to those skilled in the art given the teachings herein; other embodiments are utilized and derived therefrom, such that structural and logical substitutions and changes can be made without departing from the scope of this disclosure. The drawings are also merely representational and are not drawn to scale. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.
Embodiments of the inventive subject matter are referred to herein, individually and/or collectively, by the term “embodiment” merely for convenience and without intending to limit the scope of this application to any single embodiment or inventive concept if more than one is, in fact, shown. Thus, although specific embodiments have been illustrated and described herein, it should be understood that an arrangement achieving the same purpose can be substituted for the specific embodiment(s) shown; that is, this disclosure is intended to cover any and all adaptations or variations of various embodiments. Combinations of the above embodiments, and other embodiments not specifically described herein, will become apparent to those of skill in the art given the teachings herein.
The abstract is provided to comply with 37 C.F.R. §1.72(b), which requires an abstract that will allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description of Preferred Embodiments, it can be seen that various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim.
Given the teachings of embodiments of the invention provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of the techniques of embodiments of the invention. Although illustrative embodiments of the invention have been described herein with reference to the accompanying drawings, it is to be understood that embodiments of the invention are not limited to those precise embodiments, and that various other changes and modifications are made therein by one skilled in the art without departing from the scope of the invention.
Claims
1. A semiconductor structure comprising at least one radio frequency (RF) metal-oxide-semiconductor (MOS) transistor, the at least one RF MOS transistor comprising:
- a first insulating layer formed on a substrate;
- an active region having a first conductivity type formed on at least a portion of the first insulating layer;
- a buried well having a second conductivity type formed in the active region;
- a source region having the first conductivity type formed in the active region proximate an upper surface of the active region, the source region being electrically connected with the buried well;
- a drain region having the first conductivity type formed in the active region proximate the upper surface of the active region and spaced laterally from the source region and the buried well;
- a body region having the second conductivity type formed in the active region between the source and drain regions on at least a portion of the buried well, at least a portion of the source region extending laterally into the body region;
- a drift region having the first conductivity type formed in the active region between the drain and body regions on at least a portion of the buried well;
- a gate formed above the active region proximate the upper surface of the active region and at least partially between the source and drain regions; and
- a shielding structure formed proximate the upper surface of the active region, the shielding structure being spaced laterally from the gate and overlapping at least a portion of the gate, the shielding structure being electrically connected at one end to the source region;
- wherein the at least one RF MOS transistor is configured such that during conduction under a potential applied to the drain region, the buried well forms a PN junction with the drift region which, in conjunction with the shielding structure, depletes at least a portion of the drift region between the shielding structure and the buried well, and wherein the transistor is configured to induce a velocity saturation mode of operation in the depleted drift region when the potential applied to the drain region is larger than an applied gate bias to thereby sustain a linear mode of operation of an inversion channel formed under the gate for all operating conditions of the transistor.
2. The semiconductor structure of claim 1, wherein during conduction of the at least one RF MOS transistor under the potential applied to the drain region, the transistor is configured such that the buried well, in conjunction with the shielding structure, depletes a portion of the drift region under the shielding structure and current flow through the depleted drift region is limited by velocity saturation of carriers in the transistor.
3. The semiconductor structure of claim 1, wherein the buried well, drift region, and the contour of the shielding structure in the at least one RF MOS transistor are configured such that a net charge associated with the drift region is substantially balanced with a net charge associated with the buried well.
4. The semiconductor structure of claim 1, wherein the drift region in the at least one RF MOS transistor is configured to prevent a potential applied to the drain region from penetrating into a channel region formed in the body region under an applied gate potential to thereby substantially eliminate a drain current dependence on the potential applied to the drain region and to sustain a long-channel operation of the transistor with a linear relationship between drain current and gate-to-source voltage for a drain bias larger than a gate-to-source voltage of the transistor.
5. The semiconductor structure of claim 1, wherein the buried well in the at least one RF MOS transistor is configured to form a PN clamping diode operative to position a breakdown avalanche region between the buried well and the drain region, a breakdown voltage of the transistor being a function of one or more characteristics of the buried well.
6. The semiconductor structure of claim 1, further comprising a plurality of trench structures formed substantially vertically through the active region and into the buried well, each of the trenches including sidewalls and a bottom wall having an insulating material formed thereon, each of the trenches being filled with a conductive material, wherein a voltage applied to at least one of the plurality of trenches is operative to modulate a conduction current which flows between at least two of the trenches, an amplitude of the conduction current being controlled as a function of the applied voltage.
7. The semiconductor structure of claim 6, wherein at least a subset of the plurality of trenches is operative to one of deplete and enhance a gate/body interface formed in the semiconductor structure to thereby control a current flow through an inversion channel formed in the MOS transistor.
8. The semiconductor structure of claim 6, wherein at least a subset of the trenches are connected with the gate, and wherein a voltage applied to the gate is operative to generate a conduction current which flows between at least two of the trenches, an amplitude of the conduction current being controlled as a function of the applied gate voltage.
9. The semiconductor structure of claim 1, wherein the shielding structure is configured to extend an electric field distribution along a top oxide interface of the at least one RF MOS transistor away from an edge of the gate nearest the drain region.
10. The semiconductor structure of claim 1, wherein the buried well is formed proximate an interface between the first insulating layer and the active region.
11. The semiconductor structure of claim 1, further comprising control circuitry integrated with the at least one RF MOS transistor on the substrate, the control circuitry being configured to selectively control an operation of the at least one RF MOS transistor.
12. The semiconductor structure of claim 11, wherein the control circuitry comprises a DC-DC converter configured to provide a supply voltage to the RF MOS transistor.
13. The semiconductor structure of claim 12, further comprising a power amplifier including the at least one RF MOS transistor, wherein the control circuitry is configured to detect an amplitude of an input signal supplied to the power amplifier and the DC-DC converter is configured to control a level of the supply voltage to the RF MOS transistor as a function of the detected amplitude of an input signal.
14. The semiconductor structure of claim 1, wherein the drift region in the at least one RF MOS transistor is configured having a maximum doping concentration of between about 1e17 atoms/cm3 and 4e17 atoms/cm3, and having a depth of between about 0.2 μm and 0.4 μm.
15. The semiconductor structure of claim 1, wherein a spacer width at the gate side wall in the at least one RF MOS transistor is configured to be between about 600 Å and 800 Å.
16. The semiconductor structure of claim 1, wherein the at least one RF MOS transistor is configured having a thickness of oxide underneath the shielding structure of between about 800 Å and 1200 Å.
17. The semiconductor structure of claim 1, wherein the at least one RF MOS transistor is configured having an extension of the buried well beyond an edge of the gate nearest the drain region of between about 0.1 μm and 0.2 μm.
18. The semiconductor structure of claim 1, wherein the buried well in the at least one RF MOS transistor is configured such that a sheet charge in the buried well has a value larger than a sheet charge in the drift region.
19. The semiconductor structure of claim 1, wherein the buried well, drift region, and a contour of the shielding structure in the at least one RF MOS transistor are configured such that a net charge associated with the drift region is balanced with a net charge associated with the buried well.
20. The semiconductor structure of claim 1, wherein the drift region in the at least one RF MOS transistor is configured to have a doping level achieved using a double phosphor implant with a first dose of about 1e12 atoms/cm2 to about 3e12 atoms/cm2 and an energy of about 50 keV, and a second dose of about 3e12 atoms/cm2 to about 6e12 atoms/cm2 and an energy of about 170 keV.
21. A method of forming an RF MOS transistor adaptable for integration with other components on a common substrate, the method comprising:
- forming a first insulating layer on a substrate;
- forming an active region having a first conductivity type on at least a portion of the first insulating layer;
- forming a buried well having a second conductivity type in the active region;
- forming a source region having the first conductivity type in the active region proximate an upper surface of the active region, the source region being electrically connected with the buried well;
- forming a drain region having the first conductivity type in the active region proximate the upper surface of the active region and spaced laterally from the source region and the buried well;
- forming a body region having the second conductivity type in the active region between the source and drain regions on at least a portion of the buried well, at least a portion of the source region extending laterally into the body region;
- forming a drift region having the first conductivity type in the active region between the drain and body regions on at least a portion of the buried well;
- forming a gate above the active region proximate the upper surface of the active region and at least partially between the source and drain regions;
- forming a shielding structure proximate the upper surface of the active region, the shielding structure being spaced laterally from the gate and overlapping at least a portion of the gate, the shielding structure being electrically connected at one end to the source region; and
- configuring the RF MOS transistor such that during conduction under a potential applied to the drain region, the buried well forms a PN junction with the drift region which, in conjunction with the shielding structure, depletes at least a portion of the drift region between the shielding structure and the buried well, wherein the transistor is configured to induce a velocity saturation mode of operation in the depleted drift region when the potential applied to the drain region is larger than an applied gate bias to thereby sustain a linear mode of operation of an inversion channel formed under the gate for all operating conditions of the transistor.
Type: Application
Filed: Jun 3, 2014
Publication Date: Sep 25, 2014
Applicant: Azure Silicon LLC (Raleigh, NC)
Inventor: Jacek Korec (Sunrise, FL)
Application Number: 14/295,309
International Classification: H01L 29/78 (20060101); H01L 29/73 (20060101); H01L 29/10 (20060101); H01L 29/66 (20060101);