And Additional Electrical Device On Insulating Substrate Or Layer Patents (Class 438/155)
  • Patent number: 10714625
    Abstract: A semiconductor device capable of high speed operation is provided. Further, a highly reliable semiconductor device is provided. An oxide semiconductor having crystallinity is used for a semiconductor layer of a transistor. A channel formation region, a source region, and a drain region are formed in the semiconductor layer. The source region and the drain region are formed in such a manner that one or more of elements selected from rare gases and hydrogen are added to the semiconductor layer by an ion doping method or an ion implantation method with the use of a channel protective layer as a mask.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: July 14, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10707234
    Abstract: A semiconductor device comprises: a substrate; a first well region of a first conductivity type and a second well region of a second conductivity type formed horizontally adjacent to each other in the substrate; a buried insulation layer formed on the first well region and the second well region; a first semiconductor layer formed to vertically overlap the first well region, and a second semiconductor layer formed to vertically overlap the second well region, on the buried insulation layer; a first isolation layer formed between the first semiconductor layer and the second semiconductor layer on the buried insulation layer; and a conductive layer formed on the first semiconductor layer and the second semiconductor layer to extend over the first semiconductor layer and the second semiconductor layer.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: July 7, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hoon-Sung Choi, Dong-Il Park, Yuri Masuoka
  • Patent number: 10636892
    Abstract: A semiconductor structure including a substrate, a complementary metal oxide semiconductor (CMOS) device and a bipolar junction transistor (BJT) is provided. The CMOS device includes an N-type metal oxide semiconductor (NMOS) transistor and a P-type metal oxide semiconductor (PMOS) transistor disposed on the substrate. The BJT includes a collector, a base and an emitter. The collector is disposed in the substrate. The base is disposed on the substrate. The emitter is disposed on the base. A top surface of a channel of the NMOS transistor, a top surface of a channel of the PMOS transistor and a top surface of the collector of the BJT have the same height. The semiconductor structure can have better overall performance.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: April 28, 2020
    Assignee: United Microelectronics Corp.
    Inventors: Purakh Raj Verma, Kuo-Yuh Yang
  • Patent number: 10586947
    Abstract: An organic light emitting diode device can have an enhanced thin film encapsulation layer for preventing moisture from permeating from the outside. The thin film encapsulation layer can have a multilayered structure in which one or more inorganic layers and one or more organic layers are alternately laminated. A barrier can be formed outside of a portion of the substrate on which the organic light emitting diode is formed. The organic layers of the thin film encapsulation layer can be formed inside an area defined by the barrier.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: March 10, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Nam-Jin Kim, Chul-Hwan Park
  • Patent number: 10553589
    Abstract: An object of one embodiment of the present invention is to provide a semiconductor device with a novel structure in which stored data can be stored even when power is not supplied in a data storing time and there is no limitation on the number of times of writing. The semiconductor device includes a first transistor which includes a first channel formation region using a semiconductor material other than an oxide semiconductor, a second transistor which includes a second channel formation region using an oxide semiconductor material, and a capacitor. One of a second source electrode and a second drain electrode of the second transistor is electrically connected to one electrode of the capacitor.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: February 4, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Kiyoshi Kato
  • Patent number: 10361256
    Abstract: The present invention provides an OLED back plate and a manufacture method thereof. In the manufacture method of the OLED back plate of the present invention, by forming the planarization layer on the interlayer dielectric layer, and the planarization layer can serve as the mask of the etching process of the interlayer dielectric layer, and also can make the surface of the second source made on the surface thereof be flattened, which is advantageous to increase the area of the OLED light emitting area and to increase the aperture ratio. In the OLED back plate of the present invention, by forming the planarization layer on the interlayer dielectric layer, the surface of the second source made on the surface of the planarization layer is flattened, of which the OLED light emitting area is larger and the aperture ratio is higher.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: July 23, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Dan Bai, Yuanjun Hsu
  • Patent number: 10297672
    Abstract: A method of forming a 14 nm triple gate by adding a MG in the dual gate process and the resulting device are provided. Embodiments include forming an EG region, a MG region and a SG region in a first, second and third portions of a Si substrate, respectively; forming an IL over the EG, MG and SG regions; oxidizing the IL; forming a HK dielectric layer over the IL; performing PDA on the HK dielectric layer; forming a PSA TiN layer over the HK dielectric layer; forming an a-Si cap layer over the PSA TiN layer; forming a photoresist over the a-Si cap layer in the EG and SG regions; removing the a-Si cap layer in the MG region, exposing the PSA TiN layer; stripping the photoresist; and annealing the a-Si cap and PSA TiN layers.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: May 21, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Seong Yeol Mun, Kwan-Yong Lim, Kijik Lee
  • Patent number: 10211276
    Abstract: A display device includes: a substrate including a bending area located between a first region and a second region; an organic layer disposed over the substrate, an upper surface of the organic layer including an uneven surface in the bending area, the uneven surface including a plurality of protrusions; and a conductive layer extending from the first region to the second region across the bending area, the conductive layer being located over the organic layer and including a plurality of through holes.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: February 19, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Yoonsun Choi, Wonsuk Choi, Cheolsu Kim, Sangjo Lee
  • Patent number: 10192909
    Abstract: The present invention involves an array substrate structure and a manufacturing method of an array substrate. The manufacturing method of an array substrate, which comprises: Step 1, a substrate is provided, a first metal layer is manufactured on the substrate, and the first metal layer is patterned with a first photo-mask, to manufacture a gate electrode. Step 2, a gate insulating layer is manufactured on the substrate; an active layer is manufactured with a second photo-mask. Step 3, a first via is formed in the gate insulating layer corresponding to the first metal layer with a third photo-mask. Step 4, a second metal layer is manufactured on the gate insulating layer, the second metal layer is patterned with a fourth photo-mask, to manufacture source/drain electrodes, and a second via is formed on where corresponding to the active layer, the first metal layer and the second metal layer are connected at the first via.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: January 29, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Sikun Hao
  • Patent number: 9983706
    Abstract: The present invention provides a touch panel including a substrate, a patterned transparent conductive layer, and a color compensation layer. The patterned transparent conductive layer is disposed on the substrate, and includes a plurality of first sensing pads and a plurality of second sensing pads, and each first sensing pad and each sensing pad adjacent thereto have a first gap between them that exposing the substrate. The color compensation layer is disposed on the substrate in the first gap, and is not in contact with the patterned transparent conductive layer.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: May 29, 2018
    Assignee: HannsTouch Solution Incorporated
    Inventors: Sian-Zong Liao, Yao-Chih Chuang, Han-Ming Chen, Jia-Ming Ye
  • Patent number: 9985149
    Abstract: A performance of a semiconductor device is improved. In a method of manufacturing a semiconductor device, a first semiconductor portion and a second semiconductor portion made of silicon are formed on a base body via an insulation layer, and a third semiconductor portion including a semiconductor layer made of germanium is formed on the second semiconductor portion. Next, an insulation film is formed above the first semiconductor portion, an opening portion reaching the first semiconductor portion from an upper surface of the insulation film is formed, and a metal silicide layer is formed on a part of an upper surface of the first semiconductor portion exposed to the opening portion.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: May 29, 2018
    Assignees: RENESAS ELECTRONICS CORPORATION, PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIATION
    Inventors: Tatsuya Usami, Yoshiaki Yamamoto, Keiji Sakamoto, Tohru Mogami, Tsuyoshi Horikawa, Keizo Kinoshita
  • Patent number: 9899622
    Abstract: An organic light emitting diode display device includes: a substrate; a first antireflection line formed on the substrate and including a first metallic layer and a first inorganic layer stacked sequentially; a gate line formed on the first antireflection line; a gate insulation layer formed on the substrate and the gate line; a second antireflection line formed on the gate insulation layer and including a second metallic layer and a second inorganic layer stacked sequentially; a data line formed on the second antireflection line; and wherein the first inorganic layer connects the first metallic layer and the gate line electrically and the second inorganic layer connects the second metallic layer and the data line.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: February 20, 2018
    Assignee: LG Display Co., Ltd.
    Inventors: Jong-Kyun Lee, Hee-Seok Yang, Seung-Min Baik
  • Patent number: 9882058
    Abstract: A semiconductor device in which variation in electrical characteristics between transistors is reduced is provided. A transistor where a channel is formed in an oxide semiconductor layer is included, and a concentration of carriers contained in a region where the channel is formed in the oxide semiconductor layer is lower than or equal to 1×1015/cm3, preferably lower than or equal to 1×1013/cm3, more preferably lower than or equal to 1×1011/cm3, whereby an energy barrier height which electrons flowing between a source and a drain should go over converges at a constant value. In this manner, a semiconductor device in which variation in the electrical characteristics between the transistors is inhibited is provided.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: January 30, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Daisuke Matsubayashi, Toshimitsu Obonai, Noritaka Ishihara, Shunpei Yamazaki
  • Patent number: 9723236
    Abstract: A time at which a potential magnitude relationship between a first electrode and a second electrode is changed from a first relationship to a second relationship in a part of the plurality of pixels and a time at which a potential magnitude relationship between the first electrode and the second electrode is changed from the second relationship to the first relationship in the other part of the plurality of pixels overlap each other.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: August 1, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Seiji Hashimoto, Hidekazu Takahashi, Atsushi Furubayashi
  • Patent number: 9671245
    Abstract: According to an aspect, a display device includes a display unit that includes a dielectric material between two substrates that face each other and a plurality of pixel circuits that apply an electric field to the dielectric material according to an image input gradation for each of a plurality of pixels arranged in a matrix, and displays an image using the plurality of pixels; a capacitance detection unit that outputs a detection signal of a magnitude corresponding to a value of capacitance of the dielectric material; and a control device determines, on the basis of the detection signal from the capacitance detection unit, that the display is normal when a correlation value of the capacitance to the image input gradation is in a predetermined correlation.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: June 6, 2017
    Assignee: Japan Display Inc.
    Inventor: Toshiharu Matsushima
  • Patent number: 9627465
    Abstract: An organic light-emitting diode (OLED) display is disclosed. In one aspect, the display includes a substrate and an active pattern formed over the substrate and including first to fourth regions. A gate insulation layer is formed over the active pattern and the substrate, and a first gate electrode is formed over the gate insulation layer and partially overlapping the active pattern. The first gate electrode, the first region and the second region define a first transistor. A second gate electrode is formed on the same layer as the first gate electrode. The second gate electrode, the third region and the fourth region define a second transistor, and the second gate electrode, the second region and the fourth region define a third transistor. A first insulating interlayer is formed over the first gate electrode, the second gate electrode, and the gate insulation layer.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: April 18, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sun-Ja Kwon, Jae-Yong Lee, Ji-Eun Lee, So-Young Kang, Sang-Ho Seo
  • Patent number: 9595527
    Abstract: A deep trench (DT) opening is provided in a semiconductor substrate and then conducting carbon nanotubes are formed within the DT. Each conducting carbon nanotube is coated with a high k dielectric material and thereafter the remaining volume of the DT is filled with a conductive material.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: March 14, 2017
    Assignee: International Business Machines Corporation
    Inventor: Reinaldo A. Vega
  • Patent number: 9543397
    Abstract: An integrated circuit transistor is formed on and in a substrate. A trench in the substrate is at least partially filed with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region epitaxially grown above the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate is preferably of the silicon on insulator (SOI) type.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: January 10, 2017
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Walter Kleemeier, John Hongguang Zhang
  • Patent number: 9502487
    Abstract: An organic electroluminescent device includes a substrate including a plurality of pixel regions each having a light emission region and an element region; a plurality of thin film transistors (TFTs) including at least one switching TFT and at least one driving TFT in each element region; a planarization layer on the plurality of TFTs; a first electrode on the planarization layer and including first to third portions connected to one another, wherein the first and second portions are at each pixel region, and the third portion is at a neighboring pixel region; an organic light emitting layer on the first electrode; and a second electrode on the organic light emitting layer, wherein an end of the third portion overlaps the driving TFT of the neighboring pixel region.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: November 22, 2016
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Jae-Hun Jeong, Ki-Sul Cho
  • Patent number: 9368357
    Abstract: A method includes etching a dielectric layer to form an opening, with an underlying region underlying the dielectric layer exposed to the opening, and performing a bombardment to bombard a surface region of the underlying region through the opening. After the bombardment, the surface region is reacted with a process gas to form a reaction layer. An anneal is then performed to remove the reaction layer.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: June 14, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wei Chang, Hung-Chang Hsu, Chun-Hsien Huang, Yu-Hung Lin, Li-Wei Chu, Sheng-Hsuan Lin, Wei-Jung Lin, Yu-Shiuan Wang
  • Patent number: 9349870
    Abstract: A method for forming low-temperature polysilicon thin film, a thin film transistor and a display device are provided. The method for forming low-temperature polysilicon thin film comprises: depositing an amorphous silicon thin film on a base substrate; covering the amorphous silicon thin film with an anti-reflective optical film; performing photolithography and etching on the anti-reflective optical film such that light condensing structures are provided in an array on the anti-reflective optical film; and irradiating the amorphous silicon thin film with the anti-reflective optical film covered by laser light such that the amorphous silicon film is converted into the low-temperature polysilicon thin film.
    Type: Grant
    Filed: December 10, 2013
    Date of Patent: May 24, 2016
    Assignee: BOE TECHNOLOGY GROUP CO., LTD
    Inventors: Lei Wang, Xueyan Tian, Jang Soon Im
  • Patent number: 9318614
    Abstract: A method of fabricating MOTFTs includes positioning opaque gate metal on a transparent substrate, depositing gate dielectric material overlying the gate metal and a surrounding area, and depositing metal oxide semiconductor material thereon. Etch stop material is deposited on the semiconductor material. Photoresist defines an isolation area in the semiconductor material. Exposing the photoresist from the rear surface of the substrate and removing exposed portions to leave the etch stop material uncovered except for a portion overlying and aligned with the gate metal. Etching uncovered portions of the semiconductor material to isolate the TFT. Using the photoresist, selectively etching the etch stop layer to leave a portion overlying and aligned with the gate metal and defining a channel area in the semiconductor material. Depositing and patterning conductive material to form source and drain areas.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: April 19, 2016
    Assignee: CBRITE INC.
    Inventors: Chan-Long Shieh, Gang Yu, Fatt Foong
  • Patent number: 9312290
    Abstract: A sensor and its fabrication method are provided, wherein the sensor includes: a base substrate, a group of gate lines and a group of data lines arranged as crossing each other, and a plurality of sensing elements arranged in an array and defined by the group of gate lines and the group of data lines, each sensing element comprising a TFT device and a photodiode sensing device, wherein the TFT device is a top gate TFT. The photodiode sensing device includes: a receiving electrode connected with a source electrode, a photodiode disposed on the receiving electrode, a transparent electrode disposed on the photodiode, and a bias line disposed on and connected with the transparent electrode, the bias line is disposed as parallel to the gate line.
    Type: Grant
    Filed: November 23, 2012
    Date of Patent: April 12, 2016
    Assignee: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Shaoying Xu, Zhenyu Xie, Xu Chen
  • Patent number: 9257350
    Abstract: A method for fabricating a field effect transistor device includes removing a portion of a first semiconductor layer and a first insulator layer to expose a portion of a second semiconductor layer, wherein the second semiconductor layer is disposed on a second insulator layer, the first insulator layer is disposed on the second semiconductor layer, and the first semiconductor layer is disposed on the first insulator layer, removing portions of the first semiconductor layer to form a first fin disposed on the first insulator layer and removing portions of the second semiconductor layer to form a second fin disposed on the second insulator layer, and forming a first gate stack over a portion of the first fin and forming a second gate stack over a portion of the second fin.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: February 9, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Kangguo Cheng, Balasubramanian S. Haran, Shom Ponoth, Theodorus E. Standaert, Tenko Yamashita
  • Patent number: 9236398
    Abstract: Device structures and design structures for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A device region is formed in a trench and is coupled with a handle wafer of a semiconductor-on-insulator substrate. The device region extends through a buried insulator layer of the semiconductor-on-insulator substrate toward a top surface of a device layer of the semiconductor-on-insulator substrate. The device region is comprised of lightly-doped semiconductor material. The device structure further includes a doped region formed in the device region and that defines a junction. A portion of the device region is laterally positioned between the doped region and the buried insulator layer of the semiconductor-on-insulator substrate. Another region of the device layer may be patterned to form fins for fin-type field-effect transistors.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: January 12, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: William F. Clark, Jr., Robert J. Gauthier, Jr., Terence B. Hook, Junjun Li, Theodorus E. Standaert, Thomas A. Wallner
  • Patent number: 9219163
    Abstract: The display device includes a gate electrode, a gate insulating film provided over the gate electrode, a semiconductor film provided over the gate insulating film to overlap with the gate electrode, an island-shaped first insulating film provided over the semiconductor film to overlap with the gate electrode, a first conductive film provided over the semiconductor film, a pair of second conductive films which is provided over the semiconductor film and between which the first insulating film is sandwiched, and a second insulating film provided over the first insulating film, the first conductive film, and the pair of second conductive films. In the second insulating film and the semiconductor film, an opening portion which is positioned between the first conductive film and the one or the other of the pair of second conductive films is provided.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: December 22, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Patent number: 9214420
    Abstract: A carbon nanotube (CNT) array is patterned on a substrate. The substrate can be a microelectronic die, an interposer-type structure for a flip-chip, a mounting substrate, or a board. The CNT array is patterned by using a patterned metallic seed layer on the substrate to form the CNT array by chemical vapor deposition. The patterned CNT array can also be patterned by using a patterned mask on the substrate to form the CNT array by growing. A computing system that uses the CNT array for heat transfer from the die is also used.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: December 15, 2015
    Assignee: Intel Corporation
    Inventors: Nachiket Raravikar, Daewoong Suh
  • Patent number: 9184191
    Abstract: A method of forming a photonic device and resulting structure are described in which the photonic device is epitaxially grown over a substrate surface vertically, and laterally over trench isolation regions formed in the substrate surface.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: November 10, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Roy Meade
  • Patent number: 9177999
    Abstract: A vertical chain memory includes two-layer select transistors having first select transistors which are vertical transistors arranged in a matrix, and second select transistors which are vertical transistors formed on the respective first select transistors, and a plurality of memory cells connected in series on the two-layer select transistors. With this configuration, the adjacent select transistors are prevented from being selected by respective shared gates, the plurality of two-layer select transistors can be selected, independently, and a storage capacity of a non-volatile storage device is prevented from being reduced.
    Type: Grant
    Filed: October 5, 2014
    Date of Patent: November 3, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Yoshitaka Sasago, Masaharu Kinoshita, Takahiro Morikawa, Akio Shima, Takashi Kobayashi
  • Patent number: 9105664
    Abstract: An apparatus includes a substrate having a strained channel region, a dielectric layer over the channel region, first and second conductive layers over the dielectric layer having a characteristic with a first value, and a strain-inducing conductive layer between the conductive layers having the characteristic with a second value different from the first value. A different aspect involves an apparatus that includes a substrate, first and second projections extending from the substrate, the first projection having a tensile-strained first channel region and the second projection having a compression-strained second channel region, and first and second gate structures engaging the first and second projections, respectively. The first gate structure includes a dielectric layer, first and second conductive layers over the dielectric layer, and a strain-inducing conductive layer between the conductive layers.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: August 11, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Lung Cheng, Yen-Chun Lin, Da-Wen Lin
  • Patent number: 9082662
    Abstract: When forming sophisticated SOI devices, a substrate diode and a film diode are formed by using one and the same implantation mask for determining the well dopant concentration in the corresponding well regions. Consequently, during the further processing, the well dopant concentration of any transistor elements may be achieved independently from the well regions of the diode in the semiconductor layer.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: July 14, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Thilo Scheiper, Stefan Flachowsky
  • Patent number: 9082755
    Abstract: A method for forming a semiconductor device is disclosed. A method for forming a semiconductor device includes forming a first bit line contact over a semiconductor substrate, forming a second bit line contact that is coupled to the first bit line contact and has a larger width than the first bit line contact, and forming a bit line over the second bit line contact. When using the semiconductor device having a buried gate, although the bit line is formed to have a small width and the bit line pattern is misaligned, the method prevents incorrect coupling between a bit line and a bit line contact, so that it basically deteriorates unique characteristics of the semiconductor device.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: July 14, 2015
    Assignee: SK HYNIX INC.
    Inventor: Hyun Jung Kim
  • Patent number: 9064744
    Abstract: The specification and drawings present a new method, ASIC and computer/software related product (e.g., a computer readable memory) are presented for realizing conformal doping in embedded deep trench applications in the ASIC. A common SOI substrate with intrinsic or low dopant concentration is used for manufacturing such ASICs comprising a logic area having MOSFETs utilizing, for example, ultra thin body and box technology and an eDRAM area having deep trench capacitors with the conformal doping.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: June 23, 2015
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Hemanth Jagannathan, Sivananda Kanakasabapathy, Babar A. Khan
  • Patent number: 9053982
    Abstract: A cluster of semiconductor fins is formed on an insulator layer. A masking material layer is formed over the array of semiconductor fins such that spaces between adjacent semiconductor fins are filled with the masking material layer. A photoresist layer is applied over the masking material layer, and is lithographically patterned. The masking material layer is etched to physically expose a sidewall surface of a portion of an outermost semiconductor fin in regions not covered by the photoresist layer. A recessed region is formed in the insulator layer such that an edge of the recessed region is formed within an area from which a portion of the semiconductor fin is removed. The photoresist layer and the masking material layer are removed. Within the cluster, a region is provided that has a lesser number of semiconductor fins than another region in which semiconductor fins are not etched.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: June 9, 2015
    Assignee: International Business Machines Corporation
    Inventors: Markus Brink, Josephine B. Chang, Michael A. Guillorn, HsinYu Tsai
  • Publication number: 20150145052
    Abstract: Embodiments of systems, methods, and apparatus for improving ESD tolerance and switching time for semiconductor devices including metal-oxide-semiconductor (MOS) field effect transistors (FETs), and particularly to MOSFETs fabricated on semiconductor-on-insulator and silicon-on-sapphire substrates. Embodiments provide an improved FET structure having an accumulated charge sink (ACS) circuit, fast switching times, and improved ESD tolerance.
    Type: Application
    Filed: October 22, 2014
    Publication date: May 28, 2015
    Inventors: Eric S. Shapiro, Matt Allison
  • Patent number: 9035383
    Abstract: A method of fabricating an electronic device includes the following steps. At least one first set and at least one second set of nanowires and pads are etched in an SOI layer of an SOI wafer. A first gate stack is formed that surrounds at least a portion of each of the first set of nanowires that serves as a channel region of a capacitor device. A second gate stack is formed that surrounds at least a portion of each of the second set of nanowires that serves as a channel region of a FET device. Source and drain regions of the FET device are selectively doped. A first silicide is formed on the source and drain regions of the capacitor device that extends at least to an edge of the first gate stack. A second silicide is formed on the source and drain regions of the FET device.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: May 19, 2015
    Assignee: International Business Machines Corporation
    Inventors: Sarunya Bangsaruntip, Amlan Majumdar, Jeffrey W. Sleight
  • Publication number: 20150129877
    Abstract: An array substrate for LCD devices and a method of manufacturing the same are provided. By using a structure where an empty space is secured in a data line area as in a DRD structure in which the number of data lines is reduced by half, a capacitance is sufficiently secured by forming a sub storage capacitor in the data line area of the empty space, and thus, an area of a main storage capacitor can be reduced. Accordingly, the cost can be reduced, and moreover, an aperture ratio can be enhanced.
    Type: Application
    Filed: November 12, 2014
    Publication date: May 14, 2015
    Applicant: LG DISPLAY CO., LTD.
    Inventors: SungJun CHO, YoungMin JEONG, KyeuSang YOON, YeonHee JANG
  • Patent number: 9029950
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a substrate, a first source/drain region, a second source/drain region, a first stack structure and a second stack structure. The first source/drain region is formed in the substrate. The second source/drain region is formed in the substrate. The first stack structure is on the substrate between the first source/drain region and the second source/drain region. The first stack structure comprises a first dielectric layer and a first conductive layer on the first dielectric layer. The second stack structure is on the first stack structure. The second stack structure comprises a second dielectric layer and a second conductive layer on the second dielectric layer.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: May 12, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Chien-Wen Chu, Wing-Chor Chan, Shyi-Yuan Wu
  • Publication number: 20150118804
    Abstract: A vertical chain memory includes two-layer select transistors having first select transistors which are vertical transistors arranged in a matrix, and second select transistors which are vertical transistors formed on the respective first select transistors, and a plurality of memory cells connected in series on the two-layer select transistors. With this configuration, the adjacent select transistors are prevented from being selected by respective shared gates, the plurality of two-layer select transistors can be selected, independently, and a storage capacity of a non-volatile storage device is prevented from being reduced.
    Type: Application
    Filed: October 5, 2014
    Publication date: April 30, 2015
    Inventors: Yoshitaka SASAGO, Masaharu KINOSHITA, Takahiro MORIKAWA, Akio SHIMA, Takashi KOBAYASHI
  • Patent number: 9018052
    Abstract: An integrated circuit comprising an N+ type layer, a buffer layer arranged on the N+ type layer; a P type region formed on with the buffer layer; an insulator layer overlying the N+ type layer, a silicon layer overlying the insulator layer, an embedded RAM FET formed in the silicon layer and connected with a conductive node of a trench capacitor that extends into the N+ type layer, the N+ type layer forming a plate electrode of the trench capacitor, a first contact through the silicon layer and the insulating layer and electrically connecting to the N+ type layer, a first logic RAM FET formed in the silicon layer above the P type region, the P type region functional as a P-type back gate of the first logic RAM FET, and a second contact through the silicon layer and the insulating layer and electrically connecting to the P type region.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: April 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Bruce B. Doris, Terence B. Hook, Ali Khakifirooz, Pranita Kerber, Tenko Yamashita, Chun-Chen Yeh
  • Publication number: 20150108573
    Abstract: A method for making a semiconductor device may include forming, on a substrate, at least one stack of alternating first and second semiconductor layers. The first semiconductor layer may comprise a first semiconductor material and the second semiconductor layer may comprise a second semiconductor material. The first semiconductor material may be selectively etchable with respect to the second semiconductor material. The method may further include removing portions of the at least one stack and substrate to define exposed sidewalls thereof, forming respective spacers on the exposed sidewalls, etching recesses through the at least one stack and substrate to define a plurality of spaced apart pillars, selectively etching the first semiconductor material from the plurality of pillars leaving second semiconductor material structures supported at opposing ends by respective spacers, and forming at least one gate adjacent the second semiconductor material structures.
    Type: Application
    Filed: October 23, 2013
    Publication date: April 23, 2015
    Applicants: GLOBALFOUNDRIES INC., STMicroelectronics, Inc.
    Inventors: Qing Liu, Xiuyu Cai, Ruilong Xie
  • Patent number: 9012273
    Abstract: A flat panel display device having increased capacitance and a method of manufacturing the flat panel display device are provided. A flat panel display device includes: a plurality of pixel areas, each located at a crossing region of a gate line, a data line, and a common voltage line; a thin film transistor (TFT) located at a region where the gate line and the data line cross each other, the TFT including a gate electrode, a source electrode, and a drain electrode; and a storage capacitor located at a region where the common voltage line and the drain electrode cross each other, the storage capacitor including first, second, and a third storage electrodes.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: April 21, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Zhi-Feng Zhan, Seung-Gyu Tae, Deok-Hoi Kim
  • Patent number: 9012900
    Abstract: An organic light emitting diode display device capable of improving capacitance Cst of a storage capacitor and transmittance and a method of fabricating the same are disclosed. The organic light emitting diode display device includes a driving thin film transistor (TFT) formed on the substrate, a passivation film formed to cover the TFT driver, a color filter formed on the passivation film in a luminescent region, a planarization film formed to cover the color filter, a transparent metal layer formed on the planarization film, an insulating film formed on the transparent metal layer, a first electrode connected to the TFT driver and overlapping the transparent metal layer while interposing the insulating film therebetween, an organic light emitting layer and a second electrode which are sequentially formed on the first electrode. The transparent metal layer, the insulating film, and the first electrode constitute a storage capacitor in the luminescent region.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: April 21, 2015
    Assignee: LG Display Co., Ltd.
    Inventors: Jung-Sun Beak, Jeong-Oh Kim, Yong-Min Kim
  • Publication number: 20150102349
    Abstract: A thin film transistor array substrate including a first TFT including a first active layer, a gate electrode, a first source electrode and a first drain electrode, a second TFT including a second active layer, a floating gate electrode, a control gate electrode, a second source electrode, and a second drain electrode, a capacitor including a first electrode and a second electrode, and a capping layer contacting a portion of the first electrode, the capping layer and the second electrode being on a same layer, is disclosed. A method of manufacturing thin film transistor array substrate is also disclosed.
    Type: Application
    Filed: April 1, 2014
    Publication date: April 16, 2015
    Applicant: SAMSUNG DISPLAY CO., LTD.
    Inventors: Wang-Woo Lee, Moo-Soon Ko, Do-Hyung Kim, Min-Woo Woo, Il-Jeong Lee, Jeong-Ho Lee, Young-Woo Park
  • Publication number: 20150104910
    Abstract: A TFT flat sensor comprises pixel units each comprising: a common electrode and a common electrode insulating layer on a substrate, wherein a first via hole is provided in the common electrode insulating layer at a location corresponding to the common electrode; a gate electrode on the common electrode insulating layer; a first conductive film layer on the common electrode and the gate electrode wherein the first conductive film layer contacts the common electrode through a first via hole; a gate insulating layer, an active layer, a drain electrode and a source electrode, a second conductive film layer, a protection layer and a third conductive film layer on the first conductive film layer; a second via hole is provided in the protection layer at a location corresponding to the source electrode through which the third conductive film layer contacts the source electrode.
    Type: Application
    Filed: November 21, 2014
    Publication date: April 16, 2015
    Inventors: Shaoying XU, Zhenyu XIE, Xu CHEN
  • Patent number: 9006024
    Abstract: In a semiconductor device in which transistors are formed in a plurality of layers to form a stack structure, a method for manufacturing the semiconductor device formed by controlling the threshold voltage of the transistors formed in the layers selectively is provided. Further, a method for manufacturing the semiconductor device by which oxygen supplying treatment is effectively performed is provided. First oxygen supplying treatment is performed on a first oxide semiconductor film including a first channel formation region of a transistor in the lower layer. Then, an interlayer insulating film including an opening which is formed so that the first channel formation region is exposed is formed over the first oxide semiconductor film and second oxygen supplying treatment is performed on a second oxide semiconductor film including a second channel formation region over the interlayer insulating film and the exposed first channel formation region.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: April 14, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kengo Akimoto
  • Patent number: 8993385
    Abstract: A method to construct a semiconductor device, the method including: forming a first layer including mono-crystallized semiconductor and first logic circuits; forming a second layer including a mono-crystallized semiconductor layer, the second layer overlying the first logic circuits; forming transistors on the second layer; forming connection paths from the second transistors to the first transistors, where the connection paths include a through layer via of less than 200 nm diameter; and connecting the first logic circuits to an external device using input/output (I/O) circuits, the input/output (I/O) circuits are constructed on the second mono-crystallized semiconductor layer.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: March 31, 2015
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Zeev Wurman
  • Patent number: 8994086
    Abstract: The invention provides a semiconductor device which is non-volatile, easily manufactured, and can be additionally written. A semiconductor device of the invention includes a plurality of transistors, a conductive layer which functions as a source wiring or a drain wiring of the transistors, and a memory element which overlaps one of the plurality of transistors, and a conductive layer which functions as an antenna. The memory element includes a first conductive layer, an organic compound layer and a phase change layer, and a second conductive layer stacked in this order. The conductive layer which functions as an antenna and a conductive layer which functions as a source wiring or a drain wiring of the plurality of transistors are provided on the same layer.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: March 31, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiroko Abe, Yukie Nemoto, Ryoji Nomura, Mikio Yukawa
  • Patent number: 8987073
    Abstract: Device structures, design structures, and fabrication methods for a metal-oxide-semiconductor field-effect transistor. A gate structure is formed on a top surface of a substrate. First and second trenches are formed in the substrate adjacent to a sidewall of the gate structure. The second trench is formed laterally between the first trench and the first sidewall. First and second epitaxial layers are respectively formed in the first and second trenches. A contact is formed to the first epitaxial layer, which serves as a drain. The second epitaxial layer in the second trench is not contacted so that the second epitaxial layer serves as a ballasting resistor.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: March 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: James P. Di Sarro, Robert J. Gauthier, Jr., Junjun Li
  • Patent number: 8980703
    Abstract: A method of forming a semiconductor structure is provided. A substrate having a cell area and a periphery area is provided. A stacked structure including a gate oxide layer, a floating gate and a first spacer is formed on the substrate in the cell area and a resistor is formed on the substrate in the periphery area. At least two doped regions are formed in the substrate beside the stacked structure. A dielectric material layer and a conductive material layer are sequentially formed on the substrate. A patterned photoresist layer is formed on the substrate to cover the stacked structure and a portion of the resistor. The dielectric material layer and the conductive material layer not covered by the patterned photoresist layer are removed, so as to form an inter-gate dielectric layer and a control gate on the stacked structure, and simultaneously form a salicide block layer on the resistor.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: March 17, 2015
    Assignee: Maxchip Electronics Corp.
    Inventors: Chen-Chiu Hsu, Tung-Ming Lai, Kai-An Hsueh, Ming-De Huang