METHODS OF FORMING A FINFET SEMICONDUCTOR DEVICE BY PERFORMING AN EPITAXIAL GROWTH PROCESS
A method of forming a FinFET device involves performing an epitaxial growth process to form a layer of semiconducting material on a semiconducting substrate, wherein a first portion of the layer of semiconducting material will become a fin structure for the FinFET device and wherein a plurality of second portions of the layer of semiconducting material will become source/drain structures of the FinFET device, forming a gate insulation layer around at least a portion of the fin structure and forming a gate electrode above the gate insulation layer.
1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of forming a FinFET semiconductor device by performing an epitaxial growth process.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET is a device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. If a voltage that is less than the threshold voltage of the device is applied to the gate electrode, then there is no current flow through the device (ignoring undesirable leakage currents, which are relatively small). However, when a voltage that is equal to or greater than the threshold voltage of the device is applied to the gate electrode, the channel region becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region. The above description is applicable for both the N-type FET as well as the P-type FET, except that the polarity of voltage in operation and the doping type of the source, the channel and the drain regions are correspondingly reversed. In so-called CMOS (Complementary Metal Oxide Semiconductor) technology, both N-type and P-type MOSFETs (which are referred to as being “complementary” to each other) are used in integrated circuit products. CMOS technology is the dominant technology as it relates to the manufacture of almost all current-day large scale logic and memory circuits.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the channel from being adversely affected by the electrical potential of the drain, which is commonly referred to as a “punch-through” of the electrical potential from the drain to the source and leads to larger leakage currents. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a planar FET, which has a planar structure, there are so-called three-dimensional (3D) devices, such as an illustrative FinFET device, which is a three-dimensional structure. More specifically, in a FinFET, a generally vertically positioned, fin-shaped active area is formed and a gate electrode encloses both of the sides and the upper surface of the fin-shaped active area to form a “tri-gate” structure so as to use a channel having a 3D “fin” structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, is positioned at the top of the fin and the FinFET device only has a dual-gate structure. Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the depletion width in the “fin” channel (as a result of the better electrostatic characteristics of the tri-gate or dual-gate structure around the fin channel) and thereby reduce so-called short channel effects. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to reduce at least some short channel effects.
In one embodiment, FinFET devices have been formed on so-called silicon-on-insulator (SOI) substrates. An SOI substrate includes a bulk silicon layer, an active layer and a buried insulation layer made of silicon dioxide (a so-called “BOX” layer) positioned between the bulk silicon layer and the active layer. Semiconductor devices are formed in and above the active layer of an SOI substrate. The fins are formed in the active layer and the buried insulation layer provides good isolation between the source and drain in FinFET adjacent fins. The processes used to form FinFET devices on SOI substrates have relatively good compatibility with various processes that are performed when forming planar transistor devices in CMOS applications. For example, in both applications, the gate stack and the gate insulation layer can be made of the same materials (as in planar CMOS on SOI), e.g., poly-SiON or high-k/metal-gate (HKMG), and both applications may involve performing various epitaxial silicon growth processes (e.g., SiGe for PMOS and raised SD for NMOS), as well as the formation of epi-silicon material on the fins so as to define the source/drain regions from the FinFET devices that provide good resistance and desirable stress characteristics. When an appropriate voltage is applied to the gate electrode of a FinFET device, the surfaces (and the inner portion near the surface) of the fins, i.e., the substantially vertically oriented sidewalls and the top upper surface of the fin with inversion carriers, contributes to current conduction. In a FinFET device, the “channel-width” is approximately two times (2×) the vertical fin-height plus the width of the top surface of the fin, i.e., the fin width. Multiple fins can be formed in the same footprint as that of a planar transistor device. Accordingly, for a given plot space (or footprint), FinFETs tend to be able to generate significantly stronger drive current than planar transistor devices. Additionally, the leakage current of FinFET devices after the device is turned “OFF” is significantly reduced as compared to the leakage current of planar transistor MOSFETs due to the superior gate electrostatic control of the “fin” channel on FinFET devices. In short, the 3D structure of a FinFET device is a superior MOSFET structure as compared to that of a planar MOSFET, especially in the 20 nm CMOS technology node and beyond.
Recently, device manufacturers have become more interested in forming FinFET devices on bulk silicon substrates in an effort to reduce costs and to make the FinFET formation processes more compatible with planar CMOS process flows on bulk substrates. However, use of a bulk substrate typically requires the formation of shallow trench isolation (STI) regions in the substrate to electrically isolate the devices. The fins of a FinFET device only need to have a relatively shallow or small fin height, e.g., about 20-40 nm. In contrast, the STI regions that are formed to electrically isolate adjacent FinFET devices are typically required to be much deeper (or taller), e.g., about 100-300 nm, than the height of the fins. Typically, a plurality of trenches are formed in the substrate to define the areas where STI regions will be formed and to define the initial structure of the fins, and these trenches are typically formed in the substrate during the same process operation for processing simplicity. The trenches are desirably designed with the same pitch (for better resolution for lithography) and they are formed to the same depth and width (for processing simplicity), wherein the depth of the trenches is sufficient for the needed fin height and deep enough to allow formation of an effective STI region. After the trenches are formed, a layer of insulating material, such as silicon dioxide, is formed so as to overfill the trenches. A chemical mechanical polishing (CMP) process is then performed to planarize the upper surface of the insulating material with the top of the fins (or the top of a patterned hard mask). Thereafter, an etch-back process is performed to recess the layer of insulating material between the fins and thereby expose the upper portions of the fins, which corresponds to the final fin height of the fins.
The above-described process flow resulted in the fin height for all FinFET devices, both P-type and N-type, being substantially the same. Additionally, the above-described process flow necessitated the formation of relatively deep trenches and created problems in filling such deep, high aspect ratio trenches. Moreover, the channel width of the P-type and N-type FinFET devices could not be selectively adjusted without adding additional masking and etching steps, etc., thereby depriving device designers of an economical means of forming N-type and P-type FinFET devices with channel widths which are adjustable by virtue of the process.
The present disclosure is directed to various methods of forming a FinFET semiconductor device by performing an epitaxial growth process that may solve or reduce one or more of the problems identified above.
SUMMARY OF THE INVENTIONThe following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
Generally, the present disclosure is directed to various methods of forming a FinFET semiconductor device by performing an epitaxial growth process. One illustrative method of forming a FinFET device involves performing an epitaxial growth process to form a layer of semiconducting material on a semiconducting substrate, wherein a first portion of the layer of semiconducting material will become a fin structure for the FinFET device and wherein a plurality of second portions of the layer of semiconducting material will become source/drain structures of the FinFET device, forming a gate insulation layer around at least a portion of the fin structure and forming a gate electrode above the gate insulation layer.
Another illustrative method involves forming a masking layer above a semiconducting substrate, wherein the masking layer exposes a first exposed region of the substrate where at least one fin structure for the device will be formed and a plurality of second exposed regions where a plurality of source/drain structures for the device will be formed, with the masking layer in position, performing an epitaxial growth process to form a layer of semiconducting material on the first and second exposed regions of the substrate to thereby form the fin structure and the plurality of source/drain structures, performing a process operation to reduce an initial thickness of the masking layer (so that the fin is revealed with the fin height equal to the thickness reduction of the masking layer) and forming a gate insulation layer around at least a portion of the fin structure and forming a gate electrode above the gate insulation layer.
Yet another illustrative method involves forming a FinFET device comprised of at least first and second fin structures and a plurality of source/drain structures, wherein the first fin structure has a width that is different than a width of the second fin structure. In this example, the method involves forming a masking layer above a semiconducting substrate, wherein the masking layer exposes a first exposed region of the substrate where the first fin structure will be formed, a second region of the substrate where the second fin structure will be formed and a plurality of third exposed regions of the substrate where the plurality of source/drain structures will be formed, the first and second exposed regions having different widths, with the masking layer in position, performing an epitaxial growth process to form a layer of semiconducting material on the first, second and third exposed regions of the substrate, performing at least one process operation to remove the second masking layer and to reduce an initial thickness of the first masking layer (so that the fins are revealed), forming a first gate insulation layer around at least a portion of the first fin structure, forming a second gate insulation layer around at least a portion of the second fin structure, forming a first gate electrode above the first gate insulation layer and forming a second gate electrode above the second gate insulation layer.
Another method disclosed herein is directed to forming first and second FinFET devices above first and second portions of a semiconducting substrate, respectively, wherein the first FinFET device has at least one first fin structure and a plurality of first source/drain structures, the second FinFET device has at least one second fin structure and a plurality of second source/drain structures, and wherein the first fin structure is shorter (or has a lower fin height) than the second fin structure. In this example, the method involves forming a first masking layer above the first and second portions of the substrate, wherein the first masking layer covers the second portion of the substrate while it exposes a first exposed region of the first portion of the substrate where the first fin structure will be formed, with the first masking layer in position, performing a first epitaxial growth process to form a first layer of semiconducting material on the first portion of the substrate, wherein a first portion of the first layer of semiconducting material is the first fin structure for the first FinFET device and a plurality of second portions of the first layer of semiconducting material are the plurality of first source/drain structures of the first FinFET device, forming a second masking layer above the first masking layer and above the first and second portions of the substrate, forming at least one opening through the first and second masking layers positioned above the second portion of the substrate so as to expose a first exposed region of the second portion of the substrate where the second fin structure will be formed, with the first and second masking layers in position, performing a second epitaxial growth process to form a second layer of semiconducting material on the second portion of the semiconducting substrate, wherein a first portion of the second layer of semiconducting material is the second fin structure for the second FinFET device and wherein a plurality of second portions of the second layer of semiconducting material are the second source/drain structures of the second FinFET device, performing at least one process operation to remove the second masking layer and to reduce an initial thickness of the first masking layer (so that the fins are revealed), forming a first gate insulation layer around at least a portion of the first fin structure, forming a second gate insulation layer around at least a portion of the second fin structure, forming a first gate electrode above the first gate insulation layer and forming a second gate electrode above the second gate insulation layer.
One example of a novel FinFET device disclosed herein includes a layer of a semiconducting material positioned above an active region of a semiconducting substrate, wherein a first portion of the layer of semiconducting material constitutes at least one fin structure for the FinFET device and wherein a plurality of second portions of the layer of semiconducting material constitutes source/drain structures of the FinFET device. In this example, the source/drain structures have a width that is the same as the width dimension of the active region in a direction that is parallel to the gate width of the FinFET device. The device further includes a gate insulation layer positioned around at least a portion of the fin structure and a gate electrode positioned above the gate insulation layer.
The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
DETAILED DESCRIPTIONVarious illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
The present subject matter will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.
The present disclosure is directed to various methods of forming a FinFET semiconductor device by performing a selective epitaxial growth (SEG) process. As will be readily apparent to those skilled in the art upon a complete reading of the present application, the methods disclosed herein may be employed in manufacturing a variety of different integrated circuit products, including, but not limited to, logic devices, memory devices, etc., and they may be employed with respect to a variety of different technologies, e.g., N-type devices, P-type devices, CMOS applications, etc. With reference to the attached figures, various illustrative embodiments of the methods and devices disclosed herein will now be described in more detail.
As will be described more fully below, in one illustrative embodiment, the device 10 may be formed with super-steep channel profiles. In general, such super-steep channel profiles may be formed by forming non-doped epitaxially grown layers of a semiconductor material and then performing ion implantation processes with, for example, carbon to form doped regions (underneath the non-doped epi grown layer) in a semiconducting material, such as the substrate 12. Alternatively, an implant process may be performed on the surface of a bulk substrate or an SOI substrate, then the epi-grown non-doped layer may be formed on top to form a super-steep dopant profile. The non-doped or low-doped portion will be used for channel regions of the FinFET device 10. Both techniques are known to those skilled in field. As described above, the super-steep channel profiles may be formed by performing only epitaxial growth/deposition processes, by performing only ion implantation processes or by performing any combination of epitaxial growth/deposition processes and ion implantation processes in any desired order. Thus, when it is stated in this specification and/or in the claims that a “carbon doped layer” is formed relative to another structure or layer, it should be understood that such a “carbon doped layer” may be formed by an epitaxial growth/deposition process (with in situ carbon doping) or it may be a carbon implanted region formed in a semiconducting substrate, such as the illustrative substrate 12.
Accordingly, the present inventions should not be considered to be limited to the manner in which the doped layers that are part of the super-steep profile are formed.
As shown in
In the example depicted in
With continuing reference to
As noted above, using the methods disclosed herein, FinFET devices 10 may be formed wherein the width of the fins, which corresponds to the width of the trenches formed in the masking layer 17, may be individually varied if desired. For example,
By “substantially un-doped” it is meant that no dopant materials are intentionally included in manufacturing the substantially un-doped layer of semiconducting material 21. Thus, the substantially un-doped layer of semiconducting material 21 may have a dopant concentration of less than about 1015 atoms/cm3. As a result, the FinFET device 10 that will be formed using portions of the substantially un-doped layer of semiconducting material 21 will be fully depleted during device operation. The thickness of the substantially un-doped layer of semiconducting material 21 will generally correspond to the thickness 17T of the masking layer 17, although there may be a small amount of overfilling of the trenches 17A-D and 19 during the epitaxial deposition process, as reflected in
However, as noted above, in some applications, it may desired to have the source/drain structures that will become the source/drain regions for the device 10 not be merged together. For example,
If desired, as shown in
Of course, as will be recognized by those skilled in the art after a complete reading of the present application, in one specific example, the methods disclosed in
As shown in
The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims below.
Claims
1.-35. (canceled)
36. A FinFET device formed above an active region of a semiconducting substrate, said active region having a width dimension, wherein the width dimension is in a direction parallel to a gate width direction of said FinFET device, the device comprising:
- a layer of a semiconducting material positioned above said active region of said semiconducting substrate, wherein a first portion of said layer of semiconducting material constitutes at least one fin structure for said FinFET device and wherein a plurality of second portions of said layer of semiconducting material constitutes source/drain structures of said FinFET device that have a width that is the same as said width dimension of said active region;
- a gate insulation layer positioned around at least a portion of said at least one fin structure; and
- a gate electrode positioned above said gate insulation layer.
37. The device of claim 36, wherein said layer of semiconducting material is a layer of substantially un-doped silicon.
38. The device of claim 36, wherein said layer of semiconducting material is a continuous layer of semiconductor material.
39. The device of claim 36, wherein a vertical height of said at least one fin structure is substantially the same as a thickness of said second portions of said layer of semiconducting material.
40. The device of claim 36, wherein said first portion constitutes at least two fin structures and wherein said at least two fin structures have different fin widths.
41. The device of claim 40, wherein said layer of semiconducting material is a continuous layer of semiconductor material and wherein said at least two fin structures and said plurality of second portions of said layer of semiconducting material are defined in said continuous layer of semiconductor material.
42. A FinFET device formed above an active region of a semiconducting substrate, the device comprising:
- a layer of a semiconducting material positioned above said active region of said semiconducting substrate, wherein a first portion of said layer of semiconducting material constitutes a first fin structure for said FinFET device, a second portion of said layer of semiconducting material constitutes a second fin structure for said FinFET device, a plurality of third portions of said layer of semiconducting material constitutes first source/drain structures of said FinFET device that are in contact with said first fin structure and a plurality of fourth portions of said layer of semiconducting material constitutes second source/drain structures of said FinFET device that are in contact with said second fin structure, wherein said first and second source/drain structures are spaced apart from one another;
- a gate insulation layer positioned around at least a portion of said first and second fin structures; and
- a gate electrode positioned above said gate insulation layer and around a portion of said first and second fin structures.
43. The device of claim 42, wherein said layer of semiconducting material is a layer of substantially un-doped silicon.
44. The device of claim 42, wherein said layer of semiconducting material is a continuous layer of semiconductor material.
45. The device of claim 42, wherein a vertical height of said first and second fin structures is substantially the same.
46. The device of claim 42, wherein a thickness of the said first and second source/drain structures is substantially the same.
47. The device of claim 42, wherein a vertical height of said first and second fin structures and a thickness of said first and second source/drain structures are all substantially the same.
48. The device of claim 42, wherein said first and second fin structures have different fin widths.
49. The device of claim 42, wherein said layer of semiconducting material is a continuous layer of semiconductor material and wherein said first and second fin structures and said first and second source/drain structures are defined in said continuous layer of semiconductor material.
50. A FinFET device formed above an active region of a semiconducting substrate, the device comprising:
- a layer of a semiconducting material positioned above said active region of said semiconducting substrate, wherein a first portion of said layer of semiconducting material constitutes a first fin structure for said FinFET device, a second portion of said layer of semiconducting material constitutes a second fin structure for said FinFET device and a plurality of third portions of said layer of semiconducting material constitutes source/drain structures of said FinFET device that are in contact with said first and second fin structures, wherein said first and second fin structures have different fin widths;
- a gate insulation layer positioned around at least a portion of said first and second fin structures; and
- a gate electrode positioned above said gate insulation layer and around a portion of said first and second fin structures.
51. The device of claim 50, wherein said layer of semiconducting material is a layer of substantially un-doped silicon.
52. The device of claim 50, wherein said layer of semiconducting material is a continuous layer of semiconductor material.
53. The device of claim 50, wherein a vertical height of said first and second fin structures is substantially the same.
54. The device of claim 50, wherein a vertical height of said first and second fin structures and a thickness of said third portions of said layer of semiconducting material are all substantially the same.
55. The device of claim 50, wherein said layer of semiconducting material is a continuous layer of semiconductor material and wherein said first and second fin structures and said third portions of said layer of semiconducting material are defined in said continuous layer of semiconductor material.
Type: Application
Filed: Jul 10, 2014
Publication Date: Oct 30, 2014
Inventors: Min-hwa Chi (Malta, NY), Nam Sung Kim (Watervliet, NY)
Application Number: 14/327,712
International Classification: H01L 29/78 (20060101); H01L 27/088 (20060101);