And Patterning Of Conductive Layer Patents (Class 438/669)
  • Patent number: 12148627
    Abstract: A method for forming a semiconductor memory structure includes sequentially forming an active layer, a hard mask layer and a core layer over a substrate, and etching the core layer to form a core pattern. The core pattern includes a first strip, a second strip, and a plurality of supporting features abutting the first and second strips. The method also includes forming a spacer layer alongside the core pattern, removing the core pattern, forming a photoresist pattern above the spacer layer, etching the hard mask layer using the photoresist pattern and the spacer layer to form a hard mask pattern, and transferring the hard mask pattern into the active layer to form a gate stack.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: November 19, 2024
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Hsin-Hung Chou, Tsung-Wei Lin, Kao-Tsair Tsai
  • Patent number: 12094719
    Abstract: The present disclosure relates to a method of forming an etching pattern in a semiconductor manufacturing process. Unlike a conventional method of forming a four-layer structure composed of a photoresist film, an anti-reflective film, a SiON film, and an organic hard mask film on a wafer, as preparation for an etching process, the method according to the present disclosure is an innovative etching pattern forming method capable of implementing the same etching pattern as is formed by the conventional method, using a double-layer structure composed of a photoresist film and a multifunctional organic-inorganic mask film.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: September 17, 2024
    Assignee: YOUNG CHANG CHEMICAL CO., LTD
    Inventors: Su Jin Lee, Gi Hong Kim, Seung Hun Lee, Seung Hyun Lee
  • Patent number: 11990421
    Abstract: A semiconductor device has a substrate and first and second electrical component disposed over the substrate. A first metal bar is disposed over the substrate between the first electrical component and second electrical component. The first metal bar is formed by disposing a mask over a carrier. An opening is formed in the mask and a metal layer is sputtered over the mask. The mask is removed to leave the metal layer within the opening as the first metal bar. The first metal bar can be stored in a tape-and-reel.
    Type: Grant
    Filed: January 19, 2022
    Date of Patent: May 21, 2024
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: YongKook Shin, KyoWang Koo, HeeYoun Kim, SeongKuk Kim
  • Patent number: 11976364
    Abstract: A material layer manufacturing method is provided. The material layer manufacturing method may comprise the steps of: preparing a substrate having a base pattern formed thereon; providing a first precursor on the substrate having the base pattern formed thereon, in a state where a first voltage is applied to the base pattern; and providing a second precursor on the substrate having the first precursor provided thereon, in a state where a second voltage is applied to the base pattern, to form, on the substrate having the base pattern formed thereon, a material layer resulting from the reaction of the first precursor with the second precursor.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: May 7, 2024
    Assignee: INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY ERICA CAMPUS
    Inventors: Tae Joo Park, Ji Won Han
  • Patent number: 11972978
    Abstract: A method used in forming a conductive via of integrated circuitry comprises forming a lining laterally over sidewalls of an elevationally-elongated opening. The lining comprises elemental-form silicon. The elemental-form silicon of an uppermost portion of the lining is ion implanted in the elevationally-elongated opening. The ion-implanted elemental-form silicon of the uppermost portion of the lining is etched selectively relative to the elemental-form silicon of a lower portion of the lining below the uppermost portion that was not subjected to said ion implanting. The elemental-form silicon of the lower portion of the lining is reacted with a metal halide to form elemental-form metal in a lower portion of the elevationally-elongated opening that is the metal from the metal halide. Conductive material in the elevationally-elongated opening is formed atop and directly against the elemental-form metal. Other embodiments, including structure independent of method, are disclosed.
    Type: Grant
    Filed: May 4, 2022
    Date of Patent: April 30, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Yiping Wang, Jordan D. Greenlee, Collin Howder
  • Patent number: 11955646
    Abstract: A supported catalyst includes: (1) a catalyst support; and (2) deposits of a catalyst covering the catalyst support, wherein the deposits have an average thickness of about 2 nm or less, and the deposits are spaced apart from one another.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: April 9, 2024
    Assignees: The Board of Trustees of the Leland Stanford Junior University, Volkswagen Aktiengesellschaft
    Inventors: Friedrich B. Prinz, Thomas Jaramillo, Drew C. Higgins, Yongmin Kim, Shicheng Xu, Thomas Schladt, Tanja Graf
  • Patent number: 11923246
    Abstract: A method of via formation including forming a sacrificial mask over a conductive layer, forming a plurality of pillars in the sacrificial mask and the conductive layer, wherein each pillar of the plurality of pillars includes a sacrificial cap and a first conductive via, depositing a spacer between the plurality of pillars, masking at least one of the sacrificial caps, removing at least one of the sacrificial caps to create openings, forming second conductive vias in the openings, and depositing a dielectric coplanar to a top surface of the second conductive vias.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: March 5, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Koichi Motoyama, Dominik Metzler, Ekmini Anuja De Silva, Chanro Park, Hsueh-Chung Chen
  • Patent number: 11895835
    Abstract: Integrated circuitry comprising a memory array comprises strings of memory cells comprising laterally-spaced memory blocks individually comprising a first vertical stack comprising alternating insulative tiers and conductive tiers. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The conductive tiers individually comprise a horizontally-elongated conductive line. A second vertical stack is aside the first vertical stack. The second vertical stack comprises an tipper portion and a lower portion. The upper portion comprises vertically alternating first tiers and second insulating tiers that are of different composition relative one another. The lower portion comprises an upper polysilicon-comprising layer, a lower polysilicon-comprising layer, an intervening-material layer vertically between the tipper and lower polysilicon-comprising layers.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: February 6, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Alyssa N. Scarbrough, Jordan D. Greenlee, John D. Hopkins
  • Patent number: 11855177
    Abstract: The structure of a semiconductor device with dual silicide contact structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming first and second fin structures on a substrate, forming first and second epitaxial regions on the first and second fin structures, respectively, forming first and second contact openings on the first and second epitaxial regions, respectively, selectively forming an oxide capping layer on exposed surfaces of the second epitaxial region, selectively forming a first metal silicide layer on exposed surfaces of the first epitaxial region, removing the oxide capping layer, and forming first and second conductive regions on the metal silicide layer and on the exposed surfaces of the second epitaxial region, respectively. The first metal silicide layer includes a first metal. The first and second conductive regions includes a second metal different from the first metal.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Peng-Wei Chu, Ding-Kang Shih, Sung-Li Wang, Yasutoshi Okuno
  • Patent number: 11830732
    Abstract: Methods for selective deposition are provided. Material is selectively deposited on a first surface of a substrate relative to a second surface of a different material composition. An inhibitor, such as a polyimide layer, is selectively formed from vapor phase reactants on the first surface relative to the second surface. A layer of interest is selectively deposited from vapor phase reactants on the second surface relative to the first surface. The first surface can be metallic while the second surface is dielectric. Accordingly, material, such as a dielectric transition metal oxides and nitrides, can be selectively deposited on metallic surfaces relative dielectric surfaces using techniques described herein.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: November 28, 2023
    Assignee: ASM IP Holding B.V.
    Inventors: Jan Willem Hub Maes, Michael Eugene Givens, Suvi P. Haukka, Vamsi Paruchuri, Ivo Johannes Raaijmakers, Shaoren Deng, Andrea Illiberi, Eva E. Tois, Delphine Longrie, Viljami Pore
  • Patent number: 11676820
    Abstract: A method for fabricating a semiconductor device includes: preparing a substrate; forming an isolation layer defining an active region in the substrate; forming a first insulation structure over the substrate, the first insulation structure defining a line-type opening that exposes the isolation layer and the active region; forming a plug pad through a Selective Epitaxial Growth (SEG) process over the exposed active regions; forming a second insulation structure inside the line-type opening, the second insulation structure defining a contact hole landing on the plug pad; and filling the contact hole with a contact plug.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: June 13, 2023
    Assignee: SK hynix Inc.
    Inventors: Oh-Hyun Kim, Sung-Hwan Ahn, Hae-Jung Park, Tae-Hang Ahn
  • Patent number: 11646311
    Abstract: A semiconductor device including a substrate, a first transistor and a second transistor is provided. The first transistor includes a first gate structure over the first semiconductor fin. The first gate structure includes a first high-k layer and a first work function layer sequentially disposed on the substrate, a material of the first work function layer may include metal carbide and aluminum, and a content of aluminum in the first work function layer is less than 10% atm. The second transistor includes a second gate structure. The second gate structure includes a second high-k layer and a second work function layer sequentially disposed on the substrate. A work function of the first work function layer is greater than a work function of the second work function layer.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: May 9, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Yi Lee, Cheng-Lung Hung, Weng Chang, Chi-On Chui
  • Patent number: 11522145
    Abstract: A method for manufacturing a transistor being a bottom-gate transistor is provided. The method for manufacturing a transistor includes a step of forming a first metal layer 32 on an insulator layer 20 provided on a substrate 10 including a gate electrode, a step of applying a resist onto the first metal layer 32, and patterning the first metal layer 32 by a photolithographic method, an oxide film removal step of removing an oxide film 26 formed on the patterned first metal layer 32, and a step of forming a source electrode and a drain electrode by forming a second metal layer 42 on the first metal layer 32.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: December 6, 2022
    Assignee: NIKON CORPORATION
    Inventor: Shohei Koizumi
  • Patent number: 11508617
    Abstract: A method of forming an interconnect structure for semiconductor devices is described. The method comprises etching a patterned interconnect stack for form first conductive lines and expose a top surface of a first etch stop layer; etching the first etch stop layer to form second conductive lines and expose a top surface of a barrier layer; and forming a self-aligned via.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: November 22, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Hao Jiang, Chi Lu, He Ren, Chi-I Lang, Ho-yung David Hwang, Mehul Naik
  • Patent number: 11469491
    Abstract: An antenna device is provided. The antenna device includes a first substrate, a multilayer electrode, a second substrate, and a liquid-crystal layer. The multilayer electrode is disposed on the first substrate, and the multilayer electrode includes a first conductive layer, a second conductive layer, and a third conductive layer. The second conductive layer is disposed on the first conductive layer. The third conductive layer is disposed on the second conductive layer. The liquid-crystal layer is disposed between the first substrate and the second substrate. In addition, the third conductive layer includes a first portion that extends beyond the second conductive layer.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: October 11, 2022
    Assignee: INNOLUX CORPORATION
    Inventors: Chia-Ping Tseng, Ker-Yih Kao, Chia-Chi Ho, Ming-Yen Weng, Hung-I Tseng, Shu-Ling Wu, Huei-Ying Chen
  • Patent number: 11442321
    Abstract: A display panel may include a first display substrate. The first display substrate may include a base layer defining a display area and a non-display area that is adjacent to the display area, a gate line disposed on the base layer, a first insulating layer disposed on the base layer and covering the gate line, and a test line overlapping the non-display area and disposed on the first insulating layer, the test line being in electric contact with the gate line through a first contact hole defined in the first insulating layer.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: September 13, 2022
    Inventor: Dong Hee Shin
  • Patent number: 11441071
    Abstract: An etchant composition of an embodiment includes a persulfate, a four-nitrogen ring compound, a two-chlorine compound, a fluorine compound and water, and has a weight ratio of the four-nitrogen ring compound and the two-chlorine compound of about 1:0.5 to about 1:4. The etchant composition may etch a multilayer metal substrate of titanium/copper and may be used for manufacturing a multilayer metal pattern and an array substrate having excellent properties of etched patterns.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: September 13, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Bong-Kyun Kim, JinSeuk Kim, SeungBo Shim, ShinHyuk Choi, Seung-Hee Kim, Donghee Lee
  • Patent number: 11414756
    Abstract: Time projection chambers are useful for high energy particle physics, nuclear physics, and astronomy. To enhance the particle detection efficiency and performance of the projection chambers functional bilayer thin film coatings based on the atomic layer deposition method are utilized. Coating material selection is based on Auger neutralization process ion induced electron emission from metallic surfaces (e.g., Mo or W) combined with a high secondary electron emission coefficient. Application of high secondary electron emission materials (e.g., MgO and CaF2) enhances the multiplication of these emitted electrons from ion induction processes. Therefore, using suitable bilayer coatings the overall TPC signal detection efficiency can be increased.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: August 16, 2022
    Assignee: UChicago Argonne, LLC
    Inventors: Jeffrey W. Elam, Anil U. Mane, Stephen Magill
  • Patent number: 11367618
    Abstract: A semiconductor patterning process includes the following steps. A substrate is provided, wherein the substrate has a first region, a second region, and a third region, and the second region is located between the first region and the third region. A plurality of initial mask patterns are formed on the substrate. A first mask material layer is conformally formed on the substrate. A first mask pattern is formed above at least two adjacent initial mask patterns in the second region and on the first mask material layer in between, and a second mask pattern is formed on the first mask material layer on sidewalls of remaining initial mask patterns. A portion of the first mask material layer is removed using the first mask pattern and the second mask pattern as a mask to form a final mask pattern on the substrate.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: June 21, 2022
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Zih-Song Wang
  • Patent number: 11274230
    Abstract: An aqueous alkaline chemical mechanical polishing composition includes a quaternary phosphonium compound having aromatic groups which enables enhanced reduction of defects on silicon oxide substrates and enables good silicon oxide removal rates during chemical mechanical polishing. The chemical mechanical polishing composition is stable.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: March 15, 2022
    Assignee: Rohm and Haas Electronic Materials CMP Holdings, Inc.
    Inventor: Yi Guo
  • Patent number: 11133218
    Abstract: A semiconductor apparatus having through silicon via structure and a manufacturing method thereof to enable the significant process and cost reduction and the improvement of performance of through silicon via by forming barrier and seed metal layers with electroless plating, the barrier layer applied in forming through silicon via with wet electroless plating thereby enabling structural uniformity and improvement in electrical properties with less process cost and higher yield to meet the both performance and economic objectives. The instant invention enables the formation of TSV with smaller diameter of the opening and, if necessary, omitting the formation of copper seed layer. Direct copper plating on the barrier layer is possible and this reduces the number of processes, charges the inside of via at once through copper plating to bring more improvements in electrical properties as effect.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: September 28, 2021
    Inventors: Tae Young Lee, Youn Tak Park
  • Patent number: 10943784
    Abstract: The present invention provides a method for optimizing a critical dimension for double patterning for NAND flash, forming a core oxide layer on amorphous silicon layer on substrate; densifying the core oxide layer and etching it to form a core pattern; measuring CD values of the bottom and top of the core pattern; providing etching rates of a non-densified core oxide layer and a densified core oxide layer under the same etching condition; calculating the thickness of the core oxide layer required to be densified according to the CD values of the bottom and top of the core pattern and the etching rates to determine the densifying time. The present invention precisely controls the morphology and CD, and obtains a double-patterned target pattern with consistent CD sizes of a top and a bottom and a consistent bottom height, so as to improve a product yield.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: March 9, 2021
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventors: Li He, Xiaohua Ju, Guanqun Huang
  • Patent number: 10790150
    Abstract: A method for fabricating a semiconductor device includes: preparing a substrate; forming an isolation layer defining an active region in the substrate; forming a first insulation structure over the substrate, the first insulation structure defining a line-type opening that exposes the isolation layer and the active region; forming a plug pad through a Selective Epitaxial Growth (SEG) process over the exposed active regions; forming a second insulation structure inside the line-type opening, the second insulation structure defining a contact hole landing on the plug pad; and filling the contact hole with a contact plug.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: September 29, 2020
    Assignee: SK hynix Inc.
    Inventors: Oh-Hyun Kim, Sung-Hwan Ahn, Hae-Jung Park, Tae-Hang Ahn
  • Patent number: 10648087
    Abstract: Disclosed are processes of removing layers from substrates using fluorinated reactants having the formula MFx(adduct)n, wherein x ranges from 2 to 6 inclusive; n ranges from 0 to 5 inclusive; M is selected from the group consisting of P, Ti, Zr, Hf, V, Nb, Ta, Mo, and W; and the adduct is a neutral organic molecule selected from THF, dimethylether, diethylether, glyme, diglyme, triglyme, polyglyme, dimethylsulphide, diethylsulphide, or methylcyanide. The fluorinated reactants dry etch the nitride layers without utilizing any plasma.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: May 12, 2020
    Assignee: L'Air Liquide, SociétéAnonyme pour l'Exploitation et l'Etude des Procédés Georges Claude
    Inventors: Clément Lansalot-Matras, Jooho Lee, Jean-Marc Girard, Nicolas Blasco, Satoko Gatineau
  • Patent number: 10643895
    Abstract: A method of forming an interconnect structure for semiconductor or MEMS structures at a 10 nm Node (16 nm HPCD) down to 5 nm Node (7 nm HPCD), or lower, where the conductive contacts of the interconnect structure are fabricated using solely subtractive techniques applied to conformal layers of conductive materials.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: May 5, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Bencherki Mebarki, Huixiong Dai, Yongmei Chen, He Ren, Mehul Naik
  • Patent number: 10622214
    Abstract: Methods and systems relating to processes for treating a tungsten film on a workpiece including supporting the workpiece in a chamber, introducing hydrogen gas into the chamber and establishing a pressure of at least 5 atmospheres, and exposing the tungsten film on the workpiece to the hydrogen gas while the pressure in the chamber is at least 5 atmospheres.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: April 14, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Keith Tatseun Wong, Thomas Jongwan Kwon, Sean Kang, Ellie Y. Yieh
  • Patent number: 10468252
    Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The method comprises sequentially forming a target layer and a first mask layer on a substrate, patterning the first mask layer to form a first opening in the first mask layer, forming a spacer covering an inner wall of the first opening, forming on the first mask layer a first photoresist pattern having a second opening vertically overlapping at least a portion of the spacer, forming a third opening in the first mask layer that is adjacent to the first opening by using the spacer as a mask to remove a portion of the first mask layer that is exposed to the second opening, and using the first mask layer and the spacer as a mask to pattern the target layer.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: November 5, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jongchan Shin
  • Patent number: 10366890
    Abstract: Techniques herein enable integrating stack materials and multiple color materials that require no corrosive gases for etching. Techniques enable a multi-line layer for self-aligned pattern shrinking in which all layers or colors or materials can be limited to silicon-containing materials and organic materials. Such techniques enable self-aligned block integration for 5 nm back-end-of-line trench patterning with an all non-corrosive etch compatible stack for self-aligned block. Embodiments include using lines of a same material but at different heights to provided etch selectivity to one of several lines based on type of material and/or height of material and etch rate.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: July 30, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Anton J. deVilliers, Nihar Mohanty
  • Patent number: 10263092
    Abstract: A thin film transistor, a method for manufacturing the same, an array substrate and a display device are disclosed. The thin film transistor includes a gate having a gate metal layer on a surface of a substrate; a gate insulating layer on the substrate and covering the gate; an active layer on a surface of the gate insulating layer away from the substrate; a source comprising a source metal layer on a surface of the active layer away from the substrate; and a drain having a drain metal layer on a surface of the active layer away from the substrate, wherein the gate, the source or the drain further includes a metal complex layer on a surface of the gate metal layer, the source metal layer or the drain metal layer away from the substrate.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: April 16, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Haixu Li, Zhanfeng Cao, Qi Yao, Jianguo Wang, Dapeng Xue
  • Patent number: 10132928
    Abstract: A lidar-based apparatus and method are used for the solid state steering of laser beams using Photonic Integrated Circuits. Integrated optic design and fabrication micro- and nanotechnologies are used for the production of chip-scale optical splitters that distribute an optical signal from a laser essentially uniformly to an array of pixels, said pixels comprising tunable optical delay lines and optical antennas. Said antennas achieve out-of-plane coupling of light. As the delay lines of said antenna-containing pixels in said array are tuned, each antenna emits light of a specific phase to form a desired far-field radiation pattern through interference of these emissions. Said array serves the function of solid state optical phased array.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: November 20, 2018
    Assignee: Quanergy Systems, Inc.
    Inventors: Louay Eldada, Tianyue Yu, Angus Pacala
  • Patent number: 9953123
    Abstract: A layout file for an integrated circuit has drawn geometries. Variable fill geometries are added to local areas based on densities of the drawn geometries in windows associated with the local areas and on the global density of all the drawn geometries in the layout file. Each window has a separate local area associated with it. The densities of the variable fill geometries in the local areas are not all equal. Densities of the fill geometries are higher in local areas associated with windows having lower densities of the drawn geometries, and for lower values of the global density. The layout file is stored in a computer-readable medium.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: April 24, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sumanth Somashekar, Shaibal Barua, Padman Sooryamoorthy
  • Patent number: 9613853
    Abstract: Approaches for fabricating copper wires in integrated circuits are provided. A method of manufacturing a semiconductor structure includes forming a wire opening in a mask. The method also includes electroplating a conductive material in the wire opening. The method additionally includes forming a cap layer on the conductive material. The method further includes removing the mask. The method still further includes forming spacers on sides of the conductive material. The method additionally includes forming a dielectric film on surfaces of the cap layer and the sidewall spacers.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: April 4, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Fen Chen, Jeffrey P. Gambino, Zhong-Xiang He, Trevor A. Thompson, Eric J. White
  • Patent number: 9589787
    Abstract: The present invention makes it possible to increase the reliability of a semiconductor device. A manufacturing method of a semiconductor device according to the present invention includes a step of removing a patterned resist film and the step of removing a patterned resist film includes the steps of: (A) introducing at least a gas containing oxygen into a processing room; (B) starting electric discharge for transforming the gas containing oxygen into plasma; and (C) introducing a water vapor or an alcohol vapor into the processing room. On this occasion, the step (C) is applied either simultaneously with or after the step (B).
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: March 7, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Toru Shinaki, Takehiko Saito, Yoshinori Kondo, Masatoshi Fukushima
  • Patent number: 9508723
    Abstract: A dummy active region is formed in a region in which a gate contact for supplying operation power to the buried gate is formed, and a PN junction diode connected to the gate contact in a reverse bias direction is formed in the dummy active region. Current leakage, in which current flows out toward a substrate, is prevented even when misalignment of the gate contact occurs.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: November 29, 2016
    Assignee: SK HYNIX INC.
    Inventors: Sang Gon Lee, Sun Joo Park
  • Patent number: 9437836
    Abstract: The present disclosure discloses a method for improving the reflectivity of aluminum in OLED structure. The OLED structure includes a top ITO layer, a middle reflective layer made by aluminum and a bottom ITO layer. The method comprises; forming a bottom ITO layer; coating the aluminous reflective layer on the surface of the bottom ITO layer and forming an aluminum oxide layer on the surface of the aluminous reflective layer uniformly by introducing plenty of oxygen gas simultaneously; adjusting the velocity of coating the aluminous reflective until the aluminum oxide layer is formed; and forming an top ITO layer on the surface of the aluminum oxide layer. The present disclosure can repair and cover the defects on the surface of the metal aluminum film and can reduce the concavities and hillocks on the surface of the metal aluminum film. Consequently, the reflectivity of aluminum in OLED structure is improved.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: September 6, 2016
    Assignee: EVERDISPLAY OPTRONICS (SHANGHAI) LIMITED
    Inventors: Chenghsien Wang, Chihhong Liu
  • Patent number: 9437447
    Abstract: Techniques disclosed herein include increasing pattern density for creating high-resolution contact openings, slots, trenches, and other features. A conformal spacer is applied on a bi-layer or tri-layer mandrel (multi-layer) or other relief feature. The conformal spacer thus wraps around the mandrels and is also deposited on an underlying layer. A fill material is deposited to fill gaps or spaces between sidewall spacers. A CMP planarization step then removes substrate stack material down to a material interface of the bi-layer or tri-layer mandrel, with a middle or lower material of the mandrel being a CMP-stop material. This technique essentially cuts off or removes rounded features such as upper portions of sidewall spacers, thereby providing a spacer material with a planar top surface that can be uniformly etched and transferred to underlying layers.
    Type: Grant
    Filed: February 17, 2015
    Date of Patent: September 6, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Anton J. deVilliers
  • Patent number: 9299705
    Abstract: A semiconductor structure may be formed by forming a first semiconductor fin and a second inactive semiconductor fin above a substrate; depositing a masking layer above the first semiconductor fin and the second semiconductor fin; etching a trench in the masking layer exposing the second semiconductor fin while the first semiconductor fin remains covered by the masking layer; removing the second semiconductor fin to form a fin recess beneath the trench; filling the fin recess with an insulating material to form an insulating fence fin; and removing the masking layer to expose the first semiconductor fin and the insulating fence fin. A third semiconductor fin separating the first semiconductor fin from the second semiconductor fin may also be formed prior to depositing the masking layer and covered by the masking layer. The first semiconductor fin may be a pFET fin and the third semiconductor fin may be an nFET fin.
    Type: Grant
    Filed: February 17, 2014
    Date of Patent: March 29, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Sivananda K. Kanakasabapathy
  • Patent number: 9252050
    Abstract: A method of forming a semiconductor device is disclosed. The method including providing a substrate with at least one insulating layer disposed thereon, the at least one insulating layer including a trench; forming at least one liner layer on the at least one insulating layer; forming a nucleation layer on the at least one liner layer; forming a first metal film on a surface of the nucleation layer; etching the first metal film; and depositing a second metal film on the etched surface of the first metal film, the second metal film substantially forming an overburden above the trench.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: February 2, 2016
    Assignees: International Business Machines Corporation, STMicroelectronics, Inc.
    Inventors: Lindsey H. Hall, Michael Hatzistergos, Ahmet S. Ozcan, Filippos Papadatos, Yiyi Wang
  • Patent number: 9209073
    Abstract: Presented herein is a method for electrolessly forming a metal cap in a via opening, comprising bringing a via into contact with metal solution, the via disposed in an opening in a substrate, and forming a metal cap in the opening and in contact with the via, the metal cap formed by an electroless chemical reaction. A metal solution may be applied to the via to form the metal cap. The metal solution may comprises at least cobalt and the cap may comprise at least cobalt, and may optionally further comprise tungsten, and wherein the forming the cap comprises forming the cap to further comprise at least tungsten. The metal solution may further comprise at least hypophosphite or dimethylaminoborane.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: December 8, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Liang-Yueh Ou Yang, Chih-Yi Chang, Chen-Yuan Kao, Hung-Wen Su
  • Patent number: 9153363
    Abstract: The present invention provides a light-transmitting metal electrode including a substrate and a metal electrode layer having plural openings. The metal electrode layer also has such a continuous metal part that any pair of point-positions in the part is continuously connected without breaks. The openings in the metal electrode layer are periodically arranged to form plural microdomains. The plural microdomains are so placed that the in-plane arranging directions thereof are oriented independently of each other. The thickness of the metal electrode layer is in the range of 10 to 200 nm.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: October 6, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Eishi Tsutsumi, Tsutomu Nakanishi, Akira Fujimoto, Koji Asakawa
  • Publication number: 20150145060
    Abstract: Devices and methods of forming a device are disclosed. A substrate prepared with at least a first transistor and a second transistor is provided. Each of the first and second transistors includes a gate disposed on the substrate between first and second contact regions in the substrate. A silicide block layer is formed on the substrate and is patterned to expose portions of the first and second contact regions. Silicide contacts are formed in the exposed first and second contact regions. The silicide contacts are displaced from sides of the gates of the first and second transistors. A contact dielectric layer is formed and contacts are formed in the contact dielectric layer. The contacts are in communication with the silicide contacts in the contact regions.
    Type: Application
    Filed: November 26, 2013
    Publication date: May 28, 2015
    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Zhibiao ZHOU, Yudi SETIAWAN
  • Publication number: 20150147839
    Abstract: A method for manufacturing a semiconductor device may include: forming a metal layer structure over a semiconductor workpiece; forming a first layer over the metal layer structure, the first layer including a first material; forming at least one opening in the first layer and the metal layer structure; depositing a second layer to fill the at least one opening and at least partially cover a surface of the first layer facing away from the metal layer structure, the second layer including a second material that is different from the first material; removing the second layer from at least the surface of the first layer facing away from the metal layer structure; and removing the first layer.
    Type: Application
    Filed: November 26, 2013
    Publication date: May 28, 2015
    Applicant: Infineon Technologies Dresden GmbH
    Inventors: Alessia Scire, Alfred Vater, Mirko Vogt, Momtchil Stavrev, Tarja Hauck, Bee Kim Hong, Heiko Estel
  • Publication number: 20150140811
    Abstract: A method of patterning a semiconductor device is disclosed. A tri-layer photoresist is formed over a plurality of patterned features. The tri-layer photoresist includes a bottom layer, a middle layer disposed over the bottom layer, and a top layer disposed over the middle layer, the top layer containing a photo-sensitive material. The top layer is patterned via a photolithography process, the patterned top layer including an opening. The opening is extended into the bottom layer by etching the bottom layer and continuously forming a protective layer on etched surfaces of the bottom layer and on exposed surfaces of the patterned features. The bottom layer is removed. At least some portions of the protective layer remain on the exposed surfaces of the patterned features after the bottom layer is removed.
    Type: Application
    Filed: November 20, 2013
    Publication date: May 21, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Min Huang, Chung-Ju Lee, Yung-Hsu Wu
  • Publication number: 20150140812
    Abstract: Embodiments of methods for etching cobalt metal using fluorine radicals are provided herein. In some embodiments, a method of etching a cobalt layer in a substrate processing chamber includes: forming a plasma from a process gas comprising a fluorine-containing gas; and exposing the cobalt layer to fluorine radicals from the plasma while maintaining the cobalt layer at a temperature of about 50 to about 500 degrees Celsius to etch the cobalt layer.
    Type: Application
    Filed: October 22, 2014
    Publication date: May 21, 2015
    Inventors: BHUSHAN N. ZOPE, AVGERINOS V. GELATOS
  • Patent number: 9034758
    Abstract: A spacer etching process produces ultra-narrow conductive lines in a plurality of semiconductor dice. Trenches are formed in a first dielectric then a sacrificial film is deposited onto the first dielectric and the trench surfaces formed therein. Planar sacrificial film is removed from the face of the first dielectric and bottom of the trenches, leaving only sacrificial films on the trench walls. A gap between the sacrificial films on the trench walls is filled in with a second dielectric. A portion of the second dielectric is removed to expose tops of the sacrificial films. The sacrificial films are removed leaving ultra-thin gaps that are filled in with a conductive material. The tops of the conductive material in the gaps are exposed to create “fence conductors.” Portions of the fence conductors and surrounding insulating materials are removed at appropriate locations to produce desired conductor patterns comprising isolated fence conductors.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 19, 2015
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventor: Paul Fest
  • Publication number: 20150118776
    Abstract: A manufacturing method of a display device includes: forming a thin film transistor on a substrate, forming a pixel electrode connected to the thin film transistor, and forming a common electrode insulated from the pixel electrode. At least one of forming the pixel electrode and forming the common electrode includes: forming an electrode layer on the substrate, coating a photoresist on the electrode layer to form a first electrode sub-layer on which the photoresist is coated and a second electrode sub-layer on which the photoresist is not coated, generating etching vapor by heating an etching solution in a double boiler, and etching the second electrode sub-layer by using the etching vapor.
    Type: Application
    Filed: May 1, 2014
    Publication date: April 30, 2015
    Applicant: Samsung Display Co., Ltd.
    Inventors: Hongsick Park, Seon-il Kim
  • Publication number: 20150115414
    Abstract: A sapphire structure with a metal substructure is disclosed. The sapphire structure with a metal substructure includes a sapphire structure and a metal substructure. The sapphire structure includes a flat surface and a concave portion on the flat surface. The metal substructure in the concave portion is bonded to an inner surface of the concave portion and includes a surface portion that is substantially flush with the flat surface.
    Type: Application
    Filed: August 18, 2014
    Publication date: April 30, 2015
    Inventors: Motohiro Umehara, Yoshinori Kubo
  • Patent number: 9018095
    Abstract: A conductive circuit is formed by printing a pattern of an ink composition and curing the pattern. The ink composition is a substantially solvent-free, liquid, addition curable, ink composition comprising (A) an organopolysiloxane having at least two alkenyl groups, (B) an organohydrogenpolysiloxane having at least two SiH groups, (C) conductive particles having an average particle size ?5 ?m, (D) conductive micro-particles having an average particle size <5 ?m, (E) a thixotropic agent, and (F) a hydrosilylation catalyst.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: April 28, 2015
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventor: Yoshitaka Hamada
  • Publication number: 20150111374
    Abstract: Embodiments of present invention provide a method of forming semiconductor devices. The method includes creating an opening in a semiconductor structure; depositing a first layer of metal inside the opening with the first layer of metal partially filling up the opening; modifying a top surface of the first layer of metal in an etching process; passivating the modified top surface of the first layer of metal to form a passivation layer; and depositing a second layer of metal directly on top of the passivation layer.
    Type: Application
    Filed: October 18, 2013
    Publication date: April 23, 2015
    Applicant: International Business Machines Corporation
    Inventors: Ruqiang Bao, Domingo A. Ferrer, Filippos Papadatos, Daniel P. Stambaugh
  • Publication number: 20150111379
    Abstract: A semiconductor structure having a substrate; an active device formed in an active semiconductor region of the substrate, the active device having a control electrode for controlling a flow of carriers through the active semiconductor region between a pair of electrical contacts; and a photolithographic, thickness non-uniformity, compensation feature, disposed on the surface substrate off of the active semiconductor region. In one embodiment the feature comprises pads on the surface of the substrate and off of the active semiconductor region.
    Type: Application
    Filed: January 5, 2015
    Publication date: April 23, 2015
    Inventors: Paul J. Duval, Paul M. Ryan, Christopher J. MacDonald