And Patterning Of Conductive Layer Patents (Class 438/669)
  • Patent number: 10790150
    Abstract: A method for fabricating a semiconductor device includes: preparing a substrate; forming an isolation layer defining an active region in the substrate; forming a first insulation structure over the substrate, the first insulation structure defining a line-type opening that exposes the isolation layer and the active region; forming a plug pad through a Selective Epitaxial Growth (SEG) process over the exposed active regions; forming a second insulation structure inside the line-type opening, the second insulation structure defining a contact hole landing on the plug pad; and filling the contact hole with a contact plug.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: September 29, 2020
    Assignee: SK hynix Inc.
    Inventors: Oh-Hyun Kim, Sung-Hwan Ahn, Hae-Jung Park, Tae-Hang Ahn
  • Patent number: 10648087
    Abstract: Disclosed are processes of removing layers from substrates using fluorinated reactants having the formula MFx(adduct)n, wherein x ranges from 2 to 6 inclusive; n ranges from 0 to 5 inclusive; M is selected from the group consisting of P, Ti, Zr, Hf, V, Nb, Ta, Mo, and W; and the adduct is a neutral organic molecule selected from THF, dimethylether, diethylether, glyme, diglyme, triglyme, polyglyme, dimethylsulphide, diethylsulphide, or methylcyanide. The fluorinated reactants dry etch the nitride layers without utilizing any plasma.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: May 12, 2020
    Assignee: L'Air Liquide, SociétéAnonyme pour l'Exploitation et l'Etude des Procédés Georges Claude
    Inventors: Clément Lansalot-Matras, Jooho Lee, Jean-Marc Girard, Nicolas Blasco, Satoko Gatineau
  • Patent number: 10643895
    Abstract: A method of forming an interconnect structure for semiconductor or MEMS structures at a 10 nm Node (16 nm HPCD) down to 5 nm Node (7 nm HPCD), or lower, where the conductive contacts of the interconnect structure are fabricated using solely subtractive techniques applied to conformal layers of conductive materials.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: May 5, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Bencherki Mebarki, Huixiong Dai, Yongmei Chen, He Ren, Mehul Naik
  • Patent number: 10622214
    Abstract: Methods and systems relating to processes for treating a tungsten film on a workpiece including supporting the workpiece in a chamber, introducing hydrogen gas into the chamber and establishing a pressure of at least 5 atmospheres, and exposing the tungsten film on the workpiece to the hydrogen gas while the pressure in the chamber is at least 5 atmospheres.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: April 14, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Keith Tatseun Wong, Thomas Jongwan Kwon, Sean Kang, Ellie Y. Yieh
  • Patent number: 10468252
    Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The method comprises sequentially forming a target layer and a first mask layer on a substrate, patterning the first mask layer to form a first opening in the first mask layer, forming a spacer covering an inner wall of the first opening, forming on the first mask layer a first photoresist pattern having a second opening vertically overlapping at least a portion of the spacer, forming a third opening in the first mask layer that is adjacent to the first opening by using the spacer as a mask to remove a portion of the first mask layer that is exposed to the second opening, and using the first mask layer and the spacer as a mask to pattern the target layer.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: November 5, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jongchan Shin
  • Patent number: 10366890
    Abstract: Techniques herein enable integrating stack materials and multiple color materials that require no corrosive gases for etching. Techniques enable a multi-line layer for self-aligned pattern shrinking in which all layers or colors or materials can be limited to silicon-containing materials and organic materials. Such techniques enable self-aligned block integration for 5 nm back-end-of-line trench patterning with an all non-corrosive etch compatible stack for self-aligned block. Embodiments include using lines of a same material but at different heights to provided etch selectivity to one of several lines based on type of material and/or height of material and etch rate.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: July 30, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Anton J. deVilliers, Nihar Mohanty
  • Patent number: 10263092
    Abstract: A thin film transistor, a method for manufacturing the same, an array substrate and a display device are disclosed. The thin film transistor includes a gate having a gate metal layer on a surface of a substrate; a gate insulating layer on the substrate and covering the gate; an active layer on a surface of the gate insulating layer away from the substrate; a source comprising a source metal layer on a surface of the active layer away from the substrate; and a drain having a drain metal layer on a surface of the active layer away from the substrate, wherein the gate, the source or the drain further includes a metal complex layer on a surface of the gate metal layer, the source metal layer or the drain metal layer away from the substrate.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: April 16, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Haixu Li, Zhanfeng Cao, Qi Yao, Jianguo Wang, Dapeng Xue
  • Patent number: 10132928
    Abstract: A lidar-based apparatus and method are used for the solid state steering of laser beams using Photonic Integrated Circuits. Integrated optic design and fabrication micro- and nanotechnologies are used for the production of chip-scale optical splitters that distribute an optical signal from a laser essentially uniformly to an array of pixels, said pixels comprising tunable optical delay lines and optical antennas. Said antennas achieve out-of-plane coupling of light. As the delay lines of said antenna-containing pixels in said array are tuned, each antenna emits light of a specific phase to form a desired far-field radiation pattern through interference of these emissions. Said array serves the function of solid state optical phased array.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: November 20, 2018
    Assignee: Quanergy Systems, Inc.
    Inventors: Louay Eldada, Tianyue Yu, Angus Pacala
  • Patent number: 9953123
    Abstract: A layout file for an integrated circuit has drawn geometries. Variable fill geometries are added to local areas based on densities of the drawn geometries in windows associated with the local areas and on the global density of all the drawn geometries in the layout file. Each window has a separate local area associated with it. The densities of the variable fill geometries in the local areas are not all equal. Densities of the fill geometries are higher in local areas associated with windows having lower densities of the drawn geometries, and for lower values of the global density. The layout file is stored in a computer-readable medium.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: April 24, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sumanth Somashekar, Shaibal Barua, Padman Sooryamoorthy
  • Patent number: 9613853
    Abstract: Approaches for fabricating copper wires in integrated circuits are provided. A method of manufacturing a semiconductor structure includes forming a wire opening in a mask. The method also includes electroplating a conductive material in the wire opening. The method additionally includes forming a cap layer on the conductive material. The method further includes removing the mask. The method still further includes forming spacers on sides of the conductive material. The method additionally includes forming a dielectric film on surfaces of the cap layer and the sidewall spacers.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: April 4, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Fen Chen, Jeffrey P. Gambino, Zhong-Xiang He, Trevor A. Thompson, Eric J. White
  • Patent number: 9589787
    Abstract: The present invention makes it possible to increase the reliability of a semiconductor device. A manufacturing method of a semiconductor device according to the present invention includes a step of removing a patterned resist film and the step of removing a patterned resist film includes the steps of: (A) introducing at least a gas containing oxygen into a processing room; (B) starting electric discharge for transforming the gas containing oxygen into plasma; and (C) introducing a water vapor or an alcohol vapor into the processing room. On this occasion, the step (C) is applied either simultaneously with or after the step (B).
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: March 7, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Toru Shinaki, Takehiko Saito, Yoshinori Kondo, Masatoshi Fukushima
  • Patent number: 9508723
    Abstract: A dummy active region is formed in a region in which a gate contact for supplying operation power to the buried gate is formed, and a PN junction diode connected to the gate contact in a reverse bias direction is formed in the dummy active region. Current leakage, in which current flows out toward a substrate, is prevented even when misalignment of the gate contact occurs.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: November 29, 2016
    Assignee: SK HYNIX INC.
    Inventors: Sang Gon Lee, Sun Joo Park
  • Patent number: 9437836
    Abstract: The present disclosure discloses a method for improving the reflectivity of aluminum in OLED structure. The OLED structure includes a top ITO layer, a middle reflective layer made by aluminum and a bottom ITO layer. The method comprises; forming a bottom ITO layer; coating the aluminous reflective layer on the surface of the bottom ITO layer and forming an aluminum oxide layer on the surface of the aluminous reflective layer uniformly by introducing plenty of oxygen gas simultaneously; adjusting the velocity of coating the aluminous reflective until the aluminum oxide layer is formed; and forming an top ITO layer on the surface of the aluminum oxide layer. The present disclosure can repair and cover the defects on the surface of the metal aluminum film and can reduce the concavities and hillocks on the surface of the metal aluminum film. Consequently, the reflectivity of aluminum in OLED structure is improved.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: September 6, 2016
    Assignee: EVERDISPLAY OPTRONICS (SHANGHAI) LIMITED
    Inventors: Chenghsien Wang, Chihhong Liu
  • Patent number: 9437447
    Abstract: Techniques disclosed herein include increasing pattern density for creating high-resolution contact openings, slots, trenches, and other features. A conformal spacer is applied on a bi-layer or tri-layer mandrel (multi-layer) or other relief feature. The conformal spacer thus wraps around the mandrels and is also deposited on an underlying layer. A fill material is deposited to fill gaps or spaces between sidewall spacers. A CMP planarization step then removes substrate stack material down to a material interface of the bi-layer or tri-layer mandrel, with a middle or lower material of the mandrel being a CMP-stop material. This technique essentially cuts off or removes rounded features such as upper portions of sidewall spacers, thereby providing a spacer material with a planar top surface that can be uniformly etched and transferred to underlying layers.
    Type: Grant
    Filed: February 17, 2015
    Date of Patent: September 6, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Anton J. deVilliers
  • Patent number: 9299705
    Abstract: A semiconductor structure may be formed by forming a first semiconductor fin and a second inactive semiconductor fin above a substrate; depositing a masking layer above the first semiconductor fin and the second semiconductor fin; etching a trench in the masking layer exposing the second semiconductor fin while the first semiconductor fin remains covered by the masking layer; removing the second semiconductor fin to form a fin recess beneath the trench; filling the fin recess with an insulating material to form an insulating fence fin; and removing the masking layer to expose the first semiconductor fin and the insulating fence fin. A third semiconductor fin separating the first semiconductor fin from the second semiconductor fin may also be formed prior to depositing the masking layer and covered by the masking layer. The first semiconductor fin may be a pFET fin and the third semiconductor fin may be an nFET fin.
    Type: Grant
    Filed: February 17, 2014
    Date of Patent: March 29, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Sivananda K. Kanakasabapathy
  • Patent number: 9252050
    Abstract: A method of forming a semiconductor device is disclosed. The method including providing a substrate with at least one insulating layer disposed thereon, the at least one insulating layer including a trench; forming at least one liner layer on the at least one insulating layer; forming a nucleation layer on the at least one liner layer; forming a first metal film on a surface of the nucleation layer; etching the first metal film; and depositing a second metal film on the etched surface of the first metal film, the second metal film substantially forming an overburden above the trench.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: February 2, 2016
    Assignees: International Business Machines Corporation, STMicroelectronics, Inc.
    Inventors: Lindsey H. Hall, Michael Hatzistergos, Ahmet S. Ozcan, Filippos Papadatos, Yiyi Wang
  • Patent number: 9209073
    Abstract: Presented herein is a method for electrolessly forming a metal cap in a via opening, comprising bringing a via into contact with metal solution, the via disposed in an opening in a substrate, and forming a metal cap in the opening and in contact with the via, the metal cap formed by an electroless chemical reaction. A metal solution may be applied to the via to form the metal cap. The metal solution may comprises at least cobalt and the cap may comprise at least cobalt, and may optionally further comprise tungsten, and wherein the forming the cap comprises forming the cap to further comprise at least tungsten. The metal solution may further comprise at least hypophosphite or dimethylaminoborane.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: December 8, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Liang-Yueh Ou Yang, Chih-Yi Chang, Chen-Yuan Kao, Hung-Wen Su
  • Patent number: 9153363
    Abstract: The present invention provides a light-transmitting metal electrode including a substrate and a metal electrode layer having plural openings. The metal electrode layer also has such a continuous metal part that any pair of point-positions in the part is continuously connected without breaks. The openings in the metal electrode layer are periodically arranged to form plural microdomains. The plural microdomains are so placed that the in-plane arranging directions thereof are oriented independently of each other. The thickness of the metal electrode layer is in the range of 10 to 200 nm.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: October 6, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Eishi Tsutsumi, Tsutomu Nakanishi, Akira Fujimoto, Koji Asakawa
  • Publication number: 20150145060
    Abstract: Devices and methods of forming a device are disclosed. A substrate prepared with at least a first transistor and a second transistor is provided. Each of the first and second transistors includes a gate disposed on the substrate between first and second contact regions in the substrate. A silicide block layer is formed on the substrate and is patterned to expose portions of the first and second contact regions. Silicide contacts are formed in the exposed first and second contact regions. The silicide contacts are displaced from sides of the gates of the first and second transistors. A contact dielectric layer is formed and contacts are formed in the contact dielectric layer. The contacts are in communication with the silicide contacts in the contact regions.
    Type: Application
    Filed: November 26, 2013
    Publication date: May 28, 2015
    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Zhibiao ZHOU, Yudi SETIAWAN
  • Publication number: 20150147839
    Abstract: A method for manufacturing a semiconductor device may include: forming a metal layer structure over a semiconductor workpiece; forming a first layer over the metal layer structure, the first layer including a first material; forming at least one opening in the first layer and the metal layer structure; depositing a second layer to fill the at least one opening and at least partially cover a surface of the first layer facing away from the metal layer structure, the second layer including a second material that is different from the first material; removing the second layer from at least the surface of the first layer facing away from the metal layer structure; and removing the first layer.
    Type: Application
    Filed: November 26, 2013
    Publication date: May 28, 2015
    Applicant: Infineon Technologies Dresden GmbH
    Inventors: Alessia Scire, Alfred Vater, Mirko Vogt, Momtchil Stavrev, Tarja Hauck, Bee Kim Hong, Heiko Estel
  • Publication number: 20150140812
    Abstract: Embodiments of methods for etching cobalt metal using fluorine radicals are provided herein. In some embodiments, a method of etching a cobalt layer in a substrate processing chamber includes: forming a plasma from a process gas comprising a fluorine-containing gas; and exposing the cobalt layer to fluorine radicals from the plasma while maintaining the cobalt layer at a temperature of about 50 to about 500 degrees Celsius to etch the cobalt layer.
    Type: Application
    Filed: October 22, 2014
    Publication date: May 21, 2015
    Inventors: BHUSHAN N. ZOPE, AVGERINOS V. GELATOS
  • Publication number: 20150140811
    Abstract: A method of patterning a semiconductor device is disclosed. A tri-layer photoresist is formed over a plurality of patterned features. The tri-layer photoresist includes a bottom layer, a middle layer disposed over the bottom layer, and a top layer disposed over the middle layer, the top layer containing a photo-sensitive material. The top layer is patterned via a photolithography process, the patterned top layer including an opening. The opening is extended into the bottom layer by etching the bottom layer and continuously forming a protective layer on etched surfaces of the bottom layer and on exposed surfaces of the patterned features. The bottom layer is removed. At least some portions of the protective layer remain on the exposed surfaces of the patterned features after the bottom layer is removed.
    Type: Application
    Filed: November 20, 2013
    Publication date: May 21, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Min Huang, Chung-Ju Lee, Yung-Hsu Wu
  • Patent number: 9034758
    Abstract: A spacer etching process produces ultra-narrow conductive lines in a plurality of semiconductor dice. Trenches are formed in a first dielectric then a sacrificial film is deposited onto the first dielectric and the trench surfaces formed therein. Planar sacrificial film is removed from the face of the first dielectric and bottom of the trenches, leaving only sacrificial films on the trench walls. A gap between the sacrificial films on the trench walls is filled in with a second dielectric. A portion of the second dielectric is removed to expose tops of the sacrificial films. The sacrificial films are removed leaving ultra-thin gaps that are filled in with a conductive material. The tops of the conductive material in the gaps are exposed to create “fence conductors.” Portions of the fence conductors and surrounding insulating materials are removed at appropriate locations to produce desired conductor patterns comprising isolated fence conductors.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 19, 2015
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventor: Paul Fest
  • Publication number: 20150118776
    Abstract: A manufacturing method of a display device includes: forming a thin film transistor on a substrate, forming a pixel electrode connected to the thin film transistor, and forming a common electrode insulated from the pixel electrode. At least one of forming the pixel electrode and forming the common electrode includes: forming an electrode layer on the substrate, coating a photoresist on the electrode layer to form a first electrode sub-layer on which the photoresist is coated and a second electrode sub-layer on which the photoresist is not coated, generating etching vapor by heating an etching solution in a double boiler, and etching the second electrode sub-layer by using the etching vapor.
    Type: Application
    Filed: May 1, 2014
    Publication date: April 30, 2015
    Applicant: Samsung Display Co., Ltd.
    Inventors: Hongsick Park, Seon-il Kim
  • Publication number: 20150115414
    Abstract: A sapphire structure with a metal substructure is disclosed. The sapphire structure with a metal substructure includes a sapphire structure and a metal substructure. The sapphire structure includes a flat surface and a concave portion on the flat surface. The metal substructure in the concave portion is bonded to an inner surface of the concave portion and includes a surface portion that is substantially flush with the flat surface.
    Type: Application
    Filed: August 18, 2014
    Publication date: April 30, 2015
    Inventors: Motohiro Umehara, Yoshinori Kubo
  • Patent number: 9018095
    Abstract: A conductive circuit is formed by printing a pattern of an ink composition and curing the pattern. The ink composition is a substantially solvent-free, liquid, addition curable, ink composition comprising (A) an organopolysiloxane having at least two alkenyl groups, (B) an organohydrogenpolysiloxane having at least two SiH groups, (C) conductive particles having an average particle size ?5 ?m, (D) conductive micro-particles having an average particle size <5 ?m, (E) a thixotropic agent, and (F) a hydrosilylation catalyst.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: April 28, 2015
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventor: Yoshitaka Hamada
  • Publication number: 20150111379
    Abstract: A semiconductor structure having a substrate; an active device formed in an active semiconductor region of the substrate, the active device having a control electrode for controlling a flow of carriers through the active semiconductor region between a pair of electrical contacts; and a photolithographic, thickness non-uniformity, compensation feature, disposed on the surface substrate off of the active semiconductor region. In one embodiment the feature comprises pads on the surface of the substrate and off of the active semiconductor region.
    Type: Application
    Filed: January 5, 2015
    Publication date: April 23, 2015
    Inventors: Paul J. Duval, Paul M. Ryan, Christopher J. MacDonald
  • Publication number: 20150111374
    Abstract: Embodiments of present invention provide a method of forming semiconductor devices. The method includes creating an opening in a semiconductor structure; depositing a first layer of metal inside the opening with the first layer of metal partially filling up the opening; modifying a top surface of the first layer of metal in an etching process; passivating the modified top surface of the first layer of metal to form a passivation layer; and depositing a second layer of metal directly on top of the passivation layer.
    Type: Application
    Filed: October 18, 2013
    Publication date: April 23, 2015
    Applicant: International Business Machines Corporation
    Inventors: Ruqiang Bao, Domingo A. Ferrer, Filippos Papadatos, Daniel P. Stambaugh
  • Patent number: 9012325
    Abstract: One or more embodiments relate to a method of making a semiconductor structure, comprising: forming a opening partially through a semiconductor substrate, the opening including an upper portion and a lower portion; forming a first dielectric layer over a sidewall surface of the upper portion, wherein the first dielectric layer does not overlie a sidewall surface of the lower portion; and forming a conductive material over a sidewall surface of the first dielectric layer, the conductive material not being in direct contact with a sidewall surface of the lower portion.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: April 21, 2015
    Assignee: Infineon Technologies AG
    Inventor: Manfred Engelhardt
  • Patent number: 9005462
    Abstract: In a method for manufacturing a silicon carbide semiconductor device, a conductive layer is formed on a silicon carbide layer. The silicon carbide layer and the conductive layer react with each other thus forming an alloy layer formed of a reaction layer in contact with the silicon carbide layer and a silicide layer on the reaction layer. A carbon component is removed from the silicide layer. A portion of the silicide layer is removed using an acid thus exposing at least a portion of the reaction layer. An electrode layer is formed on an upper side of the exposed reaction layer.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: April 14, 2015
    Assignee: Shindengen Electric Manufacturing Co., Ltd.
    Inventor: Jun-ichi Ohno
  • Publication number: 20150087148
    Abstract: An etchant composition including 0.5 wt % to 20 wt % of a persulfate, 0.01 wt % to 1 wt % of a fluorine compound, 1 wt % to 10 wt % of an inorganic acid, 0.01 wt % to 2 wt % of an azole-based compound, 0.1 wt % to 5 wt % of a chlorine compound, 0.05 wt % to 3 wt % of a copper salt, 0.01 wt % to 5 wt % of an antioxidant or a salt thereof, based on a total weight of the etchant composition, and water in an amount sufficient for the total weight of the etchant composition to be equal to 100 wt % is disclosed. The etchant composition is suitable for use in forming a metal wiring by etching a metal layer including copper or in fabricating a thin film transistor substrate for a display apparatus.
    Type: Application
    Filed: April 28, 2014
    Publication date: March 26, 2015
    Applicant: SAMSUNG DISPLAY CO., LTD.
    Inventors: In-Bae Kim, Jong-Hyun Choung, Youngmin Moon, Hongsick Park, Gyu-po Kim, Won-guk Seo, Hyun-cheol Shin, Ki-beom Lee, Sam-young Cho, Seung-yeon Han
  • Patent number: 8987119
    Abstract: A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first semiconductor layer in the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the first semiconductor layer, such that first conductivity type second portions of the first semiconductor layer remain in lower portions of the plurality of openings in the insulating layer, and upper portions of the plurality of openings in the insulating layer remain unfilled. The method also includes forming a second semiconductor layer in the upper portions of the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the second semiconductor layer located over the insulating layer.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: March 24, 2015
    Assignee: Sandisk 3D LLC
    Inventors: Vance Dunton, S. Brad Herner, Paul Wai Kie Poon, Chuanbin Pan, Michael Chan, Michael Konevecki, Usha Raghuram
  • Patent number: 8987134
    Abstract: Semiconductor devices and methods of making thereof are disclosed. The semiconductor device includes a substrate prepared with a first dielectric layer formed thereon. The dielectric layer includes at least first, second and third contact regions. A second dielectric layer is disposed over the first dielectric layer. The device also includes at least first, second and third via contacts disposed in the second dielectric layer. The via contacts are coupled to the respective underlying contact regions and the via contacts do not extend beyond the underlying contact regions.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: March 24, 2015
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Zhehui Wang, Kwee Liang Yeo, Hai Cong, Huang Liu, Wen Zhan Zhou
  • Publication number: 20150076714
    Abstract: A microelectronic structure includes a semiconductor having conductive elements at a first surface. Wire bonds have bases joined to the conductive elements and free ends remote from the bases, the free ends being remote from the substrate and the bases and including end surfaces. The wire bonds define edge surfaces between the bases and end surfaces thereof. A compliant material layer extends along the edge surfaces within first portions of the wire bonds at least adjacent the bases thereof and fills spaces between the first portions of the wire bonds such that the first portions of the wire bonds are separated from one another by the compliant material layer. Second portions of the wire bonds are defined by the end surfaces and portions of the edge surfaces adjacent the end surfaces that are extend from a third surface of the compliant later.
    Type: Application
    Filed: September 16, 2013
    Publication date: March 19, 2015
    Applicant: INVENSAS CORPORATION
    Inventors: Belgacem Haba, Richard Dewitt Crisp, Wael Zohni
  • Publication number: 20150076624
    Abstract: Integrated circuits with smooth metal gates and methods for fabricating integrated circuits with smooth metal gates are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a partially fabricated integrated circuit including a dielectric layer formed with a trench bound by a trench surface. The method deposits metal in the trench and forms an overburden portion of metal overlying the dielectric layer. The method includes selectively etching the metal with a chemical etchant and removing the overburden portion of metal.
    Type: Application
    Filed: September 19, 2013
    Publication date: March 19, 2015
    Applicant: GLOBALFOUNDRIES, Inc.
    Inventors: Huang Liu, Jialin Yu, Jilin Xia
  • Publication number: 20150079786
    Abstract: A solution for processing devices is provided, comprising an activator comprising at least one of pyridine, pyrole, pyrrolidine, pyrimidine, N,N-dimethylformamide, tetraethylamine chloride, 4 pyridinethiol, or other organic compounds with a single N with a lone pair electron activator and an etchant comprising at least one of thionly chloride, Cl2, Br2, I2, SOF2, SOF4, SO2Cl2, SOBr2, S2O6F2, HSO3F, or C2Cl4O2.
    Type: Application
    Filed: September 17, 2013
    Publication date: March 19, 2015
    Inventors: Samantha S.H. Tan, Alexander Kabansky, Joydeep Guha
  • Patent number: 8980762
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a film having different filling properties dependent on space width above the patterning film to cover the first line patterns and the second line patterns to form the film on the first line patterns and on the first inter-line pattern space while making a cavity in the first inter-line pattern space and to form the film on at least a bottom portion of the second inter-line pattern space and a side wall of each of the second line patterns. The method includes performing etch-back of the film to remove the film on the first line patterns and on the first inter-line pattern space while causing the film to remain on at least the side wall of the second line patterns.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: March 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazunori Iida, Yuji Kobayashi
  • Patent number: 8980752
    Abstract: A method of forming a plurality of spaced features includes forming sacrificial hardmask material over underlying material. The sacrificial hardmask material has at least two layers of different composition. Portions of the sacrificial hardmask material are removed to form a mask over the underlying material. Individual features of the mask have at least two layers of different composition, with one of the layers of each of the individual features having a tensile intrinsic stress of at least 400.0 MPa. The individual features have a total tensile intrinsic stress greater than 0.0 MPa. The mask is used while etching into the underlying material to form a plurality of spaced features comprising the underlying material. Other implementations are disclosed.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: March 17, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Farrell Good, Baosuo Zhou, Xiaolong Fang, Fatma Arzum Simsek-Ege
  • Publication number: 20150072523
    Abstract: Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is deposited along an undulating topography that extends across the pedestal and base, and a second electrode is formed over the least one layer. The first electrode, at least one layer, and second electrode together form a structure that conducts current between the first and second electrodes when voltage of one polarity is applied to the structure, and that inhibits current flow between the first and second electrodes when voltage having a polarity opposite to said one polarity is applied to the structure. Some embodiments include diodes having a first electrode that contains two or more projections extending upwardly from a base, having at least one layer over the first electrode, and having a second electrode over the at least one layer.
    Type: Application
    Filed: November 17, 2014
    Publication date: March 12, 2015
    Inventors: Gurtej S. Sandhu, Chandra Mouli
  • Publication number: 20150072522
    Abstract: Provided are an abrasive particle including auxiliary particles formed on a surface of a mother particle, a polishing slurry prepared by mixing the abrasive particles with a polishing accelerating agent and a pH adjusting agent, and a method of manufacturing a semiconductor device in which an insulating layer is polished by the polishing slurry while using a conductive layer as a polishing stop layer.
    Type: Application
    Filed: September 10, 2014
    Publication date: March 12, 2015
    Inventor: Seung Won JUNG
  • Patent number: 8970050
    Abstract: A semiconductor memory device includes a first chip and a second chip connected to the first chip physically and electrically, wherein the first chip and the second chip are coupled by through silicon vias (TSVs) formed in a first region, and the first chip and the second chip are coupled by alignment keys formed in second regions.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: March 3, 2015
    Assignee: SK hynix Inc.
    Inventor: Chang Hyun Lee
  • Publication number: 20150053988
    Abstract: The present invention provides an array substrate, a method for manufacturing the same and a display device, and relates to technical field of displays. The method for manufacturing an array substrate comprises forming a metal layer on a substrate and removing superficial metallic oxide on the metal layer by a washing process. The method for manufacturing an array substrate according to the present inversion can remove the superficial metal oxide on the metal layer and improve the performance of a TFT.
    Type: Application
    Filed: December 13, 2013
    Publication date: February 26, 2015
    Applicants: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Dengtao Li, Jaemoon Chung, Jaeyun Jung, Daeyoung Choi, Shikai Wang, Dongseob Kim, Jun Geng, Shiwei Lv
  • Publication number: 20150050807
    Abstract: Implementations described herein generally relate to methods for forming tungsten materials on substrates using vapor deposition processes. The method comprises positioning a substrate having a feature formed therein in a substrate processing chamber, depositing a first film of a bulk tungsten layer by introducing a continuous flow of a hydrogen containing gas and a tungsten halide compound to the processing chamber to deposit the first tungsten film over the feature, etching the first film of the bulk tungsten layer using a plasma treatment to remove a portion of the first film by exposing the first film to a continuous flow of the tungsten halide compound and an activated treatment gas and depositing a second film of the bulk tungsten layer by introducing a continuous flow of the hydrogen containing gas and the tungsten halide compound to the processing chamber to deposit the second tungsten film over the first tungsten film.
    Type: Application
    Filed: July 22, 2014
    Publication date: February 19, 2015
    Inventors: Kai WU, Sang Ho YU
  • Publication number: 20150044869
    Abstract: A method of forming a semiconductor device is disclosed. The method including providing a substrate with at least one insulating layer disposed thereon, the at least one insulating layer including a trench; forming at least one liner layer on the at least one insulating layer; forming a nucleation layer on the at least one liner layer; forming a first metal film on a surface of the nucleation layer; etching the first metal film; and depositing a second metal film on the etched surface of the first metal film, the second metal film substantially forming an overburden above the trench.
    Type: Application
    Filed: October 23, 2014
    Publication date: February 12, 2015
    Inventors: Lindsey H. Hall, Michael Hatzistergos, Ahmet S. Ozcan, Fillippos Papadatos, Yiyi Wang
  • Publication number: 20150037974
    Abstract: A method of patterning a platinum layer includes the following steps. A substrate is provided. A platinum layer is formed on the substrate. An etching process is performed to pattern the platinum layer, wherein an etchant used in the etching process simultaneously includes at least a chloride-containing gas and at least a fluoride-containing gas.
    Type: Application
    Filed: July 30, 2013
    Publication date: February 5, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hsin-Yi Lu, Yu-Chi Lin, Jeng-Ho Wang
  • Patent number: 8946018
    Abstract: Some embodiments include methods of forming semiconductor constructions. A heavily-doped region is formed within a first semiconductor material, and a second semiconductor material is epitaxially grown over the first semiconductor material. The second semiconductor material is patterned to form circuit components, and the heavily-doped region is patterned to form spaced-apart buried lines electrically coupling pluralities of the circuit components to one another. At least some of the patterning of the heavily-doped region occurs simultaneously with at least some of the patterning of the second semiconductor material.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: February 3, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Jaydip Guha, Shyam Surthi
  • Publication number: 20150028489
    Abstract: A method for efficient off-track routing and the resulting device are disclosed. Embodiments include: providing a hardmask on a substrate; providing a plurality of first mandrels on the hardmask; providing a first spacer on each side of each of the first mandrels; providing a plurality of first non-mandrel regions of the substrate being separated from the first mandrels and between two of the first spacers, each of the first mandrels, first non-mandrel regions, and first spacers having a width equal to a distance; and providing a second mandrel having a width of at least twice the distance and being separated from one of the first non-mandrel regions by a second spacer.
    Type: Application
    Filed: October 14, 2014
    Publication date: January 29, 2015
    Inventors: Lei YUAN, Jongwook KYE, Harry LEVINSON
  • Publication number: 20150031203
    Abstract: A method for processing a workpiece may include: providing a workpiece including a first region and a second region; forming a porous metal layer over the first region and the second region; wherein the first region and the second region are configured such that an adhesive force between the second region and the porous metal layer is lower than an adhesive force between the first region and the porous metal layer.
    Type: Application
    Filed: July 23, 2013
    Publication date: January 29, 2015
    Inventors: Michael KRENZER, Thomas KUNSTMANN, Eva-Maria HESS, Manfred FRANK
  • Publication number: 20150028399
    Abstract: Provided are semiconductor devices and methods of manufacturing the same. The methods include providing a substrate including a first region and a second region, forming first mask patterns in the first region, and forming second mask patterns having an etch selectivity with respect to the first mask patterns in the second region. The first mask patterns and the second mask patterns are formed at the same time.
    Type: Application
    Filed: June 19, 2014
    Publication date: January 29, 2015
    Inventors: Junjie Xiong, Dongho Cha, Myung Jin Kang, Kihoon Do
  • Patent number: 8941244
    Abstract: A semiconductor structure includes a molding compound, a conductive plug, and a cover. The conductive plug is in the molding compound. The cover is over a top meeting joint between the conductive plug and the molding compound. The semiconductor structure further has a dielectric. The dielectric is on the cover and the molding compound.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: January 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Po-Hao Tsai, Jui-Pin Hung, Jing-Cheng Lin, Long-Hua Lee