Method of fabricating a non-volatile memory
A structure of a memory cell includes a substrate, a well, two source/drain doped regions, a stacked layer and a metal gate. The stacked layer includes a tunneling layer, and a charge trapping layer. A method of fabricating the memory cell may vary with the change in sequence of performing steps. The difference in sequence of fabrication may yield different characteristic variations for the formed components of the memory cell.
This non-provisional application claims priority of US provisional application U.S. 61/883,205 filed on Sep. 27, 2013.
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention relates to a non-volatile memory cell, and more specifically, to a non-volatile memory cell having a metal gate and a method of fabricating the non-volatile memory cell.
2. Description of the Prior Art
Non-volatile memory can store data in the absence of a power supply, therefore it is preferred to be used by various portable electronic products such as personal digital assistants (PDAs), mobile phones, and memory cards. In order to respond to the requirements of the market, non-volatile memory technology must have compatibility with CMOS processing, low power consumption, high writing efficiency, low cost, and high density. However, as non-volatile memory becomes smaller in size, the gate oxide layer becomes accordingly thinner making stored data dissipate easily and causes a problem in the data storing ability. And as the gate length becomes smaller, the greater a problem the gate leakage power becomes. A stacked gate memory cell may be used.
In fabricating a stacked gate memory cell using an advance replacement metal gate process, problems may be encountered with regard to fitting the fabrication process of the stacked gate memory cell into the advance replacement metal gate process. Therefore, there is a need for a change in the replacement metal gate process to fit the fabrication process of the stacked gate memory cell.
SUMMARY OF THE INVENTIONAn embodiment of the present invention discloses a method of forming a memory cell. The method comprises providing a substrate, forming a plurality of isolations on the substrate, forming a well on the substrate, forming a stacked layer comprising a tunneling layer and a charge trapping layer on the substrate, forming a high-k gate dielectric layer on the stacked layer, forming a poly silicon gate on the high-k gate dielectric layer, forming at least two source/drain doped regions on the well, removing the poly silicon gate, and depositing a metal to a removed area of the poly silicon gate to form a metal gate.
Another embodiment of the present invention discloses a method of forming a memory cell. The method comprises providing a substrate, forming a plurality of isolations on the substrate, forming a well on the substrate, forming a high-k gate dielectric layer on the well, forming a poly silicon gate on the high-k gate dielectric layer, forming at least two source/drain doped regions on the well, removing the poly silicon gate, forming a stacked layer comprising a tunneling layer and a charge trapping layer and a charge stop layer on a removed area of the poly silicon gate, and depositing a metal to the removed area of the poly silicon gate to form a metal gate.
An additional embodiment of the present invention discloses a memory cell. The memory cell comprises isolations formed on a substrate, a well formed directly on the substrate wherein the isolations define a region of the well, at least two source/drain doped regions formed on the well, a stacked layer comprising a tunneling layer and a charge trapping layer formed between the at least two source/drain doped regions on the well, a high-k gate dielectric layer formed on the stacked layer, and a metal gate formed on the high-k gate dielectric layer.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
In addition, the memory cell 100 may further comprise two lightly doped regions 161 and 162. The two lightly doped regions 161 and 162 may be P-doped regions. The first lightly doped region 161 may be formed on the well 120 in contact with the first source/drain doped region 131 and between the tunneling layer 141 and the first source/drain doped region 131. The second lightly doped region 162 may be formed on the well 120 in contact with the second source/drain doped region 132 and between the tunneling layer 141 and the second source/drain doped region 132. At least two spacers 171 and 172 may be formed on two sides of the stacked layer 140 and the metal gate 150 to protect the two lightly doped regions 161 and 162 when the two source/drain doped regions 131 and 132 are being formed.
To separate the memory cell 100 from other components built on the substrate 110 at least two isolations 191 and 192 may be formed on the substrate 110. A region of the well 120 may be defined by the two isolations 191 and 192.
Step 202: Form at least two isolations 191 and 192 on the substrate 110;
Step 203: Form the well 120 on the substrate 110;
Step 204: Form the stacked layer 140 comprising the tunneling layer 141 and the charge trapping layer 142 on the substrate 110;
Step 205: Form a high-k gate dielectric layer 40 as shown in
Step 206: Form a poly silicon gate 51 as shown in
Step 207: Form a plurality of lightly doped regions 161 and 162 on the well 120;
Step 208: Format least two source/drain doped regions 131 and 132 on the well 120;
Step 209: Remove the poly silicon gate 51;
Step 210: Deposit a metal in place of the removed poly silicon gate 51 to form the metal gate 150.
In step 204, a layer of bottom dielectric compound and a layer of charge trapping compound may be deposited on the substrate 110. Selected areas of the layer of bottom dielectric compound, and the layer of charge trapping compound may be etched to form the stacked layer 140 on the well 120. In step 205, a layer of high-k gate dielectric compound may be deposited on the substrate 110. Selected areas of the layer of high-k gate dielectric compound may be etched to form the high-k gate dielectric layer 40 on the stacked layer 140. In step 206, a layer of poly silicon compound may be deposited on the substrate 110. Selected areas of the layer of poly silicon compound may be etched to form the poly silicon gate 51 on the high-k dielectric layer 40, thereafter the stacked layer 140 and the high-k dielectric layer 40 out of the poly silicon gate 51 are etched as shown in
Step 302: Form at least two isolations 191 and 192 on the substrate 110;
Step 303: Form the well 120 on the substrate 110;
Step 304: Form the stacked layer 140 comprising the tunneling layer 141, the charge trapping layer 142, and the charge stop layer 143 on the substrate 110;
Step 305: Form a high-k gate dielectric layer 40 as shown in
Step 306: Form the poly silicon gate 51 as shown in
Step 307: Form a plurality of lightly doped regions 161 and 162 on the well 120;
Step 308: Form at least two source/drain doped regions 131 and 132 on the well 120;
Step 309: Remove the poly silicon gate 51;
Step 310: Deposit a metal in place of the removed poly silicon gate 51 to form the metal gate 150.
In step 304, the layer of bottom dielectric compound, the layer of charge trapping compound, and a layer of top dielectric compound may be deposited on the substrate 110. Selected areas of the layer of bottom dielectric compound, the layer of charge trapping compound and the top dielectric layer may be etched to form the stacked layer 140 on the well 120. In step 305, a layer of high-k gate dielectric compound may be deposited on the substrate 110. Selected areas of the layer of high-k gate dielectric compound may be etched to form the high-k gate dielectric layer 40 on the stacked layer 140. In step 306, the layer of poly silicon compound may be deposited on the substrate 110. Selected areas of the layer of poly silicon compound may be etched to form the poly silicon gate 51 on the high-k dielectric layer 40, thereafter the stacked layer 140 and the high-k dielectric layer 40 out of the poly silicon gate 51 are etched as shown in
Selected areas of the layer of bottom dielectric compound and the layer of charge trapping compound may be etched from areas of the substrate 110 where the stacked layer 140 is not needed to be formed. The layer of bottom dielectric compound that remained on the substrate 110 after etching may be the tunneling layer 141. The layer of charge trapping compound that remained on the substrate 110 after etching may be the charge trapping layer 142. The tunneling layer 141 may be formed on the substrate 110. The charge trapping layer 142 may be formed on the tunneling layer 141. The high-k gate dielectric layer 40 may be formed on the stacked layer 140 and etched to align with the stacked layer 140 and functioned as a charge stop layer.
Selected areas of the layer of bottom dielectric compound, the layer of charge trapping compound, and the layer of top dielectric compound may be etched from areas of the substrate 110 where the stacked layer 140 is not needed to be formed.
The layer of bottom dielectric compound that remained on the substrate 110 after etching may be the tunneling layer 141. The layer of charge trapping compound that remained on the substrate 110 after etching may be the charge trapping layer 142. The layer of top dielectric compound that remained on the substrate 110 after etching may be the charge stop layer 143. The tunneling layer 141 may be formed on the substrate 110. The charge trapping layer 142 may be formed on the tunneling layer 141. And the charge stop layer 143 may be formed on the charge trapping layer 142. The high-k gate dielectric layer 40 may be formed on the stacked layer 140 and etched to merge with the charge stop layer 143 already formed.
In another embodiment, a layer of photoresist may be deposited on the substrate 110 after the interlayer dielectric 80 is polished in
Step 1202: Form at least two isolations 191 and 192 on the substrate 110;
Step 1203: Form the stacked layer 140 comprising the tunneling layer 141 and the charge trapping layer 142 on the substrate 110;
Step 1204: Form the well 120 on the substrate 110;
Step 1205: Form the high-k gate dielectric layer 40 as shown in
Step 1206: Form the poly silicon gate 51 on the high-k gate dielectric layer 40;
Step 1207: Form a plurality of lightly doped regions 161 and 162 on the well 120;
Step 1208: Format least two source/drain doped regions 131 and 132 on the well 120;
Step 1209: Remove the poly silicon gate 51;
Step 1210: Deposit a metal in place of the removed poly silicon gate 51 to form the metal gate 150.
Step 1302: Form at least two isolations 191 and 192 on the substrate 110;
Step 1303: Form the stacked layer 140 comprising the tunneling layer 141, the charge trapping layer 142, and the charge stop layer 143 on the substrate 110;
Step 1304: Form the well 120 on the substrate 110;
Step 1305: Form the high-k gate dielectric layer 40 as shown in
Step 1306: Form the poly silicon gate 51 on the high-k gate dielectric layer 40;
Step 1307: Form a plurality of lightly doped regions 161 and 162 on the well 120;
Step 1308: Form at least two source/drain doped regions 131 and 132 on the well 120;
Step 1309: Remove the poly silicon gate 51;
Step 1310: Deposit a metal in place of the removed poly silicon gate 51 to form the metal gate 150.
Step 1402: Form the stacked layer 140 comprising the tunneling layer 141, the charge trapping layer 142, and the charge stop layer 143 on the substrate 110;
Step 1403: Form at least two isolations 191 and 192 on the substrate 110;
Step 1404: Form the well 120 on the substrate 110;
Step 1405: Form the high-k gate dielectric layer 40 as shown in
Step 1406: Form the poly silicon gate 51 on the high-k gate dielectric layer 40;
Step 1407: Form a plurality of lightly doped regions 161 and 162 on the well 120;
Step 1408: Form at least two source/drain doped regions 131 and 132 on the well 120;
Step 1409: Remove the poly silicon gate 51;
Step 1410: Deposit a metal in place of the removed poly silicon gate 51 to form the metal gate 150.
For the methods in
Step 1502: Form the at least two isolations 191 and 192 on the substrate 110;
Step 1503: Form the well 120 on the substrate 110;
Step 1504: Form the high-k gate dielectric layer 40 on the substrate 110;
Step 1505: Form the poly silicon gate 51 on the high-k gate dielectric layer 40;
Step 1506: Form a plurality of lightly doped regions 161 and 162 on the well 120;
Step 1507: Format least two source/drain doped regions 131 and 132 on the well 120;
Step 1508: Remove the poly silicon gate 51;
Step 1509: Form the stacked layer 140 comprising the tunneling layer 141, the charge trapping layer 142, and the charge stop layer 143 on the substrate 110;
Step 1510: Deposit a metal in place of the removed poly silicon gate 51 to form the metal gate 150.
For the method of fabrication shown in
If the high-k gate dielectric layer 40 is not etched, the bottom dielectric compound may not be deposited. Instead, the charge trapping compound may be deposited to the hole to form the charge trapping layer 142 on the high-k gate dielectric layer 40. A top dielectric compound may be deposited to the hole to form the charge stop layer 143 on the charge trapping layer 142. Metal is then deposited on top of the charge trapping layer 142 to form the metal gate 150.
In FIGS. 2 and 12-15, the sequence of each of the flowcharts is just some embodiments of the method of the present invention. It is used to illustrate aspects of the present invention and is not intended to limit the scope of the invention. For example, the sequence of forming lightly doped regions and source/drain doped regions may be interchanged such that the source/drain doped regions are formed before forming the lightly doped regions.
The present invention discloses a memory cell with a metal gate and methods of fabricating the memory cell using a replacement metal gate fabrication technology. The memory cell is directly formed on a substrate. The substrate may be a silicon wafer. The use of lightly doped regions reduces the short channel effect on the non-volatile memory cell. The methods of fabricating the memory cell may differ in the sequence each step is performed. The latter components of the memory cell formed may present a closer characteristic to the targeted characteristic of the component since the latter components formed shall not be affected by forming of components formed before the latter components are formed. Also, the use of metal gate shall reduce the problems such as random parasitic resistance or capacitance or missing device gates from random voids or missing metal that is usually found in conventional memory cells using poly silicon gates. Also, standby power is reduced due to the reduction of gate leakage.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims
1. A method of forming a memory cell, comprising:
- providing a substrate;
- forming a plurality of isolations on the substrate;
- forming a well on the substrate;
- forming a stacked layer comprising a tunneling layer and a charge trapping layer on the substrate;
- forming a high-k gate dielectric layer on the stacked layer;
- forming a poly silicon gate on the high-k gate dielectric layer;
- forming at least two source/drain doped regions on the well;
- removing the poly silicon gate; and
- depositing a metal to a removed area of the poly silicon gate to form a metal gate.
2. The method of claim 1, further comprising:
- forming a plurality of lightly doped regions on the well;
- wherein each of the lightly doped regions is between one of the source/drain doped regions and the stacked layer.
3. The method of claim 1, wherein the stacked layer further comprises a charge stop layer formed on the charge trapping layer.
4. The method of claim 3, wherein the step of forming the well on the substrate is proceeded after the step of forming the stacked layer.
5. The method of claim 3, wherein the step of forming the plurality of isolations is proceeded after the step of forming the stacked layer.
6. The method of claim 1, wherein the step of forming the well on the substrate is proceeded after the step of forming the stacked layer.
7. The method of claim 1, wherein the step of forming the plurality of isolations is proceeded after the step of forming the stacked layer.
8. A method of forming a memory cell, comprising:
- providing a substrate;
- forming a plurality of isolations on the substrate;
- forming a well on the substrate;
- forming a high-k gate dielectric layer on the well;
- forming a poly silicon gate on the high-k gate dielectric layer;
- forming at least two source/drain doped regions on the well;
- removing the poly silicon gate;
- forming a stacked layer comprising a tunneling layer, a charge trapping layer and a charge stop layer on a removed area of the poly silicon gate; and
- depositing a metal to the removed area of the poly silicon gate to form a metal gate.
9. The method of claim 8, further comprising:
- forming a plurality of lightly doped regions on the well;
- wherein each of the lightly doped regions is between one of the source/drain doped regions and the stacked layer.
10. A memory cell, comprising:
- isolations formed on a substrate;
- a well formed directly on the substrate wherein the isolations define a region of the well;
- at least two source/drain doped regions formed on the well;
- a stacked layer comprising a tunneling layer and a charge trapping layer formed between the at least two source/drain doped regions on the well;
- a high-k gate dielectric layer formed on the stacked layer; and
- a metal gate formed on the high-k gate dielectric layer.
11. The memory cell of claim 10, wherein the stacked layer further comprises:
- a charge stop layer formed on the charge trapping layer.
12. The memory cell of claim 11, wherein the charge stop layer is a high-k dielectric layer.
13. The memory cell of claim 10, further comprising:
- a spacer formed on each of at least two sides of the metal gate.
14. The memory cell of claim 13, further comprising interlayer dielectric formed on the substrate encompassing the spacer.
15. The memory cell of claim 10, further comprising:
- lightly doped regions formed on the well;
- wherein each of the lightly doped regions is between one of the source/drain doped regions and the stacked layer.
16. The memory cell of claim 10, wherein the tunneling layer is a high-k dielectric layer.
17. The memory cell of claim 10, wherein the metal gate is formed of tungsten, aluminum, titanium nitride, tantalum nitride, tantalum or copper.
18. The memory cell of claim 10, wherein the substrate is a P-substrate, the well is an N-well, and the source/drain doped regions are P-type source/drain doped regions.
Type: Application
Filed: Jun 30, 2014
Publication Date: Apr 2, 2015
Inventors: Wein-Town Sun (Taoyuan County), Cheng-Yen Shen (Taoyuan County)
Application Number: 14/318,703
International Classification: H01L 29/792 (20060101); H01L 29/51 (20060101); H01L 29/66 (20060101);