Multiple Insulator Layers (e.g., Mnos Structure) Patents (Class 257/324)
  • Patent number: 11985822
    Abstract: A memory device is provided. The memory device includes a stacked structure, a tubular element, a conductive pillar and memory cells. The tubular element includes a dummy channel layer and penetrates the stacked structure. The conductive pillar is enclosed by the tubular element and extending beyond a bottom surface of the dummy channel layer. The memory cells are in the stacked structure and electrically connected to the conductive pillar.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: May 14, 2024
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Teng-Hao Yeh, Chih-Wei Hu, Hang-Ting Lue, Guan-Ru Lee
  • Patent number: 11984484
    Abstract: A semiconductor memory device according to an embodiment includes a substrate, a source line, word lines, a pillar, and a first member. The first member is provided to penetrate the source line. The first member includes a first portion which is far from the substrate, and a second portion which is near the substrate. The first member includes a first contact and a first insulating film. The first contact is provided to extend from the first portion to the second portion. The first contact is electrically connected to the substrate. The first insulating film insulates the source line from the first contact. The first member includes a stepped portion at a boundary part between the first portion and the second portion.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: May 14, 2024
    Assignee: Kioxia Corporation
    Inventors: Tomonori Kajino, Taichi Iwasaki, Tatsuya Fujishima, Masayuki Shishido, Nozomi Kido
  • Patent number: 11980031
    Abstract: According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first electrodes, a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and a memory film provided between each of the first electrodes and the semiconductor layer. The semiconductor layer includes a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode. The second portion has a thickness thinner than a thickness of the first portion in a second direction perpendicular to the first direction.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: May 7, 2024
    Assignee: Kioxia Corporation
    Inventors: Takashi Ishida, Yoshiaki Fukuzumi, Takayuki Okada, Masaki Tsuji
  • Patent number: 11974431
    Abstract: The present disclosure provides a method for forming a three-dimensional memory device. The method can comprise forming a film stack with a plurality of dielectric layer pairs on a substrate, forming a channel structure region in the film stack including a plurality of channel structures, and forming a first staircase structure in a first staircase region and a second staircase structure in a second staircase region. Each of the first staircase structure and the second staircase structure can include a plurality of division block structures arranged along a first direction. A first vertical offset defines a boundary between adjacent division block structures. Each division block structure includes a plurality of staircases arranged along a second direction that is different from the first direction. Each staircase includes a plurality of steps arranged along the first direction.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: April 30, 2024
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhong Zhang, Wenyu Hua, Zhiliang Xia
  • Patent number: 11968839
    Abstract: A memory device includes a semiconductor channel, a gate electrode, and a stack located between the semiconductor channel and the gate electrode. The stack includes, from one side to another, a first ferroelectric material portion, a second ferroelectric material portion, and a gate dielectric portion that contacts the semiconductor channel.
    Type: Grant
    Filed: September 6, 2022
    Date of Patent: April 23, 2024
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yanli Zhang, Johann Alsmeier
  • Patent number: 11967555
    Abstract: A semiconductor device includes: a stack structure including conductive patterns and stack insulating layers, which are alternately stacked; a channel structure penetrating the stack structure; a tunnel insulating layer surrounding the channel structure; a cell storage pattern surrounding the tunnel insulating layer; and a dummy storage pattern surrounding the tunnel insulating layer, the dummy storage pattern being spaced apart from the cell storage pattern. The conductive patterns include a select conductive pattern in contact with the tunnel insulating layer.
    Type: Grant
    Filed: January 30, 2023
    Date of Patent: April 23, 2024
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 11967632
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. A stack is formed comprising vertically-alternating first tiers and second tiers above the conductor tier. The stack comprises laterally-spaced memory-block regions having horizontally-elongated trenches there-between. Channel-material strings extend through the first tiers and the second tiers. Material of the first tiers is of different composition from that of the second tiers. A lowest of the first tiers is thicker than the first tiers there-above. The first-tier material is isotropically etched selectively relative to the second-tier material to form void-space in the first tiers. Conducting material is deposited into the trenches and into the void-space in the first tiers. The conducting material fills the void-space in the first tiers that are above the lowest first tier.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: April 23, 2024
    Inventor: John D. Hopkins
  • Patent number: 11956953
    Abstract: Joint opening structures of 3D memory devices and fabricating method are provided. A joint opening structure comprises a first through hole penetrating a first stacked layer and a first insulating connection layer, a first channel structure at the bottom of the first through hole, a first functional layer on the sidewall of the first through hole, a second channel structure on the sidewall of the first functional layer, a third channel structure over the first through hole, a second stacked layer on the third channel structure, a second insulating connection layer on the second stacked layer, a second through hole penetrating the second stacked layer and the second insulating connection layer, a second functional layer disposed on the sidewall of the second through hole, a fourth channel structure on the sidewall of the second functional layer, and a fifth channel structure over the second through hole.
    Type: Grant
    Filed: September 21, 2022
    Date of Patent: April 9, 2024
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhenyu Lu, Wenguang Shi, Guanping Wu, Feng Pan, Xianjin Wan, Baoyou Chen
  • Patent number: 11955441
    Abstract: An interconnect structure comprises a first dielectric layer, a first metal layer, a second dielectric layer, a metal via, and a second metal layer. The first dielectric layer is over a substrate. The first metal layer is over the first dielectric layer. The first metal layer comprises a first portion and a second portion spaced apart from the first portion. The second dielectric layer is over the first metal layer. The metal via has an upper portion in the second dielectric layer, a middle portion between the first and second portions of the first metal layer, and a lower portion in the first dielectric layer. The second metal layer is over the metal via. From a top view the second metal layer comprises a metal line having longitudinal sides respectively set back from opposite sides of the first portion of the first metal layer.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jian-Hong Lin, Kuo-Yen Liu, Hsin-Chun Chang, Tzu-Li Lee, Yu-Ching Lee, Yih-Ching Wang
  • Patent number: 11956950
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The conductive tiers comprise metal along sides of the memory blocks. Silicon is formed between the memory blocks over the metal of the conductive tiers. The silicon and the metal react to form metal silicide therefrom that is directly against and longitudinally-along the metal of individual of the conductive tiers. After the reacting, unreacted of the silicon is removed from between the memory blocks and intervening material is formed between and longitudinally-along the memory blocks. Other embodiments, including structure independent of method, are disclosed.
    Type: Grant
    Filed: December 13, 2022
    Date of Patent: April 9, 2024
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, Nancy M. Lomeli
  • Patent number: 11956964
    Abstract: A semiconductor memory device according to the present embodiment includes a semiconductor substrate, a structure including a plurality of insulating films and a plurality of conductive films alternately stacked on the semiconductor substrate, and a pillar penetrating the structure. The plurality of conductive films include a plurality of first conductive films and a second conductive film arranged closer to the semiconductor substrate than the plurality of first conductive films. The pillar has a first epitaxial growth layer doped with boron and carbon in a part in contact with the semiconductor substrate, and configured to functions as a part of a source side select gate transistor together with the second conductive film. The plurality of first conductive films configured to functions as a part of a plurality of non-volatile memory cells.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: April 9, 2024
    Assignee: Kioxia Corporation
    Inventor: Ken Komiya
  • Patent number: 11943927
    Abstract: A semiconductor memory device includes a tunnel insulating layer, a data storage layer, and a blocking insulating layer that are sequentially disposed. The tunnel insulating layer includes Metal Organic Frameworks (MOF) having a lower dielectric constant than a dielectric constant of the blocking insulating layer.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: March 26, 2024
    Assignee: SK hynix Inc.
    Inventors: Jae Hyun Han, Won Tae Koo
  • Patent number: 11930637
    Abstract: Described is selective deposition of a silicon nitride (SiN) trap layer to form a memory device. A sacrificial layer is used for selective deposition in order to permit selective trap deposition. The trap layer is formed by deposition of a mold including a sacrificial layer, memory hole (MH) patterning, sacrificial layer recess from MH side, forming a deposition-enabling layer (DEL) on a side of the recess, and selective deposition of trap layer. After removing the sacrificial layer from a slit pattern opening, the deposition-enabling layer (DEL) is converted into an oxide to be used as blocking oxide.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: March 12, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Chang Seok Kang, Tomohiko Kitajima, Mihaela A. Balseanu
  • Patent number: 11925026
    Abstract: Disclosed are novel structures and methods for 3D NVM built with vertical transistors above a logic layer. A first embodiment has a conductive film under the transistors and serving as a common node in a memory block. The conductive film may be from a semiconductor layer used to build the transistors. Metal lines are disposed above the transistors for connection through 3D vias to underlying circuitry. Contact plugs may be formed between transistors and metal lines. The conductive film may be coupled to underlying circuitry through contacts on the conductive film or through interconnect vias underneath the film. A second embodiment has conductive lines disposed under the transistors. Either of conductive lines and metal lines may serve as source lines and the other as bit lines for the memory. For low parasitic resistances, the conductive lines may be shorted to bypass metal lines residing in underlying logic layer.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: March 5, 2024
    Inventor: Sang-Yun Lee
  • Patent number: 11903197
    Abstract: A semiconductor device includes gate electrodes and insulating layers spaced apart from each other on a substrate and alternately stacked in a direction perpendicular to an upper surface of the substrate, and channel structures that extend through stack structures. Ones of the structures include a channel insulating layer, a pad layer on the channel insulating layer, and a channel layer. The channel layer includes a first channel region, and a second channel region including a semiconductor material having a length shorter than a length of the first channel region and having an impurity concentration of a first conductivity type and the pad layer includes a semiconductor material doped with a second conductivity type impurity. A height level of a lower surface of the second channel region is lower than a height level of a lower surface of a first erase gate electrode.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: February 13, 2024
    Inventors: Suhwan Lim, Jaehun Jung, Sanghoon Kim, Taehun Kim, Seongchan Lee
  • Patent number: 11887667
    Abstract: A variety of applications can include memory devices designed to provide enhanced gate-induced-drain-leakage (GIDL) current during memory erase operations. The enhanced operation can be provided by enhancing the electric field in the channel structures of select gate transistors to strings of memory cells. The channel structures can be implemented as a segmented portion for drains and a portion opposite a gate. The segmented portion includes one or more fins and one or more non-conductive regions with both fins and non-conductive regions extending vertically from the portion opposite the gate. Variations of a border region for the portion opposite the gate with the segmented portion can include fanged regions extending from the fins into the portion opposite the gate or rounded border regions below the non-conductive regions. Such select gate transistors can be formed using a single photo mask process. Additional devices, systems, and methods are discussed.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: January 30, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Darwin A. Clampitt, Albert Fayrushin, Matthew J. King, Madison D Drake
  • Patent number: 11882699
    Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell for FinFET includes a fin, a control gate and a selective metal gate. The fin is on a top surface of a substrate, wherein the fin has two sidewalls and a top surface, and the fin includes a memory region and a logic region. The control gate is disposed over the fin of the memory region and covers the two sidewalls and the top surface of the fin, wherein the control gate includes a charge trapping layer and a control electrode, wherein the charge trapping layer is sandwiched by the fin and the control electrode. The selective metal gate is disposed over the fin adjacent to the control gate and covers the two sidewalls and the top surface of the fin. The present invention also provides a method of forming said silicon-oxide-nitride-oxide-silicon (SONOS) memory cell.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: January 23, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Liang Yi, Zhiguo Li, Chi Ren
  • Patent number: 11882704
    Abstract: Provided herein may be a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device may include a stacked body including alternately stacked interlayer insulating layers and conductive patterns, and channel structures penetrating the stacked body. Each of the channel structures may include a channel layer vertically extending up to the height of the upper portion of at least one upper conductive pattern disposed uppermost, among the conductive patterns, a memory layer surrounding the channel layer and extending from the lower interlayer insulating layer to the height of the middle portion of the upper conductive pattern, and a doped semiconductor pattern disposed above the channel layer and the memory layer.
    Type: Grant
    Filed: November 22, 2022
    Date of Patent: January 23, 2024
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 11876046
    Abstract: A semiconductor device includes a wiring structure, a stacked structure located over the wiring structure, channel structures passing through the stacked structure, contact plugs passing through the stacked structure and electrically connected to the wiring structure, and insulating spacers each including loop patterns surrounding a sidewall of each of the contact plugs and stacked along the sidewall of each of the contact plugs.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: January 16, 2024
    Assignee: SK hynix Inc.
    Inventor: Ki Hong Lee
  • Patent number: 11871567
    Abstract: A three-dimensional (3D) memory device is disclosed. The 3D memory device comprises an alternating layer stack on a substrate, and a top selective gate cut structure having a laminated structure embedded in an upper portion of the alternating layer stack and extending along a lateral direction. The laminated structure of the top selective gate cut structure comprises a dielectric filling wall and a dummy channel and a dummy functional layer on both sides of the dielectric filling wall.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: January 9, 2024
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventor: Kun Zhang
  • Patent number: 11844219
    Abstract: A semiconductor device includes a semiconductor layer containing metal atoms, a charge storage layer provided on a surface of the semiconductor layer via a first insulating film, and an electrode layer provided on a surface of the charge storage layer via a second insulating film. The thickness of the first insulating film is 5 nm or more and 10 nm or less. The concentration of the metal atoms in the semiconductor layer is 5.0×1017 [EA/cm3] or higher and 1.3×1020 [EA/cm3] or lower.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: December 12, 2023
    Assignee: KIOXIA CORPORATION
    Inventors: Yuta Saito, Shinji Mori, Keiichi Sawa, Kazuhisa Matsuda, Kazuhiro Matsuo, Hiroyuki Yamashita
  • Patent number: 11837639
    Abstract: A semiconductor device and a manufacturing method thereof includes a source contact structure, a gate stack structure including a side region adjacent to the source contact structure, and a center region extending from the side region. The semiconductor device further includes a source gate pattern disposed under the side region of the first gate stack structure. The source gate pattern has an inclined surface facing the source contact structure. The semiconductor device also includes a channel pattern penetrating the center region of the gate stack structure, the channel pattern extending toward and contacting the source contact structure.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: December 5, 2023
    Assignee: SK hynix Inc.
    Inventor: Kang Sik Choi
  • Patent number: 11839079
    Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, the memory device includes a stack structure having interleaved a plurality of conductor layers and a plurality of dielectric layers over a substrate along a vertical direction. The memory device also includes a channel structure extending in the stack structure along the vertical direction. A thickness of at least one of the plurality of dielectric layers is nominally inversely proportional to a width of the channel structure at the same depth.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: December 5, 2023
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Qiguang Wang, Wenxi Zhou
  • Patent number: 11839081
    Abstract: A semiconductor memory device may include a plurality of memory blocks and at least one insulation bridge. The plurality of the memory blocks may be defined by a plurality of slits parallel to each other. The at least one insulation bridge may be formed in at least one slit located on at least one side of a memory block of the plurality of memory blocks to support the adjacent memory blocks.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: December 5, 2023
    Assignee: SK hynix Inc.
    Inventor: Jung Shik Jang
  • Patent number: 11837536
    Abstract: A semiconductor memory structure includes a first cell, a second cell, a first bit line, a first source line, a second bit line and a second source line. The first cell includes a first source structure and a first drain structure, and the second cell includes a second source structure and a second drain structure. The first source line is coupled to the first source structure, and the first bit line is coupled to the first drain structure. The second source line is coupled to the second source structure, and the second bit line is coupled to the second drain structure. A distance between the first source line and the second bit line, a distance between the second bit line and the second source line, and a distance between the second source line and the first bit line are similar.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: December 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Meng-Han Lin, Sai-Hooi Yeong, Chenchen Wang
  • Patent number: 11818895
    Abstract: A semiconductor device includes a substrate, a ferroelectric layer disposed on the substrate in a vertical direction, a charge trap layer disposed on the ferroelectric layer, a gate insulation layer disposed on the charge trap layer, and a gate electrode layer disposed on the gate insulation layer. The charge trap layer includes a metal-organic framework layer and metal particles embedded in the metal-organic framework layer.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: November 14, 2023
    Assignee: SK HYNIX INC.
    Inventors: Won Tae Koo, Jae Gil Lee
  • Patent number: 11810776
    Abstract: A semiconductor device includes a lower structure, a stack structure on the lower structure and extending from a memory cell region into a connection region, gate contact plugs on the stack structure in the connection region, and a memory vertical structure through the stack structure in the memory cell region, wherein the stack structure includes interlayer insulating layers and horizontal layers alternately stacked, wherein, in the connection region, the stack structure includes a staircase region and a flat region, wherein the staircase region includes lowered pads, wherein the flat region includes a flat pad region, a flat edge region, and a flat dummy region between the flat pad region and the flat edge region, and wherein the gate contact plugs include first gate contact plugs on the pads, flat contact plugs on the flat pad region, and a flat edge contact plug on the flat edge region.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: November 7, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seungjun Shin, Siwan Kim, Bonghyun Choi
  • Patent number: 11800708
    Abstract: A nonvolatile memory device and method for fabricating the same are provided. The nonvolatile memory device comprising: a substrate; a mold structure including a first insulating pattern and a plurality of gate electrodes alternately stacked in a first direction on the substrate; and a word line cut region which extends in a second direction different from the first direction and cuts the mold structure, wherein the word line cut region includes a common source line, and the common source line includes a second insulating pattern extending in the second direction, and a conductive pattern extending in the second direction and being in contact with the second insulating pattern and a cross-section in the second direction.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: October 24, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yoo Jin Choi, Jung-Hwan Lee
  • Patent number: 11785772
    Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a memory stack having interleaved a plurality of conductor layers and a plurality of insulating layers, a plurality of channel structures extending in the memory stack, and a source structure extending in the memory stack. The source structure includes a plurality of source contacts each in a respective insulating structure. Two adjacent source contacts are conductively connected to one another by a connection layer, the connection layer includes a pair of first portions being over the two adjacent ones of the plurality of source contacts and a second portion between the pair of first portions. A support structure is between the two adjacent source contacts. The support structure includes a cut structure over interleaved a plurality of conductor portions and a plurality of insulating portions.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: October 10, 2023
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Wenxiang Xu, Wei Xu, Pan Huang, Ping Yan, Zongliang Huo, Wenbin Zhou, Ji Xia
  • Patent number: 11769809
    Abstract: Structures and methods that facilitate the formation of gate contacts for vertical transistors constructed with semiconductor pillars and spacer-like gates are disclosed. In a first embodiment, a gate contact rests on an extended gate region, a piece of a gate film, patterned at a side of a vertical transistor at the bottom of the gate. In a second embodiment, an extended gate region is patterned on top of one or more vertical transistors, resulting in a modified transistor structure. In a third embodiment, a gate contact rests on a top surface of a gate merged between two closely spaced vertical transistors. Optional methods and the resultant intermediate structures are included in the first two embodiments in order to overcome the related topography and ease the photolithography. The third embodiment includes alternatives for isolating the gate contact from the semiconductor pillars or for isolating the affected semiconductor pillars from the substrate.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: September 26, 2023
    Assignee: BESANG, INC.
    Inventor: Sang-Yun Lee
  • Patent number: 11765898
    Abstract: Embodiments of three-dimensional memory device architectures and fabrication methods therefore are disclosed. In an example, the memory device includes a substrate having a first layer stack on it. The first layer stack includes alternating conductor and insulator layers. A second layer stack is disposed over the first layer stack where the second layer stack also includes alternating conductor and insulator layers. One or more vertical structures extend through the first layers stack. A conductive material is disposed on a top surface of the one or more vertical structures. One or more second vertical structures extend through the second layer stack and through a portion of the conductive material.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: September 19, 2023
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Jun Liu, Zongliang Huo
  • Patent number: 11756623
    Abstract: A semiconductor storage device includes word lines extending in first and second directions, and separated from each other in a third direction, sense amplifier circuits that partially overlap the word lines in the third direction, memory strings intersecting the word lines and extending in the third direction, memory-side bit lines extending in the first direction, separated from each other in the second direction, and including first and second adjacent memory-side bit lines, circuit-side bit lines between the word lines and the sense amplifier circuits and partially overlapping the respective memory-side bit lines in the third direction, and contact plugs extending in the third direction and respectively connecting the memory-side bit lines and the circuit-side bit lines. The contact plugs include first and second contract plugs that are electrically connected to the first and second memory-side bit lines, respectively, and are not aligned along the first or second direction.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: September 12, 2023
    Assignee: Kioxia Corporation
    Inventor: Hiroshi Maejima
  • Patent number: 11735240
    Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, the 3D memory device includes a film stack having a plurality of conductive and dielectric layer pairs vertically stacked on a substrate. Each conductive and dielectric layer pair includes a dielectric layer and a conductive layer. The 3D memory device also includes a staircase region having a first and a second staircase structure formed in the film stack, where the first and second staircase structures each extends laterally in a first direction and includes the plurality of conductive and dielectric layer pairs. The staircase region further includes a staircase bridge connecting the first and second staircase structures.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: August 22, 2023
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventor: Qiang Tang
  • Patent number: 11737277
    Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including interlayer insulating layers and first gate electrodes alternately stacked on each other, a semiconductor layer in an opening penetrating through the stack structure, a first dielectric layer between the semiconductor layer and the stack structure, and a lower pattern closer to the substrate than to the first gate electrodes in the stack structure, the lower pattern including a first surface facing the first dielectric layer, and a second surface facing the stack structure, the second surface defining an acute angle with the first surface, wherein the first dielectric layer includes a first portion facing the stack structure, and a second portion facing the first surface of the lower pattern, the second portion having a thickness greater than a thickness of the first portion.
    Type: Grant
    Filed: November 10, 2021
    Date of Patent: August 22, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji Hoon Choi, Sung Gil Kim, Seulye Kim, Jung Ho Kim, Hong Suk Kim, Phil Ouk Nam, Jae Young Ahn, Han Jin Lim
  • Patent number: 11728326
    Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the method for forming a memory device includes the following operations. First, a plurality of first semiconductor channels can be formed over a first wafer with a peripheral device and a plurality of first via structures neighboring the plurality of first semiconductor channels. The plurality of first semiconductor channels can extend along a direction perpendicular to a surface of the first wafer. Further, a plurality of second semiconductor channels can be formed over a second wafer with a plurality of second via structures neighboring the plurality of second semiconductor channels. The plurality of second semiconductor channels can extend along a direction perpendicular to a surface of the second wafer and a peripheral via structure.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: August 15, 2023
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Ziqi Chen, Chao Li, Guanping Wu
  • Patent number: 11729983
    Abstract: A semiconductor device and method of forming thereof that includes a transistor of a peripheral circuit on a substrate. A first interconnect structure such as a first access line is formed over the transistor. A via extends above the first access line. A plurality of memory cell structures is formed over the interconnect structure and the via. A second interconnect structure, such as a second access line, is formed over the memory cell structure. The first access line is coupled to a first memory cell of the plurality of memory cell structures and second access line is coupled to a second memory cell of the plurality of memory cell structures.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sheng-Chih Lai, Chung-Te Lin
  • Patent number: 11729978
    Abstract: Embodiments of a memory finger structure and architecture for a three-dimensional memory device and fabrication method thereof are disclosed. The method includes forming an alternating layer stack, forming a plurality of slit structures, forming a plurality of conductor/dielectric layer pairs, forming a first column of vertical memory strings, forming a second column of vertical memory strings, and forming a plurality of bitlines. The plurality of slit structures each extend vertically through the alternating layer stack and laterally along a wordline direction to divide the alternating layer stack into at least one memory finger. The vertical memory strings in the first column are displaced relative to each other along the wordline direction. The vertical memory strings in the second column are displaced relative to each other along the wordline direction. Each bitline is connected to an individual vertical memory string in the first and second columns.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: August 15, 2023
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventor: Jun Liu
  • Patent number: 11721725
    Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gate lines above the quantum well stack; a plurality of second gate lines above the quantum well stack, wherein the second gate lines are perpendicular to the first gate lines; and an array of regularly spaced magnet lines.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: August 8, 2023
    Assignees: Intel Corporation, Technische Universiteit Delft
    Inventors: Kanwaljit Singh, James S. Clarke, Menno Veldhorst, Lieven Mark Koenraad Vandersypen
  • Patent number: 11711918
    Abstract: Provided is a semiconductor memory device. The semiconductor memory device comprises a first semiconductor pattern including a first impurity region, a second impurity region, and a channel region, the first impurity region spaced apart from a substrate in a first direction and having a first conductivity type, the second impurity region having a second conductivity type different from the first conductivity type, and the channel region between the first impurity region and the second impurity region, a first conductive connection line connected to the first impurity region and extending in a second direction different from the first direction and a first gate structure extending in the first direction and including a first gate electrode and a first gate insulating film, wherein the first gate electrode penetrates the channel region and the first gate insulating film is between the first gate electrode and the semiconductor pattern.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: July 25, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung Hwan Lee, Yong Seok Kim, Hyun Cheol Kim, Satoru Yamada, Sung Won Yoo, Jae Ho Hong
  • Patent number: 11705501
    Abstract: Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a stacked body including interlayer insulating layers and a select line disposed between the interlayer insulating layers, a core insulating layer penetrating the stacked body, a semiconductor pattern extending along a sidewall of the core insulating layer and including an undoped area disposed between the select line and the core insulating layer, doped semiconductor patterns disposed between the semiconductor pattern and the interlayer insulating layers, and a gate insulating layer disposed between the semiconductor pattern and the select line.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: July 18, 2023
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 11699732
    Abstract: Memory device includes a bottom-select-gate (BSG) structure formed on a substrate. Cut slits are formed vertically through the BSG structure. A cell-layers structure is formed on the BSG structure. Gate-line slits are formed vertically through the cell-layers structure and the BSG structure, into the substrate and arranged along a first lateral direction to distinguish finger regions. The gate-line slits include a first gate-line slit between first and second finger regions, the first gate-line slit including gate-line sub-slits. The cut slits include a first cut-slit, formed in the second finger region and connecting to a gate-line sub-slit to define a BSG in a first portion of the second finger region. The BSG in the first portion of the second finger region is electrically connected to cell strings in the first finger region through an inter portion between the one gate-line sub-slit and an adjacent gate-line sub-slit.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: July 11, 2023
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhongwang Sun, Zhong Zhang, Lei Liu, Wenxi Zhou, Zhiliang Xia
  • Patent number: 11695056
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. A stack is formed comprising vertically-alternating first tiers and second tiers above the conductor tier. The stack comprises laterally-spaced memory-block regions having horizontally-elongated trenches there-between. Channel-material strings extend through the first tiers and the second tiers. Material of the first tiers is of different composition from that of the second tiers. A lowest of the first tiers is thicker than the first tiers there-above. The first-tier material is isotropically etched selectively relative to the second-tier material to form void-space in the first tiers. Conducting material is deposited into the trenches and into the void-space in the first tiers. The conducting material fills the void-space in the first tiers that are above the lowest first tier.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: July 4, 2023
    Assignee: Micron Technology, Inc.
    Inventor: John D. Hopkins
  • Patent number: 11696447
    Abstract: A semiconductor device includes a substrate having cell array and extension regions, a gate electrode structure having gate electrodes stacked in a first direction, a channel through the gate electrode structure on the cell array region, a first division pattern extending in the second direction on the cell array and extension regions, the first division pattern being at opposite sides of the gate electrode structure in a third direction, an insulation pattern structure partially through the gate electrode structure on the extension region, a through via through the insulation pattern structure, and a support layer on the gate electrode structure and extending on the cell array and extension regions, the support layer contacting an upper sidewall of the first division pattern, and the support layer not contacting an upper surface of a portion of the first division pattern on the extension region adjacent to the insulation pattern structure.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: July 4, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Beyounghyun Koh, Seungmin Song, Joongshik Shin, Yongjin Kwon, Jinhyuk Kim, Hongik Son
  • Patent number: 11683934
    Abstract: A nonvolatile memory device with improved operation performance and reliability, and a method for fabricating the same are provided. The nonvolatile memory device includes a substrate, a peripheral circuit structure on the substrate, a mold structure including a plurality of insulating patterns and a plurality of gate electrodes stacked alternately on the peripheral circuit structure, a channel structure penetrating the mold structure, a first impurity pattern in contact with first portions of the channel structure and having a first conductivity type, on the mold structure, and a second impurity pattern in contact with second portions of the channel structure and having a second conductivity type different from the first conductivity type, on the mold structure.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: June 20, 2023
    Inventors: Young-Jin Jung, Bong Tae Park, Ho Jun Seong
  • Patent number: 11672126
    Abstract: A three-dimensional memory device including first and second stacking structures and first and second conductive pillars is provided. The first stacking structure includes first stacking layers stacked along a vertical direction. Each first stacking layer includes a first gate layer, a first channel layer, and a first ferroelectric layer between the first gate and channel layers. The second stacking structure is laterally spaced from the first stacking structure and includes second stacking layers stacked along the vertical direction. Each second stacking layer includes a second gate layer, a second channel layer, and a second ferroelectric layer is between the second gate and channel layers. The first and second gate layers are disposed between the first and second ferroelectric layers, and the first and second conductive pillars extend along the vertical direction in contact respectively with the first and second channel layers.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: June 6, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-I Wu, Sai-Hooi Yeong, Yu-Ming Lin, Han-Jong Chia
  • Patent number: 11664281
    Abstract: A semiconductor device is provided. The semiconductor device includes a stack structure disposed on a lower structure; an insulating structure disposed on the stack structure; and a vertical structure extending in a direction perpendicular to an upper surface of the lower structure and having side surfaces opposing the stack structure and the insulating structure. The stack structure includes interlayer insulating layers and gate layers, alternately stacked, and the insulating structure includes a lower insulating layer, an intermediate insulating layer on the lower insulating layer, and an upper insulating layer on the intermediate insulating layer.
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: May 30, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hui Chang Moon
  • Patent number: 11665903
    Abstract: Embodiments of methods to form three-dimensional (3D) memory devices include the following operations. First, an initial channel hole is formed in a stack structure of a plurality first layers and a plurality of second layers alternatingly arranged over a substrate. An offset is formed between a side surface of each one of the plurality of first layers and a side surface of each one of the plurality of second layers on a sidewall of the initial channel hole to form a channel hole. A semiconductor channel is formed by filling the channel hole with a channel-forming structure, the semiconductor channel having a memory layer including a plurality of first memory portions each surrounding a bottom of a respective second layer and a plurality of second memory portions each connecting adjacent first memory portions.
    Type: Grant
    Filed: November 21, 2020
    Date of Patent: May 30, 2023
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventor: Li Hong Xiao
  • Patent number: 11653495
    Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a method for forming a 3D memory device includes the following operations. A cut structure is first formed in a stack structure. The stack structure includes interleaved initial sacrificial layers and initial insulating layers. A patterned cap material layer is formed over the stack structure. The patterned cap material layer includes an opening over the cut structure. Portions of the stack structure and the patterned cap material layer adjacent to the opening are removed to form a slit structure and an initial support structure. The initial support structure divides the slit structure into slit openings. Conductor portions are formed through the plurality of slit openings to form a support structure. A source contact is formed in each slit opening. A connection layer is formed over the source contact in each slit opening and over the support structure.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: May 16, 2023
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Wenxiang Xu, Wei Xu, Pan Huang, Ping Yan, Zongliang Huo, Wenbin Zhou, Ji Xia
  • Patent number: 11640243
    Abstract: A method and apparatus is disclosed for using supervised learning with closed loop feedback to improvement of output consistency for memory arrangements, such as a solid state drive.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: May 2, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Rushang Karia, Mervyn Wongso, Jacob Schmier, Kevin Corbin, Lakshmana Rao Chintada
  • Patent number: 11637123
    Abstract: A semiconductor device according to one embodiment is provided with: a substrate; a stacked body provided on the substrate; and a pillar portion penetrating the stacked body. The pillar portion has a first film including a first material and a second material, and a second film provided on an inner side of the first film. The second material is a material that increases an etching rate of the first material as a composition rate relative to the first material is higher, and the composition rate gradually decreases from an upper part to a lower part of the first film.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: April 25, 2023
    Assignee: Kioxia Corporation
    Inventors: Atsushi Fukumoto, Keisuke Suda, Takayuki Ito