Multiple Insulator Layers (e.g., Mnos Structure) Patents (Class 257/324)
  • Patent number: 11329129
    Abstract: The disclosure provides transistor cells for integrated circuits and methods to form the same. A transistor cell according to the disclosure may include a substrate region including width between a first end and a second end, and a length between a third end and a fourth end in a direction orthogonal to the width. A first doped well (FDW) within the substrate region may be oppositely doped and may extend from the first end to a first interior boundary between the first and second ends of the substrate region, and from the third end to a second interior boundary between the third and fourth ends. A second doped well (SDW) within the substrate region may extend from the second end to a third interior boundary between the first and second ends, and the fourth end to a fourth interior boundary between the third and fourth ends.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: May 10, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Stefan G. Block, Farid Labib, Herbert J. Preuthen
  • Patent number: 11329062
    Abstract: A method used in forming a memory array comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. The stack comprises an insulator tier above the wordline tiers. The insulator tier comprises first insulator material comprising silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus. The first insulator material is patterned to form first horizontally-elongated trenches in the insulator tier. Second insulator material is formed in the first trenches along sidewalls of the first insulator material. The second insulator material is of different composition from that of the first insulator material and narrows the first trenches. After forming the second insulator material, second horizontally-elongated trenches are formed through the insulative tiers and the wordline tiers. The second trenches are horizontally along the narrowed first trenches laterally between and below the second insulator material.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: May 10, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Justin B. Dorhout, Erik Byers, Merri L. Carlson, Indra V. Chary, Damir Fazil, John D. Hopkins, Nancy M. Lomeli, Eldon Nelson, Joel D. Peterson, Dimitrios Pavlopoulos, Paolo Tessariol, Lifang Xu
  • Patent number: 11322515
    Abstract: A three-dimensional semiconductor device is disclosed. The device may include first and second stacks separated from each other in a first direction, with each of the stacks including electrodes vertically stacked on a substrate. The device may also include vertical channel structures that penetrate the electrodes and are connected to the substrate, an interlayered insulating layer on top surfaces of the vertical channel structures, and a support pattern located between opposite sidewalls of the first and second stacks, in the interlayered insulating layer. A bottom surface of the support pattern may be positioned at a higher level than a top surface of an uppermost electrode of the electrodes.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: May 3, 2022
    Inventor: Juhak Song
  • Patent number: 11322517
    Abstract: A semiconductor device includes a stack structure including conductive layers and insulating layers, which are alternately stacked; an opening including a first opening penetrating the stack structure and second openings protruding from the first opening; and a channel layer including channel regions located in the second openings and impurity regions located in the first opening, the impurity regions having an impurity concentration higher than that of the channel regions.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: May 3, 2022
    Assignee: SK hynix Inc.
    Inventors: Jin Ho Bin, Il Young Kwon, Il Do Kim
  • Patent number: 11322591
    Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gate lines above the quantum well stack; a plurality of second gate lines above the quantum well stack, wherein the second gate lines are perpendicular to the first gate lines; and an array of regularly spaced magnet lines.
    Type: Grant
    Filed: June 24, 2017
    Date of Patent: May 3, 2022
    Assignee: Intel Corporation
    Inventors: Kanwaljit Singh, James S. Clarke, Menno Veldhorst, Lieven Mark Koenraad Vandersypen
  • Patent number: 11322492
    Abstract: A semiconductor device includes a ring-shaped gate electrode having an opening area disposed on a substrate, a source region and a bulk tap region disposed in the opening area, a well region disposed to overlap the ring-shaped gate electrode, a drift region disposed to be in contact with the well region, a first insulating isolation region disposed, on the drift region, to partially overlap the gate electrode, a second insulating isolation region enclosing the bulk tap region, a drain region disposed to be spaced apart from the ring-shaped gate electrode, and a deep trench isolation region disposed adjacent to the drain region.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: May 3, 2022
    Assignee: KEY FOUNDRY CO., LTD.
    Inventor: Hyun Kwang Shin
  • Patent number: 11322441
    Abstract: A semiconductor storage device according to an embodiment includes: an array chip having a memory cell array; a circuit chip having a circuit electrically connected to a memory cell; and a metal pad bonding the array chip and the circuit chip together. The metal pad includes an impurity. A concentration of the impurity is lowered as separating in a depth direction apart from a surface in a thickness direction of the metal pad.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: May 3, 2022
    Assignee: Kioxia Corporation
    Inventor: Satoshi Wakatsuki
  • Patent number: 11315948
    Abstract: A three-dimensional semiconductor device includes a stacked structure including a plurality of conductive layers stacked on a substrate, a distance along a first direction between sidewalls of an upper conductive layer and a lower conductive layer being smaller than a distance along a second direction between sidewalls of the upper conductive layer and the lower conductive layer, the first and second directions crossing each other and defining a plane parallel to a surface supporting the substrate, and vertical channel structures penetrating the stacked structure.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: April 26, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Yong Park, Jintaek Park
  • Patent number: 11315944
    Abstract: The present technology provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a channel structure, insulating structures surrounding the channel structure and stacked to be spaced apart from each other, interlayer insulating films surrounding the insulating structures, respectively, and a gate electrode extending from between the interlayer insulating films to between the insulating structures and surrounding the channel structure. The insulating structures may include protrusion portions extending to cover edges of the interlayer insulating films facing the channel structure, and the gate electrode may extend between the protrusion portions which are adjacent to each other.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: April 26, 2022
    Assignee: SK hynix Inc.
    Inventors: Moon Sik Seo, Gil Bok Choi
  • Patent number: 11309327
    Abstract: Embodiments of a channel hole plug structure of 3D memory devices and fabricating methods thereof are disclosed. The memory device includes an alternating layer stack disposed on a substrate, an insulating layer disposed on the alternating dielectric stack, a channel hole extending vertically through the alternating dielectric stack and the insulating layer, a channel structure including a channel layer in the channel hole, and a channel hole plug in the insulating layer and above the channel structure. The channel hole plug is electrically connected with the channel layer. A projection of the channel hole plug in a lateral plane covers a projection of the channel hole in the lateral plane.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: April 19, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Li Hong Xiao, Zhenyu Lu, Qian Tao, Yushi Hu, Jun Chen, LongDong Liu, Meng Wang
  • Patent number: 11309329
    Abstract: A NOR-type three-dimensional memory device includes a vertically alternating stack of insulating layers and electrically conductive layers located over a substrate, and laterally alternating sequences of respective active region pillars and respective memory stack structures. Each laterally alternating sequence is electrically isolated from the electrically conductive layers by a respective blocking dielectric layer at each level of the electrically conductive layers. Each memory stack structures include a memory film and a semiconductor channel material portion that vertically extend through the vertically alternating stack. The active region pillars include an alternating sequence of source pillar and drain pillars.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: April 19, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Hanan Borukhov
  • Patent number: 11302684
    Abstract: In one embodiment, a semiconductor device includes a first interconnection including a first extending portion extending in a first direction, and a first curved portion curved with respect to the first extending portion. The device further includes a second interconnection including a second extending portion extending in the first direction and adjacent to the first extending portion in a second direction, and a second curved portion curved with respect to the second extending portion. The device further includes a first plug provided on the first curved portion, or on a first non-opposite portion included in the first extending portion and not opposite to the second extending portion in the second direction. The device further includes a second plug provided on the second curved portion, or on a second non-opposite portion included in the second extending portion and not opposite to the first extending portion in the second direction.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: April 12, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Jun Iijima, Yumi Nakajima
  • Patent number: 11302708
    Abstract: Some embodiments include a method of forming an assembly (e.g., a memory array). A first opening is formed through a stack of alternating first and second levels. The first levels contain silicon nitride, and the second levels contain silicon dioxide. Some of the silicon dioxide of the second levels is replaced with memory cell structures. The memory cell structures include charge-storage regions adjacent charge-blocking regions. Tunneling material is formed within the first opening, and channel material is formed adjacent the tunneling material. A second opening is formed through the stack. The second opening extends through remaining portions of the silicon dioxide, and through the silicon nitride. The remaining portions of the silicon dioxide are removed to form cavities. Conductive regions are formed within the cavities. The silicon nitride is removed to form voids between the conductive regions. Some embodiments include memory arrays.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: April 12, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Changhan Kim, Chet E. Carter, Cole Smith, Collin Howder, Richard J. Hill, Jie Li
  • Patent number: 11302712
    Abstract: A method used in forming integrated circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack comprises a cavity therein that comprises a stair-step structure. At least a portion of sidewalls of the cavity is lined with sacrificial material. Insulative material is formed in the cavity radially inward of the sacrificial material. At least some of the sacrificial material is removed from being between the cavity sidewalls and the insulative material to form a void space there-between. Insulator material is formed in at least some of the void space. Other embodiments, including structure independent of method, are disclosed.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: April 12, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Chandra Tiwari, Jivaan Kishore Jhothiraman
  • Patent number: 11302715
    Abstract: Embodiments of three-dimensional (3D) memory devices having a memory layer that confines electron transportation and methods for forming the same are disclosed. The 3D memory device can include a structure of a plurality of gate electrodes insulated by a sealing structure over a substrate. The sealing structure can include an airgap between adjacent gate electrodes along a direction perpendicular to a top surface of the substrate. The 3D memory device can also include a semiconductor channel extending from a top surface of the structure to the substrate. The semiconductor channel can include a memory layer that has two portions extending along different directions. The 3D memory device can further include a source structure extending from the top surface of the structure to the substrate and between adjacent gate electrodes along a direction parallel to the top surface the substrate.
    Type: Grant
    Filed: November 21, 2020
    Date of Patent: April 12, 2022
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Jun Liu, Li Hong Xiao, Yu Ting Zhou
  • Patent number: 11295815
    Abstract: An integrated circuit device includes a plurality of word lines, a string selection line structure stacked on the plurality of word lines, and a plurality of channel structures extending in a vertical direction through the plurality of word lines and the string selection line structure. The string selection line structure includes a string selection bent line including a lower horizontal extension portion extending in a horizontal direction at a first level higher than the plurality of word lines, an upper horizontal extension portion extending in the horizontal direction at a second level higher than the first level, and a vertical extension portion connected between the lower horizontal extension portion and the upper horizontal extension portion.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: April 5, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwanyong Kim, Sunil Shim, Wonseok Cho
  • Patent number: 11296107
    Abstract: Embodiments of a memory finger structure and architecture for a three-dimensional memory device and fabrication method thereof are disclosed. The memory device includes an alternating layer stack disposed on a first substrate, the alternating layer stack including a plurality of conductor/dielectric layer pairs. The memory device further includes a first column of vertical memory strings extending through the alternating layer stack, and a first plurality of bitlines displaced along a first direction and extending along a second direction. The first column of vertical memory strings is disposed at a first angle relative to the second direction. Each of the first plurality of bitlines is connected to an individual vertical memory string in the first column.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: April 5, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventor: Jun Liu
  • Patent number: 11296110
    Abstract: A nonvolatile memory device includes a mold structure including a plurality of insulating patterns and a plurality of gate electrodes alternately stacked on a substrate, a semiconductor pattern penetrating through the mold structure and contacting the substrate, a first charge storage film, and a second charge storage film separated from the first charge storage film. The first and second charge storage films are disposed between each of the gate electrodes and the semiconductor pattern. Each of the gate electrodes includes a first recess and a second recess which are respectively recessed inward from a side surface of the gate electrodes. The first charge storage film fills at least a portion of the first recess, and the second charge storage film fills at least a portion of the second recess.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: April 5, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwang Young Jung, Jong Won Kim, Young Hwan Son, Jee Hoon Han
  • Patent number: 11289488
    Abstract: Disclosed is a semiconductor memory device including a stack structure including layers which are vertically stacked on a substrate and each of which includes a bit line extending in a first direction and a semiconductor pattern extending in a second direction from the bit line, a gate electrode which is in a hole penetrating the stack structure and extending along a stack of semiconductor patterns, a vertical insulating layer covering the gate electrode and filling the hole, and a data storage element electrically connected to the semiconductor pattern. The data storage element includes a first electrode, which is in a first recess of the vertical insulating layer and has a cylindrical shape whose one end is opened, and a second electrode, which includes a first protrusion in a cylinder of the first electrode and a second protrusion in a second recess of the vertical insulating layer.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: March 29, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joongchan Shin, Jiyoung Kim, Hui-Jung Kim, Taehyun An, Eunju Cho, Hyungeun Choi, Sangyeon Han
  • Patent number: 11282853
    Abstract: According to one embodiment, a semiconductor memory device includes a base layer, conductive layers, an insulation layer, a semiconductor layer and a charge storage layer. The conductive layers are stacked above the base layer in a first direction. The insulation layer is extending in the conductive layers in the first direction. The semiconductor layer is arranged between the insulation layer and the conductive layers. The charge storage layer is arranged between the semiconductor layer and the conductive layers. The insulation layer includes a first insulation layer arranged on a side of the base layer and containing polysilazane and a second insulation layer arranged on the first insulation layer on a side opposite from the base layer.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: March 22, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Shinichi Sotome, Tatsufumi Hamada, Yasuhiro Uchimura, Tomohiro Kuki
  • Patent number: 11282932
    Abstract: A semiconductor memory device includes a stacked structure and a memory pillar. The stacked structure includes electrode layers and insulating layers alternately provided on a substrate. The memory pillar extends through the stacked structure in a thickness direction. The memory pillar includes a semiconductor layer extending along the thickness direction, and a first insulating film, a charge storage layer, and a second insulating film provided around the semiconductor layer. The charge storage layer contains fluorine, and a fluorine concentration in the charge storage layer has a gradient along a plane direction of the substrate with a peak. A first distance from an inner end of the charge storage layer to the peak in the plane direction is shorter than a second distance from an outer end of the charge storage layer to the peak in the plane direction.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: March 22, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Shunsuke Okada, Tatsunori Isogai, Masaki Noguchi
  • Patent number: 11282931
    Abstract: A memory device includes a floating gate, a control gate, a spacer structure, a dielectric layer, and an erase gate. The floating gate is above a substrate. The floating gate has a curved sidewall. The control gate is above the floating gate. The spacer structure is in contact with the control gate and the floating gate. The spacer structure is spaced apart from the curved sidewall of the floating gate. The dielectric layer is in contact with the spacer structure and the curved sidewall of the floating gate. The erase gate is above the dielectric layer.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: March 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chu Lin, Chi-Chung Jen, Chia-Ming Pan, Su-Yu Yeh, Keng-Ying Liao, Chih-Wei Sung
  • Patent number: 11276643
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a power rail; a bottom semiconductor layer formed over the dielectric layer; a backside spacer formed along a sidewall of the bottom semiconductor layer; a conductive feature contacting a sidewall of the dielectric layer and a sidewall of the backside spacer; channel semiconductor layers over the bottom semiconductor layer, wherein the channel semiconductor layers are stacked up and separated from each other; a metal gate structure wrapping each of the channel semiconductor layers; and an epitaxial source/drain (S/D) feature contacting a sidewall of each of the channel semiconductor layers, wherein the epitaxial S/D feature contacts the conductive feature, and the conductive feature contacts the power rail.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: March 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Yu Huang, Jason Yao, Fu-Kai Yang, Mei-Yun Wang
  • Patent number: 11276530
    Abstract: An MIM capacitor or an MIS capacitor in semiconductor devices is formed of a thin dielectric layer having a total film thickness less than 100-nm and including a high-dielectric-constant amorphous insulating film, high-breakdown-voltage amorphous films such as of SiO2, and high-dielectric-constant amorphous buffer films between an upper electrode and a lower electrode. The thin high-dielectric-constant amorphous insulation film is formed of a material having a property resistant to fracture although having properties of a large leakage current and a low breakdown voltage, to enhance reliability of the thin dielectric layer and to reduce the footprint thereof in the semiconductor device.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: March 15, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventor: Masahiro Totsuka
  • Patent number: 11264400
    Abstract: In some embodiments, a semiconductor substrate includes first and second source/drain regions which are separated from one another by a channel region. The channel region includes a first portion adjacent to the first source/drain region and a second portion adjacent the second source/drain region. A select gate is spaced over the first portion of the channel region and is separated from the first portion of the channel region by a select gate dielectric. A memory gate is spaced over the second portion of the channel region and is separated from the second portion of the channel region by a charge-trapping dielectric structure. The charge-trapping dielectric structure extends upwardly alongside the memory gate to separate neighboring sidewalls of the select gate and memory gate from one another. An oxide spacer or nitride-free spacer is arranged in a sidewall recess of the charge-trapping dielectric structure nearest the second source/drain region.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: March 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei Cheng Wu, Jui-Tsung Lien
  • Patent number: 11264397
    Abstract: Embodiments of source structure of a three-dimensional (3D) memory device and method for forming the source structure of the 3D memory device are disclosed. In an example, a NAND memory device includes a substrate, an alternating conductor/dielectric stack, a NAND string, a source conductor layer, and a source contact. The alternating conductor/dielectric stack includes a plurality of conductor/dielectric pairs above the substrate. The NAND string extends vertically through the alternating conductor/dielectric stack. The source conductor layer is above the alternating conductor/dielectric stack and is in contact with an end of the NAND string. The source contact includes an end in contact with the source conductor layer. The NAND string is electrically connected to the source contact by the source conductor layer. In some embodiments, the source conductor layer includes one or more conduction regions each including one or more of a metal, a metal alloy, and a metal silicide.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: March 1, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Yushi Hu, Zhenyu Lu, Qian Tao, Jun Chen, Simon Shi-Ning Yang, Steve Weiyi Yang
  • Patent number: 11264401
    Abstract: A vertical memory device includes a substrate having a peripheral circuit structure, first gate patterns having first gate pad regions stacked vertically from the substrate, vertical channel structures penetrating the first gate patterns, first gate contact structures each extending vertically to a corresponding first gate pad region, mold patterns stacked vertically from the substrate, the mold patterns each being positioned at the same height from the substrate with a corresponding gate pattern, peripheral contact structures penetrating the mold patterns to be connected to the peripheral circuit structure, a first block separation structure disposed between the first gate contact structures and the peripheral contact structures, and a first peripheral circuit connection wiring extending across the first block separation structure to connect one of the first gate contact structures to one of the peripheral contact structures.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: March 1, 2022
    Inventors: Jun Hyoung Kim, Kwang Soo Kim, Seok Cheon Baek, Geun Won Lim
  • Patent number: 11257833
    Abstract: Provided is a memory device including a substrate, a plurality of stack structures, a spacer, a dielectric layer, and a plurality of contact plugs. The stack structures are disposed on the substrate. The spacer is embedded in the stack structures, so that a width of an upper portion of the stack structures is less than a width of a lower portion thereof. The dielectric layer conformally covers the stack structures and the spacer. The contact plugs are respectively disposed on the substrate between the stack structures.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: February 22, 2022
    Assignee: Winbond Electronics Corp.
    Inventors: Jian-Ting Chen, Yao-Ting Tsai, Hsiu-Han Liao
  • Patent number: 11257912
    Abstract: A semiconductor device and method of manufacturing the same are provided. In one embodiment, method includes forming a first oxide layer over a substrate, forming a silicon-rich, oxygen-rich, oxynitride layer on the first oxide layer, forming a silicon-rich, nitrogen-rich, and oxygen-lean nitride layer over the oxynitride layer, and forming a second oxide layer on the nitride layer. Generally, the nitride layer includes a majority of charge traps distributed in the oxynitride layer and the nitride layer. Optionally, the method further includes forming a middle oxide layer between the oxynitride layer and the nitride layer. Other embodiments are also described.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: February 22, 2022
    Assignee: LONGITUDE FLASH MEMORY SOLUTIONS LTD.
    Inventors: Fredrick B. Jenne, Krishnaswamy Ramkumar
  • Patent number: 11251260
    Abstract: Disclosed is a capacitor having a high dielectric constant and low leakage current and a method for fabricating the same wherein the capacitor may include a first conductive layer a second conductive layer, a dielectric layer stack between the first conductive layer and the second conductive layer, a dielectric interface layer between the dielectric layer stack and the second conductive layer, and a high work function interface layer between the dielectric interface layer and the second conductive layer.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: February 15, 2022
    Assignee: SK hynix Inc.
    Inventors: Myung-Soo Lee, Cheol-Hwan Park, Chee-Hong An
  • Patent number: 11251080
    Abstract: Techniques herein include methods for fabricating three-dimensional (3D) logic or memory stack integrated with 3D metal routing. The methods can include stacking metal layers within existing 3D silicon stacks. A first portion can be masked while a second, uncovered portion is etched. Predetermined layers in a bottom portion (disposed closer to the substrate) of the multilayer stack can be replaced with a conductor. The second portion can be masked while the first portion is uncovered and processed. This can enable higher density 3D circuits by having multiple metal lines contained within a multilayer 3D nano-sheet. Advantageously, this facilitates easier connections for 3D logic and memory. Moreover, better speed performance can be achieved by having reduced distance for signals to travel to transistor connections.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: February 15, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Mark I. Gardner, H. Jim Fulford, Anton Devilliers
  • Patent number: 11244719
    Abstract: A semiconductor memory device includes a substrate including a logic circuit, a memory cell array disposed over the substrate, a first conductive group including a plurality of bit lines and a first upper source line that are coupled to the memory cell array and spaced apart from each other and a first upper wire that is coupled to the logic circuit, an insulating structure covering the first conductive group.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: February 8, 2022
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 11244868
    Abstract: A method for producing a component is provided, a base of which is formed by transistors on a substrate, including: forming a gate area, spacers, and a protective coating partly covering the spacers and a sidewall portion of a cavity without covering a top face of the gate area and a base portion of the cavity; forming a contact module, the gate located in beneath the module; and removing part of the coating with an isotropic light-ion implantation to form modified superficial parts in a thickness, respectively, of the contact module, of the coating, and of the base portion, and with an application of a plasma to: etch the modified superficial parts to only preserve, in the coating, a residual part of the coating, and to form a silicon oxide-based film on exposed surfaces, respectively, of the contact module, of the cavity, and of the coating.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: February 8, 2022
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Nicolas Posseme
  • Patent number: 11239333
    Abstract: A semiconductor device and a manufacturing method thereof includes a source contact structure, a gate stack structure including a side region adjacent to the source contact structure, and a center region extending from the side region. The semiconductor device further includes a source gate pattern disposed under the side region of the first gate stack structure. The source gate pattern has an inclined surface facing the source contact structure. The semiconductor device also includes a channel pattern penetrating the center region of the gate stack structure, the channel pattern extending toward and contacting the source contact structure.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: February 1, 2022
    Assignee: SK hynix Inc.
    Inventor: Kang Sik Choi
  • Patent number: 11238934
    Abstract: A nonvolatile memory device includes a peripheral circuit region and a memory cell region. The peripheral circuit region includes a block selecting circuit, a block unselecting circuit, and a first metal pad. The memory cell region is vertically connected to the peripheral circuit region, and includes a first memory block and a second metal pad directly connected to the first metal pad. The block selecting circuit is connected with ground selection lines, word lines, and string selection lines, and provides corresponding driving voltages to the ground selection lines, the word lines, and the string selection lines in response to a block selection signal corresponding to the first memory block, respectively. The block unselecting circuit is connected only with specific string selection lines, and provides an off-voltage only to the specific string selection lines in response to a block un-selection signal.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: February 1, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Wan Nam, Euihyun Cheon, Byungjun Min
  • Patent number: 11233064
    Abstract: The semiconductor device includes interlayer insulating layers, a gate pattern and a vertical memory structure. The interlayer insulating layers are stacked on the substrate to be spaced apart from each other. The gate pattern includes an overlapping portion disposed vertically between the interlayer insulating layers, and an extension portion extending from the overlapping portion in a horizontal direction parallel to an upper surface of the substrate. The vertical memory structure includes a channel semiconductor layer and a dielectric structure, the channel semiconductor layer extends in a direction perpendicular to the substrate upper surface to have side surfaces that face side surfaces of the interlayer insulating layers and a side surface of the extension portion.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: January 25, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki Hyun Kim, Seung Wan Hong
  • Patent number: 11233067
    Abstract: A vertical memory device includes a substrate including a cell array region and a connection region adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, a channel structure on the cell array region and extending in a direction perpendicular to an upper surface of the substrate while penetrating through the plurality of gate electrode layers, a dummy channel structure on the connection region and extending in the direction perpendicular to the upper surface of the substrate while penetrating through at least a portion of the plurality of gate electrode layers, and a support insulating layer between a portion of the plurality of gate electrode layers and the dummy channel structure. The plurality of gate electrode form a stepped structure on the connection region.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: January 25, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Moon Kyu Song, Ki Yoon Kang, Jae Hoon Jang
  • Patent number: 11233043
    Abstract: A three-dimensional semiconductor memory device, including a peripheral circuit structure including a first metal pad and a cell array structure disposed on the peripheral circuit structure and including a second metal pad. The peripheral circuit structure may include a first substrate including a first peripheral circuit region and a second peripheral circuit region, first contact plugs, second contact plugs, and a first passive device on and electrically connected to the second contact plugs. The cell array structure may include a second substrate disposed on the peripheral circuit structure, the second substrate including a cell array region and a contact region. The cell array structure may further include gate electrodes and cell contact plugs. The first passive device is vertically between the gate electrodes and the second contact plugs and includes a first contact line. The first metal pad and the second metal pad may be connected by bonding manner.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: January 25, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chanho Kim, Joo-Yong Park, Daeseok Byeon
  • Patent number: 11233042
    Abstract: A three-dimensional semiconductor memory device, including a first chip and a second chip stacked on the first chip may be provided. The first chip may include a first substrate including a first peripheral circuit region and a second peripheral circuit region, first contact plugs, and second contact plugs, and a passive device on and electrically connected to the second contact plugs. The second chip may include a second substrate including a cell array region and a contact region, which vertically overlap the second peripheral circuit region and the first peripheral circuit region of the first chip, respectively. The second chip may further include gate electrodes, and cell contact plugs disposed on the contact region of the second substrate and on end portions of the gate electrodes. The first passive device may be vertically between the gate electrodes and the second contact plugs and may include a first contact line.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: January 25, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chanho Kim, Joo-Yong Park, Daeseok Byeon
  • Patent number: 11222827
    Abstract: A semiconductor device is provided. The semiconductor device includes a stack structure disposed on a lower structure; an insulating structure disposed on the stack structure; and a vertical structure extending in a direction perpendicular to an upper surface of the lower structure and having side surfaces opposing the stack structure and the insulating structure. The stack structure includes interlayer insulating layers and gate layers, alternately stacked, and the insulating structure includes a lower insulating layer, an intermediate insulating layer on the lower insulating layer, and an upper insulating layer on the intermediate insulating layer.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: January 11, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hui Chang Moon
  • Patent number: 11217600
    Abstract: In the highly efficient fabrication processes for HNOR arrays provided herein, the channel regions of the storage transistors in the HNOR arrays are protected by a protective layer after deposition until the subsequent deposition of a charge-trapping material before forming local word lines. Both the silicon for the channel regions and the protective material may be deposited in amorphous form and are subsequently crystallized in an anneal step. The protective material may be silicon boron, silicon carbon or silicon germanium. The protective material induces greater grain boundaries in the crystallized silicon in the channel regions, thereby providing greater charge carrier mobility, greater conductivity and greater current densities.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: January 4, 2022
    Assignee: SUNRISE MEMORY CORPORATION
    Inventors: Vinod Purayath, Wu-Yi Henry Chien
  • Patent number: 11211393
    Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate having one or more first recesses in a first region and one or more second recesses in a second region. A liner layer is disposed over the sidewalls and bottom of the one or more first recesses in the first region and an epitaxially-grown material is formed in the one or more second recesses in the second region. One or more NAND strings are formed over the epitaxially-grown material disposed in the one or more second recesses, and one or more vertical structures are formed over the one or more first recesses in the first region.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: December 28, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Yue Qiang Pu, Jin Wen Dong, Jun Chen, Zhenyu Lu, Qian Tao, Yushi Hu, Zhao Hui Tang, Li Hong Xiao, Yu Ting Zhou, Sizhe Li, Zhaosong Li
  • Patent number: 11211372
    Abstract: A semiconductor device includes a first substrate structure having a first substrate, circuit elements disposed on the first substrate, and first bonding pads disposed on the circuit elements. A second substrate structure is connected to the first substrate structure. The second substrate structure includes a second substrate having first and second surfaces, first and second conductive layers spaced apart from each other, a pad insulating layer having an opening exposing a portion of the second conductive layer and gate electrodes stacked to be spaced apart from each other in a first direction and electrically connected to the circuit elements. First contact plugs extend on the second surface in the first direction and connect to the gate electrodes. A second contact plug extends on the second surface in the first direction and electrically connects to the second conductive layer. Second bonding pads electrically connect to the first and second contact plugs.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: December 28, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hyun Mog Park
  • Patent number: 11211394
    Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a memory stack, a plurality of channel structures, and a source structure. The memory stack is over a substrate and includes interleaved a plurality of conductor layers and a plurality of insulating layers. The source structure includes a plurality of source contacts, and two adjacent ones of the plurality of source contacts are conductively connected to one another by a connection layer. A pair of first portions of the connection layer are over the two adjacent ones of the plurality of source contacts and a second portion of the connection layer being between the two adjacent ones of the plurality of source contacts. Top surfaces of the pair of first portions of the connection are coplanar with a top surface of the second portion.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: December 28, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Wenxiang Xu, Wei Xu, Pan Huang, Ping Yan, Zongliang Huo, Wenbin Zhou, Ji Xia
  • Patent number: 11205656
    Abstract: The present disclosure describes method and structure of a three-dimensional memory device. The memory device includes a substrate and a plurality of wordlines extending along a first direction over the substrate. The first direction is along the x direction. The plurality of wordlines form a staircase structure in a first region. A plurality of channels are formed in a second region and through the plurality of wordlines. The second region abuts the first region at a region boundary. The memory device also includes an insulating slit formed in the first and second regions and along the first direction. A first width of the insulating slit in the first region measured in a second direction is greater than a second width of the insulating slit in the second region measured in the second direction.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: December 21, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Qiang Xu, Zhiliang Xia, Ping Yan, Guangji Li, Zongliang Huo
  • Patent number: 11205662
    Abstract: Embodiments of 3D memory devices with a dielectric etch stop layer and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. The method includes forming a dielectric etch stop layer. The dielectric etch stop is disposed on a substrate. The method also includes forming a dielectric stack on the dielectric etch stop layer. The dielectric stack includes a plurality of interleaved dielectric layers and sacrificial layers. The method further includes forming an opening extending vertically through the dielectric stack and extending the opening through the dielectric etch stop layer. In addition, the method includes forming a selective epitaxial growth (SEG) plug at a lower portion of the opening. The SEG plug is disposed on the substrate. Moreover, the method includes forming a channel structure above and in contact with the SEG plug in the opening.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: December 21, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Fandong Liu, Wenyu Hua, Jia He, Linchen Wu, Yue Qiang Pu, Zhiliang Xia
  • Patent number: 11201169
    Abstract: A memory device includes: a first bit line located on a dielectric layer and a second bit line located over the dielectric layer; a first word line and a second word line located between the first bit line and the second bit line; a source line located between the first word line and the second word line; a channel pillar penetrating through the first word line and the source line and the second word line, and being connected to the first bit line, the source line and the second bit line; and a charge storage structure including an upper portion surrounding an upper sidewall of the channel pillar and located between the second word line and the channel pillar; and a lower portion surrounding a lower sidewall of the channel pillar and located between the first word line and the channel pillar.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: December 14, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chih-Hsiung Lee, Shaw-Hung Ku
  • Patent number: 11201086
    Abstract: Semiconductor devices and methods of forming the semiconductor devices are provided. The methods may include forming a fin, forming a first device isolating layer on a side of the fin, forming a second device isolating layer extending through the first device isolating layer, forming first and second gates traversing the fin and forming a third device isolating layer between the first and second gates. The first device isolating layer may include a first material and a lowermost surface at a first depth. The second device isolating layer may include a second material and a lowermost surface at a second depth greater than the first depth. The third device isolating layer may extend into the fin, may include a lowermost surface at a third depth less than the first depth and a third material different from the first and the second materials.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: December 14, 2021
    Inventors: Sung-Min Kim, Sunhom Steve Paak, Heon-Jong Shin, Dong-Ho Cha
  • Patent number: 11201166
    Abstract: A semiconductor device includes a plurality of first gate electrodes sequentially stacked on a substrate, a second gate electrode on the plurality of first gate electrodes, a first channel structure extending through the plurality of first gate electrodes and a portion of the second gate electrode, a buried insulation pattern on a sidewall of the first channel structure, of which an upper surface is at a higher level than a top end of the first channel structure, a second channel structure extending through a remainder of the second gate electrode, the second channel structure connected to the first channel structure, and a buried conductive pattern on a sidewall of the second channel structure.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: December 14, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun Yeoung Choi, Hyung Joon Kim, Su Hyeong Lee, Yong Seok Cho
  • Patent number: 11195854
    Abstract: Some embodiments include an integrated structure having a first opening extending through a stack of alternating insulative levels and conductive levels. A nitride structure is within the first opening and narrows the first opening to form a second opening. Detectable oxide is between the nitride structure and one or more of the conductive levels. Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. A first opening extends through the vertically-stacked levels to the conductive material and has opposing sidewalls along a cross-section. Nitride liners are along the sidewalls of the first opening. Detectable oxide is between at least one of the nitride liners and one or more of the vertically-stacked conductive levels. Some embodiments include methods for forming integrated structures.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: December 7, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Jie Li, James Mathew, Kunal Shrotri, Luan C. Tran, Gordon A. Haller, Yangda Zhang, Hongpeng Yu, Minsoo Lee