Multiple Insulator Layers (e.g., Mnos Structure) Patents (Class 257/324)
  • Patent number: 10438963
    Abstract: Provided herein is a method of manufacturing a semiconductor device. The method for manufacturing the semiconductor device includes: alternately stacked first material layers and second material layers on a lower structure; forming first holes passing through the first material layers and the second material layers, each of the first holes defining a channel region; removing the second material layers through the first holes such that interlayer spaces between the first material layers are formed; and forming, through the first holes, conductive patterns which fill respective interlayer spaces.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: October 8, 2019
    Assignee: SK hynix Inc.
    Inventor: Jaeseong Kim
  • Patent number: 10438801
    Abstract: A semiconductor memory device including a first semiconductor layer, first gate electrodes, a first gate insulating layer and a laminated film. The first semiconductor layer extends in a first direction intersecting a substrate. The first gate electrodes are arranged in the first direction and face the first semiconductor layer in a second direction intersecting the first direction. End portions of the first gate electrodes in the second direction have different positions from each other and form a stepped contact portion. The laminated film covers at least parts of upper surfaces and at least parts of side surfaces intersecting the second direction, of the first gate electrodes. The laminated film includes a first insulating layer, second semiconductor layers, a second gate insulating layer, and a second gate electrode. Positions in the first direction and positions in the second direction of the second semiconductor layers are different from each other.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: October 8, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kiwamu Sakuma, Masumi Saitoh
  • Patent number: 10438965
    Abstract: Disclosed are a semiconductor device and a manufacturing method thereof. According to the semiconductor device and the manufacturing method thereof according to exemplary embodiments of the present invention, after the dopant source layer is uniformly deposited on a channel layer of the device with the 3-dimensional vertical structure by the plasma-enhanced atomic layer deposition (PEALD) method, the deposited dopant source layer is heat-treated so that the dopants are diffused into the channel layer to function as charge carriers, thereby preventing the charges in the channel layer from being reduced. According to the exemplary embodiments of the present invention, the diffusion speed and concentration of the dopant may be controlled by forming the barrier layer between the channel layer and the dopant source layer.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: October 8, 2019
    Assignee: ASM IP Holding B.V.
    Inventors: Young Jae Kim, Seung Woo Choi, Yong Min Yoo
  • Patent number: 10431595
    Abstract: A memory device includes a substrate having a first source film thereon and an upper stacked structure on the first source film. An electrically conductive channel structure is provided, which extends through the upper stacked structure and the first source film. The channel structure includes a channel pattern, which extends vertically through the upper stacked structure and the first source film, and an information storage pattern on a sidewall of the channel pattern. A second source film is provided, which extends between the first source film and a surface of the substrate. The second source film, which contacts the channel pattern, includes an upward extending protrusion, which extends underneath the information storage pattern. A channel protective film is provided, which extends between at least a portion of the protrusion and at least a portion of the information storage pattern.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: October 1, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han Vit Yang, Yong Hoon Son
  • Patent number: 10431592
    Abstract: A 3D memory device comprising: a substrate; at least one first group of four first “U”-shaped memory cells strings each including a first buried string portion, a first source line selector side string portion and a first bit line selector side string portion, wherein the first buried string portion is formed in the substrate and connects the first source line selector side string portion and the first bit line selector side string portion, each of the first “U”-shaped memory cells strings including memory cells stacks along the first source line selector side string portion and along the first bit line selector side string portion; and at least one second group of four second “U”-shaped memory cells strings each including a second buried string portion, a second source line selector side string portion and a second bit line selector side string portion, wherein the second buried string portion is formed in the substrate and connects the second source line selector side string portion and the second bit line
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: October 1, 2019
    Assignee: Trinandable S.r.l.
    Inventor: Sabrina Barbato
  • Patent number: 10431589
    Abstract: A memory cell includes a memory gate structure, a first select gate structure, and a second select gate structure. In the memory gate structure, a lower memory gate insulating film, a charge storage layer, an upper memory gate insulating film, and a metal memory gate electrode are stacked in this order. The first select gate structure includes a metal first select gate electrode along a first sidewall spacer provided on a sidewall of the memory gate structure. The second select gate structure includes a metal second select gate electrode along a second sidewall spacer provided on another sidewall of the memory gate structure. Thus, the metal memory gate electrode, the metal first select gate electrode, and the metal second select gate electrode can be formed of a same metallic material as a metal logic gate electrode, permitting the memory cell to be formed together with the metal logic gate electrode.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: October 1, 2019
    Assignee: FLOADIA CORPORATION
    Inventors: Shoji Yoshida, Fukuo Owada, Daisuke Okada, Yasuhiko Kawashima, Shinji Yoshida, Kazumasa Yanagisawa, Yasuhiro Taniguchi
  • Patent number: 10431671
    Abstract: A method is provided for fabricating fin field-effect transistors. The method includes providing a substrate. The method also includes forming a plurality of fins on a surface of the substrate. Further the method includes forming a transitional layer having atoms identical to atoms of the fins on side and top surfaces of the plurality of fins by a deposition process. Further, the method also includes performing an oxidation process to convert the transitional layer and a surface portion of the fins into a dielectric material to form a gate dielectric layer on the plurality of fins.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: October 1, 2019
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Xiaopeng Yu, Youfeng He, Zhengling Chen
  • Patent number: 10424348
    Abstract: According to one embodiment, a method of controlling a memory device includes supplying a second potential having a first value to a second electrode and simultaneously, or thereafter, supplying a third potential to a third electrode, and thereafter stopping supply of the third potential such that the potential of the third electrode decays while reducing the potential of the second electrode, and thereafter supplying a first potential to the first electrode.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: September 24, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Ryota Suzuki, Tatsuo Izumi
  • Patent number: 10424593
    Abstract: A three-dimensional non-volatile memory and a method of manufacturing the same are provided. The three-dimensional non-volatile memory includes a substrate, a charge storage structure, a stacked structure and a channel layer. The charge storage structure is disposed on the substrate. The stacked structure is disposed at a side of the charge storage structure and includes insulating layers, gates, a buffer layer and a barrier layer. The insulating layers and the gates are alternately stacked. The buffer layer is disposed between each of the gates and the charge storage structure and on the surfaces of the insulating layers. The barrier layer is disposed between each of the gates and the buffer layer. An end of the gate is convex with respect to an end of the barrier layer in a direction away from the channel layer.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: September 24, 2019
    Assignee: MACRONIX International Co., Ltd.
    Inventors: I-Ting Lin, Yuan-Chieh Chiu, Hong-Ji Lee
  • Patent number: 10418375
    Abstract: A 3D memory device comprising: a substrate; at least three first “U”-shaped strings of memory cells each including a first buried string portion, a first source line selector side string portion and a first bit line selector side string portion, wherein the first buried string portion is formed in the substrate and connects the first source line selector side string portion and the first bit line selector side string portion, each of the first “U”-shaped string of memory cells including stacks of memory cells along the first source line selector string side portion and along the first bit line selector side string portion; and at least three second “U”-shaped strings of memory cells each including a second buried string portion, a second source line selector side string portion and a second bit line selector side string portion, wherein the second buried string portion is formed in the substrate and connects the second source line selector side string portion and the second bit line selector side string porti
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: September 17, 2019
    Assignee: TRINANDABLE S.R.L.
    Inventor: Sabrina Barbato
  • Patent number: 10418376
    Abstract: A semiconductor memory device according to one embodiment, includes a first electrode film, a plurality of semiconductor members, and a charge storage member. The first electrode film includes three or more first portions and a second portion connecting the first portions to each other. The first portions extend in a first direction and are arranged along a second direction that intersects with the first direction. The plurality of semiconductor members are arranged along the first direction between the first portions and extending in a third direction. The third direction intersects with a plane containing the first direction and the second direction. The charge storage member is disposed between each of the semiconductor members and each of the first portions. The second portion is disposed between the semiconductor members.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: September 17, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Koichi Sakata, Yuta Watanabe, Keisuke Kikutani, Satoshi Nagashima, Fumitaka Arai, Toshiyuki Iwamoto
  • Patent number: 10418373
    Abstract: A method of controlling the thickness of gate oxides in an integrated CMOS process which includes performing a two-step gate oxidation process to concurrently oxidize and therefore consume at least a first portion of the cap layer of the NV gate stack to form a blocking oxide and form a gate oxide of at least one metal-oxide-semiconductor (MOS) transistor in the second region, wherein the gate oxide of the at least one MOS transistor is formed during both a first oxidation step and a second oxidation step of the gate oxidation process.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: September 17, 2019
    Assignee: LONGITUDE FLASH MEMORY SOLUTIONS LTD.
    Inventor: Krishnaswamy Ramkumar
  • Patent number: 10411020
    Abstract: A plurality of gate stacks is formed over a substrate. The gate stacks are surrounded by a dielectric structure. A plurality of contact-line-blocking patterns is formed over the dielectric structure. The contact-line-blocking patterns are formed using three or more lithography masks. A plurality of trenches is formed in the dielectric structure. The contact-line-blocking patterns serve as protective masks for the dielectric structure to prevent trenches from being formed in portions of the dielectric structure underneath the contact-line-blocking patterns. The trenches are filled with a conductive material to form a plurality of contact lines of the SRAM device.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: September 10, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Han Huang, Chih-Hung Hsieh
  • Patent number: 10411034
    Abstract: An integrated circuit memory device includes a vertical stack structure containing an interlayer insulating layer and a gate electrode, on a substrate. A blocking dielectric region is provided on a sidewall of an opening in the stack structure. A lateral impurity region is provided, which extends between the blocking dielectric region and the interlayer insulating layer and between the blocking dielectric region and the gate electrode. A lower impurity region is also provided, which extends between the blocking dielectric region and the substrate.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: September 10, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo Jin Jang, Young Jin Noh, Jun Kyu Yang, Bio Kim, Kyong Won An
  • Patent number: 10411031
    Abstract: A semiconductor device includes a substrate, a stack, and channel structures penetrating the stack. The stack includes gate electrodes and insulating layers alternately and repeatedly stacked on the substrate, and extending in a first direction. The channel structures in a first row are spaced apart from each other in the first direction. The stack includes a first sidewall that includes first recessed portions and first protruding portions. Each of first recessed portions is defined by an adjacent pair of the first recessed portions. Each of the first recessed portions has a shape recessed toward a first region of the stack between an adjacent pair of the channel structures of the first row. Each of the first recessed portions has a width that decreases in a direction toward the first region when measured along the first direction.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: September 10, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byoungkeun Son, Yoocheol Shin, Changhyun Lee, Hyunjung Kim, Chung-Il Hyun
  • Patent number: 10403719
    Abstract: A three-dimensional semiconductor memory device includes common source regions, an electrode structure between the common source regions, first channel structures penetrating the electrode structure, and second channel structures between the first channel structures and penetrating the electrode structures. The electrode structure includes electrodes vertically stacked on a substrate. The first channel structures include a first semiconductor pattern and a first vertical insulation layer. The second channel structures include a second vertical insulation layer surrounding a second semiconductor pattern. The second vertical insulation layer has a bottom surface lower than a bottom surface of the first vertical insulation layer.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: September 3, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Moorym Choi, Bongyong Lee, Junhee Lim
  • Patent number: 10403633
    Abstract: The semiconductor device include a lower insulating layer; a gate stack disposed over the lower insulating layer; a plurality of supports extending from the lower insulating layer toward the gate stack; a source layer disposed between the lower insulating layer and the gate stack; and a channel pattern including a connection part disposed between the source layer and the gate stack.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: September 3, 2019
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 10403642
    Abstract: A semiconductor device includes a semiconductor layer, a first conductive layer, a tunneling insulating film, and a charge trapping film. The tunneling insulating film is provided between the semiconductor layer and the first conductive layer. The charge trapping film is provided between the first conductive layer and the tunneling insulating film. The charge trapping film includes a first separation layer, a first trapping layer, and a second trapping layer. The first trapping layer is positioned between the tunneling insulating film and the first separation layer. The second trapping layer is positioned between the first conductive layer and the first separation layer. A trapping efficiency of charge in the first trapping layer is higher than a trapping efficiency of charge in the second trapping layer.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: September 3, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kazuhiro Matsuo, Akiko Sekihara, Akira Takashima, Tomonori Aoyama, Tatsunori Isogai, Masaki Noguchi
  • Patent number: 10403635
    Abstract: According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: September 3, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Yoshiaki Fukuzumi, Hideaki Aochi
  • Patent number: 10403641
    Abstract: A semiconductor device may include a plurality of conductive patterns and an insulation pattern. The plurality of conductive patterns may be formed on a substrate. The plurality of conductive patterns may be spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate. Each of the plurality of conductive patterns may have an extension portion and a step portion. The step portion may be disposed at an edge of the corresponding conductive pattern. The insulation pattern may be formed between the plurality of conductive patterns in the vertical direction. A lower surface and an upper surface of the step portion of each of the plurality of conductive patterns may be bent upwardly.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: September 3, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Gil Kim, Seul-Ye Kim, Hong-suk Kim, Phil-Ouk Nam, Jae-Young Ahn, Ji-Hoon Choi
  • Patent number: 10395737
    Abstract: A memory structure, includes (a) active columns of polysilicon formed above a semiconductor substrate, each active column extending vertically from the substrate and including a first heavily doped region, a second heavily doped region, and one or more lightly doped regions each adjacent both the first and second heavily doped region, wherein the active columns are arranged in a two-dimensional array extending in second and third directions parallel to the planar surface of the semiconductor substrate; (b) charge-trapping material provided over one or more surfaces of each active column; and (c) conductors each extending lengthwise along the third direction.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: August 27, 2019
    Assignee: SUNRISE MEMORY CORPORATION
    Inventor: Eli Harari
  • Patent number: 10396087
    Abstract: A semiconductor device includes a stacked body 100, first insulating layers 45, a second insulating layer 46 and columnar portions CL. The stacked body 100 includes electrode layers 41 stacked with an insulating body interposed along a Z-direction. The first insulating layers 45 extend in an X-direction and are provided in the stacked body 100 from an upper end thereof to a lower end thereof. The second insulating layer extends in the X-direction and is provided in the stacked body 100 from the upper end to partway through the stacked body 100 between one of the first insulating layers 45 and another one of the first insulating layers 45. The columnar portion CL has a bowed configuration. The second insulating layer 46 is provided in a region B including a location of a maximum inner diameter Dm of the columnar portion CL.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: August 27, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Wataru Sakamoto
  • Patent number: 10396090
    Abstract: A semiconductor device includes a substrate, a cell stack structure, a channel layer, a peripheral contact plug, and first dummy conductive rings. The substrate may include a first region and a second region. The cell stack structure may include interlayer insulating layers and conductive patterns, which are alternately stacked over the first region of the substrate. The channel layer may penetrate the cell stack structure. The peripheral contact plug may extend in parallel to the channel layer over the second region of the substrate. The first dummy conductive rings may be disposed at the same levels as the conductive patterns, are spaced apart from the peripheral contact plug, and surround the peripheral contact plug.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: August 27, 2019
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 10396035
    Abstract: A three-dimensional semiconductor device includes: a substrate having a cell array region and a contact region; a stacked structure including a plurality of electrodes and a plurality of electrode isolation insulating layers, which are alternately stacked on the substrate in a vertical direction, and having a stepwise structure on the contact region; vertical structures penetrating the stacked structure in the cell array region, each of the vertical structures constituting a cell string; and word line contact plugs, each penetrating an uppermost electrode among the plurality of electrodes in a region of each of tread portions of the stacked structure having the stepwise structure, being connected to another electrode under the penetrated uppermost electrode, and being electrically insulated from the penetrated uppermost electrode.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: August 27, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hyun-mog Park
  • Patent number: 10396092
    Abstract: Disclosed are vertical memory devices and methods of manufacturing the same. The vertical memory device may include includes a substrate, a gate stack structure and channel structure on the substrate, and a charge trap structure between the gate stack structure and the channel structure. The gate stack structure includes conductive structures and insulation interlayer structures that are alternately stacked on each other in a vertical direction on the substrate such that cell regions and inter-cell regions are alternately arranged in the vertical direction. The channel structure penetrates through the gate stack structure in the vertical direction. The charge trap structure and the conductive structures define memory cells at the cell regions. The charge structure is configured to selectively store charges. The charge trap structure includes an anti-coupling structure in the inter-cell region for reducing a coupling between neighboring memory cells adjacent to each other in the vertical direction.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: August 27, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kohji Kanamori, Dong-Seog Eun
  • Patent number: 10396095
    Abstract: A semiconductor device includes: hole source patterns; electron source patterns located between adjacent hole source patterns; a stack structure over the hole source patterns and the electron source patterns; and channel layers penetrating the stack structure, wherein each channel layer is in contact with a corresponding hole source pattern and an electron source pattern adjacent to the corresponding hole source pattern.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: August 27, 2019
    Assignee: SK hynix Inc.
    Inventors: Jong Sung Jeon, Eun Mee Kwon, Da Som Lee, Bong Hoon Lee
  • Patent number: 10388661
    Abstract: Provided herein may be a semiconductor device and a method of manufacturing the same. The method of manufacturing the semiconductor device may include forming a tunnel insulating layer in a channel hole passing through a preliminary stack structure in which interlayer insulating layers and material layers are alternately stacked. The method may include forming recess areas by removing the material layers exposed through a slit passing through the preliminary stack structure. The method may include forming a data storage layer in the recess areas through the slit. The thickness of the data storage layer may be formed regardless of a size of the channel hole.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: August 20, 2019
    Assignee: SK hynix Inc.
    Inventors: Min Woo Park, Kyo Yeon Cho
  • Patent number: 10388666
    Abstract: A first-tier structure including a first alternating stack of first insulating layers and first spacer material layers is formed over a substrate. First-tier memory openings and at least one type of first-tier contact openings can be formed simultaneously employing a same anisotropic etch process. The first-tier contact openings formed over stepped surfaces of the first alternating stack may extend through the first alternating stack, or may stop on the stepped surfaces. Sacrificial first-tier opening fill portions are formed in the first-tier openings, and a second-tier structure can be formed over the first-tier structure. Memory openings including volumes of the first-tier memory openings are formed through the multi-tier structure, and memory stack structures are formed in the memory openings. Various contact openings are formed through the multi-tier structure, and various contact via structures are formed in the contact openings.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: August 20, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: James Kai, Zhixin Cui, Murshed Chowdhury, Johann Alsmeier, Tong Zhang
  • Patent number: 10388756
    Abstract: A method for fabricating a semiconductor device is disclosed. A fin is formed on a substrate. The fin protrudes from a trench isolation layer on a substrate. The fin comprises a source region, a drain region and a channel region therebetween. A dummy gate strides across the fin and surrounding the channel region. An upper portion of the fin is removed so as to form a hollow channel underneath the dummy gate. A replacement channel layer is in-situ epitaxially grown in the hollow channel.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: August 20, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yen-Hsing Chen, Chun-Yu Chen, Chung-Ting Huang, Zih-Hsuan Huang, Yu-Chien Sung
  • Patent number: 10388521
    Abstract: A patterning method that includes providing an amorphous semiconductor surface to be patterned, and terminating the amorphous semiconductor surface by forming silicon-hydrogen (Si—H) on the surface to be patterned. A photoresist is formed on the surface to be patterned. The photoresist is then lithographically patterned using an extreme ultra violet (EUV) method. A photoresist is then developed on the surface to be patterned using negative tone development (NTD).
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: August 20, 2019
    Assignee: International Business Machines Corporation
    Inventors: Nelson M. Felix, Martin Glodde, Dario L. Goldfarb
  • Patent number: 10381378
    Abstract: A memory structure, includes active columns of polysilicon formed above a semiconductor substrate, each active column includes one or more vertical NOR strings, with each NOR string having thin-film storage transistors sharing a local source line and a local bit line, the local bit line is connected by one segment of a segmented global bit line to a sense amplifier provided in the semiconductor substrate.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: August 13, 2019
    Assignee: SUNRISE MEMORY CORPORATION
    Inventor: Eli Harari
  • Patent number: 10381376
    Abstract: A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips located over a substrate and laterally spaced apart among one another by vertically undulating trenches. The vertically undulating trenches have a greater lateral extent at levels of the electrically conductive strips than at levels of the insulating strips. An interlaced two-dimensional array of memory stack assemblies and dielectric pillar structures are located in the vertically undulating trenches. Each memory stack assembly includes a vertical semiconductor channel and a pair of memory films including a respective pair of convex outer sidewalls that contact, or are spaced by a uniform distance from, concave sidewalls of the electrically conductive strips.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: August 13, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Masatoshi Nishikawa, Xiaolong Hu, Yanli Zhang
  • Patent number: 10381365
    Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, and having vertically-stacked memory cells within the conductive levels. An opening extends through the stack. Channel material is within the opening and along the memory cells. At least some of the channel material contains germanium.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: August 13, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Haitao Liu, Chandra Mouli, Sergei Koveshnikov, Dimitrios Pavlopoulos, Guangyu Huang
  • Patent number: 10381372
    Abstract: Void formation in tungsten lines in a three-dimensional memory device can be prevented by providing polycrystalline aluminum oxide liners in portions of lateral recesses that are laterally spaced from backside trenches by a distance grater than a predefined lateral offset distance. Tungsten nucleates on the polycrystalline aluminum oxide liners prior to nucleating on a metallic liner layer. Thus, tungsten layers can be deposited from the center portion of each backside recess, and the growth of tungsten can proceed toward the backside trenches. By forming the tungsten layers without voids, structural integrity of the three-dimensional memory device can be enhanced.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: August 13, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Fumitaka Amano, Takashi Arai, Genta Mizuno, Shigehisa Inoue, Naoki Takeguchi, Takashi Hamaya
  • Patent number: 10373972
    Abstract: A vertical memory device and a method of manufacturing the same, the device including a cell array including cell regions spaced apart from each other in a second direction, each cell region including a regularly arranged plurality of vertical channels; bit-lines extending in the second direction, the bit-lines being spaced apart from each other in a first direction crossing the second direction; and bit-line contacts respectively electrically connecting the vertical channels and the bit-lines, wherein each cell region includes a sub isolation region configured to electrically isolate the cell region in the second direction, the sub isolation region extending in the first direction, the vertical channels are classified into a plurality of types according to a distance from the sub isolation region in the second direction in each cell region, and the bit-line contacts are configured to electrically connect each bit-line to at least two vertical channels having different types.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: August 6, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: An-Soo Park, Sung-Hoon Kim, Pan-Suk Kwak
  • Patent number: 10374067
    Abstract: An embodiment of a semiconductor memory device including a multi-layer charge storing layer and methods of forming the same are described. Generally, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide layer overlying the channel; and a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which a stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which a stoichiometric composition of the second oxynitride layer results in it being trap dense. In one embodiment, the device comprises a non-planar transistor including a gate having multiple surfaces abutting the channel, and the gate comprises the tunnel oxide layer and the multi-layer charge storing layer.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: August 6, 2019
    Assignee: LONGITUDE FLASH MEMORY SOLUTIONS LTD.
    Inventors: Sagy Levy, Krishnaswamy Ramkumar, Fredrick Jenne, Sam Geha
  • Patent number: 10374101
    Abstract: In an example, a memory array may include a memory cell around at least a portion of a semiconductor. The memory cell may include a gate, a first dielectric stack to store a charge between a first portion of the gate and the semiconductor, and a second dielectric stack to store a charge between a second portion of the gate and the semiconductor, the second dielectric stack separate from the first dielectric stack.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: August 6, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Arup Bhattacharyya
  • Patent number: 10373971
    Abstract: A manufacturing method of a semiconductor device may be provided. The method may include forming stacks including interlayer insulating layers and separated by a slit, the interlayer insulating layers surrounding a channel layer and stacked to be spaced apart from one another with an interlayer space interposed therebetween. The method may include forming a conductive pattern filling the interlayer space. The method may include forming an isolation layer on a surface of the conductive pattern by oxidizing a portion of the conductive pattern by performing an oxidizing process.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: August 6, 2019
    Assignee: SK hynix Inc.
    Inventors: Hae Chan Park, Jang Won Kim, Gong Hyun Sa
  • Patent number: 10373968
    Abstract: A 3-D semiconductor device comprising a plurality of memory cells and a plurality of selection transistors, each of said plurality of memory cells comprises: a channel layer, distributed along a direction perpendicular to the substrate surface; a plurality of inter-layer insulating layers and a plurality of gate stack structures, alternately laminating along the sidewall of the channel layer; a plurality of floating gates, located between the plurality of inter-layer insulating layers and the sidewall of the channel layer; a plurality of drains, located at the top of the channel layer; and a plurality of sources, located in the said substrate between two adjacent memory cells of the said plurality of memory cells.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: August 6, 2019
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventor: Zongliang Huo
  • Patent number: 10367002
    Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: July 30, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Il Chang, Jun-Hee Lim, Yong-Seok Kim, Tae-Young Kim, Jae-Sung Sim, Su-Jin Ahn, Ji-Yeong Hwang
  • Patent number: 10367003
    Abstract: A vertical non-volatile memory device includes a substrate including a cell region; a lower insulating layer on the substrate; a lower wiring pattern in the cell region having a predetermined pattern and connected to the substrate through the lower insulating layer; and a plurality of vertical channel layers extending in a vertical direction with respect to a top surface of the substrate in the cell region, spaced apart from one another in a horizontal direction with respect to the top surface of the substrate, and electrically connected to the lower wiring pattern. The memory device also includes a plurality of gate electrodes stacked alternately with interlayer insulating layers in the cell region in the vertical direction along a side wall of a vertical channel layer and formed to extend in a first direction along the horizontal direction.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: July 30, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Shin-hwan Kang, Heon-kyu Lee, Kohji Kanamori, Jae-duk Lee, Jae-hoon Jang, Kwang-soo Kim
  • Patent number: 10367000
    Abstract: According to one embodiment, a semiconductor device includes a foundation layer, a stacked body provided above the foundation layer, a semiconductor body, and a charge storage portion. The stacked body includes a plurality of electrode layers stacked with an air gap interposed, a plurality of select gate layers stacked in a stacking direction of the electrode layers, and an insulating body provided between the select gate layers adjacent to each other in the stacking direction. The semiconductor body extends in the stacking direction in the stacked body. The charge storage portion is provided between the semiconductor body and one of the electrode layers.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: July 30, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Takashi Fukushima, Katsuyuki Sekine, Satoshi Nagashima, Hisataka Meguro
  • Patent number: 10355007
    Abstract: A memory stack structure includes a cavity including a back gate electrode, a back gate dielectric, a semiconductor channel, and at least one charge storage element. In one embodiment, a line trench can be filled with a memory film layer, and a plurality of semiconductor channels can straddle the line trench. The back gate electrode can extend along the lengthwise direction of the line trench. In another embodiment, an isolated memory opening overlying a patterned conductive layer can be filled with a memory film, and the back gate electrode can be formed within a semiconductor channel and on the patterned conductive layer. A dielectric cap portion electrically isolates the back gate electrode from a drain region. The back gate electrode can be employed to bias the semiconductor channel, and to enable sensing of multinary bits corresponding to different amounts of electrical charges stored in a memory cell.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: July 16, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Xiying Costa, Dana Lee, Yanli Zhang, Johann Alsmeier, Yingda Dong, Akira Matsudaira
  • Patent number: 10355009
    Abstract: A first-tier structure including a first alternating stack of first insulating layers and first spacer material layers is formed over a substrate. First-tier memory openings and at least one type of first-tier contact openings can be formed simultaneously employing a same anisotropic etch process. The first-tier contact openings formed over stepped surfaces of the first alternating stack may extend through the first alternating stack, or may stop on the stepped surfaces. Sacrificial first-tier opening fill portions are formed in the first-tier openings, and a second-tier structure can be formed over the first-tier structure. Memory openings including volumes of the first-tier memory openings are formed through the multi-tier structure, and memory stack structures are formed in the memory openings. Various contact openings are formed through the multi-tier structure, and various contact via structures are formed in the contact openings.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: July 16, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: James Kai, Zhixin Cui, Murshed Chowdhury, Johann Alsmeier, Tong Zhang
  • Patent number: 10355018
    Abstract: Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. Vertically-extending monolithic channel material is adjacent the select device gate material and the conductive levels. The monolithic channel material contains a lower segment adjacent the select device gate material and an upper segment adjacent the conductive levels. A first vertically-extending region is between the lower segment of the monolithic channel material and the select device gate material. The first vertically-extending region contains a first material. A second vertically-extending region is between the upper segment of the monolithic channel material and the conductive levels. The second vertically-extending region contains a material which is different in composition from the first material.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: July 16, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Justin B. Dorhout, David Daycock, Kunal R. Parekh, Martin C. Roberts, Yushi Hu
  • Patent number: 10355099
    Abstract: A plurality of gate electrodes is stacked on an upper surface of a substrate in a direction perpendicular to an upper surface of the substrate. A channel region penetrates through the plurality of gate electrodes to extend perpendicularly to the upper surface of the substrate. A gate dielectric layer includes a tunneling layer, a charge storage layer and a blocking layer that are sequentially disposed between the channel region and the plurality of gate electrodes. The charge storage layer includes a plurality of doping elements and a plurality of deep level traps generated by the plurality of doping element. A concentration distribution of the plurality of doping elements in a thickness direction of the charge storage layer is non-uniform.
    Type: Grant
    Filed: January 14, 2018
    Date of Patent: July 16, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun Yeoung Choi, Jun Kyu Yang, Young Jin Noh, Jae Young Ahn, Jae Hyun Yang, Dong Chul Yoo, Jae Ho Choi
  • Patent number: 10340284
    Abstract: A stack structure includes conductive layer patterns and interlayer insulating layer patterns alternately stacked on one another. A channel hole penetrates the stack structure. A dielectric layer is disposed on a sidewall of the channel hole. A channel layer is disposed on the dielectric layer and in the channel hole. A passivation layer is disposed on the channel layer and in the channel hole. The channel layer is interposed between the passivation layer and the dielectric layer. An air gap is surrounded by the passivation layer. A width of the air gap is larger than a width of the passivation layer.
    Type: Grant
    Filed: January 14, 2018
    Date of Patent: July 2, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung Gil Kim, Seul Ye Kim, Hong Suk Kim, Jin Tae Noh, Ji Hoon Choi, Jae Young Ahn
  • Patent number: 10332904
    Abstract: A semiconductor memory device includes a conductive layer; a first electrode layer provided above the conductive layer; a second electrode layer provided between the conductive layer and the first electrode layer; a first semiconductor channel body extending through the first electrode layer in a first direction from the conductive layer to the first electrode layer; a second semiconductor channel body provided between the conductive layer and the first semiconductor channel body, the second semiconductor channel body extending through the second electrode layer; and an insulating layer provided between the second semiconductor channel body and the second electrode layer. The second semiconductor channel body includes a first recessed portion in a lateral surface facing the second electrode layer, and the second electrode layer includes a second recessed portion in a surface facing the second semiconductor channel body.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: June 25, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kazuharu Yamabe, Ryota Suzuki, Tatsuo Izumi, Masahiro Fukuda, Takuo Ohashi
  • Patent number: 10332611
    Abstract: A three-dimensional semiconductor memory device including a substrate including a first connection region, a second connection region, and a cell array region disposed between the first and second connection regions. The memory device further includes an electrode structure including a plurality of electrodes vertically stacked on the substrate, wherein each of the electrodes has a pad exposed on the first connection region, and a dummy electrode structure disposed adjacent to the electrode structure and including a plurality of dummy electrodes vertically stacked on the substrate. Each dummy electrode has a dummy pad exposed on the second connection region. The electrode structure includes a first stair structure and a second stair structure which each includes the pads of the electrodes exposed on the first connection region. The first stair structure extends along a first direction, and the second stair structure extends along a second direction that crosses the first direction.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: June 25, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwang-Soo Kim, Heonkyu Lee
  • Patent number: 10332910
    Abstract: A memory cell comprises an elevationally extending programmable field effect transistor comprising a gate insulator that is reversibly programmable into two programmable states characterized by two different Vt's of the programmable transistor. The programmable transistor comprises a top source/drain region and a bottom source/drain region. A bottom select device is electrically coupled in series with and elevationally inward of the bottom source/drain region of the programmable transistor. A top select device is electrically coupled in series with and is elevationally outward of the top source/drain region of the programmable transistor. A bottom select line is electrically coupled in series with and is elevationally inward of the bottom select device. A top select line is electrically coupled in series with and is elevationally outward of the top select device. Other embodiments are disclosed.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: June 25, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Ferdinando Bedeschi