Die Seal Layout for VFTL Dual Damascene in a Semiconductor Device
A semiconductor may include several vias located in an active region and a die seal region. In the active region, a photoresist can be patterned with openings corresponding to the vias. In the die seal area, however, the photoresist can be patterned to overlap the vias. With this configuration, an underlayer etch will not affect an underlayer resist in the die seal area, allowing the die seal area to be disregarded for purposes of calculating a process window.
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This application is a Divisional Application of U.S. patent application Ser. No. 13/865,714, filed Apr. 18, 2013, which is incorporated herein by reference in its entirety.
BACKGROUND1. Technical Field
The disclosure generally relates to formation of semiconductor elements, and specifically to performing a via first trench last (VFTL) process in a die seal area of a semiconductor device.
2. Related Art
In semiconductor device manufacturing, it is often necessary to use metal fill technology to form metal in a dielectric trench and via for interconnecting different layers and/or different metal materials in the semiconductor device. One such metal fill process is commonly referred to as a “damascene” process, in which dielectric layers are first etched, and then filled with a desired metal material. There are two types of commonly-used damascene processes: (1) single damascene—separately etching and filling a trench (used for inter-level connections) and a via (used for intra-level connections); and (2) dual damascene—etching the trench and via, and then filling them together at the same time. Generally, dual damascene is preferred over single damascene processes due to reduced manufacturing costs, etc.
There are two preferred types of dual damascene processes that are common in the industry: Trench first via last (TFVL) and via first trench last (VFTL). In TFVL, as its name implies, the trench is etched prior to the via. For example, a first mask is used to define a width of the trench. The device is then etched, using the first mask as a guide to etch the trench in an upper dielectric. Following the creation of the trench, a second mask is patterned within the trench to define a width of the via. A second etch is then performed, using the second mask as a guide, to form the via in a lower dielectric. Once the trench and via have been formed, they are filled with a metal material, such as copper, for example. In VFTL, on the other hand, the via is etched before the trench. In particular, a first mask is used to define the width of the via. The via is formed by etching, using the first mask as a guide, through both an upper and lower dielectric. Once the via has been formed, a spin-on planarization process are used to fill the via holes and provide better pattern process windows. Usually, spin on organic (e.g., resist or organic BARC) or dielectric materials (e.g., spin-on-glass (SOG) or spin on low k materials) are used to fill the via holes and to planarize the wafer surface. After surface planarization, a second mask is formed over the upper dielectric to define a width of the trench. The trench is then formed by etching, using the second mask as a guide, through only the upper dielectric.
As mentioned above, in these conventional VFTL processes a planarization step using a spin technique is used to fill the via holes and to planarize the wafer surface. As a result, the spin-on underlayer may not have uniform thickness among all areas of the semiconductor device. For example, the spin on layer may be thicker in isolated via holes or areas having no vias of the semiconductor device and thinner in the area where via holes are more dense. The thinnest spin on layer will be in a die seal area (e.g., an area of the semiconductor die having a continuous trench line located at the edge of the device area, which is used to stop cracks caused during a cutting process from harming the functional areas), where the trenches are larger and require more spin on materials to fill the trench holes. As a result of the non-uniform coating of the spin on layer, a subsequent etching process may cause defects in the semiconductor device that can greatly affect performance.
For example,
As shown in
In the VFTL dual damascene process, a first mask (via mask) will include the via holes and die seal openings. The subsequent via etch process will etch vias and die seals through both top and bottom dielectric layers. However, a second mask (metal trench mask) will only open the trench lines in the device area without opening die seals. With this configuration, a subsequent trench etch process will not damage trench corners or cause contamination issues near the die seal area, allowing the die seal area to be disregarded for purposes of calculating a process window.
Embodiments are described herein with reference to the accompanying drawings. In the drawings, like reference numbers generally indicate identical or functionally similar elements. Additionally, generally, the left most digit(s) of a reference number identifies the drawing in which the reference number first appears.
The following Detailed Description refers to accompanying drawings to illustrate exemplary embodiments consistent with the disclosure. References in the Detailed Description to “one exemplary embodiment,” “an exemplary embodiment,” “an example exemplary embodiment,” etc., indicate that the exemplary embodiment described may include a particular feature, structure, or characteristic, but every exemplary embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same exemplary embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an exemplary embodiment, it is within the knowledge of those skilled in the relevant art(s) to affect such feature, structure, or characteristic in connection with other exemplary embodiments whether or not explicitly described.
The exemplary embodiments described herein are provided for illustrative purposes, and are not limiting. Other exemplary embodiments are possible, and modifications may be made to the exemplary embodiments within the spirit and scope of the disclosure. Therefore, the Detailed Description is not meant to limit the invention. Rather, the scope of the invention is defined only in accordance with the following claims and their equivalents.
Method embodiments may be implemented in hardware (e.g., circuits), firmware, software, or any combination thereof. Method embodiments may also be implemented as instructions stored on a machine-readable medium, which may be read and executed by one or more processors. A machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computing device). For example, a machine-readable medium may include read only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; electrical, optical, acoustical or other forms of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.), and others. Further, firmware, software, routines, instructions may be described herein as performing certain actions. However, it should be appreciated that such descriptions are merely for convenience and that such actions in fact results from computing devices, processors, controllers, or other devices executing the firmware, software, routines, instructions, etc. Further, any of the implementation variations may be carried out by a general purpose computer.
The following Detailed Description of the exemplary embodiments will so fully reveal the general nature of the invention that others can, by applying knowledge of those skilled in relevant art(s), readily modify and/or adapt for various applications such exemplary embodiments, without undue experimentation, without departing from the spirit and scope of the disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and plurality of equivalents of the exemplary embodiments based upon the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by those skilled in relevant art(s) in light of the teachings herein.
Those skilled in the relevant art(s) will recognize that this description may be applicable to many various semiconductor devices, and should not be limited to flash memory devices, or any other particular type of semiconductor devices. In addition, the following descriptions specifically relate to resist etch back process flow. However, the disclosure can similarly be applied to each of the conventional bi-layer resist and tri-layer dual damascene process flows to achieve similar beneficial results.
AN EXEMPLARY SEMICONDUCTOR DEVICEAs discussed above, sub-trenches and fencings are defects caused by varying underlayer resist layer thickness across a semiconductor device. Although the thickness varies within an active area of the semiconductor device, the greatest variation is between the active area and a die seal area (located near an edge of the semiconductor device). Therefore, by eliminating the need to adjust the underlayer etch to account for the die seal area, the process window can be substantially reduced, thereby greatly increasing manufacturing yield and device performance.
For example,
In the die seal area 612, an underlayer resist layer 260 is spun on the wafers to fill the trench 250 and to planarize the wafer surface. An underlayer (UL) resist etch back process is used to remove the resist on top of SiRN (silicon-rich nitride) surface 235. As shown in
In an embodiment, during the trench oxide etch process, since the die seal is protected by photoresist, as shown in
In a subsequent step of the VFTL process, an ash and SiN etch is performed on the semiconductor device 201. As one skilled in the art will readily recognize, “ashing” is the general process of using a plasma containing oxygen to oxidize (“ash”) a photoresist in order to facilitate its removal. The ash+SiN etch removes the remaining underlayer resist layer 260 from the die seal area 612 (as shown in
As can be seen in
In conventional VFTL processes, the defects are substantially created during this trench oxide etch step. However, the main cause of the defects is due to the inadequate resist recess in the via holes. Specifically, the difference in thickness between the underlayer resist layer 260 in the active area 614 and that of the underlayer resist layer 260 in the die seal area 612 required a choice to be made. By choosing to etch the thicker underlayer resist layer in the active area 614 to a preferred height, the thinner underlayer resist layer in the die seal area 612 became overetched and resulted in sub-trenches, as shown in
Therefore, as shown in
As shown in
As shown in
In summary, using the above-described method, a semiconductor device can be manufactured with greater ease because the process window has been widen by effectively making the die seal area immaterial during the initial underlayer etching step. As a result, the semiconductor device can be manufactured at lower cost and with greater yield.
As shown in
In step 410, referring to
In step 420, a UL resist etch back is performed. Referring to
In step 430, a resist patterning process is used to define trench lines (
In step 440, a dielectric etch is performed to form a dual damascene structure on the active area of the wafer. Referring to
In step 450, an ash +SiN etch is performed. Referring to FIGS. 2F/2G and 3G/3H, this process removes any remaining underlayer resist layer 260 and exposes SiRN and SiN layers (235, 225, and 215). The result of this method is a die seal area (e.g.,
Those skilled in the relevant art(s) will recognize that the above method can additionally or alternatively include any of the steps or substeps described above with respect to
The photoresist module 510 is configured to spin on a continuous photoresist layer 260 over a die seal area of a semiconductor device that covers the trenches 250 of the die seal area, and is also configured to deposit a photoresist layer 380 over an active area of the semiconductor device that has openings over the vias 350 of the active area. The widths of the openings of the photoresist 380 in the active area should be a preferred width of a trench 355 to be formed later.
The UL resist etching module 520 performs a UL etch of the semiconductor device. Referring to
After UL etch, the wafer will go back to photoresist module 510 for trench patterning. At this time, the trench lines will be defined in the active area. As mentioned before, the die seal area will be covered with resist during this resist patterning process.
The dielectric etching module 530 is configured to perform a TEOS etch of the semiconductor device. Referring to
The ash+SiN etching module 540 is configured to perform an ash+SiN etch of the semiconductor device. Referring to
Those skilled in the relevant art(s) will recognize that the above apparatus 500 can additionally or alternatively be configured to perform any of the steps or substeps described above with respect to
It is to be appreciated that the Detailed Description section, and not the
Abstract section, is intended to be used to interpret the claims. The Abstract section may set forth one or more, but not all exemplary embodiments, and thus, is not intended to limit the disclosure and the appended claims in any way.
Embodiments of the invention have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries may be defined so long as the specified functions and relationships thereof are appropriately performed.
It will be apparent to those skilled in the relevant art(s) that various changes in form and detail can be made therein without departing from the spirit and scope of the disclosure. Thus, the invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
Claims
1. A semiconductor device, comprising:
- an active area having a plurality of active elements, each of the active elements being defined by a first trench overlapping with a via, each of the active elements including a first continuous metal filling disposed in the first trench and the via; and
- a die seal area defined by a second trench, a second continuous metal filling disposed in the second trench.
2. The semiconductor device of claim 1, wherein the first trench is wider than the via.
3. The semiconductor device of claim 1, wherein the first trench is narrower than the via.
4. The semiconductor device of claim 1, wherein the second trench is formed by a single exposure and etch patterning process.
5. The semiconductor device of claim 1, wherein the first continuous metal filling and the second continuous metal filling are deposited at substantially the same time.
6. The semiconductor device of claim 1, wherein the die seal area includes a plurality of second trenches.
7. The semiconductor device of claim 1, wherein the die seal area extends around a perimeter of the semiconductor device.
8. A semiconductor device, comprising:
- an active area having a plurality of active elements, each of the plurality of active elements including: a via; a first trench that overlaps the first via; and a first continuous metal filling disposed in the first trench and the first via; and
- a die seal area having a second trench, the die seal area including a second continuous metal filling disposed in the second trench.
9. The semiconductor device of claim 8, further comprising an upper portion that houses the first trench and a lower portion that houses the via.
10. The semiconductor device of claim 9, wherein the second trench is disposed in the upper portion and the lower portion.
11. The semiconductor device of claim 9, wherein the second trench extends an entire depth of the lower portion and at least a partial depth of the upper portion.
12. The semiconductor device of claim 8, wherein the second trench has a depth larger than a depth of the via and larger than a depth of the first trench.
13. The semiconductor device of claim 8, wherein the die seal area includes a plurality of second trenches.
14. The semiconductor device of claim 8, wherein the die seal area extends around a perimeter of the semiconductor device.
15. A semiconductor device, comprising:
- a first area that includes: a via; a first trench that overlaps the first via; and a first continuous metal filling disposed in the first trench and the first via; and
- a second area that includes: a second trench; and a second continuous metal filling disposed in the second trench.
16. The semiconductor device of claim 15, wherein the first trench is wider than the via.
17. The semiconductor device of claim 15, wherein the first trench is narrower than the via.
18. The semiconductor device of claim 15, wherein the second trench has a depth larger than a depth of the via and larger than a depth of the first trench.
19. The semiconductor device of claim 15, wherein the second area includes a plurality of second trenches.
20. The semiconductor device of claim 15, wherein the second area extends around a perimeter of the semiconductor device.
Type: Application
Filed: Dec 10, 2014
Publication Date: Apr 2, 2015
Applicant: Spansion LLC (Sunnyvale, CA)
Inventor: Fei WANG (San Jose, CA)
Application Number: 14/566,462
International Classification: H01L 21/76 (20060101); H01L 29/40 (20060101);