Floating Body Contact Circuit Method for Improving ESD Performance and Switching Speed
Embodiments of systems, methods, and apparatus for improving ESD performance and switching time for semiconductor devices including metal-oxide-semiconductor (MOS) field effect transistors (FETs), and particularly to MOSFETs fabricated on Semiconductor-On-Insulator (“SOT”) and Silicon-On-Sapphire (“SOS”) substrates.
This application claims the benefit of priority from U.S. Provisional Patent Application No. 61/906,843, filed Nov. 20, 2013, entitled “Floating Body Contact Circuit Method for Improving ESD Performance and Switching Speed”, the entire disclosure of which is hereby incorporated by reference.
TECHNICAL FIELDVarious embodiments described herein relate generally to systems, methods, and apparatus for improving ESD performance and switching time for semiconductor devices, in particular floating body semiconductor devices including metal-oxide-semiconductor (MOS) field effect transistors (FETs), and more particularly to MOSFETs fabricated on Semiconductor-On-Insulator (“SOT”) and Silicon-On-Sapphire (“SOS”) substrates.
BACKGROUND INFORMATIONIt may be desirable to improve ESD performance and switching time for semiconductor devices including metal-oxide-semiconductor (MOS) field effect transistors (FETs), and particularly to MOSFETs fabricated on Semiconductor-On-Insulator (“SOP”) and Silicon-On-Sapphire (“SOS”) substrates, the present invention provides system, apparatus, and methods for same.
It is noted that the elements of
The electronic devices may include portable and non-portable devices, the portable devices may include mobile phones, personal data assistants (PDAs), tablets, laptops, digital cameras, digital audio and video players, and other devices including ESD sensitive elements or modules. The non-portable devices may include any device including electronic components including automotive, communication, test equipment, medical, RADAR, and satellite devices. It is noted that a human body induced TLP may reach 35,000 volts and have a short rise time, on the order of nanoseconds. Such an ESD event may cause a gate-oxide punch-through in an integrated circuit element including Complementary metal-oxide-semiconductor (CMOS), metal-oxide-semiconductor field-effect transistor (MOSFET), other type field-effect transistor (FET), silicon on insulator (SOI), silicon on sapphire (SOS), or other semiconductor device and damage resistors 34A, 34B, 134A, 134B, FETs 32A, 32B, 132A-132C, and diodes 136A, 136B.
In an embodiment, a semiconductor 32A may be floating body type semiconductor including an N-type MOSFET (NMOSFET) or P-type MOSFET (PMOSFET) formed on an insulator including a silicon on insulator (SOI) or silicon on sapphire (SOS). During an off state (when the source-to-gate voltage Vsg) is not sufficient to turn on the gate (allow conduction from the source to the drain) but the Vsg is not insignificant, an accumulated charge may form in the semiconductor body and operate in an accumulated charge regime (ACR) described in more detail below with reference to
In an embodiment, a semiconductor device 132A (
In order to limit an ESD strike current applied to a transistor 132A, the gate resistor 134A may be made large. A transistor 132A gate (G) may have a parasitic gate capacitance between itself and the source (Cgs) and the drain (Cgd). A larger gate resistor 134A in combination with the Cgs and Cgd parasitic capacitance may introduce an unacceptable time delay (RC time constant) for the transistor 132A (switching time, Tsw).
In an embodiment, the semiconductor transistors 32A, 32B may be SOI or SOS devices (formed on an insulating substrate). Further, the semiconductor devices 32A, 32B may be NMOSFETs formed on an insulator. The resistors 34A, 34B may enable the transistors 32A, 32B to each handle a predetermined voltage, about 2.5 to 3 volts in an embodiment. The stacked transistors 32A, 32B of module 30B may handle twice the voltage of a single transistor 32A. In an embodiment, due to the isolation between transistors 32A, 32B created by their formation on SOI or SOS (floating body type transistors). The semiconductor transistors 32A, 32B may be sized (gate, source, drain, and body width and length on die) to handle a predetermined minimum voltage and have a desired maximum switching time Tsw (affected by the gate width). A circuit module 30B switching time may be vary as function of each transistor 32A, 32B gate width and the ohmic size of each coupled gate resistor 34A, 34B, their effective RC time constant due in part to the parasitic capacitance Cgs and Cgd of the transistors 32A, 32B.
In an embodiment, an ESD across the ports 102A, 120B may be distributed between the transistors 32A, 32B as a function of the gate resistors 34A, 34B and the transistors 32A, 32B parasitic capacitances, Cgs, Cds. As noted, accumulated charge in the transistor 32A, 32B body may also affect the distribution of an ESD across the transistors 32A, 32B. Larger gate resistors 34A, 34B may reduce the ESD energy received by both transistors 32A, 32B. Further, as noted an ESD event or strike may be short in duration. A transistor's 32A, 32B gate width may be selected to enable faster switching (reduce formed parasitic capacitance, Cgs, Cgd) and enable a transistor 32A, 32B to process higher frequency ESD events. As noted above, larger gate resistors (in the order hundreds of kilo-ohms in an embodiment) may enable a circuit or switch module 30B to process larger ESD events, 2 kilo-volts in an embodiment. Larger gate resistors 34A, 34B may, however increase the switching time (Tsw) or RC time constant of a circuit module 30B, making the module 30B unusable or unsuitable for some applications including some radio frequency (RF) switching applications. Stacking semiconductor devices 32A, 32B with high gate resistance may also increase the insertion loss for a signal modulated between the ports 102A, 102B by the control signal 104A.
As explained with reference to
As noted, a transistor's 32A, 32B gate resistor's 34A, 34B size may be linearly related to the maximum ESD strike or event that the corresponding transistor 32A, 32B may be able to handle or absorb without physical damage. The current processed by a transistor 32A, 32B during an ESD event may be proportional to the transistor's gate resistor 32A, 32B. Accordingly it may be desirable to have a large gate resistor 34A, 34B to improve a circuit modules' 30A, 30B ESD performance or handling. As noted, a larger gate resistor, 34A, 34B, however may decrease the switching speed of the corresponding semiconductor device 32A, 32B. In an embodiment, 10A, 10B, the resistor 34A, 34B sizing may be selected based on the maximum acceptable switching time or the minimum acceptable ESD strike or event energy the corresponding transistor(s) 32A, 32B must absorb without damage. In addition, a circuit modules' 30B stack size (number of semiconductors 32A, 32B) may be limited. In an embodiment, based on the maximum acceptable insertion loss at the switch module 30B. Accordingly, in a system employing a circuit module 30A, 30B, the ESD performance, Tsw, and insertion loss may be balanced or sacrificed depending on the system operation requirements.
As shown in
In addition to redirecting a limited ESD energy (as shown in
In an embodiment, the transistor 42A may be configured to bypass the resistor 44A when architecture 100A is active. The control port 104B may be coupled to architecture 100A power (Vdd) so the transistor 42A is active, bypassing resistor 44A while architecture 100A is receiving power (Vdd). Given the transistor 42A is not switched at high speed, its gate resistor 44B may be made large (400K ohms or greater in an embodiment) to ensure the transistor 42A can withstand an ESD event or strike. As shown in
In an embodiment, the switchable gate resistance module 40A first resistor 44A may be hundreds of kilo ohms. The net circuit module 30A gate resistance (44A and 34A), during architecture 100A inactivity (no Vdd power) may be sufficient to handle minimum ESD event requirements while the resistor 34A may be small enough to meet minimum, Tsw switch speed requirements (when Vdd power is present).
In an embodiment, the SGRM 40A first resistor 44A may be hundreds of kilo ohms. The net circuit module 30B gate resistance at both transistors 32A, 32B, during architecture 100B inactivity (no Vdd power) may be sufficient to handle minimum ESD event requirements while the resistors 34A, 34B for each transistor 32A, 32B may be small enough to meet minimum, Tsw switch speed requirements (during normal activity—Vdd power present).
In an embodiment, the SGRM 40A, 40B first resistors 44A may be hundreds of kilo ohms. The net circuit module 30B gate resistances (44A and 34A and 44A and 34B), during architecture 100C inactivity (no Vdd power) may be sufficient to handle minimum ESD event requirements while the resistors 34A, 34B may be small enough to meet minimum Tsw switch speed requirements during normal activity.
In an embodiment, the circuit module 130A may be coupled to the port 102A and the port 102B. In an embodiment, the circuit module 130A may employed as a switch, in particular an RF switch. The ports 102A, 102B may be RF+ and RF− ports. The circuit module 130A may receive an RF signal on port 102A and generate a modulated RF signal on port 102B based on a signal received at port 104A. As shown in
Semiconductor devices operating in an ACR may introduce parasitic capacitance non-linearities, affect the drain-to-source breakdown voltage (BVDSS), and introduce harmonic distortion and intermodulation distortion to a signal processed by the semiconductor 132A including an RF signal at port 102A that is modulated by the transistor 132A. Such RF signal distortions may be unacceptable, particularly when architecture 110A is employed in communication systems. In communication systems, signal distortion may cause unacceptable interface with adjacent signals, violating system operating guidelines and government signal transmission rules.
Any semiconductor device 32A, 32B, 132A-132D (
As noted, a circuit module 130A including devices 132A may process RF signals and its parasitic capacitance Cgs and Cgd may cause harmonic distortion and intermodulation distortion to the higher frequency content of the RF signals. Architectures 100A-C, 110A-B, 140A-B, and 150A-C (
In order to reduce the effects of operating a semiconductor device 132A-132D in ACR, an accumulated charge sink (ACS) 135A, 135B may be coupled to the semiconductor device 132A-132D body. The ACS 135A, 135B may be coupled directly to a device 132A-132D transistor body or be formed on an extension of the body. In an embodiment, a device 132A-132D may be N MOSFET devices where the source and drain are N-type and the body is P-type. An ACS 135A, 135B may include a P doped section and a P+ doped section. An ACS 135A, 135B may include a metal contact or other semiconductor contact to enable conduction of accumulated charge from a device 132A-132D body.
In an embodiment, the ACS 135A, 135B may be coupled to a device 132A-132D (
ACR, ACS, circuits, systems, architecture, semiconductors, and methods for reducing accumulated charge in floating body semiconductor devices are described in the following commonly assigned U.S. Applications and Patent: Provisional Application No. 60/698,523, filed on Jul. 11, 2005, entitled “Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink;” Provisional Application No. Provisional Application No. 60/718,260, filed on Sep. 15, 2005, entitled “Method and apparatus improving gate oxide reliability by controlling accumulated charge;” application Ser. No. 11/484,370, filed Jul. 10, 2006, which issued Mar. 22, 2011 as U.S. Pat. No. 7,910,993, entitled “METHOD AND APPARATUS FOR USE IN IMPROVING LINEARITY OF MOSFETs USING AN ACCUMULATED CHARGE SINK”. All of the above-cited applications and issued patent set forth above are hereby incorporated by reference herein as if set forth in full for their teachings on ACR, ACS, circuits, systems, architecture, semiconductors, and methods for reducing accumulated charge in floating body semiconductor devices.
In an embodiment, the semiconductor devices 32A, 32B, 132A-132D may be include an ACS 135A, 135B. The circuit modules 30A, 30B, 130A-C, 142A, 142B may employ semiconductor modules or devices 32A, 32B, 132A-132D with ACS 135A, 135B. The circuit modules 32A, 32B, 132A-132D may further include an ACS transfer module 139A, 139B or circuit 136A, 136B coupling the ACS 135A, 135B to the device 32A, 32B, 132A-132D to its gate directly or indirectly. In an embodiment, a floating body semiconductor 32A, 32B, 132A-132D may be formed on a die with components to reduce the ACS such as shown and described in the incorporated U.S. Pat. No. 7,910,993.
As shown in
As noted, in a field effect transistor (FET) formed on an insulator (SOI) including sapphire (SOS), accumulated charge may get trapped in the FET when a non-zero voltage signal below threshold is present on the gate (G) of the FET (32A, 32B, 132A-132D), termed operating an accumulated charge regime (ACR). In an embodiment, the transistors 32A, 32B, 132A-132D may be NPN MOSFETs operating in enhancement mode. Such devices may operate when their gate is not negative (zero on device) or exceeds a minimum positive threshold voltage (0.7 volts in an embodiment). Further, the transistors 32A, 32B, 132A, 132B may be formed on an insulator (silicon on insulator, SOI) including sapphire (silicon on sapphire, SOS). Such a transistor 32A, 32B, 132A, 132B may have a floating body and may accumulate trapped charge when a non-zero voltage signal below threshold is present on the gate (G) of the FET (32A, 32B, 132A-132D). Such a charge accumulation may cause operational non-linearities including a non-linear parasitic capacitance, harmonic and intermodulation distortions on a processed signal, and reduce the FETs (32A, 32B, 132A-132D) breakdown voltage.
In order to reduce the trapped charge, the FET (32A, 32B, 132A-132D) may include an ACS 135A, 135B. The FET (32A, 32B, 132A-132D) ACS 135A, 135B may be electrically coupled to another location (on the FET (32A, 32B, 132A-132D) or other circuit location via a circuit (136A, 136B, 139A, 139B) to reduce or eliminate accumulated charge in the FET (32A, 32B, 132A-132D) body. In an embodiment, the circuit 136A, 136B, 139A, 139B may include a diode 136A, 136B coupled to the FET (32A, 32B, 132A-132D) ACS 135A, 135B. The diode 136A, 136B may enable the reduction in accumulated trapped charge in a FET (32A, 32B, 132A-132D).
As noted with reference to
Accordingly, while an ACS circuit 136A including a diode may reduce accumulated charge via an ACS 135A, 135B, the ACS circuit 136A may increase body damage during a positive ESD strike by preventing the operation of the parasitic bipolar device 137. ACS reduction, however may be required for system performance as noted above. Accordingly, a circuit or system may need to reduce accumulated charge of incorporated float body semiconductors while not affecting the inherent ESD performance of the incorporated floating body semiconductors during positive and negative ESD strikes.
As shown in
The resistors 134A, 134B may couple the control signal 104A to the semiconductor transistors 132C, 132D gates (G). In an embodiment, the transistor 132A drain (D) or source (S) may be coupled to the input port 102A and the transistor 132C source (S) or drain (D) may be coupled to the transistor 132D drain (D) or source (S), and the transistor 132D source (S) or drain (D) may be coupled to the output port 102B.
In a field effect transistor (FET) formed on an insulator (SOI) including sapphire (SOS), accumulated charge may get trapped in the FET when a non-zero voltage below the FET threshold is present on the FET gate (operating in an ACR). In an embodiment, the transistors 132C, 132D may be NPN MOSFETs operating in enhancement mode. Such devices may operate when their gate is not negative (zero on device) or exceeds a minimum positive threshold voltage (0.7 volts in an embodiment). Further, the transistors 132C, 132D may be formed on an insulator (silicon on insulator, SOI) including sapphire (silicon on sapphire, SOS). Such a transistor 132C, 132D may be a floating body transistor and may accumulate trapped charge when a non-zero voltage below the FET threshold is present on the FET gate. Such a charge accumulation may cause operational non-linearities including a non-linear parasitic capacitance, harmonic and intermodulation distortions to processed signals, and reduced BVDSS (breakdown voltage).
In order to reduce the trapped charge in a FET, a circuit module 142A-D including the FETs 132C, 132D may include ACS 135A, 135B and ACS transfer modules 139A-D. In an embodiment, each ACS transfer module 139A-D may include a diode 136A, 136B. The diodes 136A, 136B may enable a transistor 132C, 132D to reduce accumulated trapped charge. In an embodiment, the ACS transfer modules 139A-D may include a diode 136A, 136B coupled in series with a resistor 138A, 138B. The combination of the coupled diode 136A, 136B and resistor 138A, 138B may couple an ACS 135A, 135B to a. a location between the gate resistor 134A, 134B and the control port 104A (
As noted above, during a positive ESD event, impact ionization current Ih.gen may be directed away from the parasitic bipolar device 137 base, reducing the device 137 base current (IB) and preventing its activation. The addition of the resistor 138A, 138B to the ACS transfer module 139A, 139B may provide a greater path of resistance for the impact ionization current Ih.gen than to the parasitic bipolar device 137 base, increasing the device 137 base current (IB) during a positive ESD event. The bipolar device 137 may then activate and direct current away from the sensitive gate-body interface 54B (
In an embodiment, the SGRM 40A first resistor 44A may be hundreds of kilo ohms. The net circuit module 142B gate resistance at both transistors 132A, 132B, during architecture 150B inactivity (no Vdd power) may be sufficient to handle minimum ESD event requirements while the resistors 134A, 134B for each transistor 132A, 132B may be small enough to meet minimum, Tsw switch speed requirements. The transistors 132A, 132B with ACS transfer modules 139A, 139B may be enable dissipate remaining ESD strike or events (where a portion of the ESD strike or event energy may be absorbed or dissipated by the first resistor 44A). The combination of SGRM 40A and stacked transistors 132A, 132B with ACS transfer modules 139A, 139B may enable architecture 150B to handle required level ESD events or strikes while meeting switch time requirements (Tsw).
In an embodiment, as shown in
In an embodiment, the SGRM 40A, 40B first resistors 44A may be hundreds of kilo ohms. The net circuit module 142B gate resistance at both transistors 132A, 132B, during architecture 150B inactivity (no Vdd power) may be sufficient to handle minimum ESD event requirements while the resistors 134A, 134B for each transistor 132A, 132B may be small enough to meet minimum, Tsw switch speed requirements during normal operation. The transistors 132A, 132B with ACS transfer modules 139A, 139B may be able to dissipate remaining ESD strike or events (where a portion of the ESD strike or event energy may be absorbed or dissipated by the first resistors 44A of the SGRM 40A, 40B). The combination of the SGRM 40A, 40B and stacked transistors 132A, 132B with ACS transfer modules 139A, 139B may enable architecture 150C to handle required levels of ESD events or strikes while meeting switch time requirements (Tsw).
Applications that may include the novel apparatus and systems of various embodiments include electronic circuitry used in high-speed computers, communication and signal processing circuitry, modems, single or multi-processor modules, single or multiple embedded processors, data switches, and application-specific modules, including multilayer, multi-chip modules. Such apparatus and systems may further be included as sub-components within a variety of electronic systems, such as televisions, cellular telephones, personal computers (e.g., laptop computers, desktop computers, handheld computers, tablet computers, etc.), workstations, radios, video players, audio players (e.g., mp3 players), vehicles, medical devices (e.g., heart monitor, blood pressure monitor, etc.) and others. Some embodiments may include a number of methods.
It may be possible to execute the activities described herein in an order other than the order described. Various activities described with respect to the methods identified herein can be executed in repetitive, serial, or parallel fashion.
A software program may be launched from a computer-readable medium in a computer-based system to execute functions defined in the software program. Various programming languages may be employed to create software programs designed to implement and perform the methods disclosed herein. The programs may be structured in an object-orientated format using an object-oriented language such as Java or C++. Alternatively, the programs may be structured in a procedure-orientated format using a procedural language, such as assembly or C. The software components may communicate using a number of mechanisms well known to those skilled in the art, such as application program interfaces or inter-process communication techniques, including remote procedure calls. The teachings of various embodiments are not limited to any particular programming language or environment.
The accompanying drawings that form a part hereof show, by way of illustration and not of limitation, specific embodiments in which the subject matter may be practiced. The embodiments illustrated are described in sufficient detail to enable those skilled in the art to practice the teachings disclosed herein. Other embodiments may be utilized and derived there-from, such that structural and logical substitutions and changes may be made without departing from the scope of this disclosure. This Detailed Description, therefore, is not to be taken in a limiting sense, and the scope of various embodiments is defined only by the appended claims, along with the full range of equivalents to which such claims are entitled.
Such embodiments of the inventive subject matter may be referred to herein individually or collectively by the term “invention” merely for convenience and without intending to voluntarily limit the scope of this application to any single invention or inventive concept, if more than one is in fact disclosed. Thus, although specific embodiments have been illustrated and described herein, any arrangement calculated to achieve the same purpose may be substituted for the specific embodiments shown. This disclosure is intended to cover any and all adaptations or variations of various embodiments. Combinations of the above embodiments, and other embodiments not specifically described herein, will be apparent to those of skill in the art upon reviewing the above description.
The Abstract of the Disclosure is provided to comply with 37 C.F.R. §1.72(b), requiring an abstract that will allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In the foregoing Detailed Description, various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted to require more features than are expressly recited in each claim. Rather, inventive subject matter may be found in less than all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.
Claims
1. An apparatus for modulating the gate resistance of a transistor having a source, drain, and gate, including a modulated resistor module receiving a modulation signal, including:
- a second resistor having a second resistance, the second resistor configured to be coupled in series between a transistor gate and a gate control terminal for the transistor; and
- a bypass module, the bypass module coupled in parallel to the second resistor and configured to controllably bypass the second resistor based on the modulation signal.
2. The apparatus for modulating the gate resistance of a transistor of claim 1, the apparatus further including a first resistor having a first resistance less than the second resistance, wherein the second resistor and the first resistor are configured to be coupled in series between the transistor gate and the gate control terminal.
3. The apparatus for modulating the gate resistance of a transistor of claim 1, the bypass module including a transistor, the bypass module transistor source and drain coupled about the second resistor.
4. The apparatus for modulating the gate resistance of a transistor of claim 3, wherein the bypass module transistor is configured to bypass the second resistor during normal operation.
5. The apparatus for modulating the gate resistance of a transistor of claim 3, wherein the bypass module transistor gate is tied to a signal that exceeds gate thresholds during normal operation.
6. The apparatus for modulating the gate resistance of a transistor of claim 3, wherein the bypass module transistor and the modulated gate resistance transistor are MOSFETs.
7. The apparatus for modulating the gate resistance of a transistor of claim 3, wherein the bypass module transistor and the modulated gate resistance transistor are floating body MOSFETs.
8. A modulated gate resistance transistor apparatus, including:
- a transistor having a source, drain, and gate; and
- a gate resistance module, including: a second resistor having a second resistance, the second resistor configured to be coupled in series between the transistor gate and a gate control terminal for the transistor; and a bypass module, the bypass module coupled in parallel to the second resistor and configured to controllably bypass the second resistor based on a modulation signal.
9. The modulated gate resistance transistor apparatus of claim 8, the apparatus further including a first resistor having a first resistance, the first resistance less than the second resistance, wherein the second resistor and the first resistor are configured to be coupled in series between the transistor gate and the gate control terminal.
10. The modulated gate resistance transistor apparatus of claim 8, the bypass module including a transistor, the bypass module transistor source and drain coupled about the second resistor.
11. The modulated gate resistance transistor apparatus of claim 10, wherein the bypass module transistor is configured to bypass the second resistor during normal operation.
12. The modulated gate resistance transistor apparatus of claim 10, wherein the bypass module transistor gate is tied to a signal that exceeds gate thresholds during normal operation.
13. The modulated gate resistance transistor apparatus of claim 10, wherein the bypass module transistor and the transistor are MOSFETs.
14. The modulated gate resistance transistor apparatus of claim 10, wherein the bypass module transistor and the transistor are floating body MOSFETs.
15. The modulated gate resistance transistor apparatus of claim 9, wherein the transistor is a four-terminal accumulated charge control floating body MOSFET (ACC MOSFET) device, adapted to control charge accumulated in the body of the ACC MOSFET when the ACC MOSFET is biased to operate in an accumulated charge regime, comprising: the apparatus further comprising a third resistor, the third resistor coupled directly or indirectly between the ACS and one of the gate control terminal and the transistor gate terminal, wherein when the ACC MOSFET is operated in the accumulated charge regime, charge accumulated in the body may be removed from the body via the ACS terminal and the third resistor.
- a gate, drain, source, floating body, and a gate oxide layer positioned between the gate and the floating body, wherein the ACC MOSFET is biased to operate in the accumulated charge regime when the ACC MOSFET is biased to operate in an off-state (non-conducting state) and charge accumulates within the body in a region proximate and underneath the gate oxide layer;
- an accumulated charge sink (ACS) positioned proximate a distal end of the floating body, wherein the ACS is in electrical communication with the floating body; and
- a gate terminal electrically coupled to the gate, a drain terminal electrically coupled to the drain, a source terminal electrically coupled to the source, and an ACS terminal electrically coupled to the ACS;
16. The modulated gate resistance transistor apparatus of claim 15, wherein the ACC MOSFET has an inherent electro-static discharge (ESD) absorption characteristic and wherein the ESD absorption characteristic of the ACC MOSFET is improved by the addition of the third resistor in the apparatus.
17. The modulated gate resistance transistor apparatus of claim 15, wherein the ACC MOSFET is fabricated in a silicon-on-insulator technology.
18. The modulated gate resistance transistor apparatus of claim 15, wherein the third resistor is coupled directly or indirectly between the ACS and the gate control terminal.
19. The modulated gate resistance transistor apparatus of claim 18, wherein the third resistor is coupled indirectly between the ACS and the gate control terminal.
20. The modulated gate resistance transistor apparatus of claim 19, wherein a diode is coupled in series with the third resistor.
21. The modulated gate resistance transistor apparatus of claim 15, wherein a diode is coupled in series with the third resistor.
22. The modulated gate resistance transistor apparatus of claim 15, wherein the third resistor has a resistance from about 100 kilo ohms to several Mega ohms.
23. An accumulated charge regime apparatus, the apparatus including:
- a four-terminal accumulated charge control floating body MOSFET (ACC MOSFET) device, adapted to control charge accumulated in the body of the MOSFET when the MOSFET is biased to operate in an accumulated charge regime, comprising: a gate, drain, source, floating body, and a gate oxide layer positioned between the gate and the floating body, wherein the ACC MOSFET is biased to operate in the accumulated charge regime when the MOSFET is biased to operate in an off-state (non-conducting state) and charge accumulates within the body in a region proximate and underneath the gate oxide layer; an accumulated charge sink (ACS) positioned proximate a distal end of the floating body, wherein the ACS is in electrical communication with the floating body; and a gate terminal electrically coupled to the gate, a drain terminal electrically coupled to the drain, a source terminal electrically coupled to the source, and an ACS terminal electrically coupled to the ACS;
- a gate control terminal;
- a first resistor, the first resistor coupled between the gate control terminal and to the gate terminal; and
- a second resistor, the second resistor coupled directly or indirectly between the ACS and one of the gate control terminal and the transistor gate terminal,
- wherein, when the MOSFET is operated in the accumulated charge regime, charge accumulated in the body may be removed from the body via the ACS terminal and the second resistor.
24. The accumulated charge regime apparatus of claim 23, wherein the ACC MOSFET has an inherent electro-static discharge (ESD) absorption characteristic and wherein the ESD absorption characteristic of the ACC MOSFET is improved by the addition of the second resistor in the apparatus.
25. The ACC MOSFET of claim 23, wherein the ACC MOSFET is fabricated in a silicon-on-insulator technology.
26. The ACC MOSFET of claim 23, wherein the second resistor is coupled directly or indirectly between the ACS and the gate control terminal.
27. The ACC MOSFET of claim 26, wherein the second resistor is coupled indirectly between the ACS and the gate control terminal.
28. The ACC MOSFET of claim 23, wherein a diode is coupled in series with the second resistor.
29. The ACC MOSFET of claim 23, wherein a diode is coupled between the second resistor and the ACS.
30. The ACC MOSFET of claim 27, wherein a diode is coupled in series with the second resistor.
31. The ACC MOSFET of claim 27, wherein a diode is coupled between the second resistor and the ACS.
32. The ACC MOSFET of claim 23, wherein the second resistor has a resistance from about 100 kilo ohms to several Mega ohms.
Type: Application
Filed: Oct 22, 2014
Publication Date: May 21, 2015
Inventors: Eric S. Shapiro (San Diego, CA), Matt Allison (San Diego, CA)
Application Number: 14/521,331
International Classification: H01L 27/02 (20060101); H01L 49/02 (20060101); H01L 27/12 (20060101);