Insulated Electrode Device Is Combined With Diverse Type Device (e.g., Complementary Mosfets, Fet With Resistor, Etc.) Patents (Class 257/350)
  • Patent number: 11515162
    Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region in a gate space, one or more conductive layers are formed over the gate dielectric layer, a seed layer is formed over the one or more conductive layers, an upper portion of the seed layer is treated by introducing one or more elements selected from the group consisting of oxygen, nitrogen and fluorine, and a W layer is selectively formed on a lower portion of the seed layer that is not treated to fully fill the gate space with bottom-up filling approach.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: November 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shahaji B. More, Chandrashekhar Prakash Savant, Chun Hsiung Tsai
  • Patent number: 11495677
    Abstract: A semiconductor device includes a first active fin structure and a second active fin structure extending along a first lateral direction. The semiconductor device includes a dummy fin structure, also extending along the first lateral direction, that is disposed between the first active fin structure and the second fin structure. The dummy fin structure includes a material that is configured to induce mechanical deformation of a first source/drain structure coupled to an end of the first active fin structure and a second source/drain structure coupled to an end of the second active fin structure.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: November 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Ruei Jhan, Kuan-Ting Pan, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11489009
    Abstract: A semiconductor structure that includes a metal layer in a first interlayer dielectric that is above a semiconductor device. The semiconductor structure includes an embedded memory device on the metal layer. The embedded memory device has a first metal contact surrounded by a second interlayer dielectric. Additionally, the semiconductor structure includes a thin film transistor on the first metal contact. The thin film transistor is surrounded by a third interlayer dielectric. The third interlayer dielectric is over a portion of the embedded memory device and a portion of the second interlayer dielectric. The semiconductor structure includes a first portion of a channel of the thin film transistor covered a gate structure, where the channel is a layer of indium tin oxide.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: November 1, 2022
    Assignee: International Business Machines Corporation
    Inventors: Heng Wu, Julien Frougier, Bruce B. Doris, Chen Zhang, Ruilong Xie
  • Patent number: 11482521
    Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including: a p-type substrate, a p-well region within the p-type substrate, and an n-type barrier region between the p-type substrate and the p-well region. The n-type barrier region physically isolates the p-type substrate from the p-well region. A field effect transistor (FET) is positioned above the p-well region, and a buried insulator layer on the upper surface of the p-well region separates the transistor from the p-well region. A first voltage source electrically coupled to the p-well region induces a P-N-P junction across the p-well region, the n-type barrier region, and the p-type substrate.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: October 25, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Don R. Blackwell, Peter P. Hang, Van Ton-That, Timothy S. Miller
  • Patent number: 11430814
    Abstract: A stacked device structure includes a first device structure including a first body that includes a semiconductor material, and a plurality of terminals coupled with the first body. The stacked device structure further includes an insulator between the first device structure and a second device structure. The second device structure includes a second body such as a fin structure directly above the insulator. The second device structure further includes a gate coupled to the fin structure, a spacer including a dielectric material adjacent to the gate, and an epitaxial structure adjacent to a sidewall of the fin structure and between the spacer and the insulator. A metallization structure is coupled to a sidewall surface of the epitaxial structure, and further coupled with one of the terminals of the first device.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: August 30, 2022
    Assignee: Intel Corporation
    Inventors: Aaron D. Lilak, Anh Phan, Patrick Morrow, Willy Rachmady, Gilbert Dewey, Jessica M. Torres, Kimin Jun, Tristan A. Tronic, Christopher J. Jezewski, Hui Jae Yoo, Robert S. Chau, Chi-Hwa Tsang
  • Patent number: 11372292
    Abstract: Included are: a semiconductor layer including a drain region, a channel region, and a second LDD region between the drain region and the channel region; a gate electrode disposed overlapping the channel region; a gate wiring line electrically coupled to the gate electrode; and a second light shielding portion disposed between the second LDD region and the gate wiring line and overlapping the second LDD region and the gate wiring line in plan view.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: June 28, 2022
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Satoshi Ito, Shotaro Izawa
  • Patent number: 11348913
    Abstract: A semiconductor device includes a substrate including a first region and a second region, memory transistors on the first region, a first interconnection layer on the memory transistors and including first interconnection lines, and a second interconnection layer on the first interconnection layer and including second interconnection lines. The second interconnection lines on the first region include a first line extending along a first direction and spaced from the second region by a first distance along the first direction, and a second line extending along the first direction, spaced from the first line along a second direction intersecting the first direction, and having a width smaller than that of the first line. The first line includes a protrusion extending along a third direction toward the substrate. The protrusion is spaced from the second region by a second distance along the first direction greater than the first distance.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: May 31, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Lakgyo Jeong, Seolun Yang, Yongrae Cho, Hee Bum Hong
  • Patent number: 11315783
    Abstract: A method of fabricating a display substrate is provided. The method includes forming a conductive layer on a base substrate; and performing a chemical vapor deposition process to form an oxide layer on a side of an exposed surface of the conductive layer away from the base substrate, the exposed surface of the conductive layer including copper, the oxide layer formed to include an oxide of a target element M. The chemical vapor deposition process is performed using a mixture of a first reaction gas including oxygen and a second reaction gas including the target element M, at a reaction temperature in a range of 200 Celsius degrees to 280 Celsius degrees. A mole ratio of oxygen element to the target element M in the mixture of the first reaction gas and the second reaction gas is in a range of 40:1 to 60:1.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: April 26, 2022
    Assignees: Hefei Xinsheng Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Yuankui Ding, Heekyu Kim, Liangchen Yan, Ce Zhao, Bin Zhou, Yingbin Hu, Wei Song, Dongfang Wang
  • Patent number: 11264457
    Abstract: Semiconductor structures with electrical isolation and methods of forming a semiconductor structure with electrical isolation. A shallow trench isolation region, which contains a dielectric material, is positioned in a semiconductor substrate. A trench extendes through the shallow trench isolation region and to a trench bottom in the semiconductor substrate beneath the shallow trench isolation region. A dielectric layer at least partially fills the trench. A polycrystalline region, which is arranged in the semiconductor substrate, includes a portion that is positioned beneath the trench bottom.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: March 1, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Mark Levy, Siva P. Adusumilli, Steven M. Shank, Alvin J. Joseph, Anthony K. Stamper
  • Patent number: 11257815
    Abstract: In some embodiments, the present disclosure relates to an integrated chip including first, second, and third nanosheet field effect transistors (NSFETs) arranged over a substrate. The first NSFET has a first threshold voltage and includes first nanosheet channel structures embedded in a first gate electrode layer. The first nanosheet channel structures extend from a first source/drain region to a second source/drain region. The second NSFET has a second threshold voltage different than the first threshold voltage and includes second nanosheet channel structures embedded in a second gate electrode layer. The second nanosheet channel structures extend from a third source/drain region to a fourth source/drain region. The third NSFET has a third threshold voltage different than the second threshold voltage and includes third nanosheet channel structures embedded in a third gate electrode layer. The third nanosheet channel structures extend from a fifth source/drain region to a sixth source/drain region.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: February 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mao-Lin Huang, Chih-Hao Wang, Kuo-Cheng Chiang, Jia-Ni Yu, Lung-Kun Chu, Chung-Wei Hsu
  • Patent number: 11217578
    Abstract: A resistor includes a substrate including an active region protruding from an upper surface of the substrate and extending in a first horizontal direction, a doped region extending in the first horizontal direction on the active region and comprising a semiconductor layer with n-type impurities, a plurality of channel layers spaced apart from each other in a vertical direction on the active region and connected to the doped region, a first gate electrode and a second gate electrode extending in the second horizontal direction intersecting the first horizontal direction and surrounding the plurality of channel layers, a first contact plug and a second contact plug in contact with an upper surface of the doped region. The first contact plug is adjacent to the first gate electrode. The second contact plug is adjacent to the second gate electrode.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: January 4, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woocheol Shin, Myunggil Kang
  • Patent number: 11211467
    Abstract: A highly reliable semiconductor device is provided. The semiconductor device includes a first insulator; a first oxide provided over the first insulator; a second oxide provided over the first oxide; a first conductor and a second conductor provided apart from each other over the second oxide; a third oxide provided over the second oxide, the first conductor, and the second conductor; a second insulating film provided over the third oxide; and a third conductor provided over the second oxide with the third oxide and the second insulating film positioned therebetween. The third oxide contains a metal element and nitrogen, and the metal element is bonded to nitrogen.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: December 28, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Tomoki Hiramatsu, Yusuke Nonaka, Noritaka Ishihara, Shota Sambonsuge, Yasumasa Yamane, Yuta Endo
  • Patent number: 11189520
    Abstract: The present technology relates to an imaging device capable of preventing a decrease of sensitivity of the imaging device in a case where a capacitance element is provided in a pixel, a method of manufacturing an imaging device, and an electronic device. The imaging device includes, in a pixel, a photoelectric conversion element and a capacitance element accumulating an electric charge generated by the photoelectric conversion element. The capacitance element includes a first electrode including a plurality of trenches, a plurality of second electrodes each having a cross-sectional area smaller than a contact connected to a gate electrode of a transistor in the pixel, and buried in each of the trenches, and a first insulating film disposed between the first electrode and the second electrode in each of the trenches. The present technology can be applied, for example, to a backside irradiation-type CMOS image sensor.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: November 30, 2021
    Assignee: SONY CORPORATION
    Inventor: Kyohei Mizuta
  • Patent number: 11177255
    Abstract: Embodiments include a first nanowire transistor having a first source and a first drain with a first channel in between, where the first channel includes a first III-V alloy. A first gate stack is around the first channel, where a portion of the first gate stack is between the first channel and a substrate. The first gate stack includes a gate electrode metal in contact with a gate dielectric. A second nanowire transistor is on the substrate, having a second source and a second drain with a second channel therebetween, the second channel including a second III-V alloy. A second gate stack is around the second channel, where an intervening material is between the second gate stack and the substrate, the intervening material including a third III-V alloy. The second gate stack includes the gate electrode metal in contact with the gate dielectric.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: November 16, 2021
    Assignee: Intel Corporation
    Inventors: Sean T. Ma, Willy Rachmady, Gilbert Dewey, Matthew V. Metz, Harold W. Kennel, Cheng-Ying Huang, Jack T. Kavalieros, Anand S. Murthy, Tahir Ghani
  • Patent number: 11152485
    Abstract: A semiconductor structure including a substrate, a complementary metal oxide semiconductor (CMOS) device, a bipolar junction transistor (BJT), and a first protection layer is provided. The CMOS device includes an N-type metal oxide semiconductor (NMOS) transistor and a P-type metal oxide semiconductor (PMOS) transistor disposed on the substrate. The BJT includes a collector, a base and an emitter. The collector is disposed in the substrate. The base is disposed on the substrate. The emitter is disposed on the base. A top surface of a channel of the NMOS transistor, a top surface of a channel of the PMOS transistor and a top surface of the collector of the BJT have the same height. The first protection layer is disposed on the substrate and exposes the substrate. The base is disposed on the substrate exposed by the first protection layer. The semiconductor structure can have better overall performance.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: October 19, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Purakh Raj Verma, Kuo-Yuh Yang
  • Patent number: 11152484
    Abstract: A semiconductor structure including a substrate, a CMOS device and a BJT is provided. The substrate has a first side and a second side opposite to each other. The CMOS device includes an NMOS transistor and a PMOS transistor. The NMOS transistor includes a first N-type doped region and a second N-type doped region disposed in the substrate. The PMOS transistor includes a first P-type doped region and a second P-type doped region disposed in the substrate. The BJT includes a collector, a base and an emitter. The base is disposed on the first side of the substrate. The emitter is disposed on the base. A first metal silicide layer, a second metal silicide layer, and a third metal silicide layer are respectively located on the second side of the substrate and respectively disposed on the collector, the first N-type doped region, and the first P-type doped region.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: October 19, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Purakh Raj Verma, Kuo-Yuh Yang
  • Patent number: 11145663
    Abstract: A method of fabrication of a ferroelectric memory including a first electrode, a second electrode and a layer of active material made of hafnium dioxide HfO2 positioned between the first electrode and the second electrode, where the method includes depositing a first electrode layer; depositing the layer of active material; doping the layer of active material; depositing a second electrode layer; wherein the method includes sub-microsecond laser annealing of the layer of doped active material.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: October 12, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Laurent Grenouillet, Christelle Charpin-Nicolle, Jean Coignus, Terry Francois, Sébastien Kerdiles
  • Patent number: 11139307
    Abstract: A vertical field effect transistor (FET) includes a vertical semiconductor channel having a first end that contacts an upper surface of a substrate and an opposing second end that contacts a source/drain region. An electrically conductive gate encapsulates the vertical semiconductor channel. The vertical FET further includes a split-channel antifuse device between the source/drain region and the electrically conductive gate. The split-channel antifuse device includes a gate dielectric having a thickness that varies between the source/drain region and the electrically conductive gate.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: October 5, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Patent number: 11133669
    Abstract: A limiter having a more ideal limiting function, a short response time, and an adjustable limiting threshold. In one embodiment, a self-activating limiter stack is coupled between circuit ground and a signal line between a source and a receiver. The limiter stack limits the power from the source when the voltage on the signal line exceeds the breakdown voltage of the limiter stack. The threshold of the limiter stack is controlled in part by a first control voltage applied to a control input. A rectifying power detector circuit connected between a node on the signal line and the control input of the limiter stack provides a second control voltage as a function of the signal power at the node. The combined first and second control voltages are applied to the control input to modulate the ON resistance of the limiter stack, thereby limiting the leakage power reaching the protected receiver.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: September 28, 2021
    Assignee: pSemi Corporation
    Inventors: Jianhua Lu, Hojung Ju
  • Patent number: 11126052
    Abstract: According to an aspect, an array substrate includes: a substrate; a light-shielding layer; a first gate electrode; a semiconductor layer; a signal line; and an electrode. A first surface of the substrate is provided with, in sequence, the light-shielding layer, the first gate electrode, the semiconductor layer, the signal line, and the electrode. The semiconductor layer includes a first impurity region electrically coupled to the electrode, a first channel region overlapping the first gate electrode, a second impurity region opposite to the first impurity region with respect to the first channel region, and a first lightly doped drain region between the first impurity region and the first channel region. The light-shielding layer has a first end and a second end opposite to each other. The first end overlaps the first channel region. The light-shielding layer overlaps a boundary between the first channel region and the first lightly doped drain region.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: September 21, 2021
    Assignee: Japan Display Inc.
    Inventors: Yoshitaka Ozeki, Gen Koide, Nobutaka Ozaki
  • Patent number: 11101336
    Abstract: A display device and a method for manufacturing a display device, the device including a semiconductor layer on a substrate; a gate insulation layer and an interlayer insulation layer that overlap the semiconductor layer; contact holes that penetrate the gate insulation layer and the interlayer insulation layer; a source electrode and a drain electrode that are electrically connected with the semiconductor layer through the contact holes; a light emitting diode that is connected with the drain electrode; and first spacers and second spacers between the source electrode and the interlayer insulation layer and between the drain electrode and the interlayer insulation layer in the contact holes.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: August 24, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Yu-Gwang Jeong, Su Bin Bae, Joon Geol Lee, Sang Gab Kim, Shin Il Choi
  • Patent number: 11101374
    Abstract: One or more gated nanosheet diodes are disposed on a substrate and made from a nanosheet structure. A first (second) source/drain (S/D) is disposed on the substrate. The first (second) S/D has a first (second) S/D doping concentration with a first (second) S/D doping type. One or more p-n junctions form one or more respective diodes. There is a first side and a second side of each of the p-n junctions. The first (second) sides of the p-n junctions electrically and physically connect to the first (second) S/Ds and have the same type of doping, respectively. A gate stack, made of a gate dielectric layer and a gate metal, interfaces and surrounds each of the p-n junctions.
    Type: Grant
    Filed: June 13, 2020
    Date of Patent: August 24, 2021
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Bahman Hekmatshoartabari, Karthik Balakrishnan
  • Patent number: 11094599
    Abstract: A semiconductor structure including a substrate, a complementary metal oxide semiconductor (CMOS) device, a bipolar junction transistor (BJT), and a first interconnect structure is provided. The substrate has a first side and a second side opposite to each other. The CMOS device includes an NMOS transistor and a PMOS transistor disposed on the substrate. The BJT includes a collector, a base and an emitter. The collector is disposed in the substrate. The base is disposed on the first side of the substrate. The emitter is disposed on the base. A top surface of a channel of the NMOS transistor, a top surface of a channel of the PMOS transistor and a top surface of the collector of the BJT have the same height. The first interconnect structure is electrically connected to the base at the first side of the substrate and extends to the second side of the substrate.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: August 17, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Purakh Raj Verma, Kuo-Yuh Yang
  • Patent number: 11088163
    Abstract: A semiconductor device includes a lower stack structure that includes a lower word line, an upper stack structure that is on the lower stack structure and includes an upper word line, a decoder that is adjacent to the lower stack structure and the upper stack structure, a signal interconnection that is connected to the decoder, a lower selector that is connected to the signal interconnection and further connected to the lower word line, and an upper selector that is connected to the signal interconnection, isolated from direct contact with the lower selector, and further connected to the upper word line.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: August 10, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kohji Kanamori, Yong Seok Kim, Kyung Hwan Lee, Jun Hee Lim, Jee Hoon Han
  • Patent number: 11056483
    Abstract: Apparatus and methods relating to heterolithic microwave integrated circuits HMICs are described. An HMIC can include different semiconductor devices formed from different semiconductor systems in different regions of a same substrate. An HMIC can also include bulk regions of low-loss electrically-insulating material extending through the substrate and located between the different semiconductor regions. Passive RF circuit elements can be formed on the low-loss electrically-insulating material.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: July 6, 2021
    Assignee: MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.
    Inventors: Timothy E. Boles, Wayne Mack Struble
  • Patent number: 11049955
    Abstract: One illustrative device disclosed herein includes a transistor formed above a semiconductor-on-insulator (SOI) substrate, wherein the transistor comprises a gate structure, a sidewall spacer and source/drain regions, openings formed in the active layer in the source/drain regions adjacent the sidewall spacer, recesses formed in a buried insulation layer of the SOI substrate in the source/drain regions of the transistor, wherein the recesses extend laterally under a portion of the active layer, and an epi semiconductor material positioned in at least the recesses in the buried insulation layer.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: June 29, 2021
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Shesh Mani Pandey, Jagar Singh, Judson R. Holt
  • Patent number: 11049870
    Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a memory cell array, first circuitry and a via. The semiconductor substrate includes a first main surface and a second main surface opposite the first main surface. The memory cell array is provided on the first main surface. The memory cell array includes stacked memory cells. The first circuitry is provided on the second main surface. The first circuitry is configured to operate the memory cells. The via penetrates through the semiconductor substrate. The via provides electrical connection between the memory cells and the first circuitry.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: June 29, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Tsuyoshi Sugisaki
  • Patent number: 11018327
    Abstract: This disclosure provides a mask module, a method for manufacturing a film layer, and a method for manufacturing an organic electromagnetic light-emitting display panel. The mask module is configured to manufacture a display substrate. The display substrate has at least one display area. The display area has at least one island pattern. The mask module includes at least two open type masks. Each of the open type masks has an opening area corresponding to at least one of the display areas. The opening areas of the open type masks corresponding to the same display area are not overlapped with each other, and the open type masks are stitched to constitute a joint and a blocking structure. The joint has a shape as same as that of the display area, and the blocking structure has a shape as same as that of the island pattern.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: May 25, 2021
    Assignees: BOE Technology Group Co., Ltd., Chengdu BOE Optoelectronics Technology Co., Ltd.
    Inventors: Li Wang, Ling Shi
  • Patent number: 11017999
    Abstract: A method of a forming semiconductor fin structures that includes forming a plurality of fin structures with a first etch to a first depth in a substrate. The plurality of fin structures have a first width to the first depth. A spacer is formed on sidewalls of the plurality of fin structures. A second etch step can then extend the plurality of fin structures to a second depth with a second etch. The plurality of fin structures have a second width greater than the first width at the second depth portion. At least a portion of the trench separating adjacent fin structures may then be filled with a dielectric formed by an oxidation process. The portion of the fin structures extending above the dielectric fill is the active region of the fin structures which has a uniform height for all of the fin structure in the plurality of fin structures.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: May 25, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Juntao Li, Xin Miao
  • Patent number: 10985196
    Abstract: Provided are a thin film transistor substrate and a display using the same. A thin film transistor substrate includes: a substrate, a first thin film transistor disposed on the substrate, the first thin film transistor including: a polycrystalline semiconductor layer, a first gate electrode on the polycrystalline semiconductor layer, a first source electrode, and a first drain electrode, a second thin film transistor disposed on the substrate, the second thin film transistor including: a second gate electrode, an oxide semiconductor layer on the second gate electrode, a second source electrode, and a second drain electrode, an intermediate insulating layer including a nitride layer and an oxide layer on the nitride layer, the intermediate insulating layer being disposed on the first gate electrode and the second gate electrode and under the oxide semiconductor layer, and an etch-stopper layer disposed on the oxide semiconductor layer.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: April 20, 2021
    Assignee: LG Display Co., Ltd.
    Inventors: Youngjang Lee, Kyungmo Son, Sohyung Lee, Hoyoung Jung, Moonho Park, Sungjin Lee
  • Patent number: 10985189
    Abstract: In the contact structure according to an exemplary aspect of the present disclosure and a display device including the same, the pixel may be designed regardless of the size of the contact hole by designing a size (or an area) of the contact hole to be larger than the contact area and applying different structures depending on the characteristics of the lower layer. Therefore, the size of the contact hole is increased so that the halftone mask may be easily applied and the number of masks may be advantageously reduced. Further, a degree of freedom of metal in the pixel design is increased so that the pixel may be designed in a high resolution model and the aperture ratio is increased without having the electrode margin.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: April 20, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: YounSub Kim, JongSik Shim, ByeongUk Gang, SeongHwan Hwang
  • Patent number: 10928570
    Abstract: An optical filter, a sensor device including the optical filter, and a method of fabricating the optical filter are provided. The optical filter includes one or more dielectric layers and one or more metal layers stacked in alternation. The metal layers are intrinsically protected by the dielectric layers. In particular, the metal layers have tapered edges that are protectively covered by one or more of the dielectric layers.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: February 23, 2021
    Assignee: VIAVI Solutions Inc.
    Inventors: Georg J. Ockenfuss, Tim Gustafson, Jeffrey James Kuna, Markus Bilger, Richard A. Bradley, Jr.
  • Patent number: 10930569
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device with fin structures having different top surface crystal orientations and/or different materials. The present disclosure provides a semiconductor structure including n-type FinFET devices and p-type FinFET devices with different top surface crystal orientations and with fin structures having different materials. The present disclosure provides a method to fabricate a semiconductor structure including n-type FinFET devices and p-type FinFET devices with different top surface crystal orientations and different materials to achieve optimized electron transport and hole transport. The present disclosure also provides a diode structure and a bipolar junction transistor structure that includes SiGe in the fin structures.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: February 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Chiang, Chih-Hao Wang, Ching-Wei Tsai, Kuan-Lun Cheng
  • Patent number: 10923580
    Abstract: The on-state characteristics of a transistor are improved and thus, a semiconductor device capable of high-speed response and high-speed operation is provided. A highly reliable semiconductor device showing stable electric characteristics is made. The semiconductor device includes a transistor including a first oxide layer; an oxide semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; a second oxide layer over the oxide semiconductor layer; a gate insulating layer over the second oxide layer; and a gate electrode layer over the gate insulating layer. An end portion of the second oxide layer and an end portion of the gate insulating layer overlap with the source electrode layer and the drain electrode layer.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: February 16, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Shinya Sasagawa, Motomu Kurata, Masashi Tsubuku
  • Patent number: 10916478
    Abstract: In a self-aligned fin cut process for fabricating integrated circuits, a sacrificial gate or an epitaxially-formed source/drain region is used as an etch mask in conjunction with a fin cut etch step to remove unwanted portions of the fins. The process eliminates use of a lithographically-defined etch mask to cut the fins, which enables precise and accurate alignment of the fin cut.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: February 9, 2021
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Lei L. Zhuang, Balasubramanian Pranatharthiharan, Lars Liebmann, Ruilong Xie, Terence Hook
  • Patent number: 10903336
    Abstract: A semiconductor device includes: first and second fin structures, disposed on a substrate, that respectively extend in parallel to an axis; a first gate feature that traverses the first fin structure to overlay a central portion of the first fin structure; a second gate feature that traverses the second fin structure to overlay a central portion of the second fin structure; a first spacer comprising: a first portion comprising two layers that respectively extend from sidewalls of the first gate feature toward opposite directions of the axis; and a second portion comprising two layers that respectively extend from sidewalls of the first portion of the first spacer toward the opposite directions of the axis; and a second spacer comprising two layers that respectively extend from sidewalls of the second gate feature toward the opposite directions of the axis.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: January 26, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: I-Chih Chen, Ru-Shang Hsiao, Ching-Pin Lin, Chih-Mu Huang, Fu-Tsun Tsai
  • Patent number: 10903330
    Abstract: The subject matter disclosed herein relates to metal-oxide-semiconductor (MOS) devices, such as silicon carbide (SiC) power devices (e.g., MOSFETs, IGBTs, etc.) In an embodiment, a semiconductor device includes a gate oxide layer disposed on top of a semiconductor layer. The semiconductor device also includes a gate electrode having a tapered sidewall. Further, the gate electrode includes a polysilicon layer disposed on top of the gate oxide layer and a metal silicide layer disposed on top of the polysilicon layer.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: January 26, 2021
    Assignee: General Electric Company
    Inventors: Richard Joseph Saia, Stephen Daley Arthur, Zachary Matthew Stum, Roger Raymond Kovalec, Gregory Keith Dudoff
  • Patent number: 10879241
    Abstract: Techniques are disclosed for controlling transistor sub-fin leakage. The techniques can be used for highly scaled finFETs, as well as other non-planar transistors. In some cases, the techniques include exposing a middle portion of a fin structure formed on a substrate and then converting the exposed portion to an electrically isolating material via a doping or oxidation process. For example, a monolayer doping (MLD) process may be used to deliver dopants to the exposed portion of the fin in a self-saturated monolayer scheme. In another example case, thermal oxidation may be used to convert the exposed portion to an insulator material. In some cases, a barrier layer (e.g., including carbon doping) may be located above the exposed portion of the fin to help prevent the doping or oxidation process from affecting the upper region of the fin, which is used for the transistor channel.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: December 29, 2020
    Assignee: INTEL Corporation
    Inventors: Glenn A. Glass, Prashant Majhi, Anand S. Murthy, Tahir Ghani, Daniel B. Aubertine, Heidi M. Meyer, Karthik Jambunathan, Gopinath Bhimarasetti
  • Patent number: 10847116
    Abstract: The liquid crystal display device includes a pixel portion including a plurality of pixels to which image signals are supplied; a driver circuit including a signal line driver circuit which selectively controls a signal line and a gate line driver circuit which selectively controls a gate line; a memory circuit which stores the image signals; a comparison circuit which compares the image signals stored in the memory circuit in the pixels and detects a difference; and a display control circuit which controls the driver circuit and reads the image signal in accordance with the difference. The display control circuit supplies the image signal only to the pixel where the difference is detected. The pixel includes a thin film transistor including a semiconductor layer including an oxide semiconductor.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: November 24, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Jun Koyama, Shunpei Yamazaki
  • Patent number: 10825931
    Abstract: A semiconductor device includes a semiconductor substrate, a dielectric layer, a gate structure, a source semiconductor feature, and a drain semiconductor feature. The semiconductor substrate has an active area and a shallow trench isolation (STI) structure surrounding the active area. The semiconductor substrate includes a protrusion structure in the active area and has an undercut at a periphery of the active area. The dielectric layer overlays the protrusion structure of the semiconductor substrate and fills at least a portion of the undercut of the protrusion structure. The gate structure crosses over the protrusion structure. The source semiconductor feature and the drain semiconductor feature are located in the active area and positioned at opposite sides of the gate structure.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: November 3, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ching-Chia Huang, Tseng-Fu Lu, Wei-Ming Liao
  • Patent number: 10811432
    Abstract: There is provided with the following semiconductor device to improve its reliability. In a SOI substrate including a semiconductor substrate, an insulating layer, and a semiconductor layer, a diffusion region is formed in the semiconductor layer and a plug electrically connected to the diffusion region is formed on the diffusion region. An element isolation portion is formed within the semiconductor substrate and a trench is formed in the element isolation portion. The lowest part of the bottom of the trench is lower than the surface of the semiconductor substrate and a sidewall spacer is formed in the side portion of the trench to cover the side surface of the insulating layer. As the result, even when the plug is formed in a deviated position, a disadvantage of conducting the semiconductor layer with the semiconductor substrate can be suppressed.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: October 20, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Nobuo Tsuboi
  • Patent number: 10811494
    Abstract: A power transistor assembly and method of mitigating short channel effects in a power transistor assembly are provided. The power transistor assembly includes a first layer of semiconductor material formed of a first conductivity type material and a hard mask layer covering at least a portion of the first layer and having a window therethrough exposing a surface of the first layer. The power transistor assembly also includes a first region formed in the first layer of semiconductor material of a second conductivity type material and aligned with the window, one or more source regions formed of first conductivity type material within the first region and separated by a portion of the first region, and an extension of the first region extending laterally through the surface of the first layer.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: October 20, 2020
    Assignee: Microsemi Corporation
    Inventors: Dumitru Gheorge Sdrulla, Avinash Srikrishnan Kashyap
  • Patent number: 10811556
    Abstract: A method for manufacturing a thermal sensor, the method may include forming, using ion etching, one or more first holes that pass through (a) an initial layer, (a) a first oxide layer, (c) a first semiconductor substrate; filling the one or more first holes with oxide to form supporting elements; fabricating one or more thermal semiconductor sensing elements; forming one or more second holes in the one or more upper layers and the first oxide layer; applying an isotropic etching process to remove the first semiconductor substrate and expose the supporting elements to provide a suspended first oxide layer.
    Type: Grant
    Filed: December 25, 2018
    Date of Patent: October 20, 2020
    Assignees: TODOS TECHNOLOGIES LTD., TECHNION RESEARCH AND DEVELOPEMENT FOUNDATION LTD.
    Inventors: Yael Nemirovsky, Amikam Nemirovsky
  • Patent number: 10802358
    Abstract: A display device includes a display panel, a panel driver, panel-side output terminals, image signal lines, and control signal lines. The terminals are disposed in a non-display area of the display device and connected to the panel driver. The image signal lines are routed in the non-display area from the terminals to cross a long edge of the panel driver and spread in a fan-like form toward the display area. The control signal lines including first lines and second lines are routed in the non-display area from the terminals toward a display area of the display device. The first lines are routed from the terminals to cross the long edge and along the image signal lines toward the display area. The second lines each including portions having a width larger than the first lines are routed from the terminals to cross a short edge of the panel driver.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: October 13, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Yohsuke Fujikawa
  • Patent number: 10767830
    Abstract: A device for a motor vehicle in order to transmit information to road users for safety is provided. The device includes a light source emitting a primary beam, a scattering element, at least one liquid-crystal display arranged between the light source and the scattering element, the at least one liquid crystal display being controlled in order to selectively transmit at least one portion of the primary beam toward the scattering element to form a secondary beam with at least two different distributions of light, and an image of the at least one liquid-crystal display being formed on the scattering element.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: September 8, 2020
    Assignee: VALEO VISION
    Inventor: Pierre Albou
  • Patent number: 10756146
    Abstract: In an embodiment, apparatus having a touch-sensitive screen, a touch-sensor controller and a flexible printed circuit. Conductive electrodes are substantially aligned with one or more gaps between pixels of the two-dimensional array. First conductive electrodes form vertices within the one or more gaps between pixels of the two-dimensional array such that the vertices do not obscure in plan view. The touch-sensor controller is configured to detect and process the change in capacitance at one or more touch-sensor nodes to determine the presence and location of a touch-sensor input. One or more tracks of conductive material is electrically connected to the flexible printed circuit.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: August 25, 2020
    Assignee: Neodrón Limited
    Inventors: David Brent Guard, Esat Yilmaz, Matthew Trend
  • Patent number: 10741139
    Abstract: A GOA circuit includes an output module in which a second TFT is arranged. The second TFT has a drain connected to a source of a first TFT, a gate receiving a first control signal, and a source receiving an Mth clock signal. The first control signal controls the second TFT to turn on and off. Alternatively, the drain of the second TFT is connected to the source of the first TFT, the gate receiving the Mth clock signal and the source connected to the first node to allow the second TFT to be conducted on only when the Mth clock signal is a high voltage and the first node is of a high voltage and is cut off at the remaining time. It is possible to prevent a voltage difference from being induced between the source and drain of the first TFT to reduce the electric current stress.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: August 11, 2020
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Guanghui Hong
  • Patent number: 10734541
    Abstract: A method of manufacturing the semiconductor device includes: (a) providing a substrate having a semiconductor layer; (b) forming a first insulating film over an insulating layer so as to cover the semiconductor layer; (c) forming an opening extending through the first insulating film and reaching the semiconductor layer; (d) forming, over the semiconductor layer exposed at a bottom surface of the opening, a semiconductor portion having a thickness smaller than that of the first insulating film over the semiconductor layer by a selective epitaxial growth method; (e) forming a second insulating film over the first insulating film and the semiconductor portion; (f) removing the second insulating film from over the first insulating film, while leaving the second insulating film in the opening; (g) removing a semiconductor particle formed over the first insulating film in the (d); and (h) forming a third insulating film over the first insulating film.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: August 4, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tatsuya Usami
  • Patent number: 10727319
    Abstract: Stress memorization techniques (SMTs) for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a capping layer over a fin structure; forming an amorphous region within the fin structure while the capping layer is disposed over the fin structure; and performing an annealing process to recrystallize the amorphous region. The capping layer enables the fin structure to retain stress effects induced by forming the amorphous region and/or performing the annealing process.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Wen-Cheng Lo, Sun-Jay Chang
  • Patent number: RE48965
    Abstract: A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: March 8, 2022
    Assignee: pSemi Corporation
    Inventors: Michael A. Stuber, Christopher N. Brindle, Dylan J. Kelly, Clint L. Kemerling, George P. Imthurn, Robert B. Welstand, Mark L. Burgener, Alexander Dribinsky, Tae Youn Kim