Abstract: A display panel and a display device are provided in the present disclosure. The display panel includes a first display region and a second display region which are adjacently arranged. A light transmittance of the first display region is greater than a light transmittance of the second display region. The display panel further includes a plurality of scan lines and a plurality of data lines extending along the second direction. One first sub-pixel row is electrically connected to at least two of the plurality of scan lines. The plurality of data lines includes first data lines, where one of the first data lines is electrically connected to the first sub-pixel column, and at least a part of the first data lines is made of a transparent conductive material. In the first display region, at least two of the first data lines are connected through a connection line.

Abstract: A display device and a mobile terminal device including the same are provided, wherein the display device includes a display panel including a display area in which a plurality of display pixels are disposed, and a sensing area in which a plurality of display pixels and a plurality of sensor pixels are disposed. The display pixels of the display area and the display pixels of the first sensing area emit light by receiving a data voltage of an input image in a display mode. The sensor pixels in the first sensing area generate an electric currents according to light reflected from a fingerprint in a fingerprint recognition mode. A resolution of the display pixel is lower than a resolution of the sensor pixel in the first sensing area.

Abstract: A display device includes a base layer; a first pattern disposed on the base layer; an insulating layer disposed on the first pattern and including layers; and a second pattern disposed on the insulating layer. At least two of the layers of the insulating layer include a same material.

Abstract: A method and apparatus are disclosed for use in improving gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit includes a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device including a gate electrode over a semiconductor substrate. An epitaxial source/drain layer is disposed on the semiconductor substrate and is laterally adjacent to the gate electrode. The epitaxial source/drain layer comprises a first dopant. A diffusion barrier layer is between the epitaxial source/drain layer and the semiconductor substrate. The diffusion barrier layer comprises a barrier dopant that is different from the first dopant.

Abstract: Structures for an extended-drain metal-oxide-semiconductor device and methods of forming a structure for an extended-drain metal-oxide-semiconductor device. The structure includes a semiconductor substrate containing a first semiconductor material, a source region and a drain region in the semiconductor substrate, a gate electrode positioned in a lateral direction between the source region and the drain region, and a semiconductor layer positioned on the semiconductor substrate. The semiconductor layer contains a second semiconductor material that differs in composition from the first semiconductor material. The gate electrode includes a first section positioned in a vertical direction over the semiconductor layer and a second section positioned in the vertical direction over the semiconductor substrate.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first transistor having a first conductivity type arranged over a substrate. The first transistor includes a first gate electrode layer having a first work function and extending from a first source/drain region to a second source/drain region, and a first channel structure embedded in the first gate electrode layer and extending from the first source/drain region to the second source/drain region. A second transistor having the first conductivity type is arranged laterally beside the first transistor. The second transistor includes a second gate electrode layer having a second work function that is different than the first work function and extending from a third source/drain region to a fourth source/drain region. A second channel structure is embedded in the second gate electrode layer and extends from the third source/drain region to the fourth source/drain region.

Abstract: A semiconductor structure includes: a substrate, a first conductive layer disposed on the substrate, a second conductive layer disposed on a surface of the first conductive layer away from the substrate, and third conductive layers covering side walls of the first conductive layer and in contact with the second conductive layer. Contact resistance between the third conductive layers and the second conductive layer is less than contact resistance between the first conductive layer and the second conductive layer.

Abstract: Electrostatic discharge (ESD) structures are provided. An ESD structure includes a semiconductor substrate, a first epitaxy region with a first type of conductivity over the semiconductor substrate, a second epitaxy region with a second type of conductivity over the semiconductor substrate, and a plurality of first semiconductor layers and a plurality of second semiconductor layers. The first and second semiconductor layers are alternatingly stacked over the semiconductor substrate and between the first and second epitaxy regions. A first conductive feature is formed over the first epitaxy region and outside an oxide diffusion region. A second conductive feature is formed over the second epitaxy region and outside the oxide diffusion region. The oxide diffusion region is disposed between the first and second conductive features.

Abstract: In a semiconductor device capable of product-sum operation, variations in transistor characteristics are reduced. The semiconductor device includes a first circuit including a driver unit, a correction unit, and a holding unit, and an inverter circuit. The first circuit has a function of generating an inverted signal of a signal input to an input terminal of the first circuit and outputting the inverted signal to an output terminal of the first circuit. The driver unit includes a p-channel first transistor and an n-channel second transistor having a back gate. The correction unit has a function of correcting the threshold voltage of one or both of the first transistor and the second transistor. The holding unit has a function of holding the potential of the back gate of the second transistor. The output terminal of the first circuit is electrically connected to an input terminal of the inverter circuit.

Abstract: Semiconductor-on-insulator (SOI) field effect transistors (FETs) including body regions having different thicknesses may be formed on an SOI substrate by selectively thinning a region of a top semiconductor layer while preventing thinning of an additional region of the top semiconductor layer. An oxidation process or an etch process may be used to thin the region of the top semiconductor layer, and a patterned oxidation barrier mask or an etch mask may be used to prevent oxidation or etching of the additional portion of the top semiconductor layer. Shallow trench isolation structures may be formed prior to, or after, the selective thinning processing steps. FETs having different depletion region configurations may be formed using the multiple thicknesses of the patterned portions of the top semiconductor layer. For example, partially depleted SOT FETs and fully depleted SOI FETs may be provided.

Abstract: Improving a reliability of a semiconductor device. A resistive element is comprised of a semiconductor layer of the SOI substrate and an epitaxial semiconductor layer formed on the semiconductor layer. The epitaxial semiconductor layer EP has two semiconductor portions formed on the semiconductor layer and spaced apart from each other. The semiconductor layer has a region on where one of the semiconductor portion is formed, a region on where another of the semiconductor portion is formed, and a region on where the epitaxial semiconductor layer is not formed.

Abstract: A resistor includes a substrate including an active region protruding from an upper surface of the substrate and extending in a first horizontal direction, a doped region extending in the first horizontal direction on the active region and comprising a semiconductor layer with n-type impurities, a plurality of channel layers spaced apart from each other in a vertical direction on the active region and connected to the doped region, a first gate electrode and a second gate electrode extending in the second horizontal direction intersecting the first horizontal direction and surrounding the plurality of channel layers, a first contact plug and a second contact plug in contact with an upper surface of the doped region. The first contact plug is adjacent to the first gate electrode. The second contact plug is adjacent to the second gate electrode.

Abstract: A technique relates to a semiconductor device. A source/drain layer is formed. Fins with gate stacks are formed in a fill material, a dummy fin template including at least one fin of the fins and at least one gate stack of the gate stacks, the fins being formed on the source/drain layer. A trench is formed through the fill material by removing the dummy fin template, such that a portion of the source/drain layer is exposed in the trench. A source/drain metal contact is formed on the portion of the source/drain layer in the trench.

Abstract: Single gate and dual gate FinFET devices suitable for use in an SRAM memory array have respective fins, source regions, and drain regions that are formed from portions of a single, contiguous layer on the semiconductor substrate, so that STI is unnecessary. Pairs of FinFETs can be configured as dependent-gate devices wherein adjacent channels are controlled by a common gate, or as independent-gate devices wherein one channel is controlled by two gates. Metal interconnects coupling a plurality of the FinFET devices are made of a same material as the gate electrodes. Such structural and material commonalities help to reduce costs of manufacturing high-density memory arrays.

Abstract: A wireless single-phase AC-to-AC conversion circuit based on a 2.4G microwave includes a receiving antenna unit, a RF switch unit, a positive voltage rectification unit, a negative voltage rectification unit and an AC synthesis unit. An output port of the receiving antenna unit is connected to the common input port of the RF switch unit. A first microwave output end of the RF switch unit and a second microwave output end of the RF switch unit are correspondingly connected to a microwave input end of the positive voltage rectification unit and a microwave input end of the negative voltage rectification unit, respectively. A DC output end of the positive voltage rectification unit and a DC output end of the negative voltage rectification unit are correspondingly connected to a positive voltage input port of the AC synthesis unit and a negative voltage input port of the AC synthesis unit, respectively.

Abstract: Provided are a charge trap evaluation method and semiconductor device including, in an embodiment, a step for applying an initialization voltage that has the same sign as a threshold voltage and is greater than or equal to the threshold voltage between the source electrode 15 and drain electrode 16 of a semiconductor device 1 having an HEMT structure and the substrate 10 of the semiconductor device 1 and initializing a trap state by forcing out trapped charge from a trap level and a step for monitoring the current flowing between the source electrode 15 and drain electrode 16 after the trap state initialization and evaluating at least one from among charge trapping, current collapse, and charge release.

Abstract: Semiconductor optical modulators are described that utilize bipolar junction transistor (BJT) structure within the optical modulator. The junctions within the BJT can be designed and biased to increase modulator efficiency and speed. An optical mode may be located in a selected region of the BJT structure to improve modulation efficiency. The BJT structure can be included in optical waveguides of interferometers and resonators to form optical modulators.

Abstract: In an embodiment, a method includes: performing a self-limiting process to modify a top surface of a wafer; after the self-limiting process completes, removing the modified top surface from the wafer; and repeating the performing the self-limiting process and the removing the modified top surface from the wafer until a thickness of the wafer is decreased to a predetermined thickness.

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment the semiconductor device comprises a first semiconductor layer, where first transistors are fabricated in the first semiconductor layer, and a back end stack over the first transistors. In an embodiment the back end stack comprises conductive traces and vias electrically coupled to the first transistors. In an embodiment, the semiconductor device further comprises a second semiconductor layer over the back end stack, where the second semiconductor layer is a different semiconductor than the first semiconductor layer. In an embodiment, second transistors are fabricated in the second semiconductor layer.

Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region in a gate space, one or more conductive layers are formed over the gate dielectric layer, a seed layer is formed over the one or more conductive layers, an upper portion of the seed layer is treated by introducing one or more elements selected from the group consisting of oxygen, nitrogen and fluorine, and a W layer is selectively formed on a lower portion of the seed layer that is not treated to fully fill the gate space with bottom-up filling approach.

Abstract: A semiconductor device includes a first active fin structure and a second active fin structure extending along a first lateral direction. The semiconductor device includes a dummy fin structure, also extending along the first lateral direction, that is disposed between the first active fin structure and the second fin structure. The dummy fin structure includes a material that is configured to induce mechanical deformation of a first source/drain structure coupled to an end of the first active fin structure and a second source/drain structure coupled to an end of the second active fin structure.

Abstract: A semiconductor structure that includes a metal layer in a first interlayer dielectric that is above a semiconductor device. The semiconductor structure includes an embedded memory device on the metal layer. The embedded memory device has a first metal contact surrounded by a second interlayer dielectric. Additionally, the semiconductor structure includes a thin film transistor on the first metal contact. The thin film transistor is surrounded by a third interlayer dielectric. The third interlayer dielectric is over a portion of the embedded memory device and a portion of the second interlayer dielectric. The semiconductor structure includes a first portion of a channel of the thin film transistor covered a gate structure, where the channel is a layer of indium tin oxide.

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including: a p-type substrate, a p-well region within the p-type substrate, and an n-type barrier region between the p-type substrate and the p-well region. The n-type barrier region physically isolates the p-type substrate from the p-well region. A field effect transistor (FET) is positioned above the p-well region, and a buried insulator layer on the upper surface of the p-well region separates the transistor from the p-well region. A first voltage source electrically coupled to the p-well region induces a P-N-P junction across the p-well region, the n-type barrier region, and the p-type substrate.

Abstract: A stacked device structure includes a first device structure including a first body that includes a semiconductor material, and a plurality of terminals coupled with the first body. The stacked device structure further includes an insulator between the first device structure and a second device structure. The second device structure includes a second body such as a fin structure directly above the insulator. The second device structure further includes a gate coupled to the fin structure, a spacer including a dielectric material adjacent to the gate, and an epitaxial structure adjacent to a sidewall of the fin structure and between the spacer and the insulator. A metallization structure is coupled to a sidewall surface of the epitaxial structure, and further coupled with one of the terminals of the first device.

Abstract: Included are: a semiconductor layer including a drain region, a channel region, and a second LDD region between the drain region and the channel region; a gate electrode disposed overlapping the channel region; a gate wiring line electrically coupled to the gate electrode; and a second light shielding portion disposed between the second LDD region and the gate wiring line and overlapping the second LDD region and the gate wiring line in plan view.

Abstract: A semiconductor device includes a substrate including a first region and a second region, memory transistors on the first region, a first interconnection layer on the memory transistors and including first interconnection lines, and a second interconnection layer on the first interconnection layer and including second interconnection lines. The second interconnection lines on the first region include a first line extending along a first direction and spaced from the second region by a first distance along the first direction, and a second line extending along the first direction, spaced from the first line along a second direction intersecting the first direction, and having a width smaller than that of the first line. The first line includes a protrusion extending along a third direction toward the substrate. The protrusion is spaced from the second region by a second distance along the first direction greater than the first distance.

Abstract: A method of fabricating a display substrate is provided. The method includes forming a conductive layer on a base substrate; and performing a chemical vapor deposition process to form an oxide layer on a side of an exposed surface of the conductive layer away from the base substrate, the exposed surface of the conductive layer including copper, the oxide layer formed to include an oxide of a target element M. The chemical vapor deposition process is performed using a mixture of a first reaction gas including oxygen and a second reaction gas including the target element M, at a reaction temperature in a range of 200 Celsius degrees to 280 Celsius degrees. A mole ratio of oxygen element to the target element M in the mixture of the first reaction gas and the second reaction gas is in a range of 40:1 to 60:1.

Abstract: Semiconductor structures with electrical isolation and methods of forming a semiconductor structure with electrical isolation. A shallow trench isolation region, which contains a dielectric material, is positioned in a semiconductor substrate. A trench extendes through the shallow trench isolation region and to a trench bottom in the semiconductor substrate beneath the shallow trench isolation region. A dielectric layer at least partially fills the trench. A polycrystalline region, which is arranged in the semiconductor substrate, includes a portion that is positioned beneath the trench bottom.

Abstract: In some embodiments, the present disclosure relates to an integrated chip including first, second, and third nanosheet field effect transistors (NSFETs) arranged over a substrate. The first NSFET has a first threshold voltage and includes first nanosheet channel structures embedded in a first gate electrode layer. The first nanosheet channel structures extend from a first source/drain region to a second source/drain region. The second NSFET has a second threshold voltage different than the first threshold voltage and includes second nanosheet channel structures embedded in a second gate electrode layer. The second nanosheet channel structures extend from a third source/drain region to a fourth source/drain region. The third NSFET has a third threshold voltage different than the second threshold voltage and includes third nanosheet channel structures embedded in a third gate electrode layer. The third nanosheet channel structures extend from a fifth source/drain region to a sixth source/drain region.

Abstract: A resistor includes a substrate including an active region protruding from an upper surface of the substrate and extending in a first horizontal direction, a doped region extending in the first horizontal direction on the active region and comprising a semiconductor layer with n-type impurities, a plurality of channel layers spaced apart from each other in a vertical direction on the active region and connected to the doped region, a first gate electrode and a second gate electrode extending in the second horizontal direction intersecting the first horizontal direction and surrounding the plurality of channel layers, a first contact plug and a second contact plug in contact with an upper surface of the doped region. The first contact plug is adjacent to the first gate electrode. The second contact plug is adjacent to the second gate electrode.

Abstract: A highly reliable semiconductor device is provided. The semiconductor device includes a first insulator; a first oxide provided over the first insulator; a second oxide provided over the first oxide; a first conductor and a second conductor provided apart from each other over the second oxide; a third oxide provided over the second oxide, the first conductor, and the second conductor; a second insulating film provided over the third oxide; and a third conductor provided over the second oxide with the third oxide and the second insulating film positioned therebetween. The third oxide contains a metal element and nitrogen, and the metal element is bonded to nitrogen.

Abstract: The present technology relates to an imaging device capable of preventing a decrease of sensitivity of the imaging device in a case where a capacitance element is provided in a pixel, a method of manufacturing an imaging device, and an electronic device. The imaging device includes, in a pixel, a photoelectric conversion element and a capacitance element accumulating an electric charge generated by the photoelectric conversion element. The capacitance element includes a first electrode including a plurality of trenches, a plurality of second electrodes each having a cross-sectional area smaller than a contact connected to a gate electrode of a transistor in the pixel, and buried in each of the trenches, and a first insulating film disposed between the first electrode and the second electrode in each of the trenches. The present technology can be applied, for example, to a backside irradiation-type CMOS image sensor.

Abstract: Embodiments include a first nanowire transistor having a first source and a first drain with a first channel in between, where the first channel includes a first III-V alloy. A first gate stack is around the first channel, where a portion of the first gate stack is between the first channel and a substrate. The first gate stack includes a gate electrode metal in contact with a gate dielectric. A second nanowire transistor is on the substrate, having a second source and a second drain with a second channel therebetween, the second channel including a second III-V alloy. A second gate stack is around the second channel, where an intervening material is between the second gate stack and the substrate, the intervening material including a third III-V alloy. The second gate stack includes the gate electrode metal in contact with the gate dielectric.

Abstract: A semiconductor structure including a substrate, a complementary metal oxide semiconductor (CMOS) device, a bipolar junction transistor (BJT), and a first protection layer is provided. The CMOS device includes an N-type metal oxide semiconductor (NMOS) transistor and a P-type metal oxide semiconductor (PMOS) transistor disposed on the substrate. The BJT includes a collector, a base and an emitter. The collector is disposed in the substrate. The base is disposed on the substrate. The emitter is disposed on the base. A top surface of a channel of the NMOS transistor, a top surface of a channel of the PMOS transistor and a top surface of the collector of the BJT have the same height. The first protection layer is disposed on the substrate and exposes the substrate. The base is disposed on the substrate exposed by the first protection layer. The semiconductor structure can have better overall performance.

Abstract: A semiconductor structure including a substrate, a CMOS device and a BJT is provided. The substrate has a first side and a second side opposite to each other. The CMOS device includes an NMOS transistor and a PMOS transistor. The NMOS transistor includes a first N-type doped region and a second N-type doped region disposed in the substrate. The PMOS transistor includes a first P-type doped region and a second P-type doped region disposed in the substrate. The BJT includes a collector, a base and an emitter. The base is disposed on the first side of the substrate. The emitter is disposed on the base. A first metal silicide layer, a second metal silicide layer, and a third metal silicide layer are respectively located on the second side of the substrate and respectively disposed on the collector, the first N-type doped region, and the first P-type doped region.

Abstract: A method of fabrication of a ferroelectric memory including a first electrode, a second electrode and a layer of active material made of hafnium dioxide HfO2 positioned between the first electrode and the second electrode, where the method includes depositing a first electrode layer; depositing the layer of active material; doping the layer of active material; depositing a second electrode layer; wherein the method includes sub-microsecond laser annealing of the layer of doped active material.

Abstract: A vertical field effect transistor (FET) includes a vertical semiconductor channel having a first end that contacts an upper surface of a substrate and an opposing second end that contacts a source/drain region. An electrically conductive gate encapsulates the vertical semiconductor channel. The vertical FET further includes a split-channel antifuse device between the source/drain region and the electrically conductive gate. The split-channel antifuse device includes a gate dielectric having a thickness that varies between the source/drain region and the electrically conductive gate.

Abstract: A limiter having a more ideal limiting function, a short response time, and an adjustable limiting threshold. In one embodiment, a self-activating limiter stack is coupled between circuit ground and a signal line between a source and a receiver. The limiter stack limits the power from the source when the voltage on the signal line exceeds the breakdown voltage of the limiter stack. The threshold of the limiter stack is controlled in part by a first control voltage applied to a control input. A rectifying power detector circuit connected between a node on the signal line and the control input of the limiter stack provides a second control voltage as a function of the signal power at the node. The combined first and second control voltages are applied to the control input to modulate the ON resistance of the limiter stack, thereby limiting the leakage power reaching the protected receiver.

Abstract: According to an aspect, an array substrate includes: a substrate; a light-shielding layer; a first gate electrode; a semiconductor layer; a signal line; and an electrode. A first surface of the substrate is provided with, in sequence, the light-shielding layer, the first gate electrode, the semiconductor layer, the signal line, and the electrode. The semiconductor layer includes a first impurity region electrically coupled to the electrode, a first channel region overlapping the first gate electrode, a second impurity region opposite to the first impurity region with respect to the first channel region, and a first lightly doped drain region between the first impurity region and the first channel region. The light-shielding layer has a first end and a second end opposite to each other. The first end overlaps the first channel region. The light-shielding layer overlaps a boundary between the first channel region and the first lightly doped drain region.

Abstract: One or more gated nanosheet diodes are disposed on a substrate and made from a nanosheet structure. A first (second) source/drain (S/D) is disposed on the substrate. The first (second) S/D has a first (second) S/D doping concentration with a first (second) S/D doping type. One or more p-n junctions form one or more respective diodes. There is a first side and a second side of each of the p-n junctions. The first (second) sides of the p-n junctions electrically and physically connect to the first (second) S/Ds and have the same type of doping, respectively. A gate stack, made of a gate dielectric layer and a gate metal, interfaces and surrounds each of the p-n junctions.

Abstract: A display device and a method for manufacturing a display device, the device including a semiconductor layer on a substrate; a gate insulation layer and an interlayer insulation layer that overlap the semiconductor layer; contact holes that penetrate the gate insulation layer and the interlayer insulation layer; a source electrode and a drain electrode that are electrically connected with the semiconductor layer through the contact holes; a light emitting diode that is connected with the drain electrode; and first spacers and second spacers between the source electrode and the interlayer insulation layer and between the drain electrode and the interlayer insulation layer in the contact holes.

Abstract: A semiconductor structure including a substrate, a complementary metal oxide semiconductor (CMOS) device, a bipolar junction transistor (BJT), and a first interconnect structure is provided. The substrate has a first side and a second side opposite to each other. The CMOS device includes an NMOS transistor and a PMOS transistor disposed on the substrate. The BJT includes a collector, a base and an emitter. The collector is disposed in the substrate. The base is disposed on the first side of the substrate. The emitter is disposed on the base. A top surface of a channel of the NMOS transistor, a top surface of a channel of the PMOS transistor and a top surface of the collector of the BJT have the same height. The first interconnect structure is electrically connected to the base at the first side of the substrate and extends to the second side of the substrate.

Abstract: A semiconductor device includes a lower stack structure that includes a lower word line, an upper stack structure that is on the lower stack structure and includes an upper word line, a decoder that is adjacent to the lower stack structure and the upper stack structure, a signal interconnection that is connected to the decoder, a lower selector that is connected to the signal interconnection and further connected to the lower word line, and an upper selector that is connected to the signal interconnection, isolated from direct contact with the lower selector, and further connected to the upper word line.

Abstract: Apparatus and methods relating to heterolithic microwave integrated circuits HMICs are described. An HMIC can include different semiconductor devices formed from different semiconductor systems in different regions of a same substrate. An HMIC can also include bulk regions of low-loss electrically-insulating material extending through the substrate and located between the different semiconductor regions. Passive RF circuit elements can be formed on the low-loss electrically-insulating material.

Abstract: One illustrative device disclosed herein includes a transistor formed above a semiconductor-on-insulator (SOI) substrate, wherein the transistor comprises a gate structure, a sidewall spacer and source/drain regions, openings formed in the active layer in the source/drain regions adjacent the sidewall spacer, recesses formed in a buried insulation layer of the SOI substrate in the source/drain regions of the transistor, wherein the recesses extend laterally under a portion of the active layer, and an epi semiconductor material positioned in at least the recesses in the buried insulation layer.

Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a memory cell array, first circuitry and a via. The semiconductor substrate includes a first main surface and a second main surface opposite the first main surface. The memory cell array is provided on the first main surface. The memory cell array includes stacked memory cells. The first circuitry is provided on the second main surface. The first circuitry is configured to operate the memory cells. The via penetrates through the semiconductor substrate. The via provides electrical connection between the memory cells and the first circuitry.

Abstract: A method of a forming semiconductor fin structures that includes forming a plurality of fin structures with a first etch to a first depth in a substrate. The plurality of fin structures have a first width to the first depth. A spacer is formed on sidewalls of the plurality of fin structures. A second etch step can then extend the plurality of fin structures to a second depth with a second etch. The plurality of fin structures have a second width greater than the first width at the second depth portion. At least a portion of the trench separating adjacent fin structures may then be filled with a dielectric formed by an oxidation process. The portion of the fin structures extending above the dielectric fill is the active region of the fin structures which has a uniform height for all of the fin structure in the plurality of fin structures.

Abstract: This disclosure provides a mask module, a method for manufacturing a film layer, and a method for manufacturing an organic electromagnetic light-emitting display panel. The mask module is configured to manufacture a display substrate. The display substrate has at least one display area. The display area has at least one island pattern. The mask module includes at least two open type masks. Each of the open type masks has an opening area corresponding to at least one of the display areas. The opening areas of the open type masks corresponding to the same display area are not overlapped with each other, and the open type masks are stitched to constitute a joint and a blocking structure. The joint has a shape as same as that of the display area, and the blocking structure has a shape as same as that of the island pattern.

Abstract: A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET.