Insulated Electrode Device Is Combined With Diverse Type Device (e.g., Complementary Mosfets, Fet With Resistor, Etc.) Patents (Class 257/350)
  • Patent number: 11126052
    Abstract: According to an aspect, an array substrate includes: a substrate; a light-shielding layer; a first gate electrode; a semiconductor layer; a signal line; and an electrode. A first surface of the substrate is provided with, in sequence, the light-shielding layer, the first gate electrode, the semiconductor layer, the signal line, and the electrode. The semiconductor layer includes a first impurity region electrically coupled to the electrode, a first channel region overlapping the first gate electrode, a second impurity region opposite to the first impurity region with respect to the first channel region, and a first lightly doped drain region between the first impurity region and the first channel region. The light-shielding layer has a first end and a second end opposite to each other. The first end overlaps the first channel region. The light-shielding layer overlaps a boundary between the first channel region and the first lightly doped drain region.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: September 21, 2021
    Assignee: Japan Display Inc.
    Inventors: Yoshitaka Ozeki, Gen Koide, Nobutaka Ozaki
  • Patent number: 11101336
    Abstract: A display device and a method for manufacturing a display device, the device including a semiconductor layer on a substrate; a gate insulation layer and an interlayer insulation layer that overlap the semiconductor layer; contact holes that penetrate the gate insulation layer and the interlayer insulation layer; a source electrode and a drain electrode that are electrically connected with the semiconductor layer through the contact holes; a light emitting diode that is connected with the drain electrode; and first spacers and second spacers between the source electrode and the interlayer insulation layer and between the drain electrode and the interlayer insulation layer in the contact holes.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: August 24, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Yu-Gwang Jeong, Su Bin Bae, Joon Geol Lee, Sang Gab Kim, Shin Il Choi
  • Patent number: 11101374
    Abstract: One or more gated nanosheet diodes are disposed on a substrate and made from a nanosheet structure. A first (second) source/drain (S/D) is disposed on the substrate. The first (second) S/D has a first (second) S/D doping concentration with a first (second) S/D doping type. One or more p-n junctions form one or more respective diodes. There is a first side and a second side of each of the p-n junctions. The first (second) sides of the p-n junctions electrically and physically connect to the first (second) S/Ds and have the same type of doping, respectively. A gate stack, made of a gate dielectric layer and a gate metal, interfaces and surrounds each of the p-n junctions.
    Type: Grant
    Filed: June 13, 2020
    Date of Patent: August 24, 2021
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Bahman Hekmatshoartabari, Karthik Balakrishnan
  • Patent number: 11094599
    Abstract: A semiconductor structure including a substrate, a complementary metal oxide semiconductor (CMOS) device, a bipolar junction transistor (BJT), and a first interconnect structure is provided. The substrate has a first side and a second side opposite to each other. The CMOS device includes an NMOS transistor and a PMOS transistor disposed on the substrate. The BJT includes a collector, a base and an emitter. The collector is disposed in the substrate. The base is disposed on the first side of the substrate. The emitter is disposed on the base. A top surface of a channel of the NMOS transistor, a top surface of a channel of the PMOS transistor and a top surface of the collector of the BJT have the same height. The first interconnect structure is electrically connected to the base at the first side of the substrate and extends to the second side of the substrate.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: August 17, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Purakh Raj Verma, Kuo-Yuh Yang
  • Patent number: 11088163
    Abstract: A semiconductor device includes a lower stack structure that includes a lower word line, an upper stack structure that is on the lower stack structure and includes an upper word line, a decoder that is adjacent to the lower stack structure and the upper stack structure, a signal interconnection that is connected to the decoder, a lower selector that is connected to the signal interconnection and further connected to the lower word line, and an upper selector that is connected to the signal interconnection, isolated from direct contact with the lower selector, and further connected to the upper word line.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: August 10, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kohji Kanamori, Yong Seok Kim, Kyung Hwan Lee, Jun Hee Lim, Jee Hoon Han
  • Patent number: 11056483
    Abstract: Apparatus and methods relating to heterolithic microwave integrated circuits HMICs are described. An HMIC can include different semiconductor devices formed from different semiconductor systems in different regions of a same substrate. An HMIC can also include bulk regions of low-loss electrically-insulating material extending through the substrate and located between the different semiconductor regions. Passive RF circuit elements can be formed on the low-loss electrically-insulating material.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: July 6, 2021
    Assignee: MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.
    Inventors: Timothy E. Boles, Wayne Mack Struble
  • Patent number: 11049955
    Abstract: One illustrative device disclosed herein includes a transistor formed above a semiconductor-on-insulator (SOI) substrate, wherein the transistor comprises a gate structure, a sidewall spacer and source/drain regions, openings formed in the active layer in the source/drain regions adjacent the sidewall spacer, recesses formed in a buried insulation layer of the SOI substrate in the source/drain regions of the transistor, wherein the recesses extend laterally under a portion of the active layer, and an epi semiconductor material positioned in at least the recesses in the buried insulation layer.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: June 29, 2021
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Shesh Mani Pandey, Jagar Singh, Judson R. Holt
  • Patent number: 11049870
    Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a memory cell array, first circuitry and a via. The semiconductor substrate includes a first main surface and a second main surface opposite the first main surface. The memory cell array is provided on the first main surface. The memory cell array includes stacked memory cells. The first circuitry is provided on the second main surface. The first circuitry is configured to operate the memory cells. The via penetrates through the semiconductor substrate. The via provides electrical connection between the memory cells and the first circuitry.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: June 29, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Tsuyoshi Sugisaki
  • Patent number: 11018327
    Abstract: This disclosure provides a mask module, a method for manufacturing a film layer, and a method for manufacturing an organic electromagnetic light-emitting display panel. The mask module is configured to manufacture a display substrate. The display substrate has at least one display area. The display area has at least one island pattern. The mask module includes at least two open type masks. Each of the open type masks has an opening area corresponding to at least one of the display areas. The opening areas of the open type masks corresponding to the same display area are not overlapped with each other, and the open type masks are stitched to constitute a joint and a blocking structure. The joint has a shape as same as that of the display area, and the blocking structure has a shape as same as that of the island pattern.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: May 25, 2021
    Assignees: BOE Technology Group Co., Ltd., Chengdu BOE Optoelectronics Technology Co., Ltd.
    Inventors: Li Wang, Ling Shi
  • Patent number: 11017999
    Abstract: A method of a forming semiconductor fin structures that includes forming a plurality of fin structures with a first etch to a first depth in a substrate. The plurality of fin structures have a first width to the first depth. A spacer is formed on sidewalls of the plurality of fin structures. A second etch step can then extend the plurality of fin structures to a second depth with a second etch. The plurality of fin structures have a second width greater than the first width at the second depth portion. At least a portion of the trench separating adjacent fin structures may then be filled with a dielectric formed by an oxidation process. The portion of the fin structures extending above the dielectric fill is the active region of the fin structures which has a uniform height for all of the fin structure in the plurality of fin structures.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: May 25, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Juntao Li, Xin Miao
  • Patent number: 10985189
    Abstract: In the contact structure according to an exemplary aspect of the present disclosure and a display device including the same, the pixel may be designed regardless of the size of the contact hole by designing a size (or an area) of the contact hole to be larger than the contact area and applying different structures depending on the characteristics of the lower layer. Therefore, the size of the contact hole is increased so that the halftone mask may be easily applied and the number of masks may be advantageously reduced. Further, a degree of freedom of metal in the pixel design is increased so that the pixel may be designed in a high resolution model and the aperture ratio is increased without having the electrode margin.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: April 20, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: YounSub Kim, JongSik Shim, ByeongUk Gang, SeongHwan Hwang
  • Patent number: 10985196
    Abstract: Provided are a thin film transistor substrate and a display using the same. A thin film transistor substrate includes: a substrate, a first thin film transistor disposed on the substrate, the first thin film transistor including: a polycrystalline semiconductor layer, a first gate electrode on the polycrystalline semiconductor layer, a first source electrode, and a first drain electrode, a second thin film transistor disposed on the substrate, the second thin film transistor including: a second gate electrode, an oxide semiconductor layer on the second gate electrode, a second source electrode, and a second drain electrode, an intermediate insulating layer including a nitride layer and an oxide layer on the nitride layer, the intermediate insulating layer being disposed on the first gate electrode and the second gate electrode and under the oxide semiconductor layer, and an etch-stopper layer disposed on the oxide semiconductor layer.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: April 20, 2021
    Assignee: LG Display Co., Ltd.
    Inventors: Youngjang Lee, Kyungmo Son, Sohyung Lee, Hoyoung Jung, Moonho Park, Sungjin Lee
  • Patent number: 10928570
    Abstract: An optical filter, a sensor device including the optical filter, and a method of fabricating the optical filter are provided. The optical filter includes one or more dielectric layers and one or more metal layers stacked in alternation. The metal layers are intrinsically protected by the dielectric layers. In particular, the metal layers have tapered edges that are protectively covered by one or more of the dielectric layers.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: February 23, 2021
    Assignee: VIAVI Solutions Inc.
    Inventors: Georg J. Ockenfuss, Tim Gustafson, Jeffrey James Kuna, Markus Bilger, Richard A. Bradley, Jr.
  • Patent number: 10930569
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device with fin structures having different top surface crystal orientations and/or different materials. The present disclosure provides a semiconductor structure including n-type FinFET devices and p-type FinFET devices with different top surface crystal orientations and with fin structures having different materials. The present disclosure provides a method to fabricate a semiconductor structure including n-type FinFET devices and p-type FinFET devices with different top surface crystal orientations and different materials to achieve optimized electron transport and hole transport. The present disclosure also provides a diode structure and a bipolar junction transistor structure that includes SiGe in the fin structures.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: February 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Chiang, Chih-Hao Wang, Ching-Wei Tsai, Kuan-Lun Cheng
  • Patent number: 10923580
    Abstract: The on-state characteristics of a transistor are improved and thus, a semiconductor device capable of high-speed response and high-speed operation is provided. A highly reliable semiconductor device showing stable electric characteristics is made. The semiconductor device includes a transistor including a first oxide layer; an oxide semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; a second oxide layer over the oxide semiconductor layer; a gate insulating layer over the second oxide layer; and a gate electrode layer over the gate insulating layer. An end portion of the second oxide layer and an end portion of the gate insulating layer overlap with the source electrode layer and the drain electrode layer.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: February 16, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Shinya Sasagawa, Motomu Kurata, Masashi Tsubuku
  • Patent number: 10916478
    Abstract: In a self-aligned fin cut process for fabricating integrated circuits, a sacrificial gate or an epitaxially-formed source/drain region is used as an etch mask in conjunction with a fin cut etch step to remove unwanted portions of the fins. The process eliminates use of a lithographically-defined etch mask to cut the fins, which enables precise and accurate alignment of the fin cut.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: February 9, 2021
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Lei L. Zhuang, Balasubramanian Pranatharthiharan, Lars Liebmann, Ruilong Xie, Terence Hook
  • Patent number: 10903336
    Abstract: A semiconductor device includes: first and second fin structures, disposed on a substrate, that respectively extend in parallel to an axis; a first gate feature that traverses the first fin structure to overlay a central portion of the first fin structure; a second gate feature that traverses the second fin structure to overlay a central portion of the second fin structure; a first spacer comprising: a first portion comprising two layers that respectively extend from sidewalls of the first gate feature toward opposite directions of the axis; and a second portion comprising two layers that respectively extend from sidewalls of the first portion of the first spacer toward the opposite directions of the axis; and a second spacer comprising two layers that respectively extend from sidewalls of the second gate feature toward the opposite directions of the axis.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: January 26, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: I-Chih Chen, Ru-Shang Hsiao, Ching-Pin Lin, Chih-Mu Huang, Fu-Tsun Tsai
  • Patent number: 10903330
    Abstract: The subject matter disclosed herein relates to metal-oxide-semiconductor (MOS) devices, such as silicon carbide (SiC) power devices (e.g., MOSFETs, IGBTs, etc.) In an embodiment, a semiconductor device includes a gate oxide layer disposed on top of a semiconductor layer. The semiconductor device also includes a gate electrode having a tapered sidewall. Further, the gate electrode includes a polysilicon layer disposed on top of the gate oxide layer and a metal silicide layer disposed on top of the polysilicon layer.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: January 26, 2021
    Assignee: General Electric Company
    Inventors: Richard Joseph Saia, Stephen Daley Arthur, Zachary Matthew Stum, Roger Raymond Kovalec, Gregory Keith Dudoff
  • Patent number: 10879241
    Abstract: Techniques are disclosed for controlling transistor sub-fin leakage. The techniques can be used for highly scaled finFETs, as well as other non-planar transistors. In some cases, the techniques include exposing a middle portion of a fin structure formed on a substrate and then converting the exposed portion to an electrically isolating material via a doping or oxidation process. For example, a monolayer doping (MLD) process may be used to deliver dopants to the exposed portion of the fin in a self-saturated monolayer scheme. In another example case, thermal oxidation may be used to convert the exposed portion to an insulator material. In some cases, a barrier layer (e.g., including carbon doping) may be located above the exposed portion of the fin to help prevent the doping or oxidation process from affecting the upper region of the fin, which is used for the transistor channel.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: December 29, 2020
    Assignee: INTEL Corporation
    Inventors: Glenn A. Glass, Prashant Majhi, Anand S. Murthy, Tahir Ghani, Daniel B. Aubertine, Heidi M. Meyer, Karthik Jambunathan, Gopinath Bhimarasetti
  • Patent number: 10847116
    Abstract: The liquid crystal display device includes a pixel portion including a plurality of pixels to which image signals are supplied; a driver circuit including a signal line driver circuit which selectively controls a signal line and a gate line driver circuit which selectively controls a gate line; a memory circuit which stores the image signals; a comparison circuit which compares the image signals stored in the memory circuit in the pixels and detects a difference; and a display control circuit which controls the driver circuit and reads the image signal in accordance with the difference. The display control circuit supplies the image signal only to the pixel where the difference is detected. The pixel includes a thin film transistor including a semiconductor layer including an oxide semiconductor.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: November 24, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Jun Koyama, Shunpei Yamazaki
  • Patent number: 10825931
    Abstract: A semiconductor device includes a semiconductor substrate, a dielectric layer, a gate structure, a source semiconductor feature, and a drain semiconductor feature. The semiconductor substrate has an active area and a shallow trench isolation (STI) structure surrounding the active area. The semiconductor substrate includes a protrusion structure in the active area and has an undercut at a periphery of the active area. The dielectric layer overlays the protrusion structure of the semiconductor substrate and fills at least a portion of the undercut of the protrusion structure. The gate structure crosses over the protrusion structure. The source semiconductor feature and the drain semiconductor feature are located in the active area and positioned at opposite sides of the gate structure.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: November 3, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ching-Chia Huang, Tseng-Fu Lu, Wei-Ming Liao
  • Patent number: 10811556
    Abstract: A method for manufacturing a thermal sensor, the method may include forming, using ion etching, one or more first holes that pass through (a) an initial layer, (a) a first oxide layer, (c) a first semiconductor substrate; filling the one or more first holes with oxide to form supporting elements; fabricating one or more thermal semiconductor sensing elements; forming one or more second holes in the one or more upper layers and the first oxide layer; applying an isotropic etching process to remove the first semiconductor substrate and expose the supporting elements to provide a suspended first oxide layer.
    Type: Grant
    Filed: December 25, 2018
    Date of Patent: October 20, 2020
    Assignees: TODOS TECHNOLOGIES LTD., TECHNION RESEARCH AND DEVELOPEMENT FOUNDATION LTD.
    Inventors: Yael Nemirovsky, Amikam Nemirovsky
  • Patent number: 10811432
    Abstract: There is provided with the following semiconductor device to improve its reliability. In a SOI substrate including a semiconductor substrate, an insulating layer, and a semiconductor layer, a diffusion region is formed in the semiconductor layer and a plug electrically connected to the diffusion region is formed on the diffusion region. An element isolation portion is formed within the semiconductor substrate and a trench is formed in the element isolation portion. The lowest part of the bottom of the trench is lower than the surface of the semiconductor substrate and a sidewall spacer is formed in the side portion of the trench to cover the side surface of the insulating layer. As the result, even when the plug is formed in a deviated position, a disadvantage of conducting the semiconductor layer with the semiconductor substrate can be suppressed.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: October 20, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Nobuo Tsuboi
  • Patent number: 10811494
    Abstract: A power transistor assembly and method of mitigating short channel effects in a power transistor assembly are provided. The power transistor assembly includes a first layer of semiconductor material formed of a first conductivity type material and a hard mask layer covering at least a portion of the first layer and having a window therethrough exposing a surface of the first layer. The power transistor assembly also includes a first region formed in the first layer of semiconductor material of a second conductivity type material and aligned with the window, one or more source regions formed of first conductivity type material within the first region and separated by a portion of the first region, and an extension of the first region extending laterally through the surface of the first layer.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: October 20, 2020
    Assignee: Microsemi Corporation
    Inventors: Dumitru Gheorge Sdrulla, Avinash Srikrishnan Kashyap
  • Patent number: 10802358
    Abstract: A display device includes a display panel, a panel driver, panel-side output terminals, image signal lines, and control signal lines. The terminals are disposed in a non-display area of the display device and connected to the panel driver. The image signal lines are routed in the non-display area from the terminals to cross a long edge of the panel driver and spread in a fan-like form toward the display area. The control signal lines including first lines and second lines are routed in the non-display area from the terminals toward a display area of the display device. The first lines are routed from the terminals to cross the long edge and along the image signal lines toward the display area. The second lines each including portions having a width larger than the first lines are routed from the terminals to cross a short edge of the panel driver.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: October 13, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Yohsuke Fujikawa
  • Patent number: 10767830
    Abstract: A device for a motor vehicle in order to transmit information to road users for safety is provided. The device includes a light source emitting a primary beam, a scattering element, at least one liquid-crystal display arranged between the light source and the scattering element, the at least one liquid crystal display being controlled in order to selectively transmit at least one portion of the primary beam toward the scattering element to form a secondary beam with at least two different distributions of light, and an image of the at least one liquid-crystal display being formed on the scattering element.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: September 8, 2020
    Assignee: VALEO VISION
    Inventor: Pierre Albou
  • Patent number: 10756146
    Abstract: In an embodiment, apparatus having a touch-sensitive screen, a touch-sensor controller and a flexible printed circuit. Conductive electrodes are substantially aligned with one or more gaps between pixels of the two-dimensional array. First conductive electrodes form vertices within the one or more gaps between pixels of the two-dimensional array such that the vertices do not obscure in plan view. The touch-sensor controller is configured to detect and process the change in capacitance at one or more touch-sensor nodes to determine the presence and location of a touch-sensor input. One or more tracks of conductive material is electrically connected to the flexible printed circuit.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: August 25, 2020
    Assignee: NeodrĂ³n Limited
    Inventors: David Brent Guard, Esat Yilmaz, Matthew Trend
  • Patent number: 10741139
    Abstract: A GOA circuit includes an output module in which a second TFT is arranged. The second TFT has a drain connected to a source of a first TFT, a gate receiving a first control signal, and a source receiving an Mth clock signal. The first control signal controls the second TFT to turn on and off. Alternatively, the drain of the second TFT is connected to the source of the first TFT, the gate receiving the Mth clock signal and the source connected to the first node to allow the second TFT to be conducted on only when the Mth clock signal is a high voltage and the first node is of a high voltage and is cut off at the remaining time. It is possible to prevent a voltage difference from being induced between the source and drain of the first TFT to reduce the electric current stress.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: August 11, 2020
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Guanghui Hong
  • Patent number: 10734541
    Abstract: A method of manufacturing the semiconductor device includes: (a) providing a substrate having a semiconductor layer; (b) forming a first insulating film over an insulating layer so as to cover the semiconductor layer; (c) forming an opening extending through the first insulating film and reaching the semiconductor layer; (d) forming, over the semiconductor layer exposed at a bottom surface of the opening, a semiconductor portion having a thickness smaller than that of the first insulating film over the semiconductor layer by a selective epitaxial growth method; (e) forming a second insulating film over the first insulating film and the semiconductor portion; (f) removing the second insulating film from over the first insulating film, while leaving the second insulating film in the opening; (g) removing a semiconductor particle formed over the first insulating film in the (d); and (h) forming a third insulating film over the first insulating film.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: August 4, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tatsuya Usami
  • Patent number: 10727319
    Abstract: Stress memorization techniques (SMTs) for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a capping layer over a fin structure; forming an amorphous region within the fin structure while the capping layer is disposed over the fin structure; and performing an annealing process to recrystallize the amorphous region. The capping layer enables the fin structure to retain stress effects induced by forming the amorphous region and/or performing the annealing process.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Wen-Cheng Lo, Sun-Jay Chang
  • Patent number: 10714501
    Abstract: An electronic integrated circuit chip includes a first transistor arranged inside and on top of a solid substrate, a second transistor arranged inside and on top of a layer of semiconductor material on insulator having a first thickness, and a third transistor arranged inside and on top of a layer of semiconductor material on insulator having a second thickness. The second thickness is greater than the first thickness. The solid substrate extends underneath the layers of semiconductor material and is insulated from those layers by the insulator.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: July 14, 2020
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SAS
    Inventors: Jean-Jacques Fagot, Philippe Boivin, Franck Arnaud
  • Patent number: 10700210
    Abstract: A semiconductor device includes a substrate and a thin film transistor supported by the substrate. The thin film transistor includes a gate electrode, an oxide semiconductor layer, a gate insulating layer provided between the gate electrode and the oxide semiconductor layer, and source and drain electrodes electrically connected to the oxide semiconductor layer. The gate insulating layer includes a first portion which is covered with the oxide semiconductor layer and a second portion which is adjacent to the first portion and which is not covered with any of the oxide semiconductor layer, the source electrode and the drain electrode. The second portion is smaller in thickness than the first portion, and the difference in thickness between the second portion and the first portion is more than 0 nm and not more than 50 nm.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: June 30, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tetsuo Kikuchi, Hajime Imai, Hisao Ochi, Tetsuo Fujita, Hideki Kitagawa, Masahiko Suzuki, Shingo Kawashima, Tohru Daitoh
  • Patent number: 10684512
    Abstract: A cell forming device, including a first platform configured to carry a first substrate, a second platform configured to carry a second substrate, and a pre-alignment mechanism. The first platform includes a first suction surface and a second suction surface arranged opposite to each other and configured to attach the first substrate. The pre-alignment mechanism is configured to adjust a position of the first platform to pre-align the first substrate with the second substrate. The cell forming device further includes a turn-over mechanism configured to turn the first platform over to turn the first substrate over, an alignment mechanism configured to adjust a position of the second platform to align the turned first substrate with the second substrate, and a cell forming mechanism configured to move the first substrate to form a cell with the second substrate.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: June 16, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Yangkun Jing, Jian Sun, Junwei Xia, Xuling Xue, Dongdong Zhai, Zhongqing Li
  • Patent number: 10680000
    Abstract: A vertical field effect transistor (FET) includes a vertical semiconductor channel having a first end that contacts an upper surface of a substrate and an opposing second end that contacts a source/drain region. An electrically conductive gate encapsulates the vertical semiconductor channel. The vertical FET further includes a split-channel antifuse device between the source/drain region and the electrically conductive gate. The split-channel antifuse device includes a gate dielectric having a thickness that varies between the source/drain region and the electrically conductive gate.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: June 9, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Patent number: 10680110
    Abstract: A first transistor and a second transistor are stacked. The first transistor and the second transistor have a gate electrode in common. At least one of semiconductor films used in the first transistor and the second transistor is an oxide semiconductor film. With the use of the oxide semiconductor film as the semiconductor film in the transistor, high field-effect mobility and high-speed operation can be achieved. Since the first transistor and the second transistor are stacked and have the gate electrode in common, the area of a region where the transistors are disposed can be reduced.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: June 9, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Seiichi Yoneda
  • Patent number: 10658037
    Abstract: A memory device may include a local bit line electrically coupled to a plurality of memory cells and a global bit line electrically coupled to the local bit line through first and second selectable parallel paths having first and second impedances, respectively. The first path may be active and the second path may be in an off state in at least one of a set operation or a forming operation. The second path may be active in a reset operation, wherein the second impedance of the second path has a lower impedance than the first impedance of the first path.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: May 19, 2020
    Assignee: Rambus Inc.
    Inventors: Deepak Chandra Sekar, Brent S. Haukness, Bruce L. Bateman
  • Patent number: 10658506
    Abstract: A fin cut last methodology for manufacturing a vertical FinFET includes forming a plurality of semiconductor fins over a substrate, forming shallow trench isolation between active fins and, following the formation of a functional gate of the active fins, using a selective etch to remove a sacrificial fin from within an isolation region. A further etching step can be used to remove a portion of the gate stack proximate to the sacrificial fin to create an isolation trench and a laterally-extending cavity within the isolation region that are back-filled with an isolation dielectric.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: May 19, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chanro Park, Kangguo Cheng
  • Patent number: 10651790
    Abstract: An oscillator capable of quick startup is provided. A transistor is provided between an output terminal of a certain stage inverter and an input terminal of the following stage inverter included in the voltage controlled oscillator. With the use of the on resistance of the transistor, the oscillation frequency of the clock signal is controlled. While supply of the power supply voltage is stopped, a signal that is input to the input terminal of the inverter just before supply of the power supply voltage is stopped is stored by turning off the transistor. This operation makes it possible to immediately output a clock signal that has the same frequency as that before supply of the power supply voltage is stopped at the time when the power supply voltage is supplied again.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: May 12, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuki Okamoto, Yoshiyuki Kurokawa
  • Patent number: 10629582
    Abstract: A semiconductor device includes a substrate including a first region and a second region, memory transistors on the first region, a first interconnection layer on the memory transistors and including first interconnection lines, and a second interconnection layer on the first interconnection layer and including second interconnection lines. The second interconnection lines on the first region include a first line extending along a first direction and spaced from the second region by a first distance along the first direction, and a second line extending along the first direction, spaced from the first line along a second direction intersecting the first direction, and having a width smaller than that of the first line. The first line includes a protrusion extending along a third direction toward the substrate. The protrusion is spaced from the second region by a second distance along the first direction greater than the first distance.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: April 21, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Lakgyo Jeong, Seolun Yang, Yongrae Cho, Hee Bum Hong
  • Patent number: 10622432
    Abstract: A display device includes a substrate including a pixel region and a peripheral region. The display device also includes a plurality of pixels provided in the pixel region for displaying an image. The display device also includes a light emitting element provided in each pixel for emitting light. The display device includes a first transistor provided in each pixel for driving the light emitting element, and a second transistor connected to the first transistor. The display device includes an insulating layer disposed between a second semiconductor layer of the second transistor and the substrate; and a crack blocking layer disposed between the insulating layer and the second semiconductor layer of the second transistor. A first semiconductor layer of the first transistor and the second semiconductor layer of the second transistor are provided in layers different from each other.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: April 14, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Sun Ho Kim, Ju Chan Park, Young Gug Seol, Sun Hee Lee
  • Patent number: 10593808
    Abstract: A thin film transistor includes an active layer over a substrate, a gate electrode over the active layer, a gate line connected with the gate electrode, and a gate insulation film between the active layer and the gate electrode. The active layer includes a channel region overlapping the gate electrode, and a drain region and a source region on respective sides of the channel region. A length of a straight line connecting the drain region and the source region by a shortest distance may be greater than a width of the gate line parallel to the straight line.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: March 17, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Joonseok Park, Jihun Lim, Myounghwa Kim, Taesang Kim, Yeonkeon Moon
  • Patent number: 10580771
    Abstract: A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FINFET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: March 3, 2020
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Qing Liu, Prasanna Khare, Nicolas Loubet
  • Patent number: 10572049
    Abstract: A display substrate, a display panel, a substrate, a touch substrate and a cutting method of the substrate are disclosed. The display substrate includes a plurality of imagined touch electrodes, a plurality of connection wires, a grounding electrode and a first cutting alignment mark. The plurality of imagined touch electrodes are located at an imagined touch zone of the display substrate; the plurality of connection wires are located at a bonding zone of the display substrate and are connected with the imagined touch electrodes; the grounding electrode is arranged at the bonding zone and is electrically connected with the a plurality of connection wires; the first cutting alignment mark is arranged at a side of the grounding electrode adjacent to the connection wires, and configured that the grounding electrode being able to be cut away from the display substrate by cutting the display substrate through the first cutting alignment mark.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: February 25, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Zhen Zhang, Sheng Wang, Lisen Wang, Peng Li
  • Patent number: 10559691
    Abstract: Methods of forming a compact FinFET OTP/MTP cell and a compact FDSOI OTP/MTP cell and resulting devices are provided. Embodiments include providing a substrate having a BOX layer; forming fins on the BOX layer with a gap in between; forming first and second gates, laterally separated, over and perpendicular to the fins; forming at least one third gate between the first and second gates and contacting the BOX layer through the gap, each third gate overlapping an end of a fin or both fins; forming a S/D region in each of the fins adjacent to the first and second gates, respectively, remote from the at least one third gate; utilizing each of the first and second gates as a WL; utilizing each third gate as a SL or connecting a SL to the S/D region; and connecting a BL to the S/D region or the at least one third gate.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: February 11, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Eng Huat Toh, Shyue Seng Tan, Elgin Kiok Boone Quek
  • Patent number: 10546853
    Abstract: A device including RM below the top surface of an HKMG structure, and method of production thereof. Embodiments include first and second HKMG structures over a portion of the substrate and on opposite sides of the STI region, the first and second HKMG structures having a top surface; and a RM over the STI region and between the first and second HKMG structures, wherein the RM is below the top surface of the first and second HKMG structures.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: January 28, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Laertis Economikos, Hui Zang, Ruilong Xie
  • Patent number: 10541329
    Abstract: Techniques related to a boosted vertical field effect transistor and method of fabricating the same are provided. A logic device can comprise a vertical field effect transistor comprising a substrate, a first epitaxial layer and a second epitaxial layer. A bottom source/drain contact can be between a top surface and the first epitaxial layer and a top source/drain contact can be between the top surface and the second epitaxial layer at respective first portions of one or more vertical fins. The logic device can also comprise a boosted bipolar junction transistor. A bipolar junction transistor contact can be between the top surface and the second epitaxial layer at respective second portions of the one or more vertical fins. The respective first portions and the respective second portions can be opposite portions of the one or more vertical fins.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: January 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Injo Ok, Choonghyun Lee, Soon-Cheon Seo, Seyoung Kim
  • Patent number: 10535664
    Abstract: A method of changing a formation rate of silicon oxide includes providing a substrate, wherein two conductive lines are disposed on the substrate and a recess is between the conductive lines. Later, a cleaning process is performed to clean the substrate and the conductive lines using diluted hydrofluoric acid. After the cleaning process, a silicon oxide layer is formed to cover a sidewall and a bottom of the recess, wherein a formation rate of the silicon oxide layer at the bottom of the recess is greater than a formation rate of the silicon oxide layer at the sidewall of the recess.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: January 14, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Po-Chun Chen, Wei-Hsin Liu, Chia-Lung Chang, Yi-Wei Chen, Han-Yung Tsai
  • Patent number: 10515968
    Abstract: Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and method of operating said memory arrays are disclosed for making a memory device.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: December 24, 2019
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: 10510618
    Abstract: A structure includes a stepped crystalline substrate that includes an upper step, a lower step, and a step rise. A first fin includes a crystalline structure having a first lattice constant. The first fin is formed over the lower step. A second fin includes a crystalline structure having a second lattice constant, the second lattice constant being different than the first lattice constant. The second fin can be formed over the upper step apart from the first fin. A second crystalline structure can be formed over the first crystalline structure and the tops of the fins aligned. The first and second fins can be made of the same material, but with different heights and different channel strain values. The first fin can be used as an NMOS fin and the second fin can be used as a PMOS fin of a CMOS FinFET.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Han Lee, Chih-Yu Ma, Shih-Chieh Chang
  • Patent number: 10504928
    Abstract: A display panel includes a substrate having a display region and a border region adjacent to the display region; a first transistor disposed on the border region and including an active layer on the substrate; and a transparent conductive layer disposed on the border region and including an opening disposed on the active layer, wherein an opening area of the opening is larger than an area of the active layer.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: December 10, 2019
    Assignee: INNOLUX CORPORATION
    Inventors: Yi-Ling Yu, Chun-Liang Lin