Insulated Electrode Device Is Combined With Diverse Type Device (e.g., Complementary Mosfets, Fet With Resistor, Etc.) Patents (Class 257/350)
  • Patent number: 10331001
    Abstract: A manufacturing method of a TFT substrate uses a bottom gate structure and the entire process can be completely done with seven masks. The number of masks used is reduced. The manufacturing process of a TFT substrate is simplified. Product yield and increase productivity are effectively improved. By subjecting two ends of a semiconductor pattern to heavy ion doping to form a source electrode and a drain electrode, the manufacturing steps can be reduced and the source electrode and the drain electrode so formed do not need to extend through a via hole formed in an interlayer dielectric layer to get in connection with the two ends of the active layer so as to effectively reduce contact resistance and improve product yield. Also provided is a TFT substrate manufactured with the method.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: June 25, 2019
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Yuanfu Liu
  • Patent number: 10332954
    Abstract: A semiconductor device and a manufacturing method thereof, the semiconductor device including an insulation layer; a metal resistance pattern on the insulation layer; a spacer on a side wall of the metal resistance pattern; and a gate contact spaced apart from the spacer, the gate contact extending into the insulation layer, wherein the insulation layer includes a projection projecting therefrom, the projection contacting the gate contact.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: June 25, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung Hun Choi, Young Tak Kim, Da Il Eom, Sun Jung Lee
  • Patent number: 10325937
    Abstract: The present disclosure relates to a thin film transistor substrate having two different types of thin film transistors on the same substrate. A thin film transistor substrate includes a substrate; a first thin film transistor disposed on the substrate, the first thin film transistor including a poly crystalline semiconductor layer, a first gate electrode over the poly crystalline semiconductor layer, a first source electrode, and a first drain electrode; a second thin film transistor disposed on the substrate, the second thin film transistor including a second gate electrode, an oxide semiconductor layer over the second gate electrode, a second source electrode, and a second drain electrode; and an intermediate insulating layer including a nitride layer and an oxide layer on the nitride layer, the intermediate insulating layer disposed over the first gate electrode and the second gate electrode and under the oxide semiconductor layer.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: June 18, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Youngjang Lee, Kyungmo Son, Sohyung Lee, Moonho Park, Sungjin Lee
  • Patent number: 10304772
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate, a gate stack, and an interconnect structure over the gate stack and the semiconductor substrate. The semiconductor device structure also includes a resistive element over the interconnect structure, and the resistive element is directly above the gate stack. The semiconductor device structure further includes a thermal conductive element over the interconnect structure. A direct projection of the thermal conductive element on a main surface of the resistive element extends across a portion of a first imaginary line and a portion of a second imaginary line of the main surface. The first imaginary line is perpendicular to the second imaginary line. The first imaginary line and the second imaginary line intersect at a center of the main surface. The semiconductor device structure includes a dielectric layer separating the thermal conductive element from the resistive element.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: May 28, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wan-Te Chen, Chung-Hui Chen, Wei-Chih Chen, Chii-Ping Chen, Wen-Sheh Huang, Bi-Ling Lin, Sheng-Feng Liu
  • Patent number: 10304964
    Abstract: A semiconductor device includes a first transistor, a second transistor and a third transistor provided on a substrate, the first to third transistors respectively including source and drain regions spaced apart from each other, a gate structure extending in a first direction on the substrate and interposed between the source and drain regions, and a channel region connecting the source and drain regions to each other. A channel region of the second transistor and a channel region of the third transistor respectively include a plurality of channel portions, the plurality of channel portions spaced apart from each other in a second direction, perpendicular to an upper surface of the substrate, and connected to the source and drain regions, respectively. A width of a channel portion of the third transistor in the first direction is greater than a width of a channel portion of the second transistor in the first direction.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: May 28, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Mongsong Liang, Sung-Dae Suk, Guemjong Bae
  • Patent number: 10304895
    Abstract: A method for manufacturing a solid-state image pickup apparatus includes forming a first insulating film over a substrate after forming a gate electrode of a first transfer transistor and a gate electrode of a second transfer transistor, forming a second insulating film on the first insulating film, forming a first structure and a second structure on side surfaces of the gate electrodes of the first and second transfer transistors, respectively, via the first insulating film by etching the second insulating film in such a manner that the first insulating film remains on a semiconductor region of a photoelectric conversion unit and a semiconductor region of a charge holding unit, and forming a light shielding film that covers the gate electrode of the first transfer transistor, the semiconductor region of the charge holding unit, and the gate electrode of the second transfer transistor.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: May 28, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shunsuke Nakatsuka, Kentaro Suzuki, Mari Isobe, Masatsugu Itahashi, Yasuhiro Sekine, Sho Suzuki
  • Patent number: 10297445
    Abstract: A substrate includes a support structure comprising: a polycrystalline ceramic core; a first adhesion layer coupled to the polycrystalline ceramic core; a conductive layer coupled to the first adhesion layer; a second adhesion layer coupled to the conductive layer; and a barrier layer coupled to the second adhesion layer. The substrate also includes a silicon oxide layer coupled to the support structure, a substantially single crystalline silicon layer coupled to the silicon oxide layer, and an epitaxial III-V layer coupled to the substantially single crystalline silicon layer.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: May 21, 2019
    Assignee: Qromis, Inc.
    Inventors: Vladimir Odnoblyudov, Cem Basceri, Shari Farrens
  • Patent number: 10290698
    Abstract: An illustrative method includes, among other things, forming a plurality of fins. A subset of the plurality of fins is selectively removed, leaving at least a first fin to define a first fin portion and at least a second fin to define a second fin portion. A first type of dopant is implanted into a substrate to define a resistor body and the first type of dopant is implanted into the first and second fins. The first fin portion is disposed above a first end of the resistor body and the second fin is disposed above a second end of the resistor body. An insulating layer is formed above the resistor body. At least one gate structure is formed above the insulating layer and above the resistor body.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: May 14, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Jagar Singh
  • Patent number: 10283527
    Abstract: An SOI substrate having a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and a semiconductor layer formed on the insulating layer is provided. A first region is one for forming a low breakdown voltage MISFET in the semiconductor layer, and a second region, in which the insulating layer and the semiconductor layer have been removed, is one for forming a high breakdown voltage MISFET. After an n-type semiconductor region is formed in the second region and an n-type extension region is formed in the first region, a first heat treatment is performed on the semiconductor substrate. Thereafter, a diffusion layer is formed in each of the first and second regions, and then a second heat treatment is performed on the semiconductor substrate. Herein, the time for which the first heat treatment is performed is longer than the time for which the second heat treatment is performed.
    Type: Grant
    Filed: March 10, 2018
    Date of Patent: May 7, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yoshiki Yamamoto
  • Patent number: 10268094
    Abstract: An array substrate, a display panel and a method of manufacturing array substrate are provided. The array substrate, comprising first substrate and data line, data line positioned on first substrate; auxiliary electrode positioned on first substrate, auxiliary electrode for electrically connecting to color filter, vertical projection of auxiliary electrode on first substrate does not intersect with data line; insulating layer positioned on surface of auxiliary electrode which away first substrate, insulating layer has hole; and shielding electrode comprises main section and protrusion section are integrated, main section is located on lateral side of data line which away first substrate, and vertical projection of main section on first substrate is covering data line, protrusion section is positioned on insulating layer, and protrusion section pass through hole and contacting to auxiliary electrode. It achieves to highly product yield and saving production costs.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: April 23, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Zhuming Deng, Minggang Liu
  • Patent number: 10262898
    Abstract: A silicon on insulator substrate includes a semiconductor bulk handle wafer, an insulating layer on said semiconductor bulk handle wafer and a semiconductor film on said insulating layer. An opening extends completely through the semiconductor film and insulating layer to expose a surface of the semiconductor bulk handle wafer. Epitaxial material fills the opening and extends on said semiconductor film, with the epitaxial material and semiconductor film forming a thick semiconductor film. A trench isolation surrounds a region of the thick semiconductor film to define an electrical contact made to the semiconductor bulk handle wafer through the opening.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: April 16, 2019
    Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Didier Dutartre, Jean-Pierre Carrere, Jean-Luc Huguenin, Clement Pribat, Sarah Kuster
  • Patent number: 10242618
    Abstract: An organic light emitting diode (OELD) driver for driving at least one OELD having a transition time. The OLED driver has a power supply coupled to a bias pulse controller and an injection pulse controller. The bias pulse controller is configured to generate a bias pulse output based on the OLED transition time. The injection pulse controller is configured to generate an injection pulse output. A combiner is coupled to the bias pulse output and the injection pulse output. The combiner is configured to generate a combined output to drive the OLED. A system controller may be coupled to at least one of the power supply, bias pulse controller and injection pulse controller to adjust the voltage/current delivered to the OLED to adjust a light level output of the OLED. The OLED driver may include a switch that changes a dwell time of the bias pulse controller output.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: March 26, 2019
    Assignee: THIRDEYE GEN, INC
    Inventor: Michael K. Rafailov
  • Patent number: 10243005
    Abstract: An object is to improve reliability of a semiconductor device. A semiconductor device including a driver circuit portion and a display portion (also referred to as a pixel portion) over the same substrate is provided. The driver circuit portion and the display portion include thin film transistors in which a semiconductor layer includes an oxide semiconductor; a first wiring; and a second wiring. The thin film transistors each include a source electrode layer and a drain electrode layer which each have a shape whose end portions are located on an inner side than end portions of the semiconductor layer. In the thin film transistor in the driver circuit portion, the semiconductor layer is provided between a gate electrode layer and a conductive layer. The first wiring and the second wiring are electrically connected in an opening provided in a gate insulating layer through an oxide conductive layer.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: March 26, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichiro Sakata, Masayuki Sakakura, Yoshiaki Oikawa, Kenichi Okazaki, Hotaka Maruyama
  • Patent number: 10242979
    Abstract: A device includes an integrated circuit (IC) layer, an insulative layer such as a buried oxide (BOX) layer, a substrate layer separated from the IC layer by the insulative layer, and a set of protective components such as a set of Zener diodes or a Zener stack coupled to the IC layer to protect the IC layer from transient electric events such as an electrostatic discharge (ESD), an inductive flyback, and a back electromotive force (back-EMF) event. The Zener stack has a Zener breakdown voltage greater than a breakdown voltage of the IC layer. An effective bias voltage has a voltage level less than the breakdown voltage of the IC layer. The Zener diode or Zener stack may be coupled to one or more isolation structures of the IC layer. The isolation structures separate the IC layer into electrically distinct portions or wells in which other electric components are formed.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: March 26, 2019
    Assignee: NXP USA, Inc.
    Inventor: Willliam Ernest Edwards
  • Patent number: 10217735
    Abstract: A semiconductor switch device and a method of making the same. The semiconductor switch device includes a field effect transistor located on a semiconductor substrate. The field effect transistor includes a plurality of gates. Each gate includes a gate electrode and gate dielectric arranged in a loop on a major surface of the substrate. The loops formed by the gates are arranged concentrically. Each gate has a source region located adjacent an inner edge or outer edge of the loop formed by that gate and a drain region located adjacent the other edge of said inner edge and said outer edge of the loop formed by that gate.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: February 26, 2019
    Assignee: NXP B.V.
    Inventors: Olivier Tesson, Thomas Francois
  • Patent number: 10199499
    Abstract: A semiconductor device includes first through fourth active fins, which extend alongside one another in a first direction; and a field insulating film that covers lower portions of the first through fourth active fins, the first and second active fins protrude from the field insulating film at a first height, the third active fin protrudes from the field insulating film at a second height different from the first height, and an interval between the first and second active fins is different from an interval between the third and fourth active fins.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: February 5, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Min Kim, Dong-Ho Cha, Sunhom Steve Paak
  • Patent number: 10192895
    Abstract: Even when a light shielding film is provided between a transistor and a substrate, a threshold voltage of the transistor can be prevented or suppressed from being shifted. A display device includes light shielding films provided between a substrate and a semiconductor layer of a transistor including a gate electrode and the semiconductor layer. The semiconductor layer includes a source region and a drain region. Both of the light shielding films overlap the semiconductor layer when seen in a plan view, and are spaced apart from each other in a direction.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: January 29, 2019
    Assignee: JAPAN DISPLAY INC.
    Inventors: Hiroyuki Abe, Takayuki Suzuki
  • Patent number: 10186508
    Abstract: A semiconductor device of an embodiment includes a transistor device in a semiconductor die including a semiconductor body. The transistor device includes transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body. The semiconductor device further includes a control terminal contact area at the first surface electrically connected to a control electrode of each of the transistor cells. A first load terminal contact area at the first surface electrically connected to a first load terminal region of each of the transistor cells. The semiconductor device further includes a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: January 22, 2019
    Assignee: Infineon Technologies AG
    Inventors: Dirk Ahlers, Markus Zundel, Peter Brandl, Kurt Matoy, Thomas Ostermann
  • Patent number: 10177156
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region and the substrate includes a semiconductor layer on top of an insulating layer; forming a first front gate on the first region of the substrate and a second front gate on the second region of the substrate; removing part of the insulating layer under the first front gate; forming a first back gate on the insulating layer under the first front gate; and forming a second back gate under the second front gate.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: January 8, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wanxun He, Su Xing
  • Patent number: 10163714
    Abstract: Disclosed herein is a semiconductor structure including: a host substrate and one or more bonding layers on top of the host substrate. The structure further includes an entity on the one or more bonding layers, where the entity includes two transistors on opposite sides of a common layer of channel material, where each transistor includes a gate, where both gates overlap each other, where both transistors share the same source and drain regions, and where each transistor have a channel defined within a same portion of the common layer of channel material overlapped by both transistor gates.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: December 25, 2018
    Assignee: IMEC VZW
    Inventors: Amey Mahadev Walke, Nadine Collaert
  • Patent number: 10153323
    Abstract: A production method for a semiconductor epitaxial wafer includes: a first step of irradiating a surface of a semiconductor wafer with cluster ions to form a modified layer that is located in a surface portion of the semiconductor wafer and that includes a constituent element of the cluster ions in solid solution; and a second step of forming an epitaxial layer on the modified layer of the semiconductor wafer. The first step is performed such that a portion of the modified layer in terms of a thickness direction becomes an amorphous layer and an average depth of an amorphous layer surface at a semiconductor wafer surface-side of the amorphous layer is at least 20 nm from the surface of the semiconductor wafer.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: December 11, 2018
    Assignee: SUMCO CORPORATION
    Inventor: Ryosuke Okuyama
  • Patent number: 10141351
    Abstract: An array substrate is disclosed. The array substrate includes: a substrate adopting an organic material; an isolation layer adopting a metal material, and the isolation layer is formed on the substrate; and a buffering layer formed at a side of the isolation layer away from the substrate. In the array substrate of the present invention, in a high-temperature PECVD process, a pollution problem caused by the plasma directly bombarding the substrate made of an organic material can be avoid. A display device applying the array substrate and a manufacturing method for an array substrate are also disclosed.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: November 27, 2018
    Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd
    Inventor: Fang Qin
  • Patent number: 10134879
    Abstract: The on-state characteristics of a transistor are improved and thus, a semiconductor device capable of high-speed response and high-speed operation is provided. A highly reliable semiconductor device showing stable electric characteristics is made. The semiconductor device includes a transistor including a first oxide layer; an oxide semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; a second oxide layer over the oxide semiconductor layer; a gate insulating layer over the second oxide layer; and a gate electrode layer over the gate insulating layer. An end portion of the second oxide layer and an end portion of the gate insulating layer overlap with the source electrode layer and the drain electrode layer.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: November 20, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Shinya Sasagawa, Motomu Kurata, Masashi Tsubuku
  • Patent number: 10134898
    Abstract: Methods and structures for forming highly-doped, ultrathin layers for transistors formed in semiconductor-on-insulator substrates are described. High dopant concentrations may be achieved in ultrathin semiconductor layers to improve device characteristics. Ion implantation at elevated temperatures may mitigate defect formation for stoichiometric dopant concentrations up to about 30%. In-plane stressors may be formed adjacent to channels of transistors formed in ultrathin semiconductor layers.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: November 20, 2018
    Assignee: STMICROELECTRONICS, INC.
    Inventor: Jocelyne Gimbert
  • Patent number: 10134761
    Abstract: The present disclosure provides semiconductor devices, fin field-effect transistors and fabrication methods thereof. An exemplary fin field-effect transistor includes a semiconductor substrate; an insulation layer configured for inhibiting a short channel effect and increasing a heat dissipation efficiency of the fin field-effect transistor formed over the semiconductor substrate; at least one fin formed over the insulation layer; a gate structure crossing over at least one fin and covering top and side surfaces of the fin formed over the semiconductor substrate; and a source formed in the fin at one side of the gate structure and a drain formed in the fin at the other side of the gate structure.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: November 20, 2018
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Xinyun Xie, Ming Zhou
  • Patent number: 10128329
    Abstract: A method of making a circuit device includes forming core circuitry. The core circuitry includes a doped region in the core circuit. The method further includes implanting a first set of guard rings around a periphery of the core circuitry. The first set of guard rings has a first dopant type. Implanting the first set of guard rings includes implanting the first set of guard rings spaced from the doped region. The method further includes implanting a second set of guard rings having a second dopant type, wherein the second dopant type being opposite to the first dopant type. At least one guard ring of the second set of guard rings is around a periphery of at least one guard ring of the first set of guard rings.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: November 13, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wan-Yen Lin, Wun-Jie Lin, Yu-Ti Su, Bo-Ting Chen, Jen-Chou Tseng, Kuo-Ji Chen, Sun-Jay Chang, Min-Chang Liang
  • Patent number: 10121846
    Abstract: The present disclosure provides resistor structures in sophisticated integrated circuits on the basis of an SOI architecture, wherein a very thin semiconductor layer, typically used for forming fully depleted SOI transistors, may be used as a resistor body. In this manner, significantly higher sheet resistance values may be achieved, thereby providing the potential for implementing high ohmic resistors into sophisticated integrated circuits.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: November 6, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Alban Zaka, Ignasi Cortes Mayol, Tom Herrmann, El Mehdi Bazizi, John Morgan
  • Patent number: 10090339
    Abstract: Disclosed is a radio frequency (RF) switch that includes a substrate and a plurality of elongated drain/source (D/S) diffusion regions laterally disposed in parallel with one another and separated by a plurality of elongated channel regions. A plurality of elongated D/S resistor regions extends between an adjacent pair of plurality of elongated D/S diffusion regions, and a plurality of elongated gate structures resides over corresponding ones of the elongated channel regions. A silicide layer resides over a majority of at least top surfaces of the plurality of the elongated D/S diffusion regions and the plurality of elongated gate structures, wherein less than a majority of each of the plurality of the elongated D/S resistor regions are covered by the silicide layer.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: October 2, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Dirk Robert Walter Leipold, George Maxim, Baker Scott, Julio C. Costa
  • Patent number: 10090193
    Abstract: Disclosed is an integrated circuit (IC) structure that incorporates stacked pair(s) of field effect transistors (FETs), where each stacked pair has a shared gate. The structure also includes an irregular-shaped buried interconnect that connects source/drain regions that are on opposite sides of the shared gate and at different levels (i.e., a lower FET's source/drain region on one side of the shared gate to an upper FET's source/drain region on the opposite side). Also disclosed is a method for forming the structure by forming, during different process stages, different sections of an irregular-shaped cavity (including sections that expose surfaces of the source/drain regions at issue and a section with sidewalls lined by a dielectric spacer) and filling the different sections with sacrificial material. When all of the sections are completed, the sacrificial material is selectively removed, thereby creating the irregular-shaped cavity. Then, the buried interconnect is formed within the cavity.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: October 2, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Daniel Chanemougame, Lars Liebmann, Ruilong Xie
  • Patent number: 10079229
    Abstract: A technique relates to forming resistor fins on a substrate. A shallow trench isolation material is formed on dummy fins and the substrate, and the dummy fins are formed on the substrate. Predefined ones of the dummy fins are removed, thereby forming voids in the shallow trench isolation material corresponding to previous locations of the predefined ones of the dummy fins. A first material is deposited into the voids. The height of the first material is reduced, thereby forming trenches in the shallow trench isolation material. A second material is deposited into the trenches to be on top of the first material, thereby forming the resistor fins of a resistor device. A metal contact layer is formed so as to contact a top surface of the first material at predefined locations.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: September 18, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 10073291
    Abstract: A display device is provided. The display device includes a first base substrate, a gate line on the first base substrate and extending in a first direction, a data line disposed on the first base substrate, insulated from the gate line, and extending in a second direction, which crosses the first direction, a switch on the first base substrate and electrically connected to the gate line and the data line, an insulating layer on the switch, a first electrode on the insulating layer, a light-shielding conductive layer directly contacting the first electrode and overlapping the switch, and a second electrode insulated from the first electrode and the light-shielding conductive layer, at least partially overlapping the first electrode, and electrically connected to the switch.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: September 11, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Dong Ju Yang, Seul Ki Kim, Hyun Jung Lee, Hyo Jin Kim, Kap Soo Yoon, Jeong Hyun Lee, Yun Seok Han, Jeong Uk Heo
  • Patent number: 10062601
    Abstract: A multilayer semiconductor device structure having different circuit functions on different semiconductor device layers is provided. The semiconductor structure comprises a first semiconductor device layer fabricated on a bulk substrate. The first semiconductor device layer comprises a first semiconductor device for performing a first circuit function. The first semiconductor device layer includes a patterned top surface of different materials. The semiconductor structure further comprises a second semiconductor device layer fabricated on a semiconductor-on-insulator (“SOI”) substrate. The second semiconductor device layer comprises a second semiconductor device for performing a second circuit function. The second circuit function is different from the first circuit function. A bonding surface coupled between the patterned top surface of the first semiconductor device layer and a bottom surface of the SOT substrate is included.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: August 28, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yi-Tang Lin, Chun Hsiung Tsai, Clement Hsingjen Wann
  • Patent number: 10038047
    Abstract: The present application discloses a light emitting diode packaging structure comprising a base substrate; a metal lead on the base substrate; a cover plate; and a seal frame sealing the cover plate and the base substrate together and forming an enclosure surrounding a display area of the base substrate. The metal lead extends from the display area outwardly and passes through below the seal frame to outside of the enclosure. The metal lead has a curved configuration in plan view of the base substrate within a region where the metal lead overlaps with the seal frame.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: July 31, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Yi Li
  • Patent number: 10032921
    Abstract: A semiconductor device with a novel structure is provided. A semiconductor device with reduced power consumption is provided. A circuit which is configured to supply a signal from an input terminal to both a gate and a backgate of a transistor in a first state and to only the gate in a second state is provided. With this structure, a current supply capability of the transistor can be changed between operations; accordingly, power consumption can be reduced by the amount needed to charge the backgate.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: July 24, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kei Takahashi, Atsushi Miyaguchi
  • Patent number: 10025148
    Abstract: A display device includes a display panel, a panel driver, panel-side output terminals, image signal lines, and control signal lines. The terminals are disposed in a non-display area of the display device and connected to the panel driver. The image signal lines are routed in the non-display area from the terminals to cross a long edge of the panel driver and spread in a fan-like form toward the display area. The control signal lines including first lines and second lines are routed in the non-display area from the terminals toward a display area of the display device. The first lines are routed from the terminals to cross the long edge and along the image signal lines toward the display area. The second lines each including portions having a width larger than the first lines are routed from the terminals to cross a short edge of the panel driver.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: July 17, 2018
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Yohsuke Fujikawa
  • Patent number: 10014258
    Abstract: The gate electrode is provided on the gate insulating film. The interlayer insulating film is provided to cover the gate electrode. The interlayer insulating film includes a first insulating film which is in contact with the gate electrode, contains silicon atoms, and contains neither phosphorus atoms nor boron atoms, a second insulating film which is provided on the first insulating film and contains silicon atoms and at least one of phosphorus atoms and boron atoms, and a third insulating film which contains silicon atoms and contains neither phosphorus atoms nor boron atoms. The second insulating film has a first surface which is in contact with the first insulating film, a second surface opposite to the first surface, and a third surface which connects the first surface and the second surface. The third insulating film is in contact with at least one of the second surface and the third surface.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: July 3, 2018
    Assignees: Sumitomo Electric Industries, Ltd., Renesas Electronics Corporation
    Inventors: Shunsuke Yamada, So Tanaka, Daisuke Hamajima, Shinji Kimura, Masayuki Kobayashi, Masaki Kijima, Maki Hamada
  • Patent number: 10008606
    Abstract: The thin film transistor includes a gate electrode formed on a surface of a substrate; a first amorphous silicon layer formed on an upper side of the gate electrode; a plurality of polysilicon layers separated by the first amorphous silicon layer and formed on the upper side of the gate electrode with a required spaced dimension; a second amorphous silicon layer and an n+ silicon layer which are formed on the upper side of the plurality of polysilicon layers and the first amorphous silicon layer; and a source electrode and a drain electrode formed on the n+ silicon layer.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: June 26, 2018
    Assignee: Sakai Display Products Corporation
    Inventors: Shigeru Ishida, Nobutake Nodera, Ryohei Takakura, Yoshiaki Matsushima, Takao Matsumoto, Kazuki Kobayashi, Taimi Oketani
  • Patent number: 10008429
    Abstract: A semiconductor device reduces measurement time. The semiconductor device according to an embodiment of the invention includes: plural series-coupled resistance elements for testing; plural switches coupled to a coupling path coupling the resistance elements; and plural selection circuits to select, by turning on or off the switches, a number of the series-coupled resistance elements to be measured as a group. In the semiconductor device: the switches include plural first switches coupled to plural groups of the resistance elements, each of the groups including N (N=2 or a larger integer) of the resistance elements; and the selection circuits turn the first switches on or off and thereby select a number of the series-coupled resistance elements to be measured as a group, the number equaling the N.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: June 26, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hiroki Shinkawata
  • Patent number: 10002885
    Abstract: A substrate in which an insulating layer, a semiconductor layer and an insulating film are stacked on a semiconductor substrate and an element isolation region is embedded in a trench is prepared. After the insulating film in a bulk region is removed by dry etching and the semiconductor layer in the bulk region is removed by dry etching, the insulating layer in the bulk region is thinned by dry etching. A first semiconductor region is formed in the semiconductor substrate in a SOI region by ion implantation, and a second semiconductor region is formed in the semiconductor substrate in the bulk region by ion implantation. Then, the insulating film in the SOI region and the insulating layer in the bulk region are removed by wet etching. Thereafter, a first transistor is formed on the semiconductor layer in the SOI region and a second transistor is formed on the semiconductor substrate in the bulk region.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: June 19, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Yoshiki Yamamoto
  • Patent number: 10002925
    Abstract: A semiconductor device comprises a first semiconductor fin having a first width, the first semiconductor fin is arranged on a first portion of the strain relaxation buffer layer, where the first portion of the strain relaxation buffer layer has a second width and a second semiconductor fin having a width substantially similar to the first width, the second semiconductor fin is arranged on a second portion of the strain relaxation buffer layer, where the second portion of the strain relaxation buffer layer has a third width. A gate stack is arranged over a channel region of the first fin and a channel region of the second fin.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: June 19, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Peng Xu
  • Patent number: 9991259
    Abstract: Provided are a semiconductor device and a fabricating method thereof.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: June 5, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Jae Kang, Jin-Wook Lee, Kang-Ill Seo, Yong-Min Cho
  • Patent number: 9985139
    Abstract: This disclosure provides p-type metal oxide semiconductor materials that display good thin film transistor (TFT) characteristics. Also provided are TFTs including channels that include p-type oxide semiconductors, and methods of fabrication. The p-type metal oxide films may be hydrogenated such that they have a hydrogen content of at least 1018 atoms/cm3, and in some implementations, at least 1020 atoms/cm3, or higher. Examples of hydrogenated p-type metal oxide films include hydrogenated tin (II)-based films and hydrogenated copper (I)-based films. The TFTs may be characterized by having one or more TFT characteristics such as high mobility, low subthreshold swing (s-value), and high on/off current ratio.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: May 29, 2018
    Assignee: QUALCOMM Incorporated
    Inventor: Kenji Nomura
  • Patent number: 9978745
    Abstract: A bipolar junction transistor (BJT) includes a semiconductor substrate and a first isolation structure. The semiconductor substrate includes a first fin structure disposed in an emitter region, a second fin structure disposed in a base region, and a third fin structure disposed in a collector region. The first, the second, and the third fin structures are elongated in a first direction respectively. The base region is adjacent to the emitter region, and the base region is located between the emitter region and the collector region. The first isolation structure is disposed between the first fin structure and the second fin structure, and a length of the first isolation structure in the first direction is shorter than or equal to 40 nanometers. An effective base width of the BJT may be reduced by the disposition of the first isolation structure, and a current gain of the BJT may be enhanced accordingly.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: May 22, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuan-Ti Wang, Ling-Chun Chou, Kun-Hsien Lee
  • Patent number: 9960229
    Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate having a bulk resistivity ??100 Ohm.cm, a front surface and a rear surface, at least one LDMOS transistor in the semiconductor substrate, and a RESURF structure. The RESURF structure includes a doped buried layer arranged in the semiconductor substrate, spaced at a distance from the front surface and the rear surface, and coupled with at least one of a channel region and a body contact region of the LDMOS transistor.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: May 1, 2018
    Assignee: Infineon Technologies AG
    Inventors: Albert Birner, Helmut Brech, Matthias Zigldrum, Michaela Braun, Christian Eckl
  • Patent number: 9960184
    Abstract: A semiconductor device includes a semiconductor-on-insulator (SOI) wafer having a semiconductor substrate, a buried insulating layer positioned above the semiconductor substrate, and a semiconductor layer positioned above the buried insulating layer. A shallow trench isolation (STI) structure is positioned in the SOI wafer and separates a first region of the SOI wafer from a second region of the SOI wafer, wherein the semiconductor layer is not present above the buried insulating layer in the first region, and wherein the buried insulating layer and the semiconductor layer are not present in at least a first portion of the second region adjacent to the STI structure. A dielectric layer is positioned above the buried insulating layer in the first region, and a conductive layer is positioned above the dielectric layer in the first region.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: May 1, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jan Hoentschel, Peter Baars, Hans-Peter Moll
  • Patent number: 9960193
    Abstract: A display driver integrated circuit and a method of manufacturing the same are provided. The method of manufacturing a display driver integrated circuit (DDI) including a first area, a second area, and an overlapping area in which the first area and the second area overlap each other includes forming a first pattern in the first area using a first reticle; and forming a second pattern in the second area using a second reticle, and ends of the first pattern and the second pattern are connected within the overlapping area and the first area and the second area are asymmetrically set based on the overlapping area such that the overlapping area includes only a metal line.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: May 1, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-Woo Park, Siwoo Kim
  • Patent number: 9947650
    Abstract: An ESD protection device includes a MOS transistor connected between a first terminal and a second terminal and having a gate region, source/drain region and a well region electrically coupled by a resistive-capacitive circuit configured to control turn on of the MOS transistor in response to an ESD event. The resistive-capacitive circuit has a common part with at least one of the source, gate or drain regions of the MOS transistor and includes a capacitive element and a resistive element. A first electrode of the capacitive element is formed by the resistive element and a second electrode of the capacitive element is formed by at least a portion of a semiconductor film within which the source/drain region is formed.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: April 17, 2018
    Assignee: STMicroelectronics SA
    Inventors: Philippe Galy, Sotirios Athanasiou
  • Patent number: 9947469
    Abstract: A thin-film dielectric having a higher dielectric constant than usual ones and not requiring a special single crystal substrate, and a large-capacity thin-film capacitor element using the thin-film dielectric, in which a BaTiO3-based perovskite solid solution and a KNbO3-based perovskite solid solution are alternately formed to form a crystal structure gradient region where a lattice constant continuously changes at the interface, and thus crystal lattice strain occurs, thereby permitting the production of a thin-film dielectric having a high dielectric constant; also, a large-capacity thin-film capacitor element can be produced by using the thin-film dielectric of the present invention.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: April 17, 2018
    Assignee: TDK CORPORATION
    Inventors: Masahito Furukawa, Masanori Kosuda, Saori Takeda
  • Patent number: 9947387
    Abstract: Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. This method further includes detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0; setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: April 17, 2018
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Benjamin S. Louie, Yuniarto Widjaja
  • Patent number: 9930769
    Abstract: Metal thermal grounds are used for dissipating heat from integrated-circuit resistors. The resistors may be formed using a front end of line layer, for example, a titanium-nitride layer. A metal region (e.g., in a first metal layer) is located over the resistors to form a heat sink. An area of thermal posts connected to the metal region is also located over the resistor. The metal region can be connected to the substrate of the integrated circuit to provide a low impedance thermal path out of the integrated circuit.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: March 27, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Arpit Mittal, Alvin Leng Sun Loke, Mehdi Saeidi, Patrick Drennan