Insulated Electrode Device Is Combined With Diverse Type Device (e.g., Complementary Mosfets, Fet With Resistor, Etc.) Patents (Class 257/350)
  • Patent number: 10734541
    Abstract: A method of manufacturing the semiconductor device includes: (a) providing a substrate having a semiconductor layer; (b) forming a first insulating film over an insulating layer so as to cover the semiconductor layer; (c) forming an opening extending through the first insulating film and reaching the semiconductor layer; (d) forming, over the semiconductor layer exposed at a bottom surface of the opening, a semiconductor portion having a thickness smaller than that of the first insulating film over the semiconductor layer by a selective epitaxial growth method; (e) forming a second insulating film over the first insulating film and the semiconductor portion; (f) removing the second insulating film from over the first insulating film, while leaving the second insulating film in the opening; (g) removing a semiconductor particle formed over the first insulating film in the (d); and (h) forming a third insulating film over the first insulating film.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: August 4, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tatsuya Usami
  • Patent number: 10727319
    Abstract: Stress memorization techniques (SMTs) for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a capping layer over a fin structure; forming an amorphous region within the fin structure while the capping layer is disposed over the fin structure; and performing an annealing process to recrystallize the amorphous region. The capping layer enables the fin structure to retain stress effects induced by forming the amorphous region and/or performing the annealing process.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Wen-Cheng Lo, Sun-Jay Chang
  • Patent number: 10714501
    Abstract: An electronic integrated circuit chip includes a first transistor arranged inside and on top of a solid substrate, a second transistor arranged inside and on top of a layer of semiconductor material on insulator having a first thickness, and a third transistor arranged inside and on top of a layer of semiconductor material on insulator having a second thickness. The second thickness is greater than the first thickness. The solid substrate extends underneath the layers of semiconductor material and is insulated from those layers by the insulator.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: July 14, 2020
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SAS
    Inventors: Jean-Jacques Fagot, Philippe Boivin, Franck Arnaud
  • Patent number: 10700210
    Abstract: A semiconductor device includes a substrate and a thin film transistor supported by the substrate. The thin film transistor includes a gate electrode, an oxide semiconductor layer, a gate insulating layer provided between the gate electrode and the oxide semiconductor layer, and source and drain electrodes electrically connected to the oxide semiconductor layer. The gate insulating layer includes a first portion which is covered with the oxide semiconductor layer and a second portion which is adjacent to the first portion and which is not covered with any of the oxide semiconductor layer, the source electrode and the drain electrode. The second portion is smaller in thickness than the first portion, and the difference in thickness between the second portion and the first portion is more than 0 nm and not more than 50 nm.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: June 30, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tetsuo Kikuchi, Hajime Imai, Hisao Ochi, Tetsuo Fujita, Hideki Kitagawa, Masahiko Suzuki, Shingo Kawashima, Tohru Daitoh
  • Patent number: 10684512
    Abstract: A cell forming device, including a first platform configured to carry a first substrate, a second platform configured to carry a second substrate, and a pre-alignment mechanism. The first platform includes a first suction surface and a second suction surface arranged opposite to each other and configured to attach the first substrate. The pre-alignment mechanism is configured to adjust a position of the first platform to pre-align the first substrate with the second substrate. The cell forming device further includes a turn-over mechanism configured to turn the first platform over to turn the first substrate over, an alignment mechanism configured to adjust a position of the second platform to align the turned first substrate with the second substrate, and a cell forming mechanism configured to move the first substrate to form a cell with the second substrate.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: June 16, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Yangkun Jing, Jian Sun, Junwei Xia, Xuling Xue, Dongdong Zhai, Zhongqing Li
  • Patent number: 10680110
    Abstract: A first transistor and a second transistor are stacked. The first transistor and the second transistor have a gate electrode in common. At least one of semiconductor films used in the first transistor and the second transistor is an oxide semiconductor film. With the use of the oxide semiconductor film as the semiconductor film in the transistor, high field-effect mobility and high-speed operation can be achieved. Since the first transistor and the second transistor are stacked and have the gate electrode in common, the area of a region where the transistors are disposed can be reduced.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: June 9, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Seiichi Yoneda
  • Patent number: 10680000
    Abstract: A vertical field effect transistor (FET) includes a vertical semiconductor channel having a first end that contacts an upper surface of a substrate and an opposing second end that contacts a source/drain region. An electrically conductive gate encapsulates the vertical semiconductor channel. The vertical FET further includes a split-channel antifuse device between the source/drain region and the electrically conductive gate. The split-channel antifuse device includes a gate dielectric having a thickness that varies between the source/drain region and the electrically conductive gate.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: June 9, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Patent number: 10658506
    Abstract: A fin cut last methodology for manufacturing a vertical FinFET includes forming a plurality of semiconductor fins over a substrate, forming shallow trench isolation between active fins and, following the formation of a functional gate of the active fins, using a selective etch to remove a sacrificial fin from within an isolation region. A further etching step can be used to remove a portion of the gate stack proximate to the sacrificial fin to create an isolation trench and a laterally-extending cavity within the isolation region that are back-filled with an isolation dielectric.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: May 19, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chanro Park, Kangguo Cheng
  • Patent number: 10658037
    Abstract: A memory device may include a local bit line electrically coupled to a plurality of memory cells and a global bit line electrically coupled to the local bit line through first and second selectable parallel paths having first and second impedances, respectively. The first path may be active and the second path may be in an off state in at least one of a set operation or a forming operation. The second path may be active in a reset operation, wherein the second impedance of the second path has a lower impedance than the first impedance of the first path.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: May 19, 2020
    Assignee: Rambus Inc.
    Inventors: Deepak Chandra Sekar, Brent S. Haukness, Bruce L. Bateman
  • Patent number: 10651790
    Abstract: An oscillator capable of quick startup is provided. A transistor is provided between an output terminal of a certain stage inverter and an input terminal of the following stage inverter included in the voltage controlled oscillator. With the use of the on resistance of the transistor, the oscillation frequency of the clock signal is controlled. While supply of the power supply voltage is stopped, a signal that is input to the input terminal of the inverter just before supply of the power supply voltage is stopped is stored by turning off the transistor. This operation makes it possible to immediately output a clock signal that has the same frequency as that before supply of the power supply voltage is stopped at the time when the power supply voltage is supplied again.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: May 12, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuki Okamoto, Yoshiyuki Kurokawa
  • Patent number: 10629582
    Abstract: A semiconductor device includes a substrate including a first region and a second region, memory transistors on the first region, a first interconnection layer on the memory transistors and including first interconnection lines, and a second interconnection layer on the first interconnection layer and including second interconnection lines. The second interconnection lines on the first region include a first line extending along a first direction and spaced from the second region by a first distance along the first direction, and a second line extending along the first direction, spaced from the first line along a second direction intersecting the first direction, and having a width smaller than that of the first line. The first line includes a protrusion extending along a third direction toward the substrate. The protrusion is spaced from the second region by a second distance along the first direction greater than the first distance.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: April 21, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Lakgyo Jeong, Seolun Yang, Yongrae Cho, Hee Bum Hong
  • Patent number: 10622432
    Abstract: A display device includes a substrate including a pixel region and a peripheral region. The display device also includes a plurality of pixels provided in the pixel region for displaying an image. The display device also includes a light emitting element provided in each pixel for emitting light. The display device includes a first transistor provided in each pixel for driving the light emitting element, and a second transistor connected to the first transistor. The display device includes an insulating layer disposed between a second semiconductor layer of the second transistor and the substrate; and a crack blocking layer disposed between the insulating layer and the second semiconductor layer of the second transistor. A first semiconductor layer of the first transistor and the second semiconductor layer of the second transistor are provided in layers different from each other.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: April 14, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Sun Ho Kim, Ju Chan Park, Young Gug Seol, Sun Hee Lee
  • Patent number: 10593808
    Abstract: A thin film transistor includes an active layer over a substrate, a gate electrode over the active layer, a gate line connected with the gate electrode, and a gate insulation film between the active layer and the gate electrode. The active layer includes a channel region overlapping the gate electrode, and a drain region and a source region on respective sides of the channel region. A length of a straight line connecting the drain region and the source region by a shortest distance may be greater than a width of the gate line parallel to the straight line.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: March 17, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Joonseok Park, Jihun Lim, Myounghwa Kim, Taesang Kim, Yeonkeon Moon
  • Patent number: 10580771
    Abstract: A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FINFET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: March 3, 2020
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Qing Liu, Prasanna Khare, Nicolas Loubet
  • Patent number: 10572049
    Abstract: A display substrate, a display panel, a substrate, a touch substrate and a cutting method of the substrate are disclosed. The display substrate includes a plurality of imagined touch electrodes, a plurality of connection wires, a grounding electrode and a first cutting alignment mark. The plurality of imagined touch electrodes are located at an imagined touch zone of the display substrate; the plurality of connection wires are located at a bonding zone of the display substrate and are connected with the imagined touch electrodes; the grounding electrode is arranged at the bonding zone and is electrically connected with the a plurality of connection wires; the first cutting alignment mark is arranged at a side of the grounding electrode adjacent to the connection wires, and configured that the grounding electrode being able to be cut away from the display substrate by cutting the display substrate through the first cutting alignment mark.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: February 25, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Zhen Zhang, Sheng Wang, Lisen Wang, Peng Li
  • Patent number: 10559691
    Abstract: Methods of forming a compact FinFET OTP/MTP cell and a compact FDSOI OTP/MTP cell and resulting devices are provided. Embodiments include providing a substrate having a BOX layer; forming fins on the BOX layer with a gap in between; forming first and second gates, laterally separated, over and perpendicular to the fins; forming at least one third gate between the first and second gates and contacting the BOX layer through the gap, each third gate overlapping an end of a fin or both fins; forming a S/D region in each of the fins adjacent to the first and second gates, respectively, remote from the at least one third gate; utilizing each of the first and second gates as a WL; utilizing each third gate as a SL or connecting a SL to the S/D region; and connecting a BL to the S/D region or the at least one third gate.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: February 11, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Eng Huat Toh, Shyue Seng Tan, Elgin Kiok Boone Quek
  • Patent number: 10546853
    Abstract: A device including RM below the top surface of an HKMG structure, and method of production thereof. Embodiments include first and second HKMG structures over a portion of the substrate and on opposite sides of the STI region, the first and second HKMG structures having a top surface; and a RM over the STI region and between the first and second HKMG structures, wherein the RM is below the top surface of the first and second HKMG structures.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: January 28, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Laertis Economikos, Hui Zang, Ruilong Xie
  • Patent number: 10541329
    Abstract: Techniques related to a boosted vertical field effect transistor and method of fabricating the same are provided. A logic device can comprise a vertical field effect transistor comprising a substrate, a first epitaxial layer and a second epitaxial layer. A bottom source/drain contact can be between a top surface and the first epitaxial layer and a top source/drain contact can be between the top surface and the second epitaxial layer at respective first portions of one or more vertical fins. The logic device can also comprise a boosted bipolar junction transistor. A bipolar junction transistor contact can be between the top surface and the second epitaxial layer at respective second portions of the one or more vertical fins. The respective first portions and the respective second portions can be opposite portions of the one or more vertical fins.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: January 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Injo Ok, Choonghyun Lee, Soon-Cheon Seo, Seyoung Kim
  • Patent number: 10535664
    Abstract: A method of changing a formation rate of silicon oxide includes providing a substrate, wherein two conductive lines are disposed on the substrate and a recess is between the conductive lines. Later, a cleaning process is performed to clean the substrate and the conductive lines using diluted hydrofluoric acid. After the cleaning process, a silicon oxide layer is formed to cover a sidewall and a bottom of the recess, wherein a formation rate of the silicon oxide layer at the bottom of the recess is greater than a formation rate of the silicon oxide layer at the sidewall of the recess.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: January 14, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Po-Chun Chen, Wei-Hsin Liu, Chia-Lung Chang, Yi-Wei Chen, Han-Yung Tsai
  • Patent number: 10515968
    Abstract: Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and method of operating said memory arrays are disclosed for making a memory device.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: December 24, 2019
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: 10510618
    Abstract: A structure includes a stepped crystalline substrate that includes an upper step, a lower step, and a step rise. A first fin includes a crystalline structure having a first lattice constant. The first fin is formed over the lower step. A second fin includes a crystalline structure having a second lattice constant, the second lattice constant being different than the first lattice constant. The second fin can be formed over the upper step apart from the first fin. A second crystalline structure can be formed over the first crystalline structure and the tops of the fins aligned. The first and second fins can be made of the same material, but with different heights and different channel strain values. The first fin can be used as an NMOS fin and the second fin can be used as a PMOS fin of a CMOS FinFET.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Han Lee, Chih-Yu Ma, Shih-Chieh Chang
  • Patent number: 10504585
    Abstract: A floating body SRAM cell that is readily scalable for selection by a memory compiler for making memory arrays is provided. A method of selecting a floating body SRAM cell by a memory compiler for use in array design is provided.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: December 10, 2019
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Benjamin S. Louie, Yuniarto Widjaja, Zvi Or-Bach
  • Patent number: 10504928
    Abstract: A display panel includes a substrate having a display region and a border region adjacent to the display region; a first transistor disposed on the border region and including an active layer on the substrate; and a transparent conductive layer disposed on the border region and including an opening disposed on the active layer, wherein an opening area of the opening is larger than an area of the active layer.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: December 10, 2019
    Assignee: INNOLUX CORPORATION
    Inventors: Yi-Ling Yu, Chun-Liang Lin
  • Patent number: 10483495
    Abstract: A lighting device is provided. The lighting device may include an organic light emitting diode arranged on one surface of a first substrate, the organic light emitting diode including a first electrode, an organic light emitting layer and a second electrode, and the first electrode is made of a transparent conductive material having a resistance value of 2,800-5,500? in each pixel, and has light scattering particles dispersed therein. Thus, even when a resistor of the organic light emitting layer is removed from a pixel due to a contact between the first electrode and the second electrode, it is possible to prevent an over current from being applied to the corresponding pixel through a resistor of the first electrode.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: November 19, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Taejoon Song, Jongmin Kim
  • Patent number: 10483285
    Abstract: An element substrate and a display device are provided. The element substrate includes a substrate and an element layer, and the element layer is disposed on the substrate, wherein the element layer includes a plurality of active elements, each of the active elements includes a gate, a gate insulating layer, a metal oxide semiconductor layer, a source and a drain. The gate is disposed on the substrate. The gate insulating layer is disposed on the substrate and overlaps the gate. The metal oxide semiconductor layer is disposed on the gate insulating layer. The source and the drain are disposed on the metal oxide semiconductor layer, wherein the source and the drain respectively include a first layer and a second layer, the first layer is between the second layer and the metal oxide semiconductor layer, and the material of the first layer includes titanium nitride.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: November 19, 2019
    Assignee: Innolux Corporation
    Inventor: Wang-Cheng Chung
  • Patent number: 10466527
    Abstract: A display device is provided. The display device includes a first base substrate, a gate line on the first base substrate and extending in a first direction, a data line disposed on the first base substrate, insulated from the gate line, and extending in a second direction, which crosses the first direction, a switch on the first base substrate and electrically connected to the gate line and the data line, an insulating layer on the switch, a first electrode on the insulating layer, a light-shielding conductive layer directly contacting the first electrode and overlapping the switch, and a second electrode insulated from the first electrode and the light-shielding conductive layer, at least partially overlapping the first electrode, and electrically connected to the switch.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: November 5, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Dong Ju Yang, Seul Ki Kim, Hyun Jung Lee, Hyo Jin Kim, Kap Soo Yoon, Jeong Hyun Lee, Yun Seok Han, Jeong Uk Heo
  • Patent number: 10468599
    Abstract: A method of patterning organic semiconductor layers is disclosed. In one aspect, a method for forming a patterned organic semiconductor layer on a substrate includes providing a plurality of first electrodes on a substrate. The method additionally includes providing a patterned self-assembling monolayer at predetermined locations on each of the plurality of first electrodes. The method further includes providing a layer comprising an organic semiconductor material over the patterned self-assembling monolayer. A corresponding device and a photovoltaic module comprising such a device are also disclosed.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: November 5, 2019
    Assignee: IMEC vzw
    Inventor: David Cheyns
  • Patent number: 10461138
    Abstract: An organic light-emitting display device and a manufacturing method thereof are provided by the embodiments of the present disclosure, and the organic light-emitting display device includes: a substrate; a plurality of pixel definition strips disposed on the substrate, in which the plurality of pixel definition strips are spaced apart from and arranged in parallel with each other, and two adjacent pixel definition strips among the plurality of pixel definition strips and a portion of the substrate between the two adjacent pixel definition strips constitute a pixel definition groove; and an organic light-emitting functional layer disposed in the pixel definition groove, the organic light-emitting functional layer includes a plurality of sub organic light-emitting functional layers which are insulated with each other and arranged along an extension direction of the plurality of pixel definition strips.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: October 29, 2019
    Assignee: BOE Technology Group Co., Ltd.
    Inventor: Ying Cui
  • Patent number: 10446436
    Abstract: A method of protecting a dielectric during fabrication is provided. A conductive layer is patterned to form a first conductive shape on a first portion of a dielectric layer and a second conductive shape on a second portion of the dielectric layer. A conductive trace is formed over at least a portion of the second conductive shape. The conductive trace electrically connects the first conductive shape with a substrate tie. An interconnect layer is coupled to the first conductive shape. The conductive trace is etched to electrically isolate the first conductive shape from the substrate tie.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: October 15, 2019
    Assignee: NXP USA, INC.
    Inventors: William Ernest Edwards, Brian George Anthony
  • Patent number: 10447032
    Abstract: A limiter having a more ideal limiting function, a short response time, and an adjustable limiting threshold. In one embodiment, a self-activating limiter stack is coupled between circuit ground and a signal line between a source and a receiver. The limiter stack limits the power from the source when the voltage on the signal line exceeds the breakdown voltage of the limiter stack. The threshold of the limiter stack is controlled in part by a first control voltage applied to a control input. A rectifying power detector circuit connected between a node on the signal line and the control input of the limiter stack provides a second control voltage as a function of the signal power at the node. The combined first and second control voltages are applied to the control input to modulate the ON resistance of the limiter stack, thereby limiting the leakage power reaching the protected receiver.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: October 15, 2019
    Assignee: pSemi Corporation
    Inventors: Jianhua Lu, Hojung Ju
  • Patent number: 10410582
    Abstract: A display panel includes a displaying area including pixels, a non-displaying area including a dummy pixel, and a switching circuit to transfer a data signal to the dummy pixel in response to a control signal. The display panel may compensate for defective pixels located in different data lines using only one dummy pixel column and may minimize an area (e.g., a dead space) including the dummy pixel column by including a distributor buffering a signal of an output line and a switching circuit selecting/providing a portion of a signal of the output line to a dummy data line.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: September 10, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jae-Sic Lee, Jung-Hoon Shim
  • Patent number: 10403846
    Abstract: An organic light-emitting diode (OLED) display is disclosed. In one aspect, the OLED display includes a substrate, an interlayer insulating layer arranged over the substrate and an OLED arranged over the interlayer insulating layer. The OLED display also includes a source electrode and a drain electrode arranged over the interlayer insulating layer and a via layer arranged over the interlayer insulating layer and having a via hole exposing the source electrode or the drain electrode. The interlayer insulating layer includes a projecting portion which projects toward the OLED in the via hole.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: September 3, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Juwon Yoon, Sewan Son, Iljeong Lee, Jiseon Lee, Deukmyung Ji
  • Patent number: 10381490
    Abstract: A semiconductor device includes a first transistor having a first threshold voltage, and including first channels, first source/drain layers connected to opposite sidewalls of the first channels, and a first gate structure surrounding the first channels and including a first gate insulation pattern, a first threshold voltage control pattern, and a first workfunction metal pattern sequentially stacked. The semiconductor device includes a second transistor having a second threshold voltage greater than the first threshold voltage, and including second channels, second source/drain layers connected to opposite sidewalls of the second channels, and a second gate structure surrounding the second channels and including a second gate insulation pattern, a second threshold voltage control pattern, and a second workfunction metal pattern sequentially stacked. A thickness of the second threshold voltage control pattern is equal to or less than a thickness of the first threshold voltage control pattern.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: August 13, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Jung Kim, Dong-Soo Lee, Sang-Yong Kim, Jin-Kyu Jang, Won-Keun Chung, Sang-Jin Hyun
  • Patent number: 10373981
    Abstract: A semiconductor device includes a transistor and a capacitor. The transistor includes a first conductive film; a first insulating film including a film containing hydrogen; a second insulating film including an oxide insulating film; an oxide semiconductor film including a first region and a pair of second regions; a pair of electrodes; a gate insulating film; and a second conductive film. The capacitor includes a lower electrode, an inter-electrode insulating film, and an upper electrode. The lower electrode contains the same material as the first conductive film. The inter-electrode insulating film includes a third insulating film containing the same material as the first insulating film and a fourth insulating film containing the same material as the gate insulating film. The upper electrode contains the same material as the second conductive film. A fifth insulating film containing hydrogen is provided over the transistor.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: August 6, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kenichi Okazaki, Masataka Nakada, Masahiro Katayama
  • Patent number: 10374030
    Abstract: A highly reliable semiconductor device including an oxide semiconductor is provided. Provided is a semiconductor device including an oxide semiconductor layer, an insulating layer in contact with the oxide semiconductor layer, a gate electrode layer overlapping with the oxide semiconductor layer, and a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer. The oxide semiconductor layer includes a first region having a crystal whose size is less than or equal to 10 nm and a second region which overlaps with the insulating layer with the first region provided therebetween and which includes a crystal part whose c-axis is aligned in a direction parallel to a normal vector of the surface of the oxide semiconductor layer.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: August 6, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiro Takahashi, Takuya Hirohashi, Masashi Tsubuku, Masashi Oota
  • Patent number: 10361183
    Abstract: The electrostatic protective device includes an insulator and a semiconductor layer. The semiconductor layer includes a device forming region and a device separating region. The device forming region includes a primary first conductive impurity diffused layer, a body region, a secondary first conductive impurity diffused layer, and a second conductive region that are arranged in order. The second conductive region includes a second conductive impurity diffused layer separated electrically from the body region. The device separating region includes a device separating layer that surrounds the device forming region. A gate electrode is further provided on the body region in the semiconductor layer with an insulating film interposed in between.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: July 23, 2019
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Hideki Mori
  • Patent number: 10345657
    Abstract: A pixel structure is disclosed. The pixel structure includes first transparent conductive films that are arranged on color-resists of a color filter substrate, and second transparent conductive films that are arranged on sub pixel regions of an array substrate and correspond to the first transparent conductive films. The first transparent conductive films are connected with one another. An area of an orthographic projection of each first transparent conductive film on a corresponding second transparent conductive film is equal to an area of the second transparent conductive film. According to the present disclosure, the pixel structure has a higher light transmittance.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: July 9, 2019
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventors: Xiaohui Yao, Bangyin Peng
  • Patent number: 10340269
    Abstract: An embodiment is a method of manufacturing a semiconductor device, the method including forming a first gate over a substrate, forming a recess in the substrate adjacent the first gate, epitaxially forming a strained material stack in the recess, the strained material stack comprising at least three layers, each of the at least three layers comprising a dopant. The method further includes co-implanting the strained material stack with dopants comprising boron, germanium, indium, tin, or a combination thereof, forming a metal layer on the strained material stack, and annealing the metal layer and the strained material stack forming a metal-silicide layer.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: July 2, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Ming-Te Chen
  • Patent number: 10340365
    Abstract: A method of manufacturing a thin film transistor is provided, and includes: providing a substrate; depositing a buffer layer and patterning the buffer layer; sequentially depositing an insulation layer and a first metal layer, coating a photoresist on the first metal layer; metal etching the first metal layer; ashing the photoresist; metal etching the first metal layer of the lightly doped region; implanting ions to an active area; and removing the photoresist.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: July 2, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOG CO. LTD
    Inventor: Macai Lu
  • Patent number: 10332954
    Abstract: A semiconductor device and a manufacturing method thereof, the semiconductor device including an insulation layer; a metal resistance pattern on the insulation layer; a spacer on a side wall of the metal resistance pattern; and a gate contact spaced apart from the spacer, the gate contact extending into the insulation layer, wherein the insulation layer includes a projection projecting therefrom, the projection contacting the gate contact.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: June 25, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung Hun Choi, Young Tak Kim, Da Il Eom, Sun Jung Lee
  • Patent number: 10331001
    Abstract: A manufacturing method of a TFT substrate uses a bottom gate structure and the entire process can be completely done with seven masks. The number of masks used is reduced. The manufacturing process of a TFT substrate is simplified. Product yield and increase productivity are effectively improved. By subjecting two ends of a semiconductor pattern to heavy ion doping to form a source electrode and a drain electrode, the manufacturing steps can be reduced and the source electrode and the drain electrode so formed do not need to extend through a via hole formed in an interlayer dielectric layer to get in connection with the two ends of the active layer so as to effectively reduce contact resistance and improve product yield. Also provided is a TFT substrate manufactured with the method.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: June 25, 2019
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Yuanfu Liu
  • Patent number: 10325937
    Abstract: The present disclosure relates to a thin film transistor substrate having two different types of thin film transistors on the same substrate. A thin film transistor substrate includes a substrate; a first thin film transistor disposed on the substrate, the first thin film transistor including a poly crystalline semiconductor layer, a first gate electrode over the poly crystalline semiconductor layer, a first source electrode, and a first drain electrode; a second thin film transistor disposed on the substrate, the second thin film transistor including a second gate electrode, an oxide semiconductor layer over the second gate electrode, a second source electrode, and a second drain electrode; and an intermediate insulating layer including a nitride layer and an oxide layer on the nitride layer, the intermediate insulating layer disposed over the first gate electrode and the second gate electrode and under the oxide semiconductor layer.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: June 18, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Youngjang Lee, Kyungmo Son, Sohyung Lee, Moonho Park, Sungjin Lee
  • Patent number: 10304964
    Abstract: A semiconductor device includes a first transistor, a second transistor and a third transistor provided on a substrate, the first to third transistors respectively including source and drain regions spaced apart from each other, a gate structure extending in a first direction on the substrate and interposed between the source and drain regions, and a channel region connecting the source and drain regions to each other. A channel region of the second transistor and a channel region of the third transistor respectively include a plurality of channel portions, the plurality of channel portions spaced apart from each other in a second direction, perpendicular to an upper surface of the substrate, and connected to the source and drain regions, respectively. A width of a channel portion of the third transistor in the first direction is greater than a width of a channel portion of the second transistor in the first direction.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: May 28, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Mongsong Liang, Sung-Dae Suk, Guemjong Bae
  • Patent number: 10304895
    Abstract: A method for manufacturing a solid-state image pickup apparatus includes forming a first insulating film over a substrate after forming a gate electrode of a first transfer transistor and a gate electrode of a second transfer transistor, forming a second insulating film on the first insulating film, forming a first structure and a second structure on side surfaces of the gate electrodes of the first and second transfer transistors, respectively, via the first insulating film by etching the second insulating film in such a manner that the first insulating film remains on a semiconductor region of a photoelectric conversion unit and a semiconductor region of a charge holding unit, and forming a light shielding film that covers the gate electrode of the first transfer transistor, the semiconductor region of the charge holding unit, and the gate electrode of the second transfer transistor.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: May 28, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shunsuke Nakatsuka, Kentaro Suzuki, Mari Isobe, Masatsugu Itahashi, Yasuhiro Sekine, Sho Suzuki
  • Patent number: 10304772
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate, a gate stack, and an interconnect structure over the gate stack and the semiconductor substrate. The semiconductor device structure also includes a resistive element over the interconnect structure, and the resistive element is directly above the gate stack. The semiconductor device structure further includes a thermal conductive element over the interconnect structure. A direct projection of the thermal conductive element on a main surface of the resistive element extends across a portion of a first imaginary line and a portion of a second imaginary line of the main surface. The first imaginary line is perpendicular to the second imaginary line. The first imaginary line and the second imaginary line intersect at a center of the main surface. The semiconductor device structure includes a dielectric layer separating the thermal conductive element from the resistive element.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: May 28, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wan-Te Chen, Chung-Hui Chen, Wei-Chih Chen, Chii-Ping Chen, Wen-Sheh Huang, Bi-Ling Lin, Sheng-Feng Liu
  • Patent number: 10297445
    Abstract: A substrate includes a support structure comprising: a polycrystalline ceramic core; a first adhesion layer coupled to the polycrystalline ceramic core; a conductive layer coupled to the first adhesion layer; a second adhesion layer coupled to the conductive layer; and a barrier layer coupled to the second adhesion layer. The substrate also includes a silicon oxide layer coupled to the support structure, a substantially single crystalline silicon layer coupled to the silicon oxide layer, and an epitaxial III-V layer coupled to the substantially single crystalline silicon layer.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: May 21, 2019
    Assignee: Qromis, Inc.
    Inventors: Vladimir Odnoblyudov, Cem Basceri, Shari Farrens
  • Patent number: 10290698
    Abstract: An illustrative method includes, among other things, forming a plurality of fins. A subset of the plurality of fins is selectively removed, leaving at least a first fin to define a first fin portion and at least a second fin to define a second fin portion. A first type of dopant is implanted into a substrate to define a resistor body and the first type of dopant is implanted into the first and second fins. The first fin portion is disposed above a first end of the resistor body and the second fin is disposed above a second end of the resistor body. An insulating layer is formed above the resistor body. At least one gate structure is formed above the insulating layer and above the resistor body.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: May 14, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Jagar Singh
  • Patent number: 10283527
    Abstract: An SOI substrate having a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and a semiconductor layer formed on the insulating layer is provided. A first region is one for forming a low breakdown voltage MISFET in the semiconductor layer, and a second region, in which the insulating layer and the semiconductor layer have been removed, is one for forming a high breakdown voltage MISFET. After an n-type semiconductor region is formed in the second region and an n-type extension region is formed in the first region, a first heat treatment is performed on the semiconductor substrate. Thereafter, a diffusion layer is formed in each of the first and second regions, and then a second heat treatment is performed on the semiconductor substrate. Herein, the time for which the first heat treatment is performed is longer than the time for which the second heat treatment is performed.
    Type: Grant
    Filed: March 10, 2018
    Date of Patent: May 7, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yoshiki Yamamoto
  • Patent number: 10268094
    Abstract: An array substrate, a display panel and a method of manufacturing array substrate are provided. The array substrate, comprising first substrate and data line, data line positioned on first substrate; auxiliary electrode positioned on first substrate, auxiliary electrode for electrically connecting to color filter, vertical projection of auxiliary electrode on first substrate does not intersect with data line; insulating layer positioned on surface of auxiliary electrode which away first substrate, insulating layer has hole; and shielding electrode comprises main section and protrusion section are integrated, main section is located on lateral side of data line which away first substrate, and vertical projection of main section on first substrate is covering data line, protrusion section is positioned on insulating layer, and protrusion section pass through hole and contacting to auxiliary electrode. It achieves to highly product yield and saving production costs.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: April 23, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Zhuming Deng, Minggang Liu
  • Patent number: 10262898
    Abstract: A silicon on insulator substrate includes a semiconductor bulk handle wafer, an insulating layer on said semiconductor bulk handle wafer and a semiconductor film on said insulating layer. An opening extends completely through the semiconductor film and insulating layer to expose a surface of the semiconductor bulk handle wafer. Epitaxial material fills the opening and extends on said semiconductor film, with the epitaxial material and semiconductor film forming a thick semiconductor film. A trench isolation surrounds a region of the thick semiconductor film to define an electrical contact made to the semiconductor bulk handle wafer through the opening.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: April 16, 2019
    Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Didier Dutartre, Jean-Pierre Carrere, Jean-Luc Huguenin, Clement Pribat, Sarah Kuster