With Means To Increase Breakdown Voltage (e.g., Field Shield Electrode, Guard Ring, Etc.) Patents (Class 257/409)
  • Patent number: 10770599
    Abstract: Apparatus and other embodiments associated with high speed and high breakdown voltage rectifier are disclosed. A Junction All Around structure, where a deep trench structure surrounds and encloses a P-N junction or a MOS structure, is created and applied in various rectifiers. In one embodiment, multiple deep trenches in ring shape enclosed a vertical P-N junction. For each deep trench, a corresponding wider ring-shape P+ region is created on top of a N? epi layer. This enclosed deep trench surrounding a vertical P-N junction and a thinner N? epitaxial layer allow higher reverse bias voltage and low leakage current. In another embodiment, an enclosed deep trench in ring shape surrounds a horizontal P-N junction, which results in a planar N-channel MOS during forward bias. The structure can be extended to multiple deep trenches with associated horizontal P-N junctions.
    Type: Grant
    Filed: December 23, 2017
    Date of Patent: September 8, 2020
    Assignees: Champion Microelectronic Corp., Yutechnix, Inc.
    Inventors: Haiping Dun, Ho-Yuan Yu, Hung-Chen Lin
  • Patent number: 10700198
    Abstract: A semiconductor device includes a substrate, a first P-type well region and a second P-type well region disposed in the substrate, wherein the first P-type well region and the second P-type well region are spaced apart from each other, an N-type source region disposed in the substrate, wherein the N-type source region is disposed spaced apart from the second P-type well region, an N-type drain region disposed in the second P-type well region, an N-type LDD region disposed near the N-type drain region, and a gate insulating layer and a gate electrode on the substrate, wherein the gate electrode partially overlaps the second P-type well region.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: June 30, 2020
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Jae Hyung Jang, Jin Yeong Son, Hee Hwan Ji
  • Patent number: 10686071
    Abstract: A semiconductor device including a first P-type well region and an asymmetric second P-type well region each formed in a semiconductor substrate; a gate insulating layer and a gate electrode formed on the substrate; a first N-type source/drain region and a second N-type source/drain region that are formed on respective sides of the gate electrode; and an asymmetric LDD region of N-type formed to extend from the second source/drain region, wherein the asymmetric second P-type well region encompasses the second N-type source/drain region and the asymmetric LDD region, and the first N-type source/drain region both the asymmetric second P-type well region and the substrate, and the asymmetric second P-type well region is formed encompassing the second N-type source/drain region and in contact with the first N-type source/drain region.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: June 16, 2020
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Jae Hyung Jang, Hee Hwan Ji, Jin Yeong Son
  • Patent number: 10686035
    Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: June 16, 2020
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Hamza Yilmaz, Daniel Ng, Lingping Guan, Anup Bhalla, Wilson Ma, Moses Ho, John Chen
  • Patent number: 10680098
    Abstract: An LDMOS device in FinFET technology is disclosed. In one aspect, the device includes a first region substantially surrounded by a second region of different polarity. The device further includes a first fin in the first region, extending into the second region, the first fin including a doped source region connected with a first local interconnect. The device further includes a second fin in the second region, including a doped drain region connected with a second local interconnect. The device further includes a third fin parallel with the first and second fins including a doped drain region connected with the second local interconnect. The device further includes a gate over the first fin at the border between the first and second regions. A first current path runs over the first and second fins. A second current path runs over and perpendicular to the first fin towards the third fin.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: June 9, 2020
    Assignee: IMEC vzw
    Inventors: Shih-Hung Chen, Dimitri Linten, Geert Hellings
  • Patent number: 10665712
    Abstract: An LDMOS device with a field plate contact having a field plate contact metal layer being positioned above the field plate contact. The field plate contact metal layer has a sub-maximum size satisfied for the electrical connection between the field plate contact and an external applying voltage. This sub-maximum size is prescribed by the physical limitation of the LDMOS device. The field plate contact metal layer extends a sub-maximum length from one edge toward to the other edge of the field plate contact.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: May 26, 2020
    Assignee: Monolithic Power Systems, Inc.
    Inventors: Eric Braun, Joel McGregor, Jeesung Jung
  • Patent number: 10630280
    Abstract: A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGS type, or a mix of positive-logic and zero VGS type FETs with end-cap FETs of the zero VGS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: April 21, 2020
    Assignee: pSemi Corporation
    Inventors: Simon Edward Willard, Tero Tapio Ranta
  • Patent number: 10553689
    Abstract: Embodiments of the invention include a high voltage transistor with one or more field plates and methods of forming such transistors. According to an embodiment, the transistor may include a source region, a drain region, and a gate electrode formed over a channel region formed between the source region and drain region. Embodiments of the invention may also include a first interlayer dielectric (ILD) formed over the channel region and a second ILD formed over the first ILD. According to an embodiment, a first field plate may be formed in the second ILD. In an embodiment the first field plate is not formed as a single bulk conductive feature with the gate electrode. In some embodiments, the first field plate may be electrically coupled to the gate electrode by one or more vias. In alternative embodiments, the first field plate may be electrically isolated from the gate electrode.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: February 4, 2020
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Sansaptak Dasgupta, Marko Radosavljevic, Sanaz K. Gardner, Seung Hoon Sung
  • Patent number: 10483348
    Abstract: A semiconductor device has transistors formed on a substrate and including first and second impurity regions of a first conductivity type, a guard ring of a second conductivity type formed on the substrate and surrounding the transistors in a plan view, a wiring formed on and electrically connected to the guard ring, and a ground wiring faulted on the wiring and electrically connected to the wiring and the second impurity region. In a plan view, the transistor includes a first part having a distance that is a first distance from the guard ring, and a second part having a distance that is a second distance shorter than the first distance from the guard ring. In a plan view, the first part is located at a position separated from the ground wiring, and the second part is located at a position overlapping the ground wiring.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: November 19, 2019
    Assignee: SOCIONEXT, INC.
    Inventor: Hidetoshi Tanaka
  • Patent number: 10483387
    Abstract: A lateral/vertical device is provided. The device includes a device structure including a device channel having a lateral portion and a vertical portion. The lateral portion of the device channel can be located adjacent to a first surface of the device structure, and one or more contacts and/or a gate can be formed on the first surface. The device structure also includes a set of insulating layers located in the device structure between the lateral portion of the device channel and a second surface of the device structure opposite the first surface. An opening in the set of insulating layers defines a transition region between the lateral portion of the device channel and a vertical portion of the device channel. A contact to the vertical portion of the device channel can be located on the second surface.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: November 19, 2019
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Grigory Simin, Mikhail Gaevski, Michael Shur, Remigijus Gaska
  • Patent number: 10468480
    Abstract: Provided is a MOSFET which includes: a semiconductor base substrate having an n-type column region and a p-type column region, a base region and a source region, wherein a super junction structure is formed of the n-type column region and the p-type column region; a trench having side walls and a bottom; a gate electrode formed in the trench by way of a gate insulation film; a carrier compensation electrode positioned between the gate electrode and the bottom of the trench; an insulation region separating the carrier compensation electrode from the side walls and the bottom; and a source electrode electrically connected to the source region and also electrically connected to the carrier compensation electrode. According to the MOSFET of the present invention, even when an irregularity in a charge balance occurs around the gate, an irregularity in switching characteristics when the MOSFET is turned off can be decreased.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: November 5, 2019
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Daisuke Arai, Mizue Kitada
  • Patent number: 10431525
    Abstract: Implementations of semiconductor devices may include: a first layer with a plurality of cells, each cell having a drain finger, a source finger and a gate ring; a second layer having a drain pad and a source pad, the drain pad having a width and a source pad having a width substantially the same as the drain pad; wherein a width of each drain finger of the first layer is wider than a width of each source finger of the first layer; and wherein each drain pad is coupled to each drain finger through a first contact and the source pad is coupled to each source finger through a second contact, where a width of the first contact is wider than a width of the second contact.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: October 1, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Woochul Jeon, Chun-Li Liu
  • Patent number: 10418480
    Abstract: A semiconductor device capable of high-voltage operation includes a semiconductor substrate having a first conductivity type. A first well doped region is formed in the semiconductor substrate, having a second conductivity type that is the opposite of the first conductivity type. A first doped region and a second doped region are formed on the first well doped region, having the second conductivity type. A first gate structure is formed over the first well doped region and adjacent to the first doped region. A second gate structure overlaps the first gate structure and the first well doped region. A third gate structure is formed beside the second gate structure and close to the second doped region. The top surface of the first well doped region between the second gate structure and the third gate structure avoids having any gate structure and silicide formed thereon.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: September 17, 2019
    Assignee: MediaTek Inc.
    Inventors: Chu-Wei Hu, Cheng Hua Lin
  • Patent number: 10411095
    Abstract: A semiconductor integrated circuit includes a first conduction-type semiconductor region, a second conduction-type first impurity region, and a guard ring formed using a first conduction-type second impurity region so as to form a protection device of an electrostatic protection circuit. The first impurity region is formed inside the semiconductor region to have a rectangular planar structure with long and short sides. The guard ring is formed inside the semiconductor region to surround the periphery of the first impurity region. A weak spot is formed on the short side of the rectangular planar structure of the first impurity region. A plurality of electrical contacts are formed in a first portion of the guard ring which faces the long side of the rectangle. A plurality of electrical contracts are not formed in a second portion of the guard ring which faces the weak spot formed on the short side of the rectangle.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: September 10, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Akihiko Yoshioka
  • Patent number: 10340347
    Abstract: A semiconductor device includes a first gate electrode, a plurality of first source electrodes, a second gate electrode, and a plurality of second source electrodes. The first gate electrode is arranged with no other electrode between the first gate electrode and a first short side of the semiconductor substrate. The plurality of first source electrodes include a plurality of approximately rectangular first source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate. The second gate electrode is arranged with no other electrode between the second gate electrode and a second short side of the semiconductor substrate. The plurality of second source electrodes include a plurality of approximately rectangular second source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: July 2, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Kazuma Yoshida, Takeshi Imamura, Toshikazu Imai, Ryosuke Okawa, Ryou Kato
  • Patent number: 10276652
    Abstract: A schottky diode includes a schottky junction, an ohmic junction, a first isolation structure and a plurality of doped regions. The schottky junction includes a first well in a substrate and a first electrode contacting the first well. The ohmic junction includes a junction region in the first well and a second electrode contacting the junction region. The first isolation structure is disposed in the substrate and separates the schottky junction from the ohmic junction. The doped regions are located in the first well and under the schottky junction, wherein the doped regions separating from each other constitute a top-view profile of concentric circles.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: April 30, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Cheng-Hua Yang, Ke-Feng Lin, Ming-Tsung Lee, Shih-Teng Huang, Chih-Chung Wang, Chiu-Te Lee, Shu-Wen Lin
  • Patent number: 10256337
    Abstract: A device includes a transistor formed on a substrate. The transistor includes an n-type drain contact layer, an n-type drain layer, an oxide layer, a p-type body region, a p-type terminal region, body trenches, and terminal trenches. The n-type drain contact layer is near a bottom surface of the substrate. The n-type drain layer is positioned on the n-type drain contact layer. The oxide layer circumscribes a transistor region. The p-type body region is positioned within the transistor region. The p-type terminal region extends from under the oxide layer to an edge of the transistor region, thereby forming a contiguous junction with the p-type body region. The body trenches is within the transistor region and interleaves with the p-type body region, whereas the terminal trenches is outside the transistor region and interleaves with the p-type terminal region.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: April 9, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hideaki Kawahara, Christopher Boguslaw Kocon, Seetharaman Sridhar, Simon John Molloy, Satoshi Suzuki
  • Patent number: 10249725
    Abstract: A semiconductor device includes an active layer, a source electrode, a drain electrode, a gate electrode, a first insulating layer, a gate metal layer, a via, a first source metal layer, a drain metal layer, and a second source metal layer. The source electrode, the drain electrode, and the gate electrode are present on the active layer. The first insulating layer is present on the source electrode, the drain electrode, and the gate electrode. The gate metal layer, the first source metal layer, the second source metal layer, and the drain metal layer are present on the first insulating layer. The gate metal layer includes a narrow portion and a wider portion. The via is present between the metal gate layer and the gate electrode. The second source metal layer is present between the gate metal layer and the drain metal layer.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: April 2, 2019
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Li-Fan Lin, Chun-Chieh Yang
  • Patent number: 10204980
    Abstract: A semiconductor device may include an element region and a peripheral voltage withstanding region. The peripheral voltage withstanding region includes inner circumferential guard rings; and outer circumferential guard rings having a width narrower than a width of the inner circumferential guard rings. An interval between the inner circumferential guard rings is narrower than an interval between the outer circumferential guard rings. Each of the inner circumferential guard rings includes a first high concentration region and a first low concentration region. Each of the outer circumferential guard rings includes a second high concentration region and a second low concentration region. A width of a part of each first low concentration region that is exposed on a front surface of the semiconductor device is wider than a width of a part of each second low concentration region that is exposed on the front surface.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: February 12, 2019
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Yoshifumi Yasuda, Tatsuji Nagaoka, Yasushi Urakami, Sachiko Aoi
  • Patent number: 10103260
    Abstract: A semiconductor device including a first P-type well region and an asymmetric second P-type well region each formed in a semiconductor substrate; a gate insulating layer and a gate electrode formed on the substrate; a first N-type source/drain region and a second N-type source/drain region that are formed on respective sides of the gate electrode; and an asymmetric LDD region of N-type formed to extend from the second source/drain region, wherein the asymmetric second P-type well region encompasses the second N-type source/drain region and the asymmetric LDD region, and the first N-type source/drain region both the asymmetric second P-type well region and the substrate, and the asymmetric second P-type well region is formed encompassing the second N-type source/drain region and in contact with the first N-type source/drain region.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: October 16, 2018
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Jae Hyung Jang, Hee Hwan Ji, Jin Yeong Son
  • Patent number: 10084079
    Abstract: A semiconductor device includes a first well disposed in a substrate and including a first impurity of a first conductivity type, a second well disposed in the substrate, including a second impurity of a second conductivity type different from the first conductivity type, and having first to third portions, and a gate structure formed on the first well and the second well, wherein the second portion is disposed between the first portion and the third portion, the first portion and the third portion are formed deeper than the second portion, and concentration of the second impurity of the first portion and the third portion is greater than concentration of the second impurity of the second portion.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: September 25, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hyun Yoo, Kwan-Young Kim, Jin-Hyun Noh, Kee-Moon Chun, Yong-Woo Jeon
  • Patent number: 10066164
    Abstract: The present invention relates to the use of light-converting, colloidal, doped semiconductor nanocrystals to provide a new generation of high performance, low cost monochromatic and white light sources based on LEDs.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: September 4, 2018
    Inventors: Tiecheng Qiao, David Battaglia, Suresh Sunderrajan, Qiang Zhang, Haoguo Zhu
  • Patent number: 10043804
    Abstract: A method of manufacturing a semiconductor device is provided. The device includes a substrate including a first type region and a second type region, first and second fins protruding from the substrate and separated by a trench. The first fin includes first and second portions of the first type on the first region and a third portion of the second type on the second region. A first gate structure surrounds the second portion and the third portion. A first work function adjusting layer is on the gate insulator layer on the first and second portions. A second work function adjusting layer is on the first work function adjusting layer, the gate insulator layer on the third portion, and the first insulator layer. The device also includes a gate on the second work function adjusting layer, a hardmask layer on the gate, and an interlayer dielectric layer surrounding the gate structure.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: August 7, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Fei Zhou
  • Patent number: 10038064
    Abstract: A nitride semiconductor device includes: a nitride semiconductor layer; a gate electrode finger having at least one end portion, and extending along a surface of the nitride semiconductor layer; and a drain electrode finger having at least one end portion on the same side as that of the one end portion of the gate electrode finger, and extending along the gate electrode finger, wherein the one end portion of the drain electrode finger protrudes relative to the one end portion of the gate electrode finger.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: July 31, 2018
    Assignee: ROHM CO., LTD.
    Inventor: Taketoshi Tanaka
  • Patent number: 10014231
    Abstract: A first set of test structures for a gallium nitride (GaN) transistor that includes N field plates is disclosed, where N is an integer and X is an integer between 0 and N inclusive. A test structure TSX of the first set of test structures includes a GaN substrate, a dielectric material overlying the GaN substrate, a respective source contact abutting the GaN substrate and a respective drain contact abutting the GaN substrate. The test structure TSX also includes a respective gate overlying the substrate and lying between the respective source contact and the respective drain contact and X respective field plates corresponding to X of the N field plates of the GaN transistor, the X respective field plates including field plates that are nearest to the GaN substrate.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: July 3, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Dong Seup Lee, Jungwoo Joh, Sameer Pendharkar
  • Patent number: 9926643
    Abstract: Disclosed herein is a multilayer nanocrystal structure comprising a nanocrystal alloy core comprising two or more nanocrystals and including an alloy interlayer formed at an interface between the two or more nanocrystals, and one or more layers of nanocrystal shells formed sequentially on the surface of the nanocrystal alloy core, wherein the nanocrystal shells each have different band gaps. The multilayer nanocrystal structure can be applied to various electronic devices owing to its advantages of high luminescence efficiency, superior optical stability, and superior chemical stability.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: March 27, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun Joo Jang, Shin Ae Jun, Jung Eun Lim, Hye Ran Choi
  • Patent number: 9899468
    Abstract: A method of making a capacitor with reduced variance comprises providing a bottom plate in a first metal layer, a first dielectric material over the bottom plate, and a middle plate in a second metal layer to form a first capacitor. The method also comprises measuring the capacitance of the first capacitor, and determining whether to couple none, one, or both of a second capacitor and a third capacitor in parallel with the first capacitor. The method may further comprise the steps of providing a second dielectric material over the middle plate, and providing a first top plate and a second top plate in a third metal layer to form the second capacitor, and a third capacitor. Electrical connections may be formed to couple one or both of the second capacitor and the third capacitor in parallel with the first capacitor based on the measured value of the first capacitor.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: February 20, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Peter J. Zampardi, Brian Moser
  • Patent number: 9852945
    Abstract: A semiconductor device is manufactured at least partially in a semiconductor substrate. The substrate has first and second opposing main surfaces. The method includes forming a cell field portion and a contact area, the contact area being electrically coupled to the cell field portion, and forming the cell field portion by at least forming a transistor. The method further includes insulating a part of the semiconductor substrate from other substrate portions to form a connection substrate portion, forming an electrode adjacent to the second main surface so as to be in contact with the connection substrate portion, forming an insulating layer over the first main surface, forming a metal layer over the insulating layer, forming a trench in the first main surface, and filling the trench with a conductive material, and electrically coupling the connection substrate portion to the metal layer via the trench.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: December 26, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Andreas Meiser, Till Schloesser, Martin Poelzl
  • Patent number: 9847411
    Abstract: A transistor device including a field plate is described. One embodiment of such a device includes a field plate separated from a semiconductor layer by a thin spacer layer. In one embodiment, the thickness of spacer layer separating the field plate from the semiconductor layers is less than the thickness of spacer layer separating the field plate from the gate. In another embodiment, the non-zero distance separating the field plate from the semiconductor layers is about 1500 ? or less. Devices according to the present invention can show capacitances which are less drain bias dependent, resulting in improved linearity.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: December 19, 2017
    Assignee: CREE, INC.
    Inventors: Saptharishi Sriram, Terry Alcorn, Fabian Radulescu, Scott Sheppard
  • Patent number: 9837366
    Abstract: A semiconductor structure has a semiconductor device, a first seal ring, and a second seal ring. The semiconductor device has a first surface and a second surface opposite to the first surface. The first seal ring is disposed on the first surface of the semiconductor device and adjacent to edges of the first surface. The second seal ring is disposed on the second surface of the semiconductor device and adjacent to edges of the second surface. A semiconductor manufacturing process is also provided.
    Type: Grant
    Filed: December 25, 2016
    Date of Patent: December 5, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hsun Liu, Chin-Yu Ku, Rung-De Wang, Wei-Lun Hsieh, Chia-Hua Wang, Jheng-Hong Chen, Pei-Shing Tsai
  • Patent number: 9837275
    Abstract: This invention involves a fabrication method of fast recovery diode, which includes following steps: growing a sacrificial oxide layer on a surface of an N? substrate; forming a P type doped field-limiting ring region on the substrate; forming a P type doped anode region on the substrate; removing the sacrificial oxide layer; annealing the substrate to form a PN junction; implanting oxygen into the surface of the substrate by ion implantation; annealing the substrate to form a silicon dioxide layer on the surface of the substrate; removing the silicon dioxide layer; forming an anode electrode and a cathode electrode of the fast recovery diode. The method eliminates the curved parts near the silicon surface of the profile of PN junction, decreases electric field intensity at the surface of the substrate, therefore increases the breakdown voltage and reliability of the fast recovery diode.
    Type: Grant
    Filed: December 10, 2013
    Date of Patent: December 5, 2017
    Assignee: SHANGHAI IC R&D CENTER CO., LTD
    Inventors: Quan Wang, Jieqiong Dong, Deming Sun, Wei Zhou
  • Patent number: 9831232
    Abstract: An electrostatic protection includes a buried layer having an outer region and an inner region which are heavily doped regions of a first conductivity type. The inner region is surrounded by an undoped or lightly doped ring region. The ring region is surrounded by the outer region. The device further includes a semiconductor region over the buried layer, a first well of the first conductivity type in the semiconductor region, a first transistor in the semiconductor region, and a second transistor in the semiconductor region. The first well forms a collector of the first transistor and a collector of the second transistor.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: November 28, 2017
    Assignee: NXP USA, Inc.
    Inventors: Changsoo Hong, Patrice Besse, Jean Philippe Laine, Rouying Zhan
  • Patent number: 9818742
    Abstract: An isolation structure prevents inter-device and intra-device leakage in first and second adjacent semiconductor devices in a substrate. The first and second semiconductor devices each include a gate region and at least one active region. A first channel stop region is configured to surround the first semiconductor device. A second channel stop region is configured to surround the second semiconductor device. A first field plate is located above at least part of the first channel stop region, and overlaps the gate region of the first semiconductor device in a first overlap region. A second field plate is located above at least part of the second channel stop region, and overlaps the gate region of the second semiconductor device in a second overlap region.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: November 14, 2017
    Assignee: POLAR SEMICONDUCTOR, LLC
    Inventor: William Larson
  • Patent number: 9773877
    Abstract: A field effect transistor comprising a buffer and channel layer formed successively on a substrate. A source electrode, drain electrode, and gate are all formed in electrical contact with the channel layer, with the gate between the source and drain electrodes. A spacer layer is formed on at least a portion of a surface of the channel layer between the gate and drain electrode and a field plate is formed on the spacer layer isolated from the gate and channel layer. The spacer layer is electrically connected by at least one conductive path to the source electrode, wherein the field plate reduces the peak operating electric field in the MESFET.
    Type: Grant
    Filed: October 4, 2004
    Date of Patent: September 26, 2017
    Assignee: CREE, INC.
    Inventors: Yifeng Wu, Primit Parikh, Umesh Mishra, Marcia Moore
  • Patent number: 9748181
    Abstract: An example apparatus includes a plurality of scribe streets arranged in rows and columns on the surface of a semiconductor wafer; and a plurality of integrated circuit dies arranged in rows and columns and spaced apart by the scribe streets. Each integrated circuit die includes plurality of active areas; a plurality of insulator layers overlying the active areas; a plurality of conductor layers interspersed with and separated by ones of the insulator layers; and a passivation layer overlying a top portion of the uppermost one of the conductor layers. A scribe seal in a scribe region surrounds the periphery of the integrated circuit dies, the scribe seal covered by the passivation layer; and a crack arrest structure is located surrounding and spaced from the scribe seal, and including an opening in the passivation layer that extends to and exposes the upper surface of the crack arrest structure. Methods are disclosed.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: August 29, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ricky Alan Jackson, Sudtida Lavangkul, Erika Lynn Mazotti
  • Patent number: 9728474
    Abstract: A semiconductor chip includes an active area including a plurality of integrated circuit structures, a seal ring enclosing the active area, a corner area of the semiconductor chip that is outside of the seal ring, and an electronic test structure disposed within the corner area. Semiconductor wafers including the above-noted semiconductor chips, as well as methods for fabricating semiconductor wafers including the above-noted semiconductor chips, are also disclosed.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: August 8, 2017
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Wanbing Yi, Juan Boon Tan, Mahesh Bhatkar, Danny Pak-Chum Shum
  • Patent number: 9679981
    Abstract: A multi-stage transistor device is described. One embodiment of such a device is a dual-gate transistor, where the second stage gate is separated from a barrier layer by a thin spacer layer and is grounded through a connection to the source. In one embodiment the thin spacer layer and the second stage gate are placed in an aperture in a spacer layer. In another embodiment, the second stage gate is separated from a barrier layer by a spacer layer. The device can exhibit improved linearity and reduced complexity and cost.
    Type: Grant
    Filed: June 9, 2013
    Date of Patent: June 13, 2017
    Assignee: CREE, INC.
    Inventors: Saptharishi Sriram, Terry Alcorn, Fabian Radulescu, Scott Sheppard
  • Patent number: 9673154
    Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: June 6, 2017
    Assignee: PANASONIC CORPORATION
    Inventors: Makoto Tsutsue, Masaki Utsumi
  • Patent number: 9660073
    Abstract: A high-voltage semiconductor device is provided. The device includes a semiconductor substrate including a well region of a first conductivity type and an isolation structure in the well region. First and second regions are respectively defined on both sides of the isolation structure. First and second gate structures are respectively disposed on the first and second regions. First and second implant regions of a second conductivity type that is different from the first conductivity type are respectively in the first and second regions and adjacent to the isolation structure. A counter implant region is in the well region under the isolation structure and laterally extends under the first and second implant regions. The counter implant region has the first conductivity type and has a doping concentration that is greater than that of the well region. A method for fabricating the high-voltage semiconductor device is also disclosed.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: May 23, 2017
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chih-Wei Lin, Pi-Kuang Chuang, Chao-Wei Wu
  • Patent number: 9647064
    Abstract: A semiconductor device may include the following elements: a first n-type region; a second n-type region; a p-type region, which directly contacts each of the first n-type region and the second n-type region; a first p-type portion, which directly contacts the first n-type region; a first n-type portion, which directly contacts each of the first n-type region and the p-type region; a first electrode, which is electrically connected to each of the first p-type portion and the first n-type portion; a second p-type portion, which directly contacts the second n-type region; a second n-type portion, which directly contacts each of the second n-type region and the p-type region; and a second electrode, which is electrically connected to each of the second p-type portion and the second n-type portion.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: May 9, 2017
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Lei Zhong, Hongwei Li, Wei Lei, Huijuan Cheng
  • Patent number: 9559097
    Abstract: A semiconductor device configured with one or more integrated breakdown protection diodes in non-isolated power transistor devices and electronic apparatus, and methods for fabricating the devices.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: January 31, 2017
    Assignee: NXP USA, Inc.
    Inventors: Patrice M. Parris, Hubert M. Bode, Weize Chen, Richard J DeSouza, Andreas Laudenbach, Kurt U. Neugebauer
  • Patent number: 9536965
    Abstract: A semiconductor device comprises: a substrate; a multilayer semiconductor layer located on the substrate; a source located on the multilayer semiconductor layer, the source including a first source portion inside an active region and a second source portion inside a passive region; a drain located on the multilayer semiconductor layer, the drain including a first drain portion inside the active region and a second drain region inside the passive region; a gate located on the multilayer semiconductor layer, the gate including a first gate portion inside the active region and a second gate portion inside the passive region, and the first gate portion being in a form of interdigital among the first source portion and the first drain portion; and a heat dissipating layer disposed at one or more of the first source portion, the first drain portion, the first gate portion, the second source portion, the second drain portion and the second gate portion.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: January 3, 2017
    Assignee: DYNAX SEMICONDUCTOR, INC.
    Inventors: Yi Pei, Mengjie Zhou, Naiqian Zhang
  • Patent number: 9520493
    Abstract: A high voltage integrated device includes a semiconductor layer having a first conductivity, a source region having a second conductivity and a drift region having the second conductivity which are disposed in the semiconductor layer and spaced apart from each other by a channel region, a drain region having the second conductivity and disposed in the drift region, a gate insulation layer disposed over the channel region, a first field insulation layer and a second field insulation layer which are disposed over the drift region and between the channel region and the drain region, wherein the first field insulation layer and the second field insulation layer are spaced apart from each other, an insulation layer disposed over the drift region and located between the first and second field insulation layers, and a gate electrode disposed over the gate insulation layer, the first field insulation layer, the insulation layer, and the second field insulation layer, wherein the first field insulation layer is adjace
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: December 13, 2016
    Assignee: SK Hynix Inc.
    Inventors: Dae Hoon Kim, Se Kyung Oh
  • Patent number: 9508792
    Abstract: An electric field buffer layer is formed so as to surround an active region. The electric field buffer layer includes a plurality of P-type impurity layers. Each of the P-type impurity layers includes P-type implantation layers and P-type diffusion layers that are formed so as to respectively surround the P-type implantation layers and contain P-type impurities at a concentration lower than that of the P-type implantation layers. A first P-type implantation layer is formed to be in contact with or to partially overlap the active region. Each of the P-type diffusion layers is formed to have an expansion to a degree to which the first P-type diffusion layer is in contact with or overlaps a second P-type diffusion layer. Intervals between the P-type implantation layers increase from the active region toward the outer peripheral portion of the semiconductor substrate.
    Type: Grant
    Filed: May 1, 2013
    Date of Patent: November 29, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tsuyoshi Kawakami, Ze Chen, Akito Nishii, Fumihito Masuoka, Katsumi Nakamura, Akihiko Furukawa, Yuji Murakami
  • Patent number: 9496334
    Abstract: A semiconductor device according to an embodiment includes a first semiconductor layer of a first conductivity type, second semiconductor regions of a second conductivity type, a third semiconductor region of the second conductivity type, a fourth semiconductor region of the first conductivity type, a gate electrode, an insulating layer, and a first electrode. The first semiconductor layer includes first semiconductor regions. The second semiconductor regions are provided respectively between the first semiconductor regions. The insulating layer is provided between the gate electrode and the third semiconductor region. The first electrode includes a first portion and a second portion. The first portion is connected to the first semiconductor region. The second portion is provided on the fourth semiconductor region side of the first portion. The first electrode is provided on the first semiconductor region and on the second semiconductor region.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: November 15, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroaki Yamashita, Syotaro Ono, Hideyuki Ura, Masahiro Shimura
  • Patent number: 9472660
    Abstract: A semiconductor device including: a first conductivity type n-type drift layer; a second conductivity type VLD region which is formed on a chip inner circumferential side of a termination structure region provided on one principal surface of the n-type drift layer and which is higher in concentration than the n-type drift layer; a second conductivity type first clip layer which is formed on a chip outer circumferential side of the VLD region so as to be separated from the VLD region and which is higher in concentration than the n-type drift layer; and a first conductivity type channel stopper layer which is formed on a chip outer circumferential side of the first clip layer so as to be separated from the first clip layer and which is higher in concentration than the n-type drift layer.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: October 18, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Hong-fei Lu
  • Patent number: 9461184
    Abstract: A capacitor for a semiconductor device includes a bottom electrode plate, an insulating layer formed on the bottom electrode plate, and a top electrode plate formed on the insulating layer. The bottom plate includes a capacitor well and at least one diffused region formed on the capacitor well. A doping concentration of the at least one diffused region is higher than a doping concentration of the capacitor well, the capacitor well comprising a first well.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: October 4, 2016
    Assignee: Fitipower Integrated Technology, Inc.
    Inventors: Chun-Ping Yang, Da-Pong Zhang
  • Patent number: 9412809
    Abstract: Provided is a semiconductor device in which movable ions in an insulation layer on a main surface are reduced and dielectric strength is enhanced. A semiconductor device has a plurality of FLRs, an insulation layer, and a semiconductor layer. The plurality of FLRs surrounds, in a plan view of a substrate, an active region in which an element is formed. The insulation layer is provided on the main surface of the semiconductor device and covers the plurality of FLRs. The semiconductor layer is provided in the insulation layer and surrounds the active region in parallel to the FLRs. The semiconductor layer contains impurities at a surface density lower than a surface density that satisfies a RESURF condition. In the plan view, the semiconductor layer overlaps with a part of the region (an inter-ring region) between adjacent FLRs and does not overlap with rest of the inter-ring region.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: August 9, 2016
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Masaru Senoo
  • Patent number: 9383266
    Abstract: A field effect transistor (FET) having a source, a drain and a gate includes a first connection electrically connected to the gate near a first end of the gate, a second connection electrically connected to the gate near the first end of the gate, a third connection electrically connected to the gate near a second end of the gate, and a fourth connection electrically connected to the gate near the second end of the gate. By performing gate resistance measurements at different ambient temperatures, a thermal coefficient of gate resistance can be derived and then used to monitor the gate temperature, which is representative of the channel temperature.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: July 5, 2016
    Assignee: HRL Laboratories, LLC
    Inventors: James Chingwei Li, Tahir Hussain
  • Patent number: 9373619
    Abstract: Provided is a high voltage semiconductor device. The high voltage semiconductor device includes a substrate that includes a doped well disposed therein. The doped well and the substrate have opposite doping polarities. The high voltage semiconductor device includes an insulating device disposed over the doped well. The high voltage semiconductor device includes an elongate resistor disposed over the insulating device. A non-distal portion of the resistor is coupled to the doped well. The high voltage semiconductor device includes a high-voltage junction termination (HVJT) device disposed adjacent to the resistor.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: June 21, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Chih-Chang Cheng, Ruey-Hsin Liu