GATE STRUCTURES FOR SEMICONDUCTOR DEVICES WITH A CONDUCTIVE ETCH STOP LAYER
One illustrative gate structure of a transistor device disclosed herein includes a high-k gate insulation layer and a work function metal layer positioned on the high-k gate insulation layer. The device further includes a first bulk metal layer positioned on the work function metal layer. The device further includes a second bulk metal layer. The first and second bulk metal layers have upper surfaces that are at substantially the same height level, and the first and second bulk metal layers are made of substantially the same material. The device further includes a conductive etch stop layer between the first and second bulk metal layers.
1. Field of the Invention
The present disclosure generally relates to the formation of semiconductor devices, and, more specifically, to various novel gate structures that comprise a conductive etch stop layer positioned between two bulk metal layers.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide semiconductor field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. The transistors are typically either NMOS (NFET) or PMOS (PFET) type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices. So-called CMOS (Complementary Metal Oxide Semiconductor) technology or products refers to integrated circuit products that are manufactured using both NMOS and PMOS transistor devices.
Field effect transistors, whether an NMOS or a PMOS device, typically include a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. For an NMOS device, if there is no voltage (or a logically low voltage) applied to the gate electrode, then there is no current flow through the device (ignoring undesirable leakage currents, which are relatively small). However, when an appropriate positive voltage (or logically high voltage) is applied to the gate electrode, the channel region of the NMOS device becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region. For a PMOS device, the control voltages are reversed. Field effect transistors may come in a variety of different physical shapes, e.g., so-called planar FET devices or so-called 3D or FinFET devices.
For many early device technology generations, the gate structures of most transistor elements have included a plurality of silicon-based materials, such as a silicon dioxide and/or silicon oxynitride gate insulation layer, in combination with a polysilicon gate electrode. However, as the channel length of aggressively scaled transistor elements has become increasingly small, many newer generation devices employ gate structures that contain alternative materials in an effort to avoid the short channel effects which may be associated with the use of traditional silicon-based materials in reduced channel length transistors. For example, in some aggressively scaled transistor elements, which may have channel lengths on the order of approximately 10-32 nm or less, gate structures that include a so-called high-k dielectric gate insulation layer and one or metal layers that function as the gate electrode (HK/MG) have been implemented. Such alternative gate structures have been shown to provide significantly enhanced operational characteristics over the heretofore more traditional silicon dioxide/polysilicon gate structure configurations.
Depending on the specific overall device requirements, several different high-k materials—i.e., materials having a dielectric constant, or k-value, of approximately 10 or greater—have been used with varying degrees of success for the gate insulation layer in an HK/MG gate structure. For example, in some transistor element designs, a high-k gate insulation layer may include tantalum oxide (Ta2O5), hafnium oxide (HfO2), zirconium oxide (ZrO2), titanium oxide (TiO2), aluminum oxide (Al2O3), hafnium silicates (HfSiOx) and the like. Furthermore, one or more non-polysilicon metal gate electrode materials—i.e., a metal gate stack—may be used in HK/MG configurations to control the work function of the transistor. These metal gate electrode materials may include, for example, one or more layers of titanium (Ti), titanium nitride (TiN), titanium-aluminum (TiAl), titanium-aluminum-carbon (TiALC), aluminum (Al), aluminum nitride (AlN), tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), tantalum silicide (TaSi) and the like.
In many cases, the metal-containing gate structures are formed by performing well-known replacement gate processing techniques. In general, the replacement gate technique involves forming a sacrificial gate structure (e.g., a silicon dioxide gate insulating layer and a polysilicon gate electrode) and a gate cap layer, followed by forming a protective sidewall spacer adjacent the gate structure. The sacrificial gate structure is eventually removed to define a replacement gate cavity between the spacer. Thereafter, the high-k gate insulating layer and the various layers of metal that will comprise the gate electrode are sequentially deposited in the gate cavity. Excess materials positioned outside of the gate cavity are removed by performing one or more CMP process operations. Next, one or more recess etching processing operations are performed to remove some of the materials within the gate cavity to create a space for the formation of a protective gate cap layer. The gate cap layer is formed by overfilling the recessed cavity with a material, such as silicon nitride, and thereafter performing a CMP process to remove the excess gate cap materials.
In modern device fabrication, transistors having relative short channel lengths and transistors having relatively long channel lengths are formed on the same substrate. Unfortunately, some of the metal materials employed in such metal gate structures, such as tungsten, have different etch characteristics depending upon the channel length of the transistor device, due to differences in grain sizes. Accordingly, during the recess etching process that is performed to make room for the gate cap layer above the replacement metal-containing gate structure, some of the gate structure materials may be inadvertently removed or etched, leading to poor device performance or lower yield. More specifically, etching the gate structures of devices having different channel lengths may result in uneven and inadvertent etching of at least the metal gate materials, such as tungsten or the like, due to the larger grain size and surface area of the metal material in the longer channel devices.
The present disclosure is directed to various novel gate structures that comprise a conductive etch stop layer positioned between two bulk metal layers that may solve or reduce one or more of the problems identified above.
SUMMARY OF THE INVENTIONThe following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
Generally, the present disclosure is directed to various novel gate structures that comprise a conductive etch stop layer positioned between two bulk metal layers. One illustrative gate structure of a transistor device disclosed herein includes a high-k gate insulation layer and a work function metal layer positioned on the high-k gate insulation layer. The device further includes a first bulk metal layer positioned on the work function metal layer. The device further includes a second bulk metal layer. The first and second bulk metal layers have upper surfaces that are at substantially the same height level, and the first and second bulk metal layers are made of substantially the same material. The device further includes a conductive etch stop layer between the first and second bulk metal layers.
Another illustrative device disclosed herein includes an integrated circuit device including a gate structure of a short channel device including a high-k gate insulation layer, a work function metal layer positioned on the high-k gate insulation layer, and a first bulk metal layer positioned on the work function metal layer. The device further includes a gate structure of a long channel device including a second high-k gate insulation layer, a second work function metal layer positioned on the second high-k gate insulation layer, another first bulk metal layer positioned on the second work function metal layer, a second bulk metal layer, and a conductive etch stop layer positioned between the another first bulk metal layer and the second bulk metal layer.
The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the disclosure as defined by the appended claims.
DETAILED DESCRIPTIONVarious illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
The present subject matter will now be described with reference to the attached figures. Various structures, systems, and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.
The present disclosure relates to various novel gate structures that comprise a conductive etch stop layer positioned between two bulk metal layers. The methods and devices disclosed herein may be employed in manufacturing products using a variety of technologies, e.g., NMOS, PMOS, CMOS, etc., and they may be employed in manufacturing a variety of different devices, e.g., memory devices, logic devices, ASICs, etc. Of course, the disclosure should not be considered limited to the illustrative examples depicted and described herein.
As will be appreciated by those skilled in the art after a complete reading of the present application, the disclosure may be employed in forming integrated circuit products using planar transistor devices, as well as so-called 3D devices, such as FinFETs, or a combination of such devices. For purposes of disclosure, reference will be made to an illustrative process flow wherein an integrated circuit product 100 is formed with a plurality of planar transistor devices 10, 11. However, the disclosure should not be considered limited to such an illustrative example. With reference to the attached figures, various illustrative embodiments of the methods and devices disclosed herein will now be described in more detail.
A replacement gate process may be used when forming the gate structures of planar devices or 3D devices. As shown in
The various components and structures of the devices 10, 11 may be formed using a variety of different materials and by performing a variety of known techniques. For example, the sacrificial gate insulation layers 14 may be made of silicon dioxide, the sacrificial gate electrodes 15 may be made of polysilicon, the sidewall spacers 16 may be made of silicon nitride and the layer of insulating material 17 may be made of silicon dioxide. The source/drain regions 18 typically include implanted dopant materials (N-type dopants for NMOS devices and P-type dopants for PMOS devices) that are implanted into the substrate 12 using known masking and ion implantation techniques. At the point of fabrication depicted in
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The particular embodiments disclosed above are illustrative only, as the disclosure may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the disclosure. Note that the use of terms, such as “first,” “second,” “third” or “fourth” to describe various processes or structures in this specification and in the attached claims is only used as a shorthand reference to such steps/structures and does not necessarily imply that such steps/structures are performed/formed in that ordered sequence. Of course, depending upon the exact claim language, an ordered sequence of such processes may or may not be required. Accordingly, the protection sought herein is as set forth in the claims below.
Claims
1. A gate structure of a transistor device, comprising:
- a high-k gate insulation layer;
- a work function metal layer positioned on said high-k gate insulation layer;
- a first bulk metal layer positioned on said work function metal layer;
- a second bulk metal layer, said first and second bulk metal layers comprising upper surfaces that are at substantially the same height level; and
- a conductive etch stop layer positioned between said first and second bulk metal layers.
2. The device of claim 1, further comprising a gate cap layer above said conductive etch stop layer.
3. The device of claim 1, wherein said conductive etch stop layer comprises a material selected from the group consisting of titanium, titanium nitride, tantalum, tantalum nitride, tungsten nitride, aluminum, ruthenium, titanium silicon nitride and tantalum silicon nitride.
4. The device of claim 1, wherein said first and second bulk metal layers comprise tungsten.
5. The device of claim 1, wherein said first and second bulk metal layers are made of the same material.
6. The device of claim 1, wherein said first bulk metal layer comprises a different material than said second bulk metal layer.
7. The device of claim 1, wherein said work function metal layer comprises titanium nitride.
8. The device of claim 1, wherein said work function metal layer and said conductive etch stop layer are made of the same material.
9. The device of claim 1, further comprising a gate cap layer that is positioned on and in contact with an upper surface of said first bulk metal layer, an upper surface of said conductive etch stop layer and an upper surface of said second bulk metal layer.
10. The device of claim 1, wherein an upper surface of said first bulk metal layer, an upper surface of said conductive etch stop layer and an upper surface of said second bulk metal layer are all positioned in a common horizontal plane
11. The device of claim 1, wherein said conductive etch stop layer comprises a material selected from the group consisting of titanium, titanium nitride, tantalum, tantalum nitride, tungsten nitride, aluminum, ruthenium, titanium silicon nitride and tantalum silicon nitride.
12. The device of claim 11, wherein said first bulk metal layer and said second bulk metal layer comprise tungsten.
13. The device of claim 1, wherein, in a cross-section taken through said gate structure in a direction that is parallel to a gate length direction of said transistor device:
- each of said high-k gate insulation layer, said work function metal layer, said first bulk metal layer, and said conductive etch stop layer have a generally U-shaped cross-sectional configuration; and
- said second bulk metal layer has a generally rectangular cross-sectional configuration, and said second bulk metal layer is bounded on three sides by said generally U-shaped conductive etch stop layer.
14. A gate structure of a transistor device, comprising:
- a high-k gate insulation layer;
- a work function metal layer positioned on said high-k gate insulation layer, said work function metal layer comprising an upper surface;
- a first bulk metal layer positioned on said work function metal layer, said first bulk metal layer comprising an upper surface;
- a second bulk metal layer, said second bulk metal layer comprising an upper surface;
- a conductive etch stop layer positioned between said first and second bulk metal layers, said conductive etch stop layer comprising an upper surface, wherein said upper surfaces of said conductive etch stop layer, said work function metal layer, said first bulk metal layer and said second bulk metal layer are positioned at substantially the same height level above an upper surface of a semiconductor substrate; and
- a gate cap layer that is positioned on and in contact with said upper surfaces of said first bulk metal layer, said conductive etch stop layer and said second bulk metal layer.
15. The device of claim 14, wherein said first and second bulk metal layers are made of the same material.
16. The device of claim 14, wherein said first bulk metal layer comprises a different material than said second bulk metal layer.
17. The device of claim 14, wherein said work function metal layer and said conductive etch stop layer are made of the same material.
18. The device of claim 15, wherein, in a cross-section taken through said gate structure in a direction that is parallel to a gate length direction of said transistor device:
- each of said high-k gate insulation layer, said work function metal layer, said first bulk metal layer, and said conductive etch stop layer have a generally U-shaped cross-sectional configuration; and
- said second bulk metal layer has a generally rectangular cross-sectional configuration, and said second bulk metal layer is bounded on three sides by said generally U-shaped conductive etch stop layer.
19. An integrated circuit device, comprising:
- a gate structure of a short channel device comprising: a first high-k gate insulation layer comprising a high-k material; a first work function metal layer positioned on said first high-k gate insulation layer, said first work function metal layer comprising a work function metal material; and a first bulk metal layer positioned on said first work function metal layer, said first bulk metal layer comprising a bulk metal material; and
- a gate structure of a long channel device comprising: a second high-k gate insulation layer comprising said high-k material; a second work function metal layer positioned on said second high-k gate insulation layer, said second work function metal layer comprising said work function metal material; another first bulk metal layer positioned on said second work function metal layer, said another bulk metal layer comprising said bulk metal material; a second bulk metal layer; and a conductive etch stop layer positioned between said another first bulk metal layer and said second bulk metal layer.
20. The device of claim 19, further comprising:
- a first gate cap layer for said short channel device, wherein said first gate cap layer is positioned on and in contact with an upper surface of said first work function metal layer and an upper surface of said first bulk metal layer of said first gate structure; and
- a second gate cap layer for said long channel device, wherein the second gate cap layer is positioned on and in contact with an upper surface of said another first bulk metal layer, an upper surface of said conductive etch stop layer and an upper surface of said second bulk metal layer of said second gate structure.
21. The device of claim 19, wherein said another first bulk metal layer and said second bulk metal layer of said second gate structure are made of the same material.
22. The device of claim 19, wherein said another first bulk metal layer and said second bulk metal layer of said second gate structure are made of different materials.
23. The device of claim 21, wherein said work function metal material comprises titanium nitride.
24. The device of claim 19, wherein said second work function metal layer and said conductive etch stop layer of said second gate structure are made of the same material.
25. The device of claim 19, wherein an upper surface of said another first bulk metal layer, an upper surface of said conductive etch stop layer and an upper surface of said second bulk metal layer of said second gate structure are all positioned in a common horizontal plane.
26. The device of claim 19, wherein, in a cross-section taken through said second gate structure in a direction that is parallel to a gate length direction of said long channel device:
- each of said second high-k gate insulation layer, said second work function metal layer, said another first bulk metal layer, and said conductive etch stop layer of said second gate structure have a generally U-shaped cross-sectional configuration; and
- said second bulk metal layer of said second gate structure has a generally rectangular cross-sectional configuration, and said second bulk metal layer is bounded on three sides by said generally U-shaped conductive etch stop layer.
Type: Application
Filed: Sep 25, 2015
Publication Date: Feb 18, 2016
Inventors: Chanro Park (Clifton Park, NY), Hoon Kim (Clifton Park, NY), Min Gyu Sung (Latham, NY)
Application Number: 14/865,784