BOND PAD WITH MICRO-PROTRUSIONS FOR DIRECT METALLIC BONDING
A bond pad with micro-protrusions for direct metallic bonding. In one embodiment, a semiconductor device comprises a semiconductor substrate, a through-silicon via (TSV) extending through the semiconductor substrate, and a copper pad electrically connected to the TSV and having a coupling side. The semiconductor device further includes a copper element that projects away from the coupling side of the copper pad. In another embodiment, a bonded semiconductor assembly comprises a first semiconductor substrate with a first TSV and a first copper pad electrically coupled to the first TSV, wherein the first copper pad has a first coupling side. The bonded semiconductor assembly further comprises a second semiconductor substrate, opposite to the first semiconductor substrate, the second semiconductor substrate comprising a second copper pad having a second coupling side. A plurality of copper connecting elements extend between the first and second coupling sides of the first and second copper pads.
The disclosed embodiments relate to semiconductor devices and more particularly to bond pads on semiconductor dies.
BACKGROUNDBond pads are formed on semiconductor dies to provide electrical and mechanical connection between one semiconductor die and another. To minimize the footprint of semiconductor assemblies, multiple semiconductor dies can be vertically stacked on top of one another. The dies in such vertically-stacked packages can be interconnected either with through-silicon-vias (TSV) that are electrically connected to each other using direct metallic bonding in which the bond pads of one die are directly bonded to the bond pads of the other. Such direct metallic bonding can be performed die-to-die (D2D), die-to-wafer (D2W), or wafer-to-wafer (W2W).
Direct metallic bonding provides several benefits over conventional solder bonding and thermocompression bonding processes. For example, direct bonding enables a high density of vertical interconnects because it does not involve reflowing or fluxing of a metal. Direct bonding also provides better electrical and mechanical performance compared to solder bonding without the need for adhesive or underfill materials. Copper is of particular interest for such direct metallic bonding. Direct copper-copper bonding—for example direct bonding between a first copper bond pad and a second copper bond pad—achieves good mechanical, thermal, and electrical performance. Direct copper-copper bonding additionally reduces intermetallic and electrical migration concerns compared to solder-based bonding approaches. However, direct copper-copper bonding presents certain challenges. First, a good bond requires adequate inter-diffusion at the copper-copper interface, which in turn requires that the surface of each bond pad must be flat and very smooth (e.g., less than several nm roughness). Typically this requires the use of chemical-mechanical planarization (CMP). However, because copper is relatively soft and subject to “dishing” and oxide erosion during CMP processing, the requisite planarity and surface quality for direct copper-copper bonding are difficult to achieve. Additionally, a high bonding force is needed for direct copper bonding, and such high forces may damage the bond pads and possibly the TSVs or circuits underneath.
Specific details of several embodiments of semiconductor die assemblies having direct metal-metal bonds and associated systems and methods are described below. The term “semiconductor die” generally refers to a die having integrated circuits or components, data storage elements, processing components, and/or other features manufactured on semiconductor substrates. For example, semiconductor dies can include integrated circuit memory and/or logic circuitry. A person skilled in the relevant art will also understand that the technology may have additional embodiments, and that the technology may be practiced without several of the details of the embodiments described below with reference to
As used herein, the terms “vertical,” “lateral,” “upper” and “lower” can refer to relative directions or positions of features in the semiconductor die assemblies in view of the orientation shown in the Figures. For example, “upper” or “uppermost” can refer to a feature positioned closer to the top of a page than another feature. These terms, however, should be construed broadly to include semiconductor devices having other orientations, such as inverted or inclined orientations where top/bottom, over/under, above/below, up/down and left/right can be interchanged depending on the orientation.
Referring back to
As shown in
In traditional approaches to direct metal bonding, the entire surface area of the bond pads of adjacent semiconductor dies would be placed directly adjacent one another and bonded together, for example via thermocompression bonding or thermosonic bonding. This requires excellent surface quality and planarity of the upper surfaces of the bond pads, which is difficult to achieve when the bond pads are made of copper as described above. Additionally, the pressure applied to bond the two bond pads together can be so high that the underlying circuitry or the TSVs can be damaged. The embodiment of the semiconductor die 100 illustrated in
Several embodiments of the semiconductor die 100 shown in
Referring still to
In the embodiment illustrated in
The structure illustrated in
Any one of the semiconductor dies described above with reference to
From the foregoing, it will be appreciated that specific embodiments of the invention have been described herein for purposes of illustration, but that various modifications may be made without deviating from the disclosure. Certain aspects of the new technology described in the context of particular embodiments may also be combined or eliminated in other embodiments. Moreover, although advantages associated with certain embodiments of the new technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages and not all embodiments need necessarily exhibit such advantages to fall within the scope of the technology. Accordingly, the disclosure and associated technology can encompass other embodiments not expressly shown or described herein.
Claims
1. A semiconductor device comprising:
- a semiconductor substrate;
- a through-silicon via (TSV) extending through the semiconductor substrate;
- a copper pad electrically connected to the TSV and having a coupling side;
- a dielectric material disposed over the coupling side of the copper pad; and
- a plurality of metallic elements that project away from the coupling side of the copper pad, the metallic elements separated from each other across the copper pad, wherein the dielectric material is disposed between adjacent metallic elements.
2. The semiconductor device of claim 1, wherein the TSV comprises copper.
3. The semiconductor device of claim 1, wherein the plurality of metallic elements comprise copper pillars.
4. The semiconductor device of claim 1, wherein the plurality of metallic elements comprises at least four metallic elements.
5. The semiconductor device of claim 1, wherein the plurality of metallic elements project beyond the dielectric material.
6. The semiconductor device of claim 5, wherein the plurality of metallic elements project beyond the dielectric material by between 0.5 and 2 microns.
7. The semiconductor device of claim 1, wherein each of the plurality of metallic elements has a cross-sectional dimension of between 0.5 and 5 microns.
8. The semiconductor device of claim 1, wherein the plurality of metallic elements are configured to deform under pressure of less than or equal to 20 MPa.
9. A semiconductor device comprising:
- a substrate comprising an interconnect extending therethrough;
- a dielectric material on the substrate;
- a metallic bond pad embedded in the dielectric material and electrically coupled to an end portion of the interconnect;
- a plurality of metallic bonding elements electrically coupled to the metallic bond pad and projecting from the bond pad, the metallic bonding elements separated from each other across the metallic bond pad and extending through the dielectric material, the metallic bonding elements having a lower portion embedded in the dielectric material, and the metallic bonding elements configured to deform under less pressure than the metallic bond pad.
10. The semiconductor device of claim 9, wherein the metallic bond pad comprises copper, and wherein the plurality of metallic bonding elements comprise copper.
11. The semiconductor device of claim 9, wherein the metallic bonding elements have an upper portion that projects beyond the dielectric material.
12. The semiconductor device of claim 9, wherein the plurality of metallic bonding elements comprise at least four metallic bonding elements.
13. The semiconductor device of claim 9, wherein the plurality of metallic bonding elements comprise pillars.
14. The semiconductor device of claim 9, wherein the plurality of metallic bonding elements project beyond the dielectric material by between 0.5 and 2 microns.
15. The semiconductor device of claim 9, wherein the plurality of metallic bonding elements each has a cross-sectional dimension of between 0.5 and 5 microns.
16. A bonded semiconductor assembly comprising:
- a first semiconductor substrate comprising a first through-silicon via (TSV) and a first copper pad electrically coupled to the first TSV, wherein the first copper pad has a first coupling side;
- a second semiconductor substrate opposite to the first substrate, the second semiconductor substrate comprising a second copper pad having a second coupling side; and
- a plurality of copper connecting elements extending between the first and second coupling sides of the first and second copper pads.
17. The bonded semiconductor assembly of claim 16, wherein the first and second TSVs each comprises copper.
18. The bonded semiconductor assembly of claim 16, wherein the plurality of copper connecting elements comprise pillars.
19. The bonded semiconductor assembly of claim 16, wherein the plurality of copper connecting elements comprise at least four copper connecting elements.
20. The bonded semiconductor assembly of claim 16, further comprising a dielectric material at least partially surrounding the plurality of copper connecting elements.
21. The bonded semiconductor assembly of claim 16, wherein the plurality of copper connecting elements each has a cross-sectional dimension of between 0.5 and 5 microns.
22. The bonded semiconductor assembly of claim 16, wherein the plurality of copper connecting elements are in electrical communication with both the first and second copper pads.
23. A semiconductor device, comprising:
- a first semiconductor substrate having a first through-silicon via (TSV), a first pad electrically coupled to the first TSV, and a first bonding feature projecting away from the first pad, wherein the first bonding feature covers only a portion of the first pad; and
- a second semiconductor substrate having a second TSV, a second pad electrically coupled to the second TSV, and a second bonding feature projecting away from the second pad, wherein the second bonding feature covers only a portion of the second pad;
- wherein the first bonding feature is directly connected to the second bonding feature by a metal-to-metal bond.
24. The semiconductor device of claim 23, wherein the first and second pads each comprise copper, and wherein the first and second bonding features each comprise copper.
25. The semiconductor device of claim 23, wherein the first bonding feature comprises a pillar.
26. The semiconductor device of claim 23, further comprising a dielectric material disposed between the first pad and the second pad, the dielectric material at least partially surrounding the first bonding feature.
27. The semiconductor device of claim 23, wherein the first and second bonding features each comprise metallic elements.
28. A semiconductor device, comprising:
- a first semiconductor substrate having a first through-silicon via (TSV), a first pad electrically coupled to the first TSV, and a first bonding feature projecting away from the first pad, wherein the first bonding feature covers only a portion of the first pad; and
- a second semiconductor substrate having a second TSV and a second pad electrically coupled to the second TSV;
- wherein the first bonding feature is directly connected to the second pad by a metal-to-metal bond.
29. The semiconductor device of claim 28, further comprising a dielectric material disposed between the first pad and the second pad, the dielectric material at least partially surrounding the first bonding feature.
30. The semiconductor device of claim 28, wherein the first and second pads each comprises copper, and wherein the first bonding feature comprises copper.
31. The semiconductor device of claim 28, wherein the first bonding feature each has a cross-sectional dimension of between 0.5 and 5 microns.
32. A method of manufacturing a semiconductor device, the method comprising:
- forming dielectric material over a bond pad electrically coupled to an interconnect that extends through a substrate;
- forming openings in the dielectric material over the bond pad; and
- forming a conductive material in the openings, the conductive material electrically coupled to the bond pad and projecting away from the bond pad to define a metallic bonding element.
33. The method of claim 32, wherein the conductive material comprises copper.
34. The method of claim 32, further comprising planarizing the conductive material to form separate conductive elements projecting away from the bond pad.
35. The method of claim 34, further comprising etching a portion of the dielectric material such that the separate conductive elements project beyond the dielectric material.
36. The method of claim 32, further comprising bonding the semiconductor device to a second semiconductor device having a second bond pad.
37. The method of claim 36, wherein the conductive material is in electrical communication with the first bond pad and the second bond pad.
38. The method of claim 32, further comprising bonding the metallic bonding element to a second metallic bonding element projecting from a bond pad of a second semiconductor device.
39. A method of manufacturing a semiconductor device, the method comprising:
- providing a first semiconductor substrate having a first through-silicon via (TSV), a first pad electrically coupled to the first TSV, and a first bonding feature projecting away from the first pad;
- disposing a second semiconductor substrate, having a second TSV and a second pad electrically coupled to the second TSV, over the first semiconductor substrate such that the first pad faces the second pad; and
- bonding the first semiconductor substrate to the second semiconductor substrate such that the first bonding feature is electrically coupled to the second pad.
40. The method of claim 39, wherein bonding the first semiconductor substrate to the second semiconductor substrate comprises applying pressure of less than or equal to 20 MPa.
41. The method of claim 39, wherein bonding the first semiconductor substrate to the second semiconductor substrate comprises directly connecting the first bonding feature to the second pad.
42. The method of claim 41, wherein the first and second pads each comprises copper, and wherein the first bonding feature comprises copper.
43. The method of claim 41, wherein the first bonding feature comprises a pillar.
44. The method of claim 41, wherein bonding the first semiconductor substrate to the second semiconductor substrate comprises at least partially deforming the first bonding feature.
45. The method of claim 39, wherein the second semiconductor substrate further comprises a second bonding feature projecting away from the second pad, and wherein bonding the first semiconductor substrate to the semiconductor substrate comprises directly connecting the first bonding feature to the second bonding feature.
46. The method of claim 45, wherein during bonding the first bonding feature is substantially aligned with the second bonding feature.
47. The method of claim 45, wherein during bonding the first bonding feature is at least partially offset with respect to the second bonding feature.
48. The method of claim 45, wherein bonding the first semiconductor substrate to the second semiconductor substrate comprises at least partially deforming the first and second bonding features.
49. The method of claim 45, wherein the first and second pads each comprises copper, and wherein the first and second bonding features each comprises copper.
50. The method of claim 45, wherein the first and second bonding features each comprises a pillar.
Type: Application
Filed: Sep 25, 2014
Publication Date: Mar 31, 2016
Inventors: Aibin Yu (Singapore), Wei Zhou (Singapore), Zhaohui Ma (Singapore)
Application Number: 14/496,082