CAPPED CONTACT STRUCTURE WITH VARIABLE ADHESION LAYER THICKNESS
Metal oxide based memory devices and methods for manufacturing are described herein. A method for manufacturing a memory cell includes forming a bottom adhesion layer in a via formed in an insulating layer. Forming a bottom conductive plug in the bottom adhesion layer. Forming a top adhesion layer over the bottom adhesion layer and bottom conductive plug. Forming a top conductive plug in the top adhesion layer. Wherein the thickness of the bottom and top adhesion layers may be different from one another.
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This application claims the benefit of U.S. Provisional Patent Application No. 62/106,745 filed on 23 Jan. 2015, which application is incorporated by reference as if fully set forth herein.
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention relates to metal oxide based memory devices and methods for manufacturing such devices.
2. Description of Related Art
Resistive random access memory, RRAM, is a type of nonvolatile memory that provides the benefits of small cell size, scalability, ultrafast operation, low-power operation, high endurance, good retention, large On/Off ratio, and CMOS compatibility. One type of RRAM includes metal oxide layers than can be caused to change resistance between two or more stable resistance ranges by application of electrical pulses at levels suitable for implementation in integrated circuits and the resistance can be read and written with random access to indicate stored data.
RRAM memory may include a metal oxide memory element in a current path between first and second electrodes. The electrodes may be terminals to access devices and/or may be coupled to access lines such as bit, word, and source lines. The access lines are connected to circuitry to perform operations, such as SET and RESET operations, which may operate to change the state of the memory element in order to store data.
In prior methods of forming a RRAM memory cell, the top surface of an interlayer conductor 102, comprising an adhesion layer 106 liner and a conductive plug 109, located in a via in an insulation layer 104, is oxidized. The resulting structure of this oxidation process is shown schematically in
Due to the thickness and/or the material of the adhesion layer 106, it is sometimes difficult for the both the conductive plug 109 and adhesion layer 106 to be fully oxidized. For example it is difficult to fully oxidize a thick TiN adhesion layer within a tungsten plug. The partial and non-uniformly oxidation of the adhesion layer within a cell and from cell to cell causes non-uniform operation of the device. This results in yield loss of large array devices.
Previous technology to prevent the uncertainty of the adhesion layer oxidation includes using an etching back process to remove a portion of the adhesion layer material, for example TiN, at top surface of the interlayer conductor.
Also, in prior methods of forming a RRAM memory cell the aspect ratio, depth divided by diameter, of the via which a single conductive plug is formed in may be high, for example over 1.5. High aspect ratios lead to voids forming in the conductive plug during deposition. Voids in the conductive plugs are also referred to as seams. The formation size and shape of the voids is inconsistent from plug to plug in a device. During a CMP process the voids may be present at the top oxidized portion of the conductive plug forming the memory element. This is undesirable because the oxide film of the memory element can not be flat and will have poor coverage. A void in the conductive plug 109 and portions of the oxidized plug 110 are visible in
It is therefore desirable to provide a memory cell and method of manufacture that includes a small ratio of oxide of the adhesion layer material to the conductive plug material without the disadvantages of the etch back process.
SUMMARY OF THE INVENTIONMemory devices based on metal oxide memory layers, for example tungsten-oxide, are described along with methods for manufacturing.
An example of a memory device comprises top and bottom electrodes with a memory element located between and electrically coupled to the top and bottom electrodes. In an example embodiment, the memory device comprises a bottom electrode in the form of a multi component interlayer conductor, a memory layer on the interlayer conductor including a metal oxide, and a top electrode over the metal oxide. The multi component interlayer conductor includes a top and bottom portion. The top and bottom portion each include a conductive plug inside of an adhesion layer lining the via and including sidewall portions and bottom portions. The top adhesion layer of the upper portion may have a different sidewall thickness than the bottom adhesion layer of the lower portion. The conductive plugs are comprised of transition metal. The memory layer can include a layer of metal oxide.
An example of a method of fabricating a memory device is carried out as follows. A bottom adhesion layer is formed in a via formed in an insulating layer, lining the bottom portion of the via. For example, this bottom adhesion layer may be TiN. A bottom conductive plug, such as a tungsten plug, is deposited using CVD in the bottom adhesion layer. The bottom conductive plug and bottom adhesion layer are then recessed below the top surface of the insulation layer. Alternatively, an additional insulation layer may be deposited with a new via created to be aligned over the bottom conductive plug and bottom adhesion layer, resulting in a similar configuration as the previously stated recessing process. A top adhesion layer, is formed in upper portion of the via lining the upper portion of the via. In the example the top adhesion layer is also composed of TiN. Because the via the top adhesion layer is formed in is aligned over the bottom adhesion layer and bottom conductive plug, the top adhesion layer is deposited over the bottom conductive plug and bottom adhesion layer. A top conductive plug, for example a tungsten plug, is deposited using CVD in the top adhesion layer. The thickness of the bottom and top adhesion layers may be different from one another.
In an example, the top adhesion layer may be thinner than the bottom adhesion layer. This difference of thickness has the advantage of a lower surface area ratio of the adhesion layer to the conductive plug which has the advantage of a more uniform device because of less uncertainty caused by oxidation of the adhesion layer. Further, the two conductive plugs of the interlayer conductor each have lower aspect ratios than a single conductive plug in the same via, therefore the likelihood of a void forming when depositing each conductive plug is significantly reduced compared to forming a single conductive plug in the via. Therefore, because the interlayer conductors produced with this method do not includes “seam”, voids, this technology is referred to as “seam free” and is a solution to “the seam issue” discussed above.
The steps of forming the upper and lower portions of the interlayer conductor are followed by forming a memory layer on the electrode surface of the interlayer conductor, specifically the top conductive plug. For example, a rapid thermal oxidation may be used to create a metal oxide layer from the metal of the top conductive plug. In the example, the metal of the conductive plug is tungsten, therefore the metal oxide is tungsten oxide (WOx). During the oxidation process, the material in the adhesion layer is also oxidized. This material may be harder to ensure complete oxidation, and it is therefore beneficial for the top surface of the interlayer conductor to have a low ratio of area of the adhesion layer to area of top conductive plug. Therefore in embodiments, it is beneficial for the top adhesion layer to have thinner sidewall portions than the bottom adhesion layer so that the ratio of adhesion layer surface to the top conductive plug surface at the top of the interlayer conductor is low.
After formation of the memory layer, a top electrode material is deposited on the memory layer. The method of fabricating a memory device may further include forming circuitry for performing read operations, and write operations (such as SET and RESET operations).
The structure and methods of the present invention are disclosed in the detailed description below. Other aspects and advantages of the present invention can be seen on review of the drawings, the detailed description and the claims, which follow.
The invention will be described with respect to the specific embodiments thereof, and reference will be made to the drawings, in which:
The following description of the disclosure will typically be with reference to specific structural embodiments and methods. It is to be understood that there is no intention to limit the disclosure to the specifically disclosed embodiments and methods, but that the disclosure may be practiced using other features, elements, methods and embodiments. Preferred embodiments are described to illustrate the present disclosure, not to limit its scope, which is defined by the claims. Those of ordinary skill in the art will recognize a variety of equivalent variations on the description that follows. Like elements in various embodiments are commonly referred to with like reference numerals.
The memory element 108 is located on the top electrode surface of the upper portion interlayer conductor including the top surfaces of the top adhesion layer 210 and the top conductive plug 212. In embodiments, the top electrode surface may be flattened and smoothed during a roughness tuning process, including an ion bombardment step. The memory element 108 may be comprised of one or more tungsten-oxygen compounds (WOx), for example one or more of WO3, W2O5, WO2. On top of the memory element 108 is a top electrode 214, in this embodiment an access line.
The memory cell shown in
As shown in
Next, a recessing process is performed, for example a CMP process, resulting in the structure shown in
Alternatively, instead of recessing the bottom adhesion layer 206 and bottom conductive plug 208 below the top surface of the dielectric insulator layer 204, a second layer 216 of dielectric material may be deposited on top of the initial dielectric material and vias formed to be aligned with the already formed bottom adhesion layer 206 and bottom conductive plug 208, resulting in the structure shown in
With either the method shown in
Next, a top conductive plug 212 is formed in the top adhesion layer 210 resulting in the structure shown in
Next a metal oxide layer may be formed to create the memory element 108. In the embodiment shown, an oxidation step is performed wherein the top portions of the top conductive plug 212 and top adhesion layer 210 are oxidized to form a metal oxide memory element 108, resulting in the structure shown in
After the memory element 108 is formed, a top electrode 214 may be formed on top of the memory element 108, resulting in the structure shown in
Forming a memory cell with the above disclosed structure and manufacturing process including a multicomponent interlayer conductor including top and bottom adhesion layers and conductive plugs results in resistive oxide memory cells with higher initial resistances than cells manufactured without this process, as shown in
A controller 34 implemented in this example, using a bias arrangement state machine, controls the application of bias arrangement supply voltages 36, such as read, program, and program verify voltages. Controller 34 may be implemented using special-purpose logic circuitry as known in the art. In alternative embodiments, controller 34 comprises a general-purpose processor, which may be implemented on the same integrated circuit to execute a computer program to control the operations of the device.
In yet other embodiments, a combination of special-purpose logic circuitry and a general-purpose processor may be utilized for implementation of controller 34.
It will be understood that the memory array is not limited to the array configuration illustrated in
While the present invention is disclosed by reference to the preferred embodiments and examples detailed above, it is to be understood that these examples are intended in an illustrative rather than in a limiting sense. It is contemplated that modifications and combinations will readily occur to those skilled in the art, which modifications and combinations will be within the spirit of the invention and the scope of the following claims.
Claims
1. A memory device comprising:
- a top electrode;
- a metal oxide layer contacting the top electrode;
- an interlayer conductor having an electrode surface contacting the metal oxide layer;
- wherein the interlayer conductor comprises an upper portion including the electrode surface and a lower portion;
- wherein the lower portion comprising a first conductive liner and a first conductive plug in the first conductive liner and the upper portion comprising a second conductive liner and a second conductive plug in the second conductive liner; and
- wherein the second conductive liner includes sidewall portions having a thickness different than a thickness of sidewall portions of the first conductive liner.
2. The memory device of claim 1, wherein the first conductive liner and the second conductive liner have different material compositions.
3. The memory of claim 1, wherein the thickness of the sidewall portion of the first conductive liner is greater than the thickness of the sidewall portion of the second conductive liner.
4. The memory of claim 1, wherein the thickness of the sidewall portion of the first conductive liner is less than the thickness of the sidewall portion of the second conductive liner.
5. The memory device of claim 1, wherein the metal oxide layer is characterized by having a programmable resistance.
6. The memory of claim 1, wherein the electrode surface of the interlayer conductor includes a top surface of the second conductive plug, the top surface consisting essentially of a metal, and the metal oxide layer comprises an oxide of said metal.
7. The memory device of claim 1, wherein the first conductive plug and the second conductive plug have different material compositions.
8. The memory device of claim 1, wherein the first conductive liner and the first conductive plug have different material compositions.
9. The memory device of claim 1, wherein the second conductive liner covers the first conductive plug and the first conductive liner.
10. A method of making a memory cell, comprising:
- forming a via through an insulation layer;
- forming a lower portion of an interlayer conductive element comprising: forming a first conductive liner contacting sidewalls of the via, and forming a first conductive plug in the first conductive liner;
- forming an upper portion of the conductive element comprising: forming a second conductive liner contacting a top surface of the first conductive plug and sidewalls of the via, and forming a second conductive plug located within the second conductive liner;
- forming a metal oxide layer on an end of the upper portion opposite an end adjacent to the lower portion; and
- forming a top electrode layer contacting the metal oxide layer;
- wherein the second conductive liner includes sidewall portions having a thickness different than a thickness of sidewall portions of the first conductive liner.
11. The method of claim 10, wherein the first conductive liner and the second conductive liner are formed of material with different material compositions.
12. The method of claim 10, wherein the thickness of the sidewall portion of the first conductive liner is greater than the thickness of the sidewall portion of the second conductive liner.
13. The method of claim 10, wherein the thickness of the sidewall portion of the first conductive liner is less than the thickness of the sidewall portion of the second conductive liner.
14. The method of claim 10, wherein the metal oxide layer is characterized by having a programmable resistance.
15. The method of claim 10, wherein forming the metal oxide layer includes oxidizing a portion of the second conductive plug.
16. The method of claim 10, wherein the first conductive plug and the second conductive plug have different material compositions.
17. The method of claim 10, wherein the first conductive plug and the second conductive plug have the same material composition.
18. The method of claim 10, wherein the first conductive liner and the first conductive plug have different material compositions.
19. The method of claim 10, wherein the second conductive liner covers the first conductive plug and the first conductive liner.
20. An integrated circuit comprising:
- an array of memory cells, the memory cells comprising; a top electrode; a metal oxide layer contacting the top electrode; and an interlayer conductor having an electrode surface contacting the metal oxide layer; wherein the interlayer conductor comprises an upper portion including the electrode surface and a lower portion; wherein the lower portion comprising a first conductive liner and a first conductive plug in the first conductive liner and the upper portion comprising a second conductive liner and a second conductive plug in the second conductive liner; and wherein the second conductive liner includes sidewall portions having a thickness different than a thickness of sidewall portions of the first conductive liner; and
- control circuitry to control application of bias arrangement supply voltages.
Type: Application
Filed: Jun 25, 2015
Publication Date: Jul 28, 2016
Applicant: MACRONIX INTERNATIONAL CO., LTD. (HSINCHU)
Inventors: Yu-Yu LIN (HSINCHU), Feng-Min LEE (HSINCHU)
Application Number: 14/750,801