Patents by Inventor Yu-Yu Lin
Yu-Yu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250022508Abstract: A memory device includes several computing memory cells each storing a weight value and comprising a first and a second switch elements and a first and a second resistors. The first switch element receives a sensing current and a first input signal related to the input value. The first resistor selectively receives the sensing current through the first switch element in response to the first input signal. The second switch element receives the sensing current and a second input signal related to the input value. The second resistor selectively receives the sensing current through the second switch element in response to the second input signal. When the sensing current flows through the first resistor or the second resistor, the computing memory cell generates a first voltage difference or a second voltage difference corresponding to an output value equal to product of an input value and a weight value.Type: ApplicationFiled: October 1, 2024Publication date: January 16, 2025Inventors: Yu-Yu LIN, Feng-Min LEE, Ming-Hsiu LEE
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Patent number: 12198757Abstract: A memory device and a method for operating the same are provided. The memory device includes a plurality of resistive memory cells and a control circuitry electrically connected to the plurality of resistive memory cells. The control circuitry provides operation modes to operate the plurality of resistive memory cells. The operation modes include a first program operation and a refresh operation. The first program operation includes applying a first program bias voltage to a selected resistive memory cell of the plurality of resistive memory cells to establish a low-resistance state in the selected resistive memory cell. The first program operation establishes a first threshold voltage in the memory device. The refresh operation includes applying a refresh bias voltage to the selected resistive memory cell to refresh the selected resistive memory cell. An absolute value of the refresh bias voltage is greater than the first threshold voltage.Type: GrantFiled: June 17, 2022Date of Patent: January 14, 2025Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Yu-Yu Lin, Feng-Min Lee, Ming-Hsiu Lee
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Patent number: 12198766Abstract: An artificial neural network operation circuit and an in-memory computation device of the artificial neural network operation circuit are proposed. The in-memory computation device includes a memory cell array, a compensation memory cell string, and an operator. The memory cell array has a plurality of memory cells to store a plurality of weight values. The memory cell array has a plurality of word lines and a plurality of bit lines. Each compensation memory cell of the compensation memory cell string stores a unit weight value. The operator multiplies a signal on a compensation bit line by peak weight information of the weight values to generate a first signal and adds the first signal to each signal on the bit lines to obtain a plurality of computation results, respectively.Type: GrantFiled: February 22, 2023Date of Patent: January 14, 2025Assignee: Macronix International Co., Ltd.Inventors: Yu-Hsuan Lin, Yu-Yu Lin, Hsiang-Lan Lung
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Patent number: 12182914Abstract: Disclosed is an image display format conversion method, comprising: a frame recognition step of performing a frame recognition process on a comic page image to obtain a plurality of comic frame images and frame position information; a frame sequence determination step of determining a frame viewing sequence according to a selected regional layout rule; and a frame reassembly step of reassembling and converting, based on the frame viewing sequence, the plurality of comic frame images into a digital media in an animation-like format or a scrolling-comic format.Type: GrantFiled: March 1, 2023Date of Patent: December 31, 2024Assignee: HYWEB TECHNOLOGY CO., LTD.Inventors: Chung-Wei Yu, Yu-Yu Lin
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Publication number: 20240412784Abstract: An in-memory computation device includes multiple computation blocks, a first reference weight block, and an output result generator. The computation blocks have multiple weighting values, receive multiple input signals respectively, and generate multiple computation results. Each of the computation blocks generates each of the computation results according to each of the corresponding input signals and corresponding weighting values. The first reference weight block provides a first reference resistance according to multiple reference weighting values and generates a first reference signal according to the first reference resistance and a read voltage. The output result generator generates multiple output computation results according to the first reference signal and the computation results.Type: ApplicationFiled: June 7, 2023Publication date: December 12, 2024Applicant: MACRONIX International Co., Ltd.Inventors: Yu-Yu Lin, Feng-Min Lee
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Patent number: 12159672Abstract: A hybrid in-memory search (IMS) content addressable memory (CAM) cell includes: a first IMS CAM cell; and a second IMS CAM cell, coupled to the first IMS CAM cell. The first IMS CAM cell and the second IMS CAM cell are of different types. When the hybrid IMS CAM cell stores a storage data, the first IMS CAM cell stores a first part of the storage data and the second IMS CAM cell stores the storage data or a second part of the storage data.Type: GrantFiled: February 1, 2023Date of Patent: December 3, 2024Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Po-Hao Tseng, Yu-Hsuan Lin, Tian-Cih Bo, Feng-Min Lee, Yu-Yu Lin
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Patent number: 12142316Abstract: A memory device includes a plurality of computing memory cells, each of which stores a weight value, receives an input value and generates an output value. Each of the computing memory cells includes a transistor connected to a bit line and a word line, receiving a sensing current through the bit line and receiving an input voltage through the word line. When the sensing current flows through the transistor, the computing memory cell generates a first voltage difference corresponding to the output value. The output value is equal to a product of the input value and the weight value.Type: GrantFiled: July 15, 2022Date of Patent: November 12, 2024Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Yu-Yu Lin, Feng-Min Lee, Ming-Hsiu Lee
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Publication number: 20240371453Abstract: A memory device for performing an in-memory computation, comprising a plurality of memory cells each stores a weight value and comprises a transistor and a resistor. A gate of the transistor receives an input voltage, the input voltage indicates an input value. When the transistor operates at a first operating point, the input voltage is equal to a first input voltage, when the transistor operates at a second operating point, the input voltage is equal to a second input voltage. The resistor is connected to a drain and a source of the transistor, when the resistor operates in a first state, the weight value is equal to a first weight value, when the resistor operates in a second state, the weight value is equal to a second weight value. Each of the memory cells performs a product computation of the input value and the weight value.Type: ApplicationFiled: May 5, 2023Publication date: November 7, 2024Inventors: Yu-Yu LIN, Feng-Min LEE
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Publication number: 20240355387Abstract: An in-memory computing memory device includes: a plurality of computing memory cells forming a plurality of memory strings, the computing memory cells storing a plurality of weight values; a loading capacitor; and a measurement circuit. In IMC operations, a plurality of input voltages, corresponding to a plurality of input values, are input into the computing memory cells; a plurality of effective resistances of the computing memory cells are corresponding to the input voltages and the weight values; when a read voltage is applied to the plurality of computing memory cells, the computing memory cells generate a plurality of cell currents which are summed into a plurality of memory string currents for charging the loading capacitor; and based a capacitor voltage of the loading capacitor, at least one delay time and a predetermined voltage, an operation result of the input values and the weight values is determined.Type: ApplicationFiled: April 20, 2023Publication date: October 24, 2024Inventors: Yu-Yu LIN, Feng-Min LEE
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Publication number: 20240311620Abstract: A neural network computing method and a neural network computing device are provided. The neural network computing method includes the following steps. At least one chosen layer is decided. A plurality of front layers previous to the chosen layer are decided. A selected element is selected from a plurality of chosen elements in the chosen layer. A front computing data group related to the selected element is defined. The front computing data group is composed of only part of a plurality of front elements in the front layers. The selected element is computed according to the at least one front computing data group.Type: ApplicationFiled: March 17, 2023Publication date: September 19, 2024Inventors: Yu-Yu LIN, Feng-Min LEE
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Publication number: 20240311638Abstract: A method of predicting the efficacy of natural killer cells, including: generating a plurality of training data corresponding to a plurality of donors based on a characteristic factor and a corresponding killing result against the target cancer cells of a plurality of cultured natural killer cells from the donors; obtaining a trained neural network model by inputting the plurality of training data into a neural network model; inputting a to-be-tested input vector corresponding to at least one characteristic factor of a to-be-tested natural killer cell into the trained neural network model to obtain an outputted result vector of the trained neural network model, wherein the result vector indicates a predicted killing result corresponding to the target cancer cell after applying the to-be-tested natural killer cell; and determining a quality of the to-be-tested natural killer cell based on the predicted killing result.Type: ApplicationFiled: December 28, 2023Publication date: September 19, 2024Applicant: Industrial Technology Research InstituteInventors: Nien-Tzu Chou, Yu-Yu Lin, Ching-Fang Lu, Jian-Hao Li, Ting-Hsuan Chen, Cheng-Tai Chen
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Publication number: 20240304238Abstract: The disclosure provides a cache device, which includes: a first transistor having a control terminal, a first terminal, and a second terminal, in which the first terminal of the first transistor is coupled to an input voltage, and the second terminal of the first transistor is coupled to a storage node; an inverter having an input terminal and an output terminal, in which the input terminal is coupled to the storage node; and a second transistor having a control terminal, a first terminal, and a second terminal, in which the first terminal of the second transistor is coupled to the output terminal of the inverter, and the second terminal of the second transistor is configured to output a read voltage.Type: ApplicationFiled: March 8, 2023Publication date: September 12, 2024Applicant: MACRONIX International Co., Ltd.Inventors: Feng-Min Lee, Yu-Yu Lin
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Publication number: 20240282382Abstract: An artificial neural network operation circuit and an in-memory computation device of the artificial neural network operation circuit are proposed. The in-memory computation device includes a memory cell array, a compensation memory cell string, and an operator. The memory cell array has a plurality of memory cells to store a plurality of weight values. The memory cell array has a plurality of word lines and a plurality of bit lines. Each compensation memory cell of the compensation memory cell string stores a unit weight value. The operator multiplies a signal on a compensation bit line by peak weight information of the weight values to generate a first signal and adds the first signal to each signal on the bit lines to obtain a plurality of computation results, respectively.Type: ApplicationFiled: February 22, 2023Publication date: August 22, 2024Applicant: Macronix International Co., Ltd.Inventors: Yu-Hsuan Lin, Yu-Yu Lin, Hsiang-Lan Lung
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Patent number: 12057162Abstract: An in-memory-computing method for a memory device includes: storing weight values in cascaded computing cells each including first and second computing memory cells, wherein the first computing memory cells are cascaded in series into a first computing memory cell string and the second computing memory cells are cascaded in series into a second computing memory cell string: receiving input values by the first and the second computing memory cell strings; performing a first logic operation on the input values and the weight values by the first computing memory cell string to generate a first logic operation result, and performing a second logic operation on the input values and the weight values by the second computing memory cell string to generate a second logic operation result: and performing a third logic operation on the first and the second logic operation results to generate an output logic operation result.Type: GrantFiled: September 2, 2022Date of Patent: August 6, 2024Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Yu-Yu Lin, Feng-Min Lee
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Publication number: 20240257873Abstract: A hybrid in-memory search (IMS) content addressable memory (CAM) cell includes: a first IMS CAM cell; and a second IMS CAM cell, coupled to the first IMS CAM cell. The first IMS CAM cell and the second IMS CAM cell are of different types. When the hybrid IMS CAM cell stores a storage data, the first IMS CAM cell stores a first part of the storage data and the second IMS CAM cell stores the storage data or a second part of the storage data.Type: ApplicationFiled: February 1, 2023Publication date: August 1, 2024Inventors: Po-Hao TSENG, Yu-Hsuan LIN, Tian-Cih BO, Feng-Min LEE, Yu-Yu LIN
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Publication number: 20240244849Abstract: A semiconductor device includes a resistor. The resistor includes two bottom electrodes adjacent to each other, a resistive layer, a top electrode and a conductive sidewall. The resistive layer is disposed on the two bottom electrodes. The top electrode is disposed on the resistive layer. The conductive sidewall surrounds the top electrode and is electrically connected to the top electrode and a bottom electrode of the two bottom electrodes. The top electrode overlaps the two bottom electrodes in the first direction, and extends above the two bottom electrodes along a second direction different from the first direction.Type: ApplicationFiled: January 12, 2023Publication date: July 18, 2024Inventors: Yu-Yu LIN, Feng-Min LEE
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Publication number: 20240242757Abstract: A universal memory for In-Memory Computing and an operation method thereof are provided. The universal memory includes at least one write word line, at least one unit cell and at least one read word line. The unit cell includes a write transistor and a read transistor. The gate of the write transistor is connected to the write word line. The write transistor is a transistor with adjustable threshold voltage. The gate of the read transistor is connected to the drain or the source of the write transistor. The read word line is connected to the drain or the source of the read transistor. The universal memory is used for a training mode and an inference mode. In the training mode and the inference mode, a weight is stored at different locations of the unit cell.Type: ApplicationFiled: April 7, 2023Publication date: July 18, 2024Inventors: Feng-Min LEE, Po-Hao TSENG, Yu-Yu LIN, Ming-Hsiu LEE
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Patent number: 12040015Abstract: A memory device and an operation method thereof for performing a multiply-accumulate operation are provided. The memory device includes at least one memory string, a plurality of data lines and a string line. The memory string includes a plurality of unit cells having a plurality of stored values. The data lines are respectively connected to the unit cells to receive a plurality of data signals having a plurality of inputting values. When the data signals are inputted into the unit cells, a plurality of nodes among the unit cells are kept at identical voltages. The string line is connected to the memory string to receive a sensing signal and obtain a measured value representing a sum-of-product result of the inputting values and the stored values. The data signals and the sensing signal are received at different time.Type: GrantFiled: June 24, 2022Date of Patent: July 16, 2024Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Yu-Yu Lin, Feng-Min Lee
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Publication number: 20240219437Abstract: An in-memory computing (IMC) memory device and an IMC method are provided. The IMC memory device includes: a plurality of memory cells, the memory cells forming a plurality of computing layers; and a plurality of computing layer connectors, the computing layer connectors connecting between the computing layers. A first computing layer input is inputted into a first computing layer of the computing layers. The first computing layer generates a first computing layer output. A first computing layer connector of the computing layer connectors converts the first computing layer output into a second computing layer input. The first computing layer connector inputs the second computing layer input into a second computing layer of the computing layers. The computing layer connectors are a plurality of inverters, a plurality of voltage-to-voltage converters or a plurality of current-to-voltage converters.Type: ApplicationFiled: December 29, 2022Publication date: July 4, 2024Inventors: Yu-Yu LIN, Feng-Min LEE
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Publication number: 20240169625Abstract: Disclosed is an image display format conversion method, comprising: a frame recognition step of performing a frame recognition process on a comic page image to obtain a plurality of comic frame images and frame position information; a frame sequence determination step of determining a frame viewing sequence according to a selected regional layout rule; and a frame reassembly step of reassembling and converting, based on the frame viewing sequence, the plurality of comic frame images into a digital media in an animation-like format or a scrolling-comic format.Type: ApplicationFiled: March 1, 2023Publication date: May 23, 2024Applicant: HYWEB TECHNOLOGY CO., LTD.Inventors: CHUNG-WEI YU, YU-YU LIN