Method of Manufacturing a Semiconductor Device with a Polysilicon-Filled Trench

Abstract

A method of manufacturing a semiconductor device includes forming a trench in a semiconductor body at a first surface of the semiconductor body, forming a polysilicon material in the trench, introducing dopants into the polysilicon material by a high dose and low energy process, and performing a thermal treatment configured to drive-in the dopants into the polysilicon material.

Description

PRIORITY CLAIM

This application is a continuation of U.S. patent application Ser. No. 14/824,339 filed on 12 Aug. 2015, which in turn is a divisional of U.S. patent application Ser. No. 14/305,359 filed on 16 Jun. 2014 (now U.S. Pat. No. 9,142,401), which in turn is a divisional of U.S. patent application Ser. No. 13/473,231 filed on 16 May 2012 (now U.S. Pat. No. 8,785,997), each of said applications incorporated herein by reference in their entirety.

BACKGROUND

Edge termination areas of semiconductor devices, e.g. power semiconductor devices having blocking voltage capabilities of several hundreds or thousands of volts, are sensitive to charges accumulated in dielectrics covering surfaces. Both positive and negative charges may affect the blocking voltage capabilities of semiconductor devices, e.g. Insulated Gate Bipolar Transistors (IGBTs), FETs (Field Effect Transistors) or diodes, adversely. Since charges accumulated in dielectrics may be displaced by electrical fields, this may lead to instabilities during operation of the semiconductor devices. Any kind of junction terminations, e.g. field rind structures, Variation of Lateral Doping (VLD) edge termination structures or Junction Termination Extension (JTE) edge termination structures may be affected adversely and deteriorate a reliability of the semiconductor device. In the edge termination area, a considerable amount of undesired charges may accumulate since the edge termination area may contribute to a substantial part an overall chip area. As an example, positive charges in oxides may be due to presence of alkaline metals, e.g, sodium (Na) and/or potassium (K), and negative charges may due to presence of impurities, e.g, OH⁻.

It is desirable to improve the reliability of semiconductor devices and to provide a method of manufacturing a semiconductor device.

SUMMARY

According to an embodiment of a semiconductor device, the semiconductor device includes a semiconductor body including a first surface. The semiconductor device further includes a continuous silicate glass structure over the first surface. A first part of the continuous glass structure over an active area of the semiconductor body includes a first composition of dopants that differs fro a second composition of dopants in a second part of the continuous glass structure over an area of the semiconductor body outside of the active area.

According to another embodiment of a semiconductor device, the semiconductor device includes a semiconductor body including a first surface. The semiconductor device further includes a continuous silicate glass structure over the first surface. At least a part of the continuous glass structure includes a concentration of at least one of phosphor and boron that decreases by at least a factor of two between a first side and a second side of the continuous glass structure, wherein the second side is closer to the first surface of the semiconductor body than the first side.

According to another embodiment of a semiconductor device, the semiconductor device includes a semiconductor body including a first surface. The semiconductor device further includes a continuous silicate glass layer stack over the first surface. The silicate glass layer stack includes at least one BPSG layer and one PSG layer.

According to an embodiment of a method of manufacturing a semiconductor device, the method includes forming a continuous silicate glass structure over a first surface of a semiconductor body including a first part of the continuous glass structure over an active area of the semiconductor body and a second part of the continuous glass structure over an area of the semiconductor body outside of the active area. A first composition of dopants included in the first part of continuo is glass structure differs from a second composition of dopants in the second part of the continuous glass structure.

According to another embodiment of a method of manufacturing a semiconductor device, the method includes forming a continuous silicate glass structure over a first surface of a semiconductor body. The method further includes forming a concentration of at least one of phosphor and boron in at least a part of the continuous glass structure that decreases by at least a factor of two between a first side and a second side of the continuous glass structure. The second side is closer to the first surface of the semiconductor body than the first side.

Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of the specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain principles of the invention. Other embodiments of the invention and many of the intended advantages will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.

FIG. 1 illustrates a cross-sectional view of one embodiment of a semiconductor device including a silicate glass structure having different compositions of dopants in a first area and in a second area.

FIG. 2 illustrates a cross-sectional view of one embodiment of a semiconductor device including a silicate glass structure having different compositions of dopants in a first area including a silicate glass layer stack and in a second area.

FIGS. 3 and 4A illustrate cross-sectional views of embodiments of a semiconductor device including a silicate glass structure having different compositions of dopants in a first area and in a second area including a silicate glass layer stack.

FIG. 4B illustrates a cross-sectional view of another embodiment of a semiconductor device including a silicate glass layer stack.

FIG. 5 illustrates a cross-sectional view of one embodiment of a semiconductor device including a silicate glass structure having silicate areas including dopants implanted at high dose and low energy.

FIG. 6 illustrates one example of a profile of implanted phosphor along a line AA′ illustrated in FIG. 5.

FIG. 7 illustrates one embodiment o a process flow of manufacturing a semiconductor device including a silicate glass structure having different compositions of dopants in a first area and in a second area.

FIG. 8 illustrates one embodiment of a process flow of manufacturing a semiconductor device including a silicate glass structure having silicate areas including dopants implanted at high dose and low energy.

FIGS. 9A to 9D illustrate schematic cross sectional views of a semiconductor body undergoing high dose and low energy implants into a polysilicon layer in a trench.

DETAILED DESCRIPTION

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustrations specific embodiments in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. For example, features illustrated or described as part of one embodiment can be used in conjunction with other embodiments to yield yet a further embodiment. It is intended that the present invention includes such modifications and variations. The examples are described using specific language which should not be construed as limiting the scope of the appending claims. The drawings are not scaled and are for illustrative purposes only. For clarity, the same elements or manufacturing processes are designated by the same references in the different drawings if not stated otherwise.

As employed in the specification, the term “electrically coupled” is not meant to mean that the elements must be directly coupled together. Instead, intervening elements may be provided between the “electrically coupled” elements. As an example, none, part, or all of the intervening element(s) may be controllable to provide a low-ohmic connection and, at another time, a non-low-ohmic connection between the “electrically coupled” elements. The term “electrically connected” intends to describe a low-ohmic electric connect on between the elements electrically connected together, e.g., a connection via a metal and/or highly doped semiconductor.

Some Figures refer to relative doping concentrations by indicating “⁻” or “⁺” next to the doping type. For example, “n³¹ ” means a doping concentration which is less than the doping concentration of an “n”-doping region while an “n⁺”-doping region has a larger doping concentration than the “n”-doping region. Doping regions of the same relative doping concentration may or may not have the same absolute doping concentration. For example, two different n⁺-doped regions can have different absolute doping concentrations. The same applies, for example, to an n⁻-doped and a p⁺-doped region. In the embodiments described below, a conductivity type of the illustrated semiconductor regions is denoted n-type or p-type, in more detail one of n⁻-type, n-type, n⁺-type, p⁻-type, p-type and p⁺-type. In each of the illustrated embodiments, the conductivity type of the illustrated semiconductor regions may be vice versa. In other words, in an alternative embodiment to any one of the embodiments described below, an illustrated p-type region may be n-type and an illustrated n-type region may be p-type.

FIG. 1 illustrates a cross-sectional view of a semiconductor device 100 according to an embodiment. The semiconductor device 100 includes a semiconductor body 105 having a first surface 110. A continuous silicate glass structure 115 is formed over the first surface 110. A first part 115a of the continuous glass structure 115 over an active area 105a of the semiconductor body 105 includes a first composition of dopants that differs from a second composition of dopants in a second part 115b of the continuous glass structure 115 over an area 105b of the semiconductor body 105 outside of the active area 105a.

The semiconductor device 100 may be any semiconductor device including IGBT, FET, e.g. Metal Oxide Semiconductor FET (MOSFET) and diode. According to one embodiment, the semiconductor device 100 is a power semiconductor device operating on similar principles to its low-power counterpart, but being able to carry a larger amount of current and typically also supporting a larger reverse-bias voltage in the off-state. As an example the semiconductor device 100 is a power semiconductor device configured to block reverse-bias voltages exceeding 30 V and/or switching currents exceeding 1 A.

The semiconducto body 105 may include a semiconductor substrate, e.g. a silicon substrate, a compound semiconductor substrate, a silicon on insulator (SOI) substrate, including none, one or a plurality of semiconductor layers, e.g. epitaxial semiconductor layers, formed thereon.

In the active area 105a of the semiconductor device 100, device elements are present that are absent in the area 105b surrounding the active area 105a. As an example, the area 105b surrounding the active area 105a may include an edge termination area including one or more of field ring structures, VLD edge termination structures and JTE edge termination structures. Device elements present in the active area 105a and absent in the area 105b surrounding the active area 105a may include gate electrode and/or source and/or body of IGBTs and FETs and anode emitter or cathode emitter of a diode.

According to one embodiment, the silicate glass structure 115 adjoins the semiconductor body 105 at the surface 110 in the area 105b. In other words, the silicate glass structure 115 is in contact with the semiconductor body 105 in the area 105b. The silicate glass structure 115 may include through hole portions, e.g. in the active area 105a and/or the area 105b that may include contact structures configured to electrically couple semiconductor regions in the semiconductor body 105 and a wiring arranged above the silicate glass structure 115.

According to one embodiment, a thickness d₁ of the silicate glass structure 115 in the first part 115a equals a thickness d₂ in the second part 115b. As an example, the different compositions of dopants in the first part 115a and in the second part 115b, i.e. the first and second compositions, may be formed by introducing dopants into one of the first part 115a and the second part 115b by an appropriate method, e.g. by introducing the dopants during epitaxial deposition or by ion implantation including ion shower implantation or plasma deposition for high dose and low energy implants. As a further example, the different compositions of dopants in the first part 115a and in the second part 115b may be formed by introducing different types and/or concentrations of dopants into the first part 115a and the second part 115b by an appropriate method, e.g. ion implantation including ion shower implantation for high dose and low energy implants.

According to another embodiment, a thickness d₁ of the silicate glass structure 115 in the first part 115a is larger than a thickness d₂ of the second part 115b, i.e. d₁>d₂. As an example, the first part 115a may include a higher number of stacked silicate glass layers than the second part 115b. According to yet another embodiment, a thickness d₁ of the silicate glass structure 115 in the first part 115a is smaller than a thickness d₂ of the second part 115b, i.e. d₁<d₂. As an example, the first part 115a may include a lower number of stacked silicate glass layers than the second part 115b.

According to one embodiment at least one wiring level including a metal is arranged over the continuous silicate glass structure 115 and a wiring level including a metal is absent between the continuous silicate glass structure 115 and the surface 110 of the semiconductor body 105 in the second area 105b. In the active area 105a, the continuous silicate glass structure 115 may include through holes including contacts.

Formation of different compositions of dopants in the first part 115a and in the second part 115b of the silicate glass structure 115 allows better adjustment of the characteristics of the silicate glass structure 115 to the specific requirements in the first part 115a and in the second part 115b which may differ. As an example, requirements on flow characteristic of the silicate glass structure 115 may be higher in the first part 115a than in the second part 115b due to more pronounced topology within the active cell area than in the edge termination area. This allows focusing on gettering efficiency in the edge termination area and flow characteristic in the active cell area, e.g. by using getter-efficient phosphosilicate glass (PSG) in the edge termination area which usually is the most sensitive area in respect to positive or negative charges due to relatively high electrical fields in this area and borophosphosilicate glass (BPSG) having a beneficial flow characteristic in the active cell area. Since different compositions of dopants in the silicate glass structure 115 allow to improve different characteristics of the silicate glass structure, the reliability of the semiconductor device can be improved by adjusting the compositions of dopants in the silicate glass structure 115 to the specific requirements in the first part 115a and in the second part 115b.

According to one embodiment of a semiconductor device 200 illustra ed in FIG. 2, the first part 115a of the continuous silicate glass structure 115 includes a borophosphosilicate glass (BPSG) layer 117. The first part 115a of the continuous glass structure 115 includes a silicate glass layer stack and the BPSG layer 117 is a lowermost layer of the stack and has a shorter distance to the first surface 110 of the semiconductor body 105 than an uppermost silicate glass layer 118 of the layer stack. Between the BPSG layer 117 and the uppermost silicate glass layer 118, none, one or a plurality of additional silicate glass layers may be formed. The layer stack in the first part 115a of the silicate glass structure 115 includes at least one of a borosilicate glass (BSG) layer and a phosphosilicate glass (PSG) layer over the BPSG layer 117. According to one example, the uppermost layer 118 is the phosphosilicate glass (PSG) layer. According to another embodiment, an optional silicate glass layer sandwiched between the BPSG layer 117 and the uppermost silicate glass layer 118 is the PSG layer. According to another embodiment, an undoped silicate glass (USG) layer may be arranged between the semiconductor body 105 and the BPSG layer 117, e.g. a thin USG layer. Further, an USG layer may be arranged on the uppermost silicate glass layer 118 to avoid or reduce diffusion of dopants out of the silicate glass structure 115 into the semiconducto body 105 and/or ambient. Thereby, an interaction or reaction between the dopant and the ambient, e.g. phosphoric acid, may be prevented or reduced. This allows to use higher P concentrations as usual, e.g. more than 8% or more than 10%. As a further example, the BPSG layer 117 may also be a PSG layer and the PSG layer 118 may be a BPSG layer.

According to one embodiment, a silicate glass layer 119 in the second part 115b of the silicate glass structure 115 is formed together with the uppermost layer 118 in the first part 115a, e,g. by conformal layer deposition after patterning the BPSG layer 117 and optional (additional) undoped or doped silicate glass layers thereon. The silicate glass layers 118, 119 may include a stack of single silicate glass layers or a single PSG layer. According to another embodiment, the silicate glass layers 118 and 119 are subsequently formed, e.g. the silicate glass layer 118 is formed before the silicate glass layer 119. In this case, the silicate glass layer 118 may be patterned together with the BPSG layer 117. According to another example, the silicate glass layer 119 is formed before the silicate glass layer 118. A thickness d₁ of the continuous silicate glass structure 115 in the first part 115a is higher than a thickness d₂ of the continuous silicate glass structure 115 in the second part 115b.

As used herein, a ratio of percentage by weights between boron and phosphor, i.e, B/P in BPSG is in a range of 30% to 70%. A ratio of percentage by weights between boron and phosphor, i.e. B/P in PSG is in a range of 0% to 10%. A ratio of percentage by weights between boron and phosphor, i.e. B/P in BSG is in a range of 90% to 100%. Further, a concentration of at least one of B and P in BPSG, PSG and BSG includes at least 10²⁰ cm⁻³, or at least 5×10²⁰ cm⁻³ or at least 3×10²¹ cm⁻³.

According to one embodiment of a semiconductor device 300 illustrated in FIG. 3, the second part 115b of the continuous silicate glass structure 115 includes a PSG layer 121. The second part 115b of the continuous glass structure 115 includes a silicate glass layer stack and the PSG layer 121 is a lowermost layer of the stack and has a shorter distance to the first surface 110 of the semiconductor body 105 than an uppermost silicate glass layer 122 of the layer stack. Between the PSG layer 121 and the uppermost silicate glass layer 122, none, one or a plurality of additional silicate glass layers may be formed. The layer stack in the second part 115b includes at least one of a BSG layer and a BPSG layer over the PSG layer 121. According to one example, the uppermost layer 122 is a BSG layer. According to another embodiment, an optional silicate glass layer sandwiched between the PSG layer 121 and the uppermost silicate glass layer 122 is a BPSG layer.

According to one embodiment, a silicate glass layer 123 in the first part 115a of the silicate glass structure 115 is formed together with the uppermost layer 122 in the second part 115b, e.g. by conformal layer deposition after patterning the PSG layer 121 and optional additional silicate glass layers thereon. The silicate glass layers 122, 123 may include a stack of single silicate glass layers. According to another embodiment, the silicate glass layers 122 and 123 are subsequently formed, e.g. the silicate glass layer 122 is formed before the silicate glass layer 123. In this case, the silicate glass layer 122 may be patterned together with the PSG layer 121. According to another example, the silicate glass layer 123 is formed before the silicate glass layer 122. A thickness d₁ of the continuous silicate glass structure 115 in the second part 115b is higher than a thickness of the continuous silicate glass structure 115 in the first part 115a. Similar to the embodiment described above, an USG layer may be provided between the semiconductor body 105 and the PSG layer 121 and/or silicate glass layer 123, e.g. a thin USG layer, or on the silicate glass layers 122 and/or 123.

According to one embodiment of a semiconductor device 400 illustrated in FIG. 4A, the second part 115b of the continuous silicate glass structure 115 includes a BSG layer 124. The second part 115b of the continuous glass structure 115 includes a silicate glass layer stack and the BSG layer 124 is a lowermost layer of the stack and has a shorter distance to the first surface 110 of the semiconductor body 105 than an uppermost silicate glass layer 125 of the layer stack. Between the BSG layer 124 and the uppermost silicate glass layer 125, none, one or a plurality of additional silicate glass layers may be formed. The layer stack in the second part 115b includes at least one of a PSG layer and a BPSG layer over the BSG layer 124. According to one example, the uppermost layer 125 is a PSG layer. According to another embodiment, an optional silicate glass layer sandwiched between the BSG layer 124 and the uppermost silicate glass layer 125 is a PSG layer.

According to one embodiment, a silicate glass layer 126 in the first part 115a is formed together with the uppermost layer 125 in the second part 115b, e.g, by conformal layer deposition after patterning the BSG layer 124 and optional additional silicate glass layers thereon. The silicate glass layers 125, 126 may include a stack of single silicate glass layers. According to another embodiment, the silicate glass layers 125 and 126 are subsequently formed, e.g. the silicate glass layer 125 is formed before the silicate glass layer 126. In this case, the silicate glass layer 125 may be patterned together with the BSG layer 124. According to another example, the silicate glass layer 126 is formed before the silicate glass layer 125. A thickness d₂ of the continuous silicate glass structure 115 in the second part 115b is higher than a thickness d₁ of the continuous silicate glass structure 115 in the first part 115a. Similar to the embodiment described above, an USG layer may be provided between the semiconductor body 105 and the BSG layer 124 and/or silicate glass layer 126, e.g. a thin USG layer, or on the silicate glass layers 125 and/or 126.

According to one embodiment, the first composition of dopants in the first part 115a of the silicate glass structure 115 that differs from the second composition of dopants in the second part 115b is formed by a high dose and low energy implant, e.g. by a masked ion shower implant or by a masked plasma deposition, in one or a plurality of the silicate glass layers 117 . . . 126 of the embodiments illustrated in FIGS. 2 to 4A or into one part, e.g. the first part 115a or the second part 115b, of the silicate glass structure 115 described in the above embodiment illustrated in FIG. 1. That part of the silicate glass structure 115 that includes dopants introduced by the high dose and low energy implant includes a concentration of at least one of phosphor and boron that decreases by at least a factor of two between a first side and a second side of the continuous glass structure 115, wherein the second side is closer to the first surface 110 of the semiconductor body 105 than the first side. According to an embodiment, a dose of the at least one of phosphor and boron introduced into the silicate glass structure 115 by the high dose and low energy implant is in a range between 5×10¹⁶ cm⁻² and 5×10¹⁷ cm⁻². As an example, the second part 115b includes dopants introduced by the high dose and low energy implant so that a concentration of at least one of phosphor and boron decreases by at least a factor of two between a first side and a second side of the continuous glass structure 115.

According to one embodiment of a semiconductor device 450 illustrated in FIG. 4B, a continuous silicate glass layer stack 460 over a surface 470 of a semiconductor body 465 includes a PSG layer 461 and a BPSG layer 462. Formation of the continuous silicate glass layer stack 460 may be carried out ithout lithography. The continuous silicate glass layer stack 460 may include further silicate glass layers, e.g. optional USG or BSG layers or even further PSG or BPSG layers. These layers may be arranged below, between or above the PSG layer 461 and the BPSG layer 462. The arrangement of the PSG layer 461 and the BPSG layer 462 may also be opposite to the illustration of FIG. 4B, i.e. the PSG layer 461 may be arranged over the BPSG layer 462. As an example, the continuous silicate layer stack 460 may include a sequence of an optional USG layer, a PSG layer, an optional BSG layer and a BPSG layer. The doping of these layers can be realized by introducing the dopants during the deposition of these layers or by implants or plasma deposition steps performed after the deposition of each layer.

FIG. 5 illustrates a cross-sectional view of a semiconductor device 500 according to an embodiment. The semiconductor device 500 includes a semiconductor body 505 having a first surface 510. A continuous silicate glass structure 515 is formed over the first surface 110. At least a part of the continuous glass structure 515, e.g. silicate glass areas 526 and 527 or even an overall area of the continuous glass structure 515, include a concentration of at least one of phosphor and boron that decreases by at least a factor of two or even at least a factor of 10 between a first side 530 and a second side 531 of the continuous glass structure 515, wherein the second side 531 is closer to the first surface 510 of the semiconductor body 505 than the first side 530.

The semiconductor device 500 may be any semiconductor device including IGBT, FET, e.g. Metal Oxide Semiconductor FET (MOSFET) and diode. According to one embodiment, the semiconductor device 500 is a power semiconductor device operating on similar principles to its low-power counterpart, but being able to carry a larger amount of current and typically also supporting a larger reverse-bias voltage in the off-state. As an example the semiconductor device 500 is a power semiconductor device configured to block reverse-bias voltages exceeding 30 V and/or switching currents exceeding 1 A, including e.g. reverse-bias voltages in the range of kV or 10 kV and currents in the range of kA.

In the silicate glass areas 526 and 527 of the continuous glass structure 515, the at least one of phosphor and boron that decreases by at least a factor of two or even at least a factor of 10 between the first side 530 and the second side 531 may be introduced into the silicate glass areas 526 and 527, e.g. in implant areas 526a, 527a, by a high dose and low energy implant, e.g. by an ion shower implant or by plasma deposition.

According to an embodiment, the continuous silicate glass structure 515 is a BPSG layer and the at least one of phosphor and boron that decreases by at least a factor of two between the first side 530 and the second side 531 in the silicate glass areas 526 and 527 is phosphor.

According to an embodiment, the silicate glass areas 526, 527 of the continuous glass structure 515 are lo ated in an area surrounding an active area of the semiconductor device 500. As an example, the silicate glass areas 526, 527 may be located in an edge termination area including one or more of field ring structures, VLD edge termination structures and JTE edge termination structures. Device elements present in the active area may be absent in an area surrounding the active area. As an example, a gate electrode and/or a source and/or a body of IGBTs and FETs and anode emitter or cathode emitter of a diode may be present in the active area but absent in the area surrounding the active area.

As an example, the silicate glass structure 515 may adjoin the semiconductor body 505 in at least part of the surface 510. In other words, the silicate glass structure 515 may be in contact with the semiconductor body 505 in at least part of the surface 510. As a further example, between the first surface 510 and the silicate glass structure 515 one or plural dielectrics may be arranged, e.g, silicon oxide. The silicate glass structure 515 may include through hole portions that may include contact structures configured to electrically couple semiconductor regions in the semiconductor body 505 and a wiring arranged above the silicate glass structure 515.

The specific embodiment illustrated in FIG. 5 includes two distinct silicate glass areas 526 and 527 including at least one of phosphor and boron that decreases by at least a factor of two between the first side 530 and the second side 531 of the continuous glass structure 515. According to another embodiment, an overall part or predominant part of the silicate glass structure 527 includes at least one of phosphor and boron that decreases by at least a factor of two between the first side 530 and the second side 531 of the continuous glass structure 515. Further, any number of distinct silicate glass areas including at least one of phosphor and boron that decreases by at least a factor of two or even at least a factor of 10 between the first side 530 and the second side 531 of the continuous glass structure 515 may be formed.

When forming the silicate glass structure 515 of BPSG and further introducing phosphor into the silicate glass structure 515 via the first side 530 in an amount that decreases by at least a factor of two or even at least a factor of 10 between the first side 530 and the second side 531 of the continuous glass structure 515, this allows to make use of a) beneficial flow characteristics of BPSG and b) beneficial gettering characteristic similar to PSG in the area including the increased amount of phosphor. As an example, introducing additional phosphor in an amount that decreases by at least a factor of two or even at least a factor of 10 between the first side 530 and the second side 531 of the continuous glass structure 515 may be carried out in an edge area of a chip and/or in an area of a wafer corresponding to a wafer dicing track. Further, by introducing phosphor and/or boron into the silicate glass layer 515 via masked implantation, the flow characteristic of the silicate glass layer 515 may be improved in areas that are sensitive to positive or negative charges or have a critical or pronounced topology. As an example, implanted areas in the range several 10 μm² to several 100 μm²may be provided in areas which are sensitive to positive or negative charges or have a critical or pronounced topology. These implanted areas may be arranged in a pattern of islands, for example. Some or all of the islands may be separate from each other, may overlap, may differ in size and/or shape.

FIG. 6 illustrates one example of profile of phosphor along a line A-A′ through the silicate glass area illustrated in FIG. 5. The profile of phosphor decreases along a depth z from the first side 530 of the cont nuous glass structure 515 illustrated in FIG. 5 to the second side 531 illustrated in FIG. 5. In a part p₁ the profile corresponds to an implant profile after thermal anneal/drive-in whereas a second part p₂ includes a constant or almost constant amount of phosphor present in a BPSG layer. Apart from the specific profile of phosphor illustrated in FIG. 6, a vast variety of different profiles may be formed provided that the concentration of phosphor decreases by at least a factor of two between the first side 530 and the second side 531. As an example, implanted phosphor may reach the second side 531 by diffusion. As an example, a dose of the implanted phosphor is in a range between 5×10¹⁶ cm⁻² and 5×10¹⁷ cm⁻². Implant voltages may be in a range of 0.1 kV to 30 kV, or in a range of 0.5 kV to 20 kV, for example.

FIG. 7 illustrates one embodiment of a process flow of manufacturing a semiconductor device. Process feature S100 includes forming a continuous silicate glass structure over a first surface of a semiconductor body including a first part of the continuous glass structure over an active area of the semiconductor body and a second part of the continuous glass structure over an area outside of the active area, wherein a first composition of dopants included in the first part of continuous glass structure differs from a second composition of dopants of the second part of the continuous glass structure.

According to one embodiment, the process flow further includes forming a first silicate glass layer of the continuous silicate glass structure over the active area and the area outside of the active area, removing at least a part of the first silicate glass layer over the area outside of the active area and forming a second silicate glass layer of the continuous silicate glass structure over the active area and the area outside of the active area. According to one embodiment, the first silicate glass layer includes BPSG and the second silicate glass layer includes at least one of PSG and BSG.

According to another embodiment, the process flow further includes forming a first silicate glass layer of the continuous silicate glass structure over the active area and the area outside of the active area, removing the first silicate glass layer over the active area, and forming a second silicate glass layer of the continuous silicate glass structure over the active area and the area outside of the active area. According to one embodiment, the first silicate glass layer includes at least one of PSG and BSG and the second silicate glass layer includes BPSG.

According to yet another embodiment, the process flow further includes forming a first silicate glass layer of the continuous silicate glass structure over the active area and the area outside of the active area, removing the first silicate glass layer over the active area, forming a second silicate glass layer of the continuous silicate glass structure over the active area and the area outside of the active area, and removing the second silicate glass layer over the area outside of the active area.

FIG. 8 illustrates one embodiment of a process flow of manufacturing a semiconductor device. Process feature S200 includes forming a continuous silicate glass structure over a first surface of a semiconductor body. Process feature S210 includes forming, in at least a part of the continuous gla structure, includes a concentration of at least one of phosphor and boron that decreases by at least a factor of two between a first side and a second side of the continuous glass structure, wherein the second side is closer to the first surface of the semiconductor body than the first side.

According to one embodiment, the continuous silicate glass structure is formed as BPSG and phosphor is planted in at least a part of the continuous glass structure with high dose at low energy, wherein a profile of the implanted boron decreases by at least a factor of two between a first side and a second side of the continuous glass structure.

According to another embodiment, the continuous silicate glass structure is formed as an undoped silicate glass (USG) and boron is implanted in at least a part of the continuous glass structure with high dose at low energy, wherein a profile of the implanted boron decreases by at least a factor of two between a first side and a second side of the continuous glass structure. A third undoped silicate glass layer can be optionally deposited between the semiconductor and the BPSG layer and another undoped silicate glass layer can be optionally deposited on the phosphorous doped BPSG layer.

According to another embodiment, the continuous silicate glass structure is formed as a stack of BSG and USG and boron is implanted in at least a part of the USG with high dose at low energy, wherein a profile of the implanted boron decreases by at least a factor of two between a first side and a second side of the continuous glass structure.

According to yet another embodiment, the continuous silicate glass structure is formed as an USG and boron and phosphor are implanted subsequently in arbitrary sequence in same or different parts of the continuous glass structure with high dose at low energy, wherein a profile of each one of the implanted boron and phosphor decreases by at least a factor of two between a first side and a second side of the continuous glass structure. Optionally, an annealing step can be performed between the individual implantation steps and/or after all implantation steps.

As an example, a dose of the at least one of phosphor and boron is in a range between 5×10¹⁶ cm⁻² and 5×10¹⁷ cm⁻². Implant voltages may be in a range of 0.1 kV to 30 kV, or in a range of 0.5 kV to 20 kV, for example. High dose and low energy implants may also be applied when doping polysilicon material in a trench.

FIG. 9A illustrates a cross sectional view of a semiconductor body 905 during manufacture of a semiconductor device, e.g. a FET or IGBT. The processing stage illustrated in FIG. 9A starts with the semiconductor body 905 including a trench 940 at a first surface 910. The trench 940 includes an optional field electrode 942 and a polysilicon gate electrode 944. The optional field electrode 942 and the gate electrode 944 are surrounded by a dielectric structure 946 acting as a gate dielectric between the gate electrode 944 and the semiconductor body 905. The polysilicon gate electrode 944 may be undoped or lightly doped.

Boron is implanted at high dose and low energy into a part 949 of the polysilicon gate electrode 944 at the first surface 910. As an example, a dose of the at least one of phosphor and boron is in a range between 5×10¹⁶ cm⁻² and 5×10¹⁷ cm⁻². Implant voltages may be in a range of 0.1 kV to 30 kV, or in a range of 0.5 kV to 20 kV, for example.

As is illustrated in the cross sectional view of FIG. 9B, a thermal treatment leads to drive-in of the implanted boron into a depth of the polysilicon gate electrode 944 leading to a low or medium p-doping in a bottom and medium part of the polysilicon gate electrode 944 while a p⁺-doping remains in a top part of the polysilicon gate electrode 944 at the first surface 910. This allows for a reduced path resistance of the polysilicon gate electrode 944 due to the p⁺-doping in the top part while counteracting diffusion of boron through the gate oxide due to the low or medium p-doping in the medium part of the polysilicon gate where the gate oxide is located.

FIG. 9C illustrates a cross sectional view of a semiconductor body 955 during manufacture of a semiconductor device, e.g. a FET or IGBT. The processing stage illustrated in FIG. 9C starts with the semiconductor body 955 including a trench 990 at a first surface 960. The trench 990 includes an optional field electrode 992 and a conformal polysilicon layer 995. The optional field electrode 992 is surrounded by a dielectric structure 996 and the conformal polysilicon layer 995 is adjoining the dielectric structure 996. The conformal polysilicon layer 995 may be undoped or lightly doped.

Boron is implanted at high dose and low energy into a surface of the conformal polysilicon layer 995 in a bottom part 999a of the trench 990 as well into a surface part 999b of the conformal polysilicon layer 995 on the first surface 960. As an example, a dose of the at least one of phosphor and boron is in a range between 5×10¹⁶ cm⁻² and 5×10¹⁷ cm⁻². Implant voltages may be in a range of 0.1 kV to 30 kV, or in a range of 0.5 kV to 20 kV, for example.

As is illustrated in the cross sectional view of FIG. 9D, the conformal polysilicon layer 995 is removed on the first surface 960, e.g. by an appropriate process such as etching or chemical mechanical polishing (CMP). A thermal treatment leads to drive-in of the implanted boron from the bottom part 999a of the conformal polysilicon layer 995 leading to a low or medium p-doping in a top part of the conformal polysilicon layer 995 in the trench 990 while a p⁺-doping remains in a bottom part of the conformal polysilicon layer 995. Thereby, variable path resistances may be realized along an extension of a trench, e,g. a trench stripe allowing to damp fast cycles of operation that may tend to resonant oscillations. According to other embodiments, subsequent high dose and low energy implants of phosphor and boron into polysilicon material in a trench allows to manufacture Zener diodes, diodes, npn or pnp structures that may be used in temperature sensors, for example. As an example, a high concentration of dopants buried at a bottom side of polysilicon in a trench may be formed.

In the embodiments illustrated in FIGS. 9A to 9D boron is implanted into the polysilicon gate electrode at high dose and low energy. According to other examples, phosphor may be likewise implanted into the polysilicon gate electrode at high dose and low energy.

Terms such as “first”, “second”, and the like, are used to describe various structures, elements, regions, sections, etc. and are not intended to be limiting. Like terms refer to like elements throughout the description.

The terms “having”, “containing”, “including”, “comprising” and the like are open and the terms indicate the presence of stated elements or features, but not preclude additional elements or features. The articles “a”, “an” and “the” are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

It is to be understood that the features of the various embodiments described herein may be combined with each other, unless specifically noted otherwise.

Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

forming a trench in a semiconductor body at a first surface of the semiconductor body;

forming a polysilicon material in the trench;

introducing dopants into the polysilicon material by a high dose and low energy process; and

performing a thermal treatment configured to drive-in the dopants into the polysilicon material.

2. The method of claim 1, wherein the high dose and low energy process is an ion shower implantation or a plasma deposition.

3. The method of claim 1, wherein the dopants are introduced at a dose in a range between 5×1016 cm−2 and 5×1017 cm−2.

4. The method of claim 1, wherein the dopants are introduced at an implant voltage in a range of 0.1 kV to 30 kV.

5. The method of claim 1, wherein one or both of phosphorus and boron are introduced as the dopants.

6. The method of claim 1, further comprising forming a gate dielectric in the trench prior to forming the polysilicon material in the trench.

7. The method of claim 6, further comprising forming a dielectric structure and a field electrode in the trench prior to forming a gate dielectric in the trench.

8. The method of claim 1, wherein, prior to introducing dopants into the polysilicon material by the high dose and low energy process, the polysilicon material is formed as a undoped or lightly doped polysilicon material.

9. The method of claim 1, wherein the polysilicon material is formed as a conformal polysilicon layer including a sidewall part and a bottom part.

10. The method of claim 9, wherein the thermal treatment leads to drive-in of the dopants from the bottom part of the conformal polysilicon layer to the sidewall part, and results in a lower doping concentration of the conformal polysilicon layer in the sidewall part than in the bottom part.

11. The method of claim 1, wherein forming the polysilicon material in the trench comprises filling the trench with the polysilicon material.

12. The method of claim 11, wherein the thermal treatment leads to drive-in of the dopants from a top part of the polysilicon material to a medium part of the polysilicon material, and results in a lower doping concentration of the polysilicon material in the medium part than in the top part.

13. The method of claim 1, wherein the polysilicon material is part of one or more of a gate structure, a zener diode, a diode, and a temperature sensor.

14. A semiconductor device, comprising:

a trench in a semiconductor body at a first surface of the semiconductor body;

a polysilicon material filling the trench up to the first surface; and

dopants in the polysilicon material,

wherein a dose of the dopants is in a range between 5×1016 cm−2 and 5×1017 cm−2,

wherein a doping concentration of the polysilicon material is lower in a medium part of the polysilicon material than in a top part of the polysilicon material.

15. The semiconductor device of claim 14, wherein the polysilicon material is part of one or more of a gate structure, a zener diode, a diode, and a temperature sensor.

16. The semiconductor device of claim 14, wherein the polysilicon material is a gate electrode, the semiconductor device further comprising a gate dielectric in the trench, a field electrode in the trench, and a dielectric structure in the trench electrically insulating the gate electrode and the field electrode.

17. A semiconductor device, comprising:

a trench in a semiconductor body at a first surface of the semiconductor body;

a conformal polysilicon layer in the trench, the conformal polysilicon layer including a sidewall part and a bottom part; and

dopants in the conformal polysilicon layer,

wherein a dose of the dopants is in a range between 5×1016 cm−2 and 5×1017 cm−2,

wherein a doping concentration of the conformal polysilicon layer is lower in the sidewall part than in the bottom part.

18. The semiconductor device of claim 17, wherein the conformal polysilicon layer is part of one or more of a gate structure, a zener diode, a diode, and a temperature sensor.

19. The semiconductor device of claim 17, wherein the conformal polysilicon layer is a gate electrode, the semiconductor device further comprising a gate dielectric in the trench, a field electrode in the trench, and a dielectric structure in the trench electrically insulating the gate electrode and the field electrode.