SEMICONDUCTOR STRUCTURE WITH JUNCTION LEAKAGE REDUCTION

A semiconductor structure is provided, which includes a semiconductor substrate, a first well region, a second well region, an active region, a shallow trench isolation (STI) and at least one deep trench isolation (DTI). The first well region of a first conductive type is on the semiconductor substrate. The second well region of a second conductive type is on the semiconductor substrate and adjacent to the first well region. The second conductive type is different from the first conductive type. The active region is on the first well region. The active region has a conductive type the same as the second conductive type of the second well region. The STI is between the first and second well regions. The DTI is below the STI. The DTI is disposed between at least a portion of the first well region and at least a portion of the second well region.

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Description
BACKGROUND

With the development of communications technologies and electronic material technologies, communication devices, such as mobile devices and wearable electronic devices, have become more and more important in human's daily life. For example, the Internet of Things (IoT) acts as an infrastructure, in which objects, animals or people are provided with unique identifiers and the ability to exchanging data over a network. Among the IoT applications, wearable devices have the advantages of wearable characteristics and small size. An embedded flash integrated circuit may be applied to such wearable devices for minimizing device size. However, such embedded flash integrated circuit may generate a non-negligible leakage current that results in additional power consumption, and consequently shortening standby time of the wearable devices. How to reduce leakage current in small and concentrative integrated circuits has now become one of the major tasks in related industries.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1A through FIG. 1H are schematic cross-sectional views of intermediate stages illustrating a method of forming a semiconductor device in accordance with some embodiments.

FIG. 2A through FIG. 2B are schematic cross-sectional views of intermediate stages illustrating a method of forming a deep trench of a semiconductor device in accordance with another embodiments.

FIG. 3 is a flow chart of a method of forming a semiconductor substrate in accordance with various embodiments.

FIG. 4A through FIG. 4C are schematic cross-sectional views of intermediate stages illustrating a method of forming a semiconductor device in accordance with some embodiments.

FIG. 5 illustrates formation of a well region using an ion implantation process with non-zero tilting angle in accordance with some embodiments.

FIG. 6 illustrates formation of a well region using an ion implantation process in accordance with some embodiments.

FIG. 7 is a schematic cross-sectional view of a laterally diffused metal oxide semiconductor (LDMOS) in accordance with some embodiments.

FIG. 8 is a flow chart of a method of forming a semiconductor device in accordance with various embodiments.

 DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

Terms used herein are only used to describe the specific embodiments, which are not used to limit the claims appended herewith. For example, unless limited otherwise, the term “a”, “an” or “the” of the single form may also represent the plural form.

The terms such as “first” and “second” are used for describing various elements, though such terms are only used for distinguishing one element from another element. Therefore, the first element may also be referred to as the second element without departing from the spirit of the claimed subject matter, and the others are deduced by analogy.

Embodiments of the present disclosure are directed to providing a semiconductor structure with a deep trench isolation (DTI). In such semiconductor structure, the DTI is formed below a shallow trench isolation (STI) and is substantially located between two adjacent well regions with different conductive types. Because of the DTI, the path of the leakage current flowing through the well regions is lengthened, such that the leakage current is reduced. Further, tilting variation of the ion implantation process due to cone angle effect can be neglected. The semiconductor structure of the present disclosure may be useful for such as memory integrated circuits, CMOS image sensors, temperature sensors, and/or the like. For example, the semiconductor structure of the present disclosure used in memory integrated circuits may help reduce power consumption or even improve reading/writing performance because read/write error due to excessive leakage current is reduced.

Referring to FIG. 1A to FIG. 1F, FIG. 1A to FIG. 1F illustrate schematic cross-sectional views of intermediate stages showing a method of forming a semiconductor device 100 in accordance with some embodiments of the present disclosure. In FIG. 1A, a semiconductor substrate 102 is provided. In some embodiments, the semiconductor substrate 102 includes such as silicon, bulk silicon, germanium or diamond. In another embodiments, the semiconductor substrate 102 may include a compound semiconductor such as silicon carbide, silicon germanium, gallium arsenide, gallium carbide, gallium phosphide, indium arsenide and indium phosphide, or an alloy semiconductor, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide and gallium indium phosphide. In addition, the semiconductor substrate 102 may be a bulk substrate or a silicon-on-insulator (SOI) substrate.

In FIG. 1B, a pad layer 104 is formed on the semiconductor substrate 102, and a barrier layer 106 is formed on the pad layer 104. The pad layer 104 includes such as silicon oxide, and the barrier layer 106 includes such as silicon nitride. In some embodiments, the pad layer 104 is formed by a process such chemical vapor deposition (CVD) process, thermal oxidation process, or another suitable process, and the barrier layer 106 is formed by a deposition process such as CVD process, low pressure CVD (LPCVD) process, plasma enhanced CVD (PECVD) process, or another suitable process.

In FIG. 1C, an etching process is performed to etch the barrier layer 106, the pad layer 104 and the semiconductor substrate 102. In the etching process, a patterned photoresist layer (not shown) is used as a mask, so as to form a shallow trench 108 through the pad layer 104, the barrier layer 106 and a portion of the semiconductor substrate 102. In some embodiments, the etching process for forming the shallow trench 108 includes such as an anisotropic etching process, an isotropic etching process, or another suitable etching process. After the etching process, the patterned photoresist layer (not shown) is stripped.

In FIG. 1D, a protective layer 110 is formed on the semiconductor substrate 102, the pad layer 104 and the barrier layer 106 for covering the shallow trench 108. The protective layer 110 may include a material such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, combinations thereof, and/or the like. The protective layer 110 may be a hard mask layer, and may be a single-layer or multi-layer structure. In some embodiments, the protective layer 110 is a two-layer structure, which includes an oxide layer and a nitride layer on the oxide layer. The protective layer 110 is formed by using one or more deposition processes, such as CVD process, PECVD process, high density plasma (HDPCVD) process, physical vapor deposition (PVD) process, atomic layer deposition (ALD) process, thermal oxidation process, combinations thereof, and/or the like.

In FIG. 1E, a first etching process is performed to the protective layer 110. The first etching process is performed until at least a portion of a bottom surface of the shallow trench 108 is exposed by the protective layer 110. The first etching process is performed until at least a portion of a bottom surface of the shallow trench 108 is exposed by the protective layer 110. The first etching process may include such as a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching (RIE) process, or another suitable etching process. As shown in FIG. 1E, the periphery area of the bottom surface of the shallow trench 108 is exposed. In various embodiments, the exposed area may be at center position of the bottom surface of the shallow trench 108, or another position, in accordance with various requirements. After the first etching process, a second etching process is then performed on the portion of the bottom surface of the shallow trench 108. The remained protective layer 110 acts as a photoresist for protecting the other portion of the shallow trench 108 from being etched. The second etching process may include such as a dry etching process, a wet etching process, a RIE process, or another suitable process. After the second etching process, a deep trench 112 is formed below the bottom surface of the shallow trench 108. The shape, width and location of the deep trench 112 may be determined by the pattern of the protective layer 110, and the thickness of the deep trench 112 may be determined by the time duration of the second etching process. In some embodiments, the deep trench 112 is formed having the thickness of at least 1000 angstroms.

In FIG. 1F, after the deep trench 112 is formed, the remaining protective layer 110 is removed. Next, as shown in FIG. 1G, the barrier layer 106 and the pad layer 104 are removed. The removing process applied to the protective layer 110, the barrier layer 106 and the pad layer 104 may include one or more etching processes, such as wet etching process, dry etching process, combinations thereof, or another suitable process.

As shown in FIG. 1H in conjunction with FIG. 1G, the shallow trench 108 and the deep trench 112 are filled with an isolation oxide, so as to form a STI 114 and a DTI 116 respectively. In some embodiments, the isolation oxide includes a material such as silicon oxide, silicon dioxide, carbon doped silicon dioxide, nitrogen doped silicon dioxide, germanium doped silicon dioxide, phosphorus doped silicon dioxide, combinations thereof, or the like. In some embodiments, the isolation oxide is deposited by such as a HDP CVD process, a HARP, a CVD process, a SACVD process, or another suitable process. In some embodiments, a chemical mechanical polishing (CMP) process may be performed to planarize the upper surface of the STI 114.

In some embodiments, the deep trench of the semiconductor device 100 may be formed by performing a dry etching process first and a wet etching process after the dry etching process. Referring to FIG. 2A through FIG. 2B, FIG. 2A through FIG. 2B are schematic cross-sectional views of intermediate stages illustrating a method of forming a deep trench of a semiconductor device in accordance with another embodiments. In FIG. 2A, a dry etching process is performed to the protective layer 110. The dry etching process is performed until at least a portion of a bottom surface of the shallow trench 108 is exposed by the protective layer 110. The dry etching process may include a plasma etching process, a sputter etching process, a RIE process, or other suitable process. The dry etching process is performed until at least a portion of a bottom surface of the shallow trench 108 is exposed by the protective layer 100. As shown in FIG. 2A, the periphery area of the bottom surface of the shallow trench 108 is exposed. In various embodiments, the exposed area may be at center position of the bottom surface of the shallow trench 108, or another position, in accordance with various requirements. After the dry etching process, a deep trench 112′ is formed below the bottom surface of the shallow trench 108. However, the dry etching process may cause damage to the semiconductor substrate 102. For example, the plasma etching process may cause crystal defects or dislocations of the semiconductor substrate 102 the bottom face and the side face of the deep trench 112′.

Next, as shown in FIG. 2B, a wet etching process is performed to deeper the deep trench 112′. The wet etching process may be isotropic or anisotropic. The enchant used for the etching process may be selected in accordance with the material of the semiconductor substrate 102. After the wet etching process, the bottom face and the side face of the deep trench 112′ with defects (crystal defects and/or dislocations) are removed from the semiconductor substrate 102, thereby improving yield rate of the semiconductor device 100.

Note that, the deep trench 112′ shown in FIG. 2B is for illustrative purposes only and is not meant to limit the scope of the present disclosure. The shape, width and location of the deep trench 112′ may be determined by the pattern of the protective layer 110, and the thickness of the deep trench 112′ may be determined by the time duration of the wet etching process. In some embodiments, the deep trench 112′ is formed having the thickness of at least 1000 angstroms. In some embodiments, a thickness ratio of the STI 114 to the deep trench 112′ is about 0.5 to about 10.

Referring to FIG. 3 in conjunction with FIG. 1A to FIG. 1H, FIG. 3 is a flow chart of a method 200 for fabricating a semiconductor device 100 in accordance with some embodiments. The method 200 begins at operation 202, where a semiconductor substrate 102 is provided. In some embodiments, the semiconductor substrate 102 includes such as silicon, bulk silicon, germanium or diamond. In another embodiments, the semiconductor substrate 102 may include a compound semiconductor such as silicon carbide, silicon germanium, gallium arsenide, gallium carbide, gallium phosphide, indium arsenide and indium phosphide, or an alloy semiconductor, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide and gallium indium phosphide. In addition, the semiconductor substrate 102 may be a bulk substrate or a SOI substrate. Further, a pad layer 104 is formed on the semiconductor substrate 102, and a barrier layer 106 is formed on the pad layer 104. In some embodiments, the pad layer 104 includes such silicon oxide, and is formed by such as a CVD process, a thermal oxidation process, or another suitable process. The barrier layer 106 includes such as silicon nitride, and is formed by such as a CVD process, a LPCVD process, a PECVD process, or another suitable process.

At operation 204, an etching process is performed to etch the barrier layer 106, the pad layer 104 and the semiconductor substrate 102 by using a patterned photoresist layer (not shown) as a mask, so as to form a shallow trench 108 through the pad layer 104, the barrier layer 106 and a portion of the semiconductor substrate 102. In some embodiments, the etching process for forming the shallow trench 108 includes such as an anisotropic etching process, an isotropic etching process, or another suitable etching process. After the etching process, the patterned photoresist layer (not shown) is stripped.

At operation 206, a protective layer 110 is formed on the semiconductor substrate 102, the pad layer 104 and the barrier layer 106 for covering the shallow trench 108. The protective layer 110 may include a material such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, combinations thereof, and/or the like. The protective layer 110 may be a hard mask layer, and may be a single-layer or multi-layer structure. In some embodiments, the protective layer 110 is a two-layer structure, which includes an oxide layer and a nitride layer on the oxide layer. The protective layer 110 is formed by using one or more deposition processes, such as CVD process, PECVD process, HDPCVD process, PVD process, ALD process, thermal oxidation process, combinations thereof, and/or the like.

At operation 208, a first etching process is performed to the protective layer 110. The first etching process is performed until at least a portion of a bottom surface of the shallow trench 108 is exposed by the protective layer 110. The first etching process is performed until at least a portion of a bottom surface of the shallow trench 108 is exposed by the protective layer 100. The first etching process may include such as a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, or another suitable etching process.

At operation 210, a second etching process is then performed on the portion of the bottom surface of the shallow trench 108. The protective layer 110 remained after the first etching process is used for protecting the other portion of the shallow trench 108 from being etched during the second etching process. The second etching process may include such as a dry etching process, a wet etching process, a RIE process, or another suitable process. After the second etching process, a deep trench 112 is formed below the bottom surface of the shallow trench 108. The shape, width and location of the deep trench 112 may be determined by the pattern of the protective layer 110, and the thickness of the deep trench 112 may be determined by the time duration of the second etching process. In some embodiments, the deep trench 112 is formed having the thickness of at least 1000 angstroms.

At operation 212, after the deep trench 112 is formed, the remaining protective layer 110, the barrier layer 106 and the pad layer 104 are removed. The applied removing process may include one or more etching processes, such as wet etching process, dry etching process, combinations thereof, or another suitable process.

At operation 214, the shallow trench 108 and the deep trench 112 are filled with an isolation oxide, so as to form a STI 114 and a DTI 116 respectively. In some embodiments, the isolation oxide includes a material such as silicon oxide, silicon dioxide, carbon doped silicon dioxide, nitrogen doped silicon dioxide, germanium doped silicon dioxide, phosphorus doped silicon dioxide, combinations thereof, or the like. In some embodiments, a deposition process, such as HDP CVD process, HARP, CVD process, SACVD process, or another suitable process, is perform to fill the isolation oxide into the shallow trench 108 and the deep trench 112. In some embodiments, a CMP process may be performed to planarize the upper surface of the STI 114.

Referring to FIG. 4A to FIG. 4C, FIG. 4A to FIG. 4C illustrate schematic cross-sectional views of intermediate stages showing a method of forming a semiconductor device 300 in accordance with some embodiments of the present disclosure. In FIG. 4A, a semiconductor substrate 302, a STI 304 and a DTI 306 are provided, and a well region 308 is formed on the semiconductor substrate 302. The semiconductor substrate 302, the STI 304 and the DTI 306 may be the semiconductor substrate 102, the STI 114 and the DTI 116 shown in FIG. 1, respectively. The semiconductor substrate 302 may be a P-type or N-type semiconductor substrate. The conductive type of the well region 308 may be P-type or N-type. For example, the dopant for implanting into the well region 308 may include boron for P-type well region, or phosphorous and/or arsenic for an N-type well region. The well region 308 may be a high voltage well with dopant concentration of between 1013 atoms/cm2 and 1016 atoms/cm2, for example. The well region 308 may be formed by a process such as ion implantation process, diffusion process, or the like. As shown in FIG. 4A, the DTI 306 is located in the well region 308 after the well region 308 is formed.

In FIG. 4B, an active region 310 is formed on the well region 308. The active region 310 may be formed by a process such as ion implantation process, diffusion process, or another suitable process. The conductive type of the active region 310 is different from that of the well region 308. For example, the active region 310 is P-type while the well region 308 is N-type.

In FIG. 4C, a photoresist 312 is formed on the active region 310, and an ion implantation process is performed through the STI 304 to form a well region 314 on the semiconductor substrate 302 and laterally adjacent to the well region 308. The photoresist 312 may be a positive photoresist or a negative photoresist, which is used for protecting the active region 310 from being damaged by the subsequent ion implantation processes. The conductive type of the well region 314 is the same as the active region 310, and is different from that of the well region 308. For example, the well region 314 and the active region 310 are P-type, and the well region 308 is N-type. In some alternative embodiments, the well region 314 and the active region 310 are N-type, and the well region 308 is P-type. As shown in FIG. 4C, after the well region 314 is formed, the DTI 306 is located in the well region 308 and near to the boundary between the well regions 308 and 314. In other words, the DTI 306 is located between the well region 314 and a majority of the well region 308. As can be seen from FIG. 4C, because the leakage current ILEAK can not pass through the DTI 306, the path of the leakage current ILEAK from the well region 314 toward the active region 310 is lengthened, such that the leakage current ILEAK can be reduced.

FIG. 4C illustrates the ion implantation process is performed with a tilting angle of zero. However, the tilting angle of the ion implantation process may be up to 7 degrees for fabricating semiconductor substrate 300 at the periphery area of the wafer. FIG. 5 illustrates formation of the well region 314 using the ion implantation process with non-zero tilting angle in accordance with some embodiments. As shown in FIG. 5, after the ion implantation process, the well region 314 is formed, such that the DTI 306 is located at the boundary between the well regions 308 and 314. As can be seen from FIG. 5, the path of the leakage current ILEAK from the well region 314 toward the active region 310 is lengthened because of the DTI 306 and, therefore, the leakage current ILEAK can be reduced in a similar manner as described above with reference to FIG. 4C.

Alternatively, the DTI 306 may be located in the well region 314 and near to the boundary between the well regions 308 and 314. Such structure also helps lengthen the path of the leakage current ILEAK from the well region 314 toward the active region 310, thus reducing the leakage current ILEAK.

FIG. 6 illustrates formation of a well region using an ion implantation process in accordance with some embodiments. The DTI 306′ shown in FIG. 6 is formed corresponding to the deep trench 112′ shown in FIG. 2B. As shown in FIG. 6, after the ion implantation process, the well region 314 is formed, such that the DTI 306′ is located at the boundary between the well regions 308 and 314. As can be seen from FIG. 6, the path of the leakage current ILEAK from the well region 314 toward the active region 310 is lengthened because of the DTI 306′ and, therefore, the leakage current ILEAK can be reduced.

The semiconductor structure of the present disclosure can reduce leakage current through well regions. For example, memory integrated circuits (e.g., flash memory chips) with such semiconductor structure can reduce power consumption or even reduce read/write error. As such, defects of the memory integrated circuits can be reduced. It should be noted that, the semiconductor structure of the present disclosure may be applied to other types of integrated circuits as well, such as CMOS image sensors, temperature sensors, and/or the like.

Referring to FIG. 7, FIG. 7 is a schematic cross-sectional view of a semiconductor structure 400 in accordance with some embodiments. The semiconductor structure 400 may a laterally diffused metal oxide semiconductor (LDMOS), a vertical diffused metal oxide semiconductor (VDMOS), or the like. In a case that the semiconductor structure 400 is a N-type LDMOS, a P-type implant region 412 is formed on a P-type semiconductor substrate 410, and a N-type well region 414 is formed on the semiconductor substrate 410 and adjacent to the P-type implant region 412. A N-type implant region 416 is formed in the N-type well region 414. A gate dielectric 418 and a gate electrode 420 are sequentially formed on the substrate 410, the P-type implant region 412 and the N-type well region 414. The gate electrode 420 may be a conductive gate structure, such as polysilicon gate structure, metal gate structure or other suitable gate electrode. A gate spacer 422 is formed on sidewalls of the gate dielectric 418 and the gate electrode 420. A STI 424A is formed on the P-type implant region 412, STIs 426A and 428A are formed on the N-type well region 414 and the N-type implant region 416, and DTIs 424B, 426B and 428B are formed below the STIs 424A, 426A and 428A, respectively. The STIs 424A, 426A and 428A and the DTIs 424B, 426B and 428B may be similar to the STI 114 and the DTI 116 in FIG. 1H respectively. The lightly doped drain (LDD) region 430 is formed in the P-type implant region 412 and below the gate spacer 422. The source/drain electrode 432 is formed between the STI 424A and the LDD region 430, and the source/drain electrode 434 is formed between the STIs 426A and 428A.

Whereas, in a case that the semiconductor structure 400 is a P-type LDMOS, a N-type implant region 412 is formed on a N-type semiconductor substrate 410, and a P-type well region 414 is formed on the substrate and adjacent to the N-type implant region 412. A P-type implant region 416 is formed in the P-type well region 414. A gate dielectric 418 and a gate electrode 420 are sequentially formed on the N-type semiconductor substrate 410, the N-type implant region 412 and the P-type well region 414. A gate spacer 422 is formed on sidewalls of the gate dielectric 418 and the gate electrode 420. A STI 424A is formed on the N-type implant region 412, STIs 426A and 428A are formed on the P-type well region 414 and the P-type implant region 416, and DTIs 424B, 426B and 428B are formed below the STIs 424A, 426A and 428A, respectively. The lightly doped drain (LDD) region 430 is formed in the N-type implant region 412 and below the gate spacer 422. The source/drain electrode 432 is formed between the STI 424A and the LDD region 430, and the source/drain electrode 434 is formed between the STIs 426A and 428A.

TABLE 1 Drain-Source STI On-State Power Width Breakdown Resistance Consumption Model (μm) Voltage (V) (mΩ × mm2) (Fixed Current) LDMOS with 1.5 55.8 24.8 24.8 DTI 1.8 58 29.3 29.3 2 59.3 32.2 32.2 2.3 59.5 36.6 36.6 LDMOS without 2.3 54.8 28.5 28.5 DTI

TABLE 1 lists experiential results of LDMOS structures with and without DTI. The LDMOS structure with DTI is the semiconductor structure 400 in the FIG. 7. The structure without DTI is similar to the semiconductor structure 400 except that no DTIs are included. As listed in TABLE 1, for the same STI width (the width L of the STI 426A in FIG. 7) of 2.3 μm, the breakdown voltage of the LDMOS with DTI is greater than that of the LDMOS without DTI, and the drain-source on-state resistance (Rdson) of the LDMOS with DTI is greater than that of the LDMOS without DTI. Because of the DTIs 426B, the current path from the source/drain electrode 434 to the source/drain electrode 432 is lengthened, such that the drain-source on-state resistance increases accordingly. If the width of the LDMOS with DTI is narrowed from 2.3 μm to 1.5 μm, the breakdown voltage decreases from 59.5 V to 55.8 V, which is still greater than that of the LDMOS without DTI, and the power consumption of the LDMOS with DTI decreases from 28.5 to 24.8, which becomes lower than that of the LDMOS without DTI. As can been from the above, the DTI helps increase the breakdown voltage the LDMOS and narrow the STI width of the LDMOS, thereby saving the size of the LDMOS.

Referring to FIG. 8 in conjunction with FIG. 4A to FIG. 4C, FIG. 8 is a flow chart of a method 500 for fabricating a semiconductor device in accordance with some embodiments. The method 500 begins at operation 502, where a semiconductor substrate 302, a STI 304 and a DTI 306 are provided, and a well region 308 is formed on the semiconductor substrate 302. The semiconductor substrate 302 may be a P-type or N-type semiconductor substrate. The well region 308 has a first conductive type, which may be P-type or N-type, for example. The well region 308 may be formed by a process such as ion implantation process, diffusion process, or the like. After the well region 308 is formed, the DTI 306 is located in the well region 308.

At operation 504, an active region 310 is formed on the well region 308. The active region 310 may be formed by a process such as ion implantation process, diffusion process, or another suitable process. The active region 310 has a conductive type is different from the first conductive type of the well region 308. For example, the conductive type of the active region 310 is P-type if the first conductive type is N-type.

At operation 506, a well region 314 of a second conductive type is formed on the semiconductor substrate 302 and laterally adjacent to the well region 308. In detail, a photoresist 312 may be formed on the active region 310 for protecting the active region 310 from being damaged by the subsequent processes. Next, an ion implantation process is performed to form the well region 314. The second conductive type of the well region 314 is the same as the conductive type of the active region 310, and is different from the first conductive type of the well region 308. For example, the second conductive type of the well region 314 and the conductive type of the active region 310 are P-type, and the first conductive type of the well region 308 is N-type. As shown in FIG. 4C, after the well region 314 is formed by the ion implantation process with a tilting angle of zero, the DTI 306 is located in the well region 308 and near to the boundary between the well regions 308 and 314. In other words, the DTI 306 is located between the well region 314 and a majority of the well region 308.

In a case that the well region 314 is formed by the ion implantation process with non-zero tilting angle, as shown in FIG. 5, after the well region 314 is formed, the DTI 306 is located at the boundary between the well regions 308 and 314. Alternatively, the DTI 306 may be located in the well region 314 and near to the boundary between the well regions 308 and 314.

In accordance with some embodiments, the present disclosure discloses another method of forming a semiconductor structure. In this method, a semiconductor substrate is provided. A shallow trench is formed by etching the semiconductor substrate. A protective layer is formed covering the shallow trench. A first etching process is performed to the protective layer until at least a portion of a bottom surface of the shallow trench is exposed by the protective layer. A second etching process is performed on the portion of the bottom surface of the shallow trench, thereby forming at least one deep trench below the bottom surface of the shallow trench. The protective layer remained on the semiconductor substrate and in the shallow trench is removed. An isolation oxide is filled into the deep trench and the shallow trench to form at least one DTI and a STI respectively. A first well region of a first conductive type is formed on the semiconductor substrate. An active region is formed on the first well region. A second well region of a second conductive type is formed on the semiconductor substrate and adjacent to the first well region. The second conductive type is different from the first conductive type, and second conductive type is the same a conductive type of the active region. The first well region and the second well region are formed such that the DTI is disposed between at least a portion of the first well region and at least a portion of the second well region.

In accordance with some embodiments, the present disclosure discloses a semiconductor structure. The semiconductor structure includes a semiconductor substrate, a first well region of a first conductive type on the semiconductor substrate, a second well region of a second conductive type on the semiconductor substrate, an active region on the second well region, a STI between the first well region and the second well region, and at least one DTI below the STI in the semiconductor substrate. The second well region is adjacent to the first well region. The second conductive type is different from the first conductive type. A conductive type of the active region is the same as the second conductive type of the second well region. The DTI is disposed between at least a portion of the first well region and at least a portion of the second well region.

In accordance with some embodiments, the present disclosure discloses a semiconductor structure. The semiconductor structure includes a semiconductor substrate, a first implant region of a first conductive type on the semiconductor substrate, a second implant region of a second conductive type on the semiconductor substrate, a first source/drain electrode in the first implant region, a second source/drain electrode in the second implant region, a gate electrode on the semiconductor substrate and between the first source/drain electrode and the second source/drain electrode, a STI between the first source/drain electrode and the second source/drain electrode, and at least one DTI below the STI in the semiconductor substrate. The second conductive type is different from the first conductive type. The DTI is disposed between at least a portion of the first implant region and at least a portion of the second implant region.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method of forming a semiconductor structure, comprising:

providing a semiconductor substrate;
forming a shallow trench by etching the semiconductor substrate;
forming a protective layer covering the shallow trench;
performing a first etching process to the protective layer until at least a portion of a bottom surface of the shallow trench is exposed by the protective layer;
performing a second etching process on the portion of the bottom surface of the shallow trench, thereby forming at least one deep trench below the bottom surface of the shallow trench;
removing the protective layer remained on the semiconductor substrate and in the shallow trench;
filling an isolation oxide into the deep trench and the shallow trench to form at least one deep trench isolation (DTI) and a shallow trench isolation (STI) respectively;
forming a first well region of a first conductive type on the semiconductor substrate;
forming an active region on the first well region; and
forming a second well region of a second conductive type on the semiconductor substrate and adjacent to the first well region, wherein the second conductive type is different from the first conductive type, and second conductive type is the same a conductive type of the active region;
wherein the first well region and the second well region are formed such that the DTI is disposed between at least a portion of the first well region and at least a portion of the second well region.

2. The method of claim 1, wherein the deep trench is formed being located at a corner region of the bottom surface of the shallow trench.

3. The method of claim 1, wherein the first well region is formed such that the DTI has at least a portion located in the first well region.

4. The method of claim 1, wherein the first well region and the second well region are formed such that the DTI has at least a portion located at a boundary between the first well region and the second well region.

5. The method of claim 1, wherein the deep trench is formed having a depth substantially greater than about 1000 angstroms.

6. The method of claim 1, wherein the first etching process comprises a dry etching process, and the second etching process comprises a wet etching process.

7. The method of claim 1, wherein the first well region is formed being a N-type well region, and the second well region is formed being a P-type well region.

8. The method of claim 1, wherein the first well region is formed as a P-type well region, and the second well region is formed as a N-type well region.

9. The method of claim 1, wherein the semiconductor substrate is a P-type semiconductor substrate.

10. A semiconductor structure, comprising:

a semiconductor substrate;
a first well region of a first conductive type on the semiconductor substrate;
a second well region of a second conductive type on the semiconductor substrate and adjacent to the first well region, the second conductive type being different from the first conductive type;
an active region on the first well region, wherein a conductive type of the active region is the same as the second conductive type of the second well region;
a shallow trench isolation (STI) between the first well region and the second well region; and
at least one deep trench isolation (DTI) below the STI in the semiconductor substrate, wherein the DTI is disposed between at least a portion of the first well region and at least a portion of the second well region.

11. The semiconductor structure of claim 10, wherein the DTI is located at a corner region of a bottom surface of the STI.

12. The semiconductor structure of claim 10, wherein at least a portion of the DTI is located in the first well region.

13. The semiconductor structure of claim 10, wherein at least a portion of the DTI is located at a boundary between the first well region and the second well region.

14. The semiconductor structure of claim 10, wherein a depth of the DTI is substantially greater than about 1000 angstroms.

15. The semiconductor structure of claim 10, wherein the first well region is a N-type well region, and the second well region is a P-type well region.

16. The semiconductor structure of claim 10, wherein the first well region is a P-type well region, and the second well region is a N-type well region.

17. The semiconductor structure of claim 10, wherein the semiconductor substrate is a P-type semiconductor substrate.

18. A semiconductor structure, comprising:

a semiconductor substrate;
a first implant region of a first conductive type on the semiconductor substrate;
a second implant region of a second conductive type on the semiconductor substrate, the second conductive type being different from the first conductive type;
a first source/drain electrode in the first implant region;
a second source/drain electrode in the second implant region;
a gate electrode on the semiconductor substrate and between the first source/drain electrode and the second source/drain electrode;
a shallow trench isolation (STI) between the first source/drain electrode and the second source/drain electrode; and
at least one deep trench isolation (DTI) below the STI in the semiconductor substrate, wherein the DTI is disposed between at least a portion of the first implant region and at least a portion of the second implant region.

19. The semiconductor structure of claim 18, wherein the DTI is located at a corner region of a bottom surface of the STI.

20. The semiconductor structure of claim 18, wherein a depth of the DTI is substantially greater than about 1000 angstroms.

Patent History
Publication number: 20160372360
Type: Application
Filed: Jun 17, 2015
Publication Date: Dec 22, 2016
Inventors: Chun-Chieh FANG (Zhongpu Township), Chien-Chang HUANG (Tainan), Chi-Yuan WEN (Tainan City), Jian WU (Shanghai), Ming-Chi WU (Kaohsiung City), Jung-Yu CHENG (Tainan City), Shih-Shiung CHEN (Tainan City), Wei-Tung HUANG (Tainan City), Yu-Lung YEH (Kaohsiung City)
Application Number: 14/742,550
Classifications
International Classification: H01L 21/762 (20060101); H01L 29/06 (20060101); H01L 21/306 (20060101); H01L 29/78 (20060101); H01L 29/66 (20060101); H01L 21/3065 (20060101); H01L 29/10 (20060101);