SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a semiconductor substrate, a conductive pad on the semiconductor substrate, and a conductor over the conductive pad. The semiconductor device further has a polymeric material disposed over the semiconductor substrate and surrounding the conductor. The semiconductor device also includes an electric conductive layer between the conductor and the polymeric material. In the semiconductor device, an adhesion strength between the electric conductive layer and the polymeric material is greater than an adhesion strength between the polymeric material and the conductor.
The disclosure relates to a semiconductor device and a method of manufacturing a semiconductor device.
BACKGROUNDElectronic equipments involving semiconductor devices are indispensable from our daily life. With the advancement of electronic technology, electronic equipments become more complicated and involve greater amount of integrated circuitry for executing the desired multi-functionality. Thus, manufacturing of the electronic equipments includes more and more steps of assembly and processing as well as materials for producing the semiconductor devices in the electronic equipments. Therefore, there is a continuous demand on simplifying the steps of production, increasing production efficiency and lowering associated manufacturing cost on each electronic equipment.
During the operations of manufacturing the semiconductor devices, the semiconductor devices are assembled with numbers of integrated components including various materials with difference in thermal properties. As such, the integrated components are in undesired configurations. The undesired configurations would lead to yield loss of the semiconductor devices, poor bondability between the components, development of cracks, delamination of the components or etc. Furthermore, the components of the semiconductor devices include various metallic materials which are in limited quantity and thus in a high cost. The undesired configurations of the components and the yield loss of the semiconductor devices would further exacerbate materials wastage and thus the manufacturing cost would increase.
As more different components with different materials are involved and a complexity of the manufacturing operations of the semiconductor device is increased, there are more challenges to modify a structure of the semiconductor device and improve the manufacturing operations. As such, there is a continuous need to improve the method for manufacturing the semiconductor and solve the above deficiencies.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
The semiconductor substrate 102 includes a surface 102b and a conductive pad 102a is disposed on the surface 102b. In some embodiments, the conductive pad 102a is electrically connected with a circuitry external to the semiconductor substrate 102, so that a circuitry internal to the semiconductor substrate 102 electrically connects with the circuitry external to the semiconductor substrate 102 through the conductive pad 102a. In some embodiments, the conductive pad 102a is configured for electrically coupling with a conductive bump through a conductive trace attached on the conductive pad 102a, so that the circuitry internal to the semiconductor substrate 102 connects with the circuitry external to the semiconductor substrate 102 from the conductive pad 102a to the conductive bump through the conductive trace. In some embodiments, the conductive pad 102a includes gold, silver, copper, nickel, tungsten, aluminum, palladium and/or alloys thereof.
In some embodiments, a passivation 103 is disposed on the surface 102b of the semiconductor substrate 102 and over the conductive pad 102a. In some embodiments, the passivation 103 surrounds the conductive pad 102a. In some embodiments, the passivation 103 partially covers a top surface 102c of the conductive pad 102a. The passivation 103 is configured for providing an electrical insulation and a moisture protection for the semiconductor substrate 102, so that the semiconductor substrate 102 is isolated from ambient environment. In some embodiments, the passivation 103 is formed with dielectric materials such as spin-on glass (SOG), silicon oxide, silicon oxynitride, silicon nitride or the like. In some embodiments, the passivation 103 is formed with a vapor deposition or a spin coating process.
In some embodiments, the passivation 103 includes an opening 103a above the conductive pad 102a for exposing a portion of the top surface 102c of the conductive pad 102a and thus for electrically connecting the conductive pad 102a with the circuitry external to the semiconductor substrate 102 through the conductive trace.
In some embodiments, several conductors 104 are disposed over the top surface 102c of the conductive pad 102a as in
In some embodiments, the conductor 104 is in a cylindrical shape with various cross-sectional shapes such as circular shape, quadrilateral shape or polygonal shape. In addition, a wide variety of materials is selected for the conductor 104 such as metal or metal alloy. In some embodiments, the conductor 104 includes copper (Cu), gold (Au), platinum (Pt), titanium (Ti), nickel (Ni), aluminum (Al), etc.
In some embodiments, a polymeric material 105 is disposed over the passivation 103 and surrounding the conductor 104. The polymeric material 105 is a dielectric filling inserted around the conductor 104 in order to isolate adjacent conductors or avoid moisture attack. In some embodiments, the polymeric material 105 includes a material such as epoxy, polyimide, polybenzoxazole (PBO), solder resist (SR), ABF film, and the like. In some embodiments, the conductor 104 and polymeric material 105 are substantially coplanar.
In some embodiments, an electric conductive layer 106 is disposed between the conductor 104 and the polymeric material 105. The electric conductive layer 106 is a layer may be substantially thinner than the conductor 104 and is extended along a longitudinal sidewall of the conductor 104. In
In some embodiment, the electric conductive layer 106 includes an element having a different standard electrode potential than the conductor 104. In some embodiments, the electric conductive layer 106 includes an element tending to grab the oxygen atoms from the polymeric material 105 more aggressively than the conductor 104. An oxide compound of the element may form between the electric conductive layer 106 and the polymeric material 105. The oxide compound provides a glue to further bond the conductor 104 and the polymeric material 105 in a more secured way. The electric conductive layer 106 also includes an element which may forms a coherent layer between the electric conductive layer 106 and the conductor 104. In order to possess two different characteristics, the electric conductive layer 106 may be a composite structure including several conductive layers.
As in
In some embodiment, the standard electrode potential ratio between layer 106a and conductor 104 is between about 2.1 and about 7.5. In some embodiment, the standard electrode potential ratio between layer 106a and conductor 104 is between about 4.0 and about 5.0. In some embodiment, the standard electrode potential ratio between layer 106a and conductor 104 is between about 4.3 and about 4.7. The layer 106a may include element such as, Ti, Cr, Al, doped-Si, Zr, Th, Ni, etc.
In some embodiment, the standard electrode potential ratio between layer 106b and conductor 104 is between about 0.85 and about 1.35. In some embodiment, the standard electrode potential ratio between layer 106b and conductor 104 is between about 0.91 and about 1.07. The layer 106b may include element such as, Pt, Au, Ag, Cu, etc.
In some embodiments, the electric conductive layer 106b includes an element having a an adhesion strength between the electric conductive layer 106 and the polymeric material 105 greater than an adhesion strength between the polymeric material 105 and the conductor 104. In some embodiments, the adhesion strength may be referred to as a quantitative interfacial energy. The quantitative interfacial energy defines as the quantitative energy value of two specific substances. The magnitude of the value represents the adhesion strength between the two specific substances. Higher quantitative interfacial energy indicates that a greater adhesion strength between the two specific substances.
In the present disclosure, the conductive layer 106 acts as a reinforce structure between conductor 104 and polymeric material 105. The conductive layer 106 possesses a quantitative interfacial energy higher than the quantitative interfacial energy between the polymeric material 105 and the conductor 104. The inserted conductive layer 106 separates the conductor 104 from directly contacting the polymeric material 105; therefore a delamination between the conductor 104 and polymeric material 105 is prevented. In some embodiments, the adhesion strength between layer 106a and polymeric material 105 may be greater than the adhesion strength between layer 106b and polymeric material 105.
In some embodiments, a ratio of atomic weight between layer 106a and layer 106b may be about 0.6 to about 1.3. In some embodiments, a ratio of atomic weight between layer 106a and layer 106b is about 0.65 to about 0.9. In some embodiments, a ratio of atomic weight between layer 106a and layer 106b is about 0.70 to about 0.85.
In some embodiments, a ratio of atomic weight between the layer 106b and the conductor 104 may be about 0.8 to about 1.2. In some embodiments, a ratio of atomic weight between the layer 106b and the conductor 104 may be about 0.9 to about 1.1. In some embodiments, a ratio of atomic weight between the layer 106b and the conductor 104 may be about 0.95 to about 1.05. In some embodiments, the layer 106b may be made with a same material as the conductor 104 but with different micro structure, such as crystal orientation, or grain size. In some embodiments, the grain size of the layer 106b may be greater than the grain size of the conductor 104. In some embodiments, thickness of the 106a is substantially greater than 50 nm, and thickness of layer 106b is substantially greater than 100 nm. In some embodiments, a ratio of the thickness between the layer 106a and the layer 106b may be about 1:1 to 1:3.
The electric conductive layer 106 may be further extended under the bottom surface of the conductor 104. In some embodiments, a portion of the electric conductive layer 106 is disposed between the conductive pad 102a and the conductor 104. In some embodiments, the electric conductive layer 106 is disposed between the passivation 103 and the conductor 104. In some embodiments, the electric conductive layer 106 is a continuous film surrounding the conductor 104. In some embodiments, the electric conductive layer 106 has a width of about 150 nm to about 250 nm. In some embodiments, a wide variety of materials is selected for the electric conductive layer 106 such as metal or metal alloy.
In some embodiments, a molding 107 is disposed to surround the semiconductor substrate 102. In some embodiments, the molding 107 is disposed adjacent to a sidewall 102d of the semiconductor substrate 102. In some embodiments, top surfaces of the conductor 104, polymeric material 105 and the molding 107 are substantially coplanar.
In some embodiments, the semiconductor device 100 includes a polymer 109 disposed over the molding 107, the conductor 104 and the polymeric material 105. A recessed portion 118 of the polymer 109 is formed above the top surface 104a of the conductor 104 as in
In operation 201, a semiconductor substrate 102 is provided as in
In operation 203, a passivation 103 is disposed over the semiconductor substrate 102, and some of the passivation 103 is removed to form an opening 103a as in
In operation 204, a polymeric material 105 is disposed over conductive pad 102a and the passivation 103, and the polymeric material 105 is patterned with an opening 105a above the conductive pad 102a as in
In operation 205, the conductive pad 102a, the passivation 103 and the polymeric material 105 are surrounded with an electric conductive layer 106 as in
In operation 206, a conductor 104 is disposed over and adjacent to the electric conductive layer 106 as in
In operation 207, the semiconductor substrate 102 is singulated into several individual dies 108 as in
In operation 208, the die 108 singulated from the semiconductor substrate 102 is placed on a carrier 116. A molding 107 is disposed on the carrier 116 to surround the die 108. A removal or planarization operation is introduced to remove a portion of the molding 107 in order to expose the top surface 104a of the conductor 104 and a top surface 105b of the polymeric material 105, such that there is no molding 107 remaining on the conductor 104 and the polymeric material.
In operation 209, a polymer 109 is disposed over molding 107, the conductor 104 and the polymeric material 105 as in
A recessed portion 118 is formed above the top surface 104a of the conductor 104 as in
A first redistribution layer (RDL) 112 is disposed as in
A polymer 110 is disposed as in
A via 117 is formed and a bond pad 114 is disposed as in
In some embodiments, the bond pad 114 is formed above the end portion 112b of the first RDL and the polymer 110. In some embodiments, the bond pad 114 fills the via 117 and extends from the top surface 110a of the polymer 110 to the end portion 112b of the first RDL, so that the bond pad 114 is electrically connected with the first RDL 112. In some embodiments, the bond pad 114 is an under bump metallurgy (UBM) pad which is a solderable surface for receiving a bump and electrically connecting the bond pad 114 with the circuitry external to the die 108.
In operation 210, a bump 115 is disposed on the bond pad 114 as in
In operation 211, the carrier 101 is removed from the semiconductor device 100 as in
The structure shown in
In some embodiments, the semiconductor device 100 is bonded with another package by a package bump to become a package on package (PoP). In some embodiments, the semiconductor device 100 is electrically connected with another package through the package bump. In some embodiments, several conductive members of the semiconductor device 100 are correspondingly bonded with several package pads of another package through several package bumps to become PoP.
In some embodiments, a semiconductor device includes a semiconductor substrate, a conductive pad on the semiconductor substrate, and a conductor over the conductive pad. The semiconductor device further has a polymeric material disposed over the semiconductor substrate and surrounding the conductor. The semiconductor device also includes an electric conductive layer between the conductor and the polymeric material. In the semiconductor device, an adhesion strength between the electric conductive layer and the polymeric material is greater than an adhesion strength between the polymeric material and the conductor.
In some embodiments, the electric conductive layer is configured as a seed layer for the conductor. In some embodiments, the spacing between the conductor and an adjacent conductor is less than about 10 um. In some embodiments, the electric conductive layer includes a first layer and a second layer, the first layer is adjacent to the polymeric material, and the second layer is adjacent to the conductor. In some embodiments, a ratio of atomic weight between the first layer and the second layer is about 0.6 to about 1.3. In some embodiments, a ratio of atomic weight between the second layer and the conductor is about 0.8 to about 1.2. In some embodiments, a thickness of the first layer is substantially greater than 50 nm, and a thickness of the second layer is substantially greater than 100 nm. In some embodiments, the second layer and the conductor is substantially made with a same material but with different grain size.
In some embodiments, a semiconductor device includes a semiconductor substrate, a conductive pad on the semiconductor substrate, and a conductor over the conductive pad. The semiconductor device further has a polymeric material disposed over the semiconductor substrate and surrounding the conductor. The semiconductor device also includes an electric conductive layer between the conductor and the polymeric material. In the semiconductor device, the electric conductive layer includes an element having a different standard electrode potential than the conductor.
In some embodiments, the element has a lower standard electrode potential than the conductor. In some embodiments, an oxide compound of the element is between the electric conductive layer and the polymeric material. In some embodiments, the electric conductive layer is a composite structure including several conductive layers. In some embodiments, the electric conductive layer includes a first layer and a second layer, the first layer is adjacent to the polymeric material, and the second layer is adjacent to the conductor. In some embodiments, the standard electrode potential ratio between the first layer and the conductor is between about 2.1 and about 7.5. In some embodiments, a thickness of the first layer is substantially greater than 50 nm, and a thickness of the second layer is substantially greater than 100 nm.
In some embodiments, a method of manufacturing a semiconductor device includes providing a semiconductor substrate, forming a conductive pad on the semiconductor substrate, and disposing a polymeric material over the semiconductor substrate. The method further includes patterning the polymeric material to provide an opening, forming an electric conductive layer to line in the opening, and disposing a conductor in the opening and adjacent to the electric conductive layer. The method also includes disposing a molding over the semiconductor substrate, and removing a portion of the molding to expose a top surface of the conductor.
In some embodiments, further comprising singulating the semiconductor substrate into a plurality of dies. In some embodiments, forming the electric conductive layer further comprises forming two distinguishable layers. In some embodiments, the polymeric material comprises a viscosity greater than about 1 Pa·s. In some embodiments, removing a portion of the molding includes grinding.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims
1. A semiconductor device, comprising:
- a semiconductor substrate;
- a conductive pad on the semiconductor substrate;
- a conductor over the conductive pad;
- a polymeric material over the semiconductor substrate and surrounding the conductor;
- an electric conductive layer between the conductor and the polymeric material, and
- an oxide compound of an element of the electric conductive layer,
- wherein the oxide compound is between the electric conductive layer and the polymeric material and the element tends to grab oxygen atoms from the polymeric material more aggressively than the conductor.
2. The semiconductor device of claim 1, wherein the electric conductive layer is configured as a seed layer for the conductor.
3. The semiconductor device of claim 1, wherein the spacing between the conductor and an adjacent conductor is less than about 10 um.
4. The semiconductor device of claim 1, wherein the electric conductive layer includes a first layer and a second layer, the first layer is adjacent to the polymeric material, and the second layer is adjacent to the conductor.
5. (canceled)
6. The semiconductor device of claim 4, wherein the second layer is made with the same material as the conductor but with a different micro structure.
7. The semiconductor device of claim 4, wherein a thickness of the first layer is substantially greater than 50 nm, and a thickness of the second layer is substantially greater than 100 nm.
8. The semiconductor device of claim 4, wherein the second layer and the conductor are substantially made with a same material but with different grain size.
9-20. (canceled)
21. The semiconductor device of claim 1, wherein the element has a different standard electrode potential than the conductor.
22. The semiconductor device of claim 4, wherein a standard electrode potential ratio between the first layer and the conductor is between about 2.1 and about 7.5.
23. The semiconductor device of claim 1, wherein the electric conductive layer has a width of about 150 nm to about 250 nm.
24. The semiconductor device of claim 4, wherein a ratio of atomic weight between the first layer and the second layer is from about 0.6 to about 1.3.
25. The semiconductor device of claim 4, wherein the first layer has a thickness substantially less than a thickness of the second layer.
26. The semiconductor device of claim 4, wherein a ratio of a thickness between the first layer and the second layer is about 1:1 to 1:3.
27. The semiconductor device of claim 1, wherein the polymeric material includes a recess for receiving the conductor.
28. The semiconductor device of claim 1, wherein the electric conductive layer is a composite structure including several conductive layers.
29. The semiconductor device of claim 1, wherein the electric conductive layer is surrounding the conductor.
30. The semiconductor device of claim 1, wherein the polymeric material comprises a viscosity greater than about 1 Pa·s.
31. A semiconductor device, comprising:
- a semiconductor substrate;
- a conductive pad on the semiconductor substrate;
- a conductor over the conductive pad;
- a polymeric material over the semiconductor substrate and surrounding the conductor; and
- an electric conductive layer surrounding the conductor;
- wherein a quantitative interfacial energy between the electric conductive layer and the polymeric material is greater than a quantitative interfacial energy between the polymeric material and the conductor,
- wherein the conductor, the polymeric material and the electric conductive layer are substantially coplanar.
32. The semiconductor device of claim 31, wherein the electric conductive layer forms a multi-layer structure.
33. The semiconductor device of claim 1, wherein an adhesion strength between the electric conductive layer and the polymeric material is greater than an adhesion strength between the polymeric material and the conductor.
Type: Application
Filed: Aug 18, 2015
Publication Date: Feb 23, 2017
Inventors: TIEN-CHUNG YANG (HSINCHU), LIN-CHIH HUANG (HSINCHU CITY), HSIEN-WEI CHEN (HSINCHU CITY), AN-JHIH SU (TAOYUAN COUNTY), LI-HSIEN HUANG (HSINCHU COUNTY)
Application Number: 14/828,946