Semiconductor Structure for Flash Memory Cells and Method of Making Same
An exemplary method includes forming a common source region in a substrate, and forming an isolation feature over the common source region. The common source region is disposed between the substrate and the isolation feature. The common source region and the isolation feature span a plurality of active regions of the substrate. A gate, such as an erase gate, may be formed after forming the common source region. In some implementations, the common source region is formed by etching the substrate to form a saw-tooth shaped recess region (or a U-shaped recess region) and performing an ion implantation process to form a doped region in a portion of the saw-tooth shaped recess region (or the U-shaped recess region), such that the common source region has a sawtooth profile (or a U-shaped profile).
This application is a divisional application of U.S. patent application Ser. No. 14/179,687, filed Feb. 13, 2014, now U.S. Pat. No. 9,679,979, the entire disclosure of which is incorporated herein by reference.
BACKGROUNDFlash memory is an increasingly popular type of non-volatile memory (NVM). NVM is a type of memory storage that can retain data even while it is not powered on.
A typical flash memory includes a memory array having a large number of memory cells arranged in blocks. Each of the memory cells includes a field effect transistor having a control gate and a floating gate. Pairs of field effect transistors share a common source region. Conventional techniques for forming a common source region involve formation of floating gate and control gate structures prior to etching to form a common source region between the structures. As device sizes decrease a width between field effect transistors and an aspect ratio relating a depth to the common source region to a width between field effect transistors makes it difficult to etch a region for the common source without damaging gate structures of the transistors.
The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Also, the components disclosed herein may be arranged, combined, or configured in ways different from the exemplary embodiments shown herein without departing from the scope of the present disclosure. It is understood that those skilled in the art will be able to devise various equivalents that, although not explicitly described herein, embody the principles of the present invention.
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The erase gate electrode may be designed to be coupled to the metal interconnects and may be disposed overlying the erase gate dielectric. The erase gate electrode includes polycrystalline silicon (or polysilicon). Alternatively, the erase gate electrode may include doped polysilicon, metal such as Al, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, other suitable conductive materials, or combinations thereof. The erase gate electrode may be formed by CVD, PVD, plating, and other proper processes. The erase gate electrode may have a multilayer structure and may be formed in a multiple step process. The erase gate electrode may have a layer of silicide, or any other material suitable to reduce resistance between the erase gate electrode and a contact, disposed thereon. The formation of the erase gate 240 may include various deposition and patterning that further includes lithography process and etch.
The floating gate 242 and the control gate 244 may include polysilicon, doped polysilicon, and combinations thereof. The floating gate 242 is deposited adjacent to the erase gate 240, and the control gate 244 is disposed above the floating gate 242. Although not shown in the figures, in some embodiments, the semiconductor structure 200 further includes another floating gate and control gate pair placed so as to couple to the common source region 220. In some embodiments, the semiconductor structure 200 further includes features, such as word lines and/or bit lines, for accessing cells of a memory array comprising the semiconductor structure 200. For example, as understood in the art, a word line can be formed adjacent to a floating gate and control gate. Furthermore, in some embodiments, the semiconductor structure 200 further includes spacers between various gates and between various gates and word lines or bit lines. For example, in some embodiments there are one or more spacers between the erase gate 240 and the control gate 244 and between the erase gate 240 and the floating gate 242. In some embodiments, the floating gate is formed by depositing a floating gate layer, followed by depositing a control gate, and finally etching of the floating gate layer.
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The disclosed semiconductor structure 200 can be used in various microelectronic devices, such as in flash memory devices. Likewise, the disclosed semiconductor structure 400 can be used in various microelectronic devices, such as flash memory devices.
Thus, the present disclosure provides semiconductor structures. In at least one embodiment, a semiconductor structure includes a common source region having a sawtooth profile; and a flat erase gate disposed above the common source region. In at least one embodiment, the semiconductor structure further includes a dielectric feature disposed between the common source region and the erase gate and having a bottom surface and a top surface, wherein the bottom surface has a sawtooth profile in contact with the common source region, and wherein the top surface has a flat profile in contact with the erase gate.
In at least one embodiment, a second semiconductor structure includes a plurality of active regions formed on a substrate; a common source region formed on the substrate and spanning the plurality of active regions, wherein the common source region has a U-shape; and a flat erase gate disposed above the common source region, wherein the active regions extend in a first direction, and wherein the common source region extends in a second direction perpendicular to the first direction. In at least one embodiment, the second semiconductor structure further includes a dielectric feature disposed between the common source region and the erase gate, wherein the dielectric feature comprises multiple shallow trench isolation features.
The present disclosure also provides a method of making a semiconductor structure. In at least one embodiment, the method includes forming a plurality of trenches in a substrate thereby forming a plurality of active regions; and forming a common source region in the substrate in a direction perpendicular to the active regions. Furthermore, the method further includes, after forming the common source region: forming a dielectric feature on the substrate thereby filling the trenches and forming a plurality of shallow trench isolation features; and forming an erase gate on the dielectric feature.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims
1. A method comprising:
- forming a common source region in a substrate;
- forming an isolation feature over the common source region, such that the common source region is disposed between the substrate and the isolation feature; and
- forming an erase gate over the isolation feature, such that the erase gate is disposed over the common source region.
2. The method of claim 1, wherein the forming the common source region includes:
- etching the substrate to form a saw-tooth shaped recess region; and
- performing an ion implantation process to form a doped region in a portion of the saw-tooth shaped recess region, such that the common source region has a sawtooth profile, and further wherein the common source region spans a plurality of active regions of the substrate.
3. The method of claim 1, wherein the forming the common source region includes:
- etching the substrate to form a U-shaped recess region in the substrate; and
- performing an ion implantation process to form a doped region in a portion of the U-shaped recess region, such that the common source region has a U-shaped profile, and further wherein the common source region spans a plurality of active regions of the substrate.
4. The method of claim 1, further including:
- forming a trench structure in the substrate;
- forming a patterned material layer over the substrate, wherein the patterned material layer exposes a portion of the trench structure and fills another portion of the trench structure; and
- forming a doped layer in the substrate along a surface of the exposed portion of the trench structure, thereby forming the common source region.
5. The method of claim 4, wherein the forming the trench structure includes etching the substrate to form a saw-tooth shaped recess region.
6. The method of claim 4, wherein the exposed portion of the trench structure is partially filled by the patterned material layer, the method further including, before forming the doped layer, etching the patterned material layer partially filling the trench structure and portions of the substrate defining the exposed portion of the trench structure to form a U-shaped recess region.
7. The method of claim 1, further including:
- after forming the common source region, forming a floating gate over the substrate; and
- forming a control gate over the floating gate.
8. The method of claim 7, wherein the floating gate is formed over the substrate and the isolation feature, such that the floating gate is adjacent to the common source region.
9. A method comprising:
- defining a plurality of active regions in a substrate;
- forming a common source region in a portion of the substrate, such that the common source region spans the plurality of active regions; and
- after forming the common source region: forming an isolation feature over the common source region, such that the isolation feature spans the plurality of active regions, and forming a gate over the isolation feature.
10. The method of claim 9, wherein the defining the plurality of active regions in the substrate includes etching the substrate to form a trench structure that includes the plurality of active regions disposed between trenches, wherein the trench structure has a saw-tooth shaped recess region.
11. The method of claim 10, the method further including:
- forming a patterned material layer over the substrate, wherein the patterned material layer exposes a portion of the trench structure and covers another portion of the trench structure; and
- forming the common source region in the exposed portion of the trench structure, such that the common source region has a sawtooth profile.
12. The method of claim 11, further including removing the patterned material layer after forming the isolation feature.
13. The method of claim 10, the method further including:
- forming a patterned material layer over the substrate, wherein the patterned material layer exposes a portion of the trench structure and covers another portion of the trench structure, wherein trenches in the exposed portion of the trench structure are partially filled by the patterned material layer; and
- etching the patterned material layer partially filling the trenches and portions of the substrate defining the exposed portion of the trench structure, such that the substrate defines a U-shaped recess region.
14. The method of claim 13, further including forming the common source region in a portion of the substrate defining the U-shaped recess region, such that the common source region has a U-shaped profile.
15. The method of claim 14, further including removing the patterned material layer after forming the isolation feature.
16. The method of claim 9, wherein the gate is an erase gate and the method further includes:
- forming a floating gate adjacent to the erase gate; and
- forming a control gate over the floating gate.
17. A method comprising:
- etching a substrate to define a plurality of active regions;
- forming a patterned material layer over the substrate that exposes a first portion of the substrate and covers a second portion of the substrate;
- performing an implantation process to form a common source region in the first portion of the substrate;
- forming an isolation feature over the common source region; and
- after removing the patterned material layer, forming a gate.
18. The method of claim 17, wherein the forming the gate includes:
- forming an erase gate on the isolation feature, such that the erase gate is disposed over the first portion of the substrate;
- forming a floating gate on the isolation feature, such that the floating gate is disposed over the second portion of the substrate; and
- forming a control gate on the floating gate.
19. The method of claim 17, wherein the etching the substrate includes forming a saw-tooth shaped recess region in the substrate.
20. The method of claim 17, further including using the patterned material layer to etch a U-shaped recess region in the substrate in the first portion of the substrate before forming the common source region.
Type: Application
Filed: Jun 8, 2017
Publication Date: Sep 21, 2017
Patent Grant number: 10453932
Inventors: Ming Chyi Liu (Hsinchu City), Chang-Ming Wu (New Taipei City), Shih-Chang Liu (Kaohsiung County), Wei Cheng Wu (Hsinchu County), Harry-Hak-Lay Chuang (Singapore), Chia-Shiung Tsai (Hsin-Chu), Ru-Liang Lee (Hsinchu)
Application Number: 15/617,691