PROTECTING, OXIDIZING, AND ETCHING OF MATERIAL LINES FOR USE IN INCREASING OR DECREASING CRITICAL DIMENSIONS OF HARD MASK LINES
A method includes, for example, a starting semiconductor structure comprising a plurality of material lines disposed over a hard mask, and the hard mask disposed over a patternable layer, forming a first protective layer over some of the plurality of material lines, the protected material lines and the unprotected material lines having a same corresponding first critical dimension, oxidizing the unprotected material lines so that the oxidized unprotected material lines have an increased second critical dimension greater than the first critical dimension, removing the first protective layer, forming a second protective layer over some of the plurality of protected material lines having the first critical dimension and some of the oxidized material lines having the second critical dimension, and oxidizing the unprotected material lines so that the oxidized unprotected material lines have an increased third critical dimension greater than the first critical dimension.
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The present disclosure generally relates to semiconductor fabrication, and more particularly, to method for use in semiconductor fabrication, for example, protecting, oxidizing, and etching of material lines for use in increasing or decreasing corresponding critical dimensions of hard mask lines.
BACKGROUND OF THE DISCLOSUREWith CMOS technology entering FinFET in 14 nanometers (nm), conventional lithography is no longer capable for patterning fine pitches. The self-align-dual-patterning (SADP), self-aligned quadruple patterning (SAQP), or sidewall image transfer (SIT) process enables the small pitch patterning in forming Fins, gates, or even in BEOL (Back-End-Of-The-Line) metal connections at 7 nanometers node and beyond. Spacer defined lithography (SIT) only offers one CD (critical dimension) such as widths for fine lines.
SUMMARY OF THE DISCLOSUREShortcomings of the prior art are overcome and additional advantages are provided through the provision, in one embodiment, of a method which includes, for example, providing a starting semiconductor structure having a plurality of material lines disposed over a hard mask, and the hard mask disposed over a patternable layer, forming a first protective layer over some of the plurality of material lines, the protected material lines and the unprotected material lines having a same corresponding first critical dimension, oxidizing the unprotected material lines so that the oxidized unprotected material lines have an increased second critical dimension greater than the first critical dimension, removing the first protective layer, forming a second protective layer over some of the plurality of protected material lines having the first critical dimension and some of the oxidized material lines having the second critical dimension, and oxidizing the unprotected material lines so that the oxidized unprotected material lines have an increased third critical dimension greater than the first critical dimension.
In another embodiment, a method is provided. The method includes, for example, providing a starting semiconductor structure having a plurality of material lines disposed over a hard mask, and the hard mask disposed over a patternable layer, forming a first protective layer over some of the plurality of material lines, the protected material lines and the unprotected material lines having a same corresponding first critical dimension, oxidizing the unprotected material lines so that the oxidized unprotected material lines have an increased second critical dimension greater than the first critical dimension, removing the first protective layer, forming a second protective layer over some of the plurality of protected material lines having the first critical dimension and some of the oxidized material lines having the second critical dimension, oxidizing the unprotected material lines so that the oxidized unprotected material lines have an increased third critical dimension greater than the first critical dimension, etching at least a portion of the first oxidized unprotected material lines so that the unprotected first oxidized material lines have a forth critical dimension less than the second critical dimension, and etching at least a portion of the second oxidized unprotected material lines so that the unprotected second oxidized material lines have a fifth critical dimension less than the third critical dimension.
In another embodiment, an intermediate semiconductor structure is provided. The intermediate semiconductor structure includes, for example, a first plurality of material lines, a second plurality of material lines, and a third plurality of material lines disposed over a hard mask, the hard mask disposed over a patternable layer, and the patentable layer disposed over a bulk semiconductor substrate. The second plurality of material lines includes etched oxide or having oxide removed. The third plurality of material lines includes etched oxide or having oxide removed. The first plurality of material lines have a first critical dimension, the second plurality of material lines have a corresponding second critical dimension, and the third plurality of material lines have a corresponding third critical dimension. The first critical dimension, the second critical dimension, and the third critical dimension being different.
Additional features and advantages are realized through the techniques of the present disclosure. Other embodiments and aspects of the present disclosure are described in detail herein and are considered a part of the claims.
The subject matter of the present disclosure is particularly pointed out and distinctly claimed in the concluding portion of the specification. The disclosure, however, may best be understood by reference to the following detailed description of various embodiments and the accompanying drawings in which:
Aspects of the present disclosure and certain features, advantages, and details thereof, are explained more fully below with reference to the non-limiting embodiments illustrated in the accompanying drawings. Descriptions of well-known materials, fabrication tools, processing techniques, etc., are omitted so as to not unnecessarily obscure the disclosure in detail. It should be understood, however, that the detailed description and the specific examples, while indicating embodiments of the present disclosure, are given by way of illustration only, and are not by way of limitation. Various substitutions, modifications, additions and/or arrangements within the spirit and/or scope of the underlying concepts will be apparent to those skilled in the art from this disclosure. Reference is made below to the drawings, which are not drawn to scale for ease of understanding, wherein the same reference numbers used throughout different figures designate the same or similar components.
The present disclosure is directed to self-align-dual-patterning (SADP), sidewall image transfer (SIT), and self-aligned quadruple patterning (SAQP) processes with selective multi-CD (critical dimension) patterning capability by selectively fine tuning the spacer CD using a combination of oxidation or partial oxidation and wet/dry oxide etching or partial wet/dry oxide etching. The present disclosure may be advantageous for fine tuning CD of multi-fin fin widths or multi-channel lengths (for multi-Vt scheme), multi-gate widths or multi-gate channel lengths (for SOC), and/or BEOL metal connections with minimum extra masking steps without selectively performing an entire SADP or SAQP process.
In one example, substrate 102 may include any silicon-containing substrate including, but not limited to, silicon (Si), single crystal silicon, polycrystalline Si, amorphous Si, silicon-on-nothing (SON), silicon-on-insulator (SOI) or silicon-on-replacement insulator (SRI) or silicon germanium substrates and the like. Substrate 102 may in addition or instead include various isolations, dopings and/or device features. The substrate may include other suitable elementary semiconductors, such as, for example, germanium (Ge) in crystal, a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and/or indium antimonide (InSb) or combinations thereof; an alloy semiconductor including GaAsP, AlinAs, GalnAs, GaInP, or GaInAsP or combinations thereof.
Starting semiconductor structure 100 may be conventionally fabricated, for example, using known processes and techniques. An initial structure may include of bulk semiconductor substrate 102, patternable layer 104, and a hard mask layer 106, and subjected to a self-align-dual-patterning (SADP) or self-aligned quadruple patterning (SAQP) process. For example, an oxide or amorphous carbon layer may be deposited on hard mask layer 106. The oxide or amorphous carbon layer may then patterned and operably etched to form patterned mandrels. A layer of amorphous silicon or polysilicon may be deposed over the patterned mandrels, and an etching process employed to form vertical spacers on mandrel. Removal or stripping back the mandrel results in the spacers forming the plurality of material lines 200 shown in
Initially, as shown in
With reference to
Patterned protective layer 300 is removed as shown in
As shown in
With reference to
An etching process is performed on the structure of
The patterned protective layer 350 is removed as shown in
Thus, the structure shown in
The different corresponding sized critical dimensions of the material lines are used for pattern transfer to the underlying layers. An etching process is employed on the resulting structure of
Initially,
In this embodiment, the etching process may result in the removal of the oxide material on material lines 210 (
Initially, as shown in
An oxidation process such as at a low temperature is performed on the structure of
As shown in
With reference to
An etching process is performed on the structure of
The patterned protective layer 1350 may be removed, as shown in
The different corresponding sized critical dimensions of the material lines are used for pattern transfer to the underlying layers. An etching process is employed on the resulting structure of
Another method according to an embodiment of the present disclosure includes providing a starting semiconductor structure, the starting semiconductor structure having a material layer, a hard mask layer over the material layer, and a plurality of material lines over the hard mask layer, forming a protective layer over one or more, but less than all of the plurality of material lines, wherein at least one protected material line and at least one unprotected material line have a same critical dimension, and after forming the protective layer, fully oxidizing unprotected material lines, wherein the fully oxidized at least one unprotected material line has a larger critical dimension than the at least one protected material line. For example, the structure in
It will be appreciated from the present disclosure provides a new SADP method or SAQP method with selective multi-CD patterning capability (e.g., 1 extra mask for 2 CDs at the same pitch, 2 masking steps for 4 CDs at same pitch, etc.) by selectively fine tuning the spacer CD using oxidation or partial oxidation and wet/dry oxide etching. Then proceed with the rest of conventional SADP or SAQP steps by etching down and transfer pattern on under-layers (e.g. HM, Si, a-Si, oxide, etc). The present method can be used for forming fins with selective fin-width for multi-Vt scheme. The present method can also be used for forming multiple channel length without using critical multiple gate litho/etch steps.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprise” (and any form of comprise, such as “comprises” and “comprising”), “have” (and any form of have, such as “has” and “having”), “include” (and any form of include, such as “includes” and “including”), and “contain” (and any form contain, such as “contains” and “containing”) are open-ended linking verbs. As a result, a method or device that “comprises”, “has”, “includes” or “contains” one or more steps or elements possesses those one or more steps or elements, but is not limited to possessing only those one or more steps or elements. Likewise, a step of a method or an element of a device that “comprises”, “has”, “includes” or “contains” one or more features possesses those one or more features, but is not limited to possessing only those one or more features. Furthermore, a device or structure that is configured in a certain way is configured in at least that way, but may also be configured in ways that are not listed.
The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below, if any, are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosure in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosure. The embodiment was chosen and described in order to best explain the principles of one or more aspects of the present disclosure and the practical application, and to enable others of ordinary skill in the art to understand one or more aspects of the disclosure for various embodiments with various modifications as are suited to the particular use contemplated.
Claims
1. A method comprising:
- providing a starting semiconductor structure comprising a plurality of material lines disposed over a hard mask, and the hard mask disposed over a patternable layer;
- forming a first protective layer over some of the plurality of material lines, the protected material lines and the unprotected material lines having a same corresponding first critical dimension;
- oxidizing the unprotected material lines so that the oxidized unprotected material lines have an increased second critical dimension greater than the first critical dimension;
- removing the first protective layer;
- forming a second protective layer over some of the plurality of protected material lines having the first critical dimension and some of the oxidized material lines having the second critical dimension; and
- oxidizing the unprotected material lines so that the oxidized unprotected material lines have an increased third critical dimension greater than the first critical dimension.
2. The method of claim 1 wherein third critical dimension is greater than the second critical dimension.
3. The method of claim 1 wherein third critical dimension is less than the second critical dimension.
4. The method of claim 1 wherein the first oxidizing comprising fully oxidizing the unprotected material lines.
5. The method of claim 1 wherein the first oxidizing comprising partially oxidizing the unprotected material lines.
6. The method of claim 1 wherein the second oxidizing comprising fully oxidizing at unprotected material lines.
7. The method of claim 1 wherein the second oxidizing comprising partially oxidizing at unprotected material lines.
8. The method of claim 1 further comprising:
- etching at least a portion of the first oxidized unprotected material lines so that the unprotected first oxidized material lines have a forth critical dimension less than the second critical dimension, and
- etching at least a portion of the second oxidized unprotected material lines so that the unprotected second oxidized material lines have a fifth critical dimension less than the third critical dimension.
9. The method of claim 8 wherein the first oxidizing comprising fully oxidizing the unprotected material lines.
10. The method of claim 8 wherein the first oxidizing comprising partially oxidizing the unprotected material lines.
11. The method of claim 8 wherein the second oxidizing comprising fully oxidizing at unprotected material lines.
12. The method of claim 8 wherein the second oxidizing comprising partially oxidizing at unprotected material lines.
13. The method of claim 8 further comprising:
- removing the protective layer;
- forming a patterned hard mask layer from the hard mask layer using at least one protected material line and the at least one etched material line; and
- wherein the patterned hard mask layer comprises material lines having the different critical dimensions.
14. The method of claim 13 further comprising:
- forming a patterned layer from the patternable layer using the patterned hard mask layer; and
- wherein the patterned layer comprise material lines having the different critical dimensions.
15. The method of claim 14 wherein the starting semiconductor structure is situated over a bulk semiconductor substrate, and further comprising using to the patterned layer having the different critical dimensions to form finFETS, dummy gates, back end of line (BEOF) features, or front end of line (FEOL) features.
16-20. (canceled)
Type: Application
Filed: Apr 7, 2016
Publication Date: Oct 12, 2017
Applicant: GLOBALFOUNDRIES Inc. (Grand Cayman)
Inventors: Hui ZANG (Guilderland, NY), Min-hwa CHI (San Jose, CA)
Application Number: 15/093,292