METHODS OF FORMING A PROTECTION LAYER ON AN ISOLATION REGION OF IC PRODUCTS COMPRISING FINFET DEVICES
One illustrative method disclosed herein includes, among other things, forming a plurality of trenches in a semiconductor substrate so as to define a plurality of fins, forming a recessed layer of insulating material comprising a first insulating material in the trenches, wherein a portion of each of the plurality of fins is exposed above an upper surface of the recessed layer of insulating material, and masking a first portion of a first fin and performing at least one first etching process to remove at least a portion of an unmasked second fin. In this example, the method further includes forming a device isolation region for the FinFET device that comprises a second insulating material and forming an isolation protection layer above the device isolation region.
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various novel methods of forming a protection layer on an isolation region of integrated circuit (IC) products comprising FinFET devices.
2. Description of the Related ArtIn modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, etc. The transistors are typically either NMOS (NFET) or PMOS (PFET) type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices. So-called CMOS (Complementary Metal Oxide Semiconductor) technology or products refers to integrated circuit products that are manufactured using both NMOS and PMOS transistor devices. Irrespective of the physical configuration of the transistor device, each device comprises drain and source regions and a gate electrode structure positioned above and between the source/drain regions. Upon application of an appropriate control voltage to the gate electrode, a conductive channel region forms between the drain region and the source region.
A conventional FET is a planar device wherein the entire channel region of the device is formed parallel and slightly below the planar upper surface of the semiconducting substrate. In contrast to a planar FET, there are so-called 3D devices, such as an illustrative FinFET device, which is a three-dimensional structure.
Both FET and FinFET semiconductor devices have an isolation structure, e.g., a shallow trench isolation structure that is formed in the semiconducting substrate around the device so as to electrically isolate the semiconductor device from adjacent devices. Traditionally, isolation structures were always the first structure that was formed when manufacturing semiconductor devices. The isolation structures were formed by etching the trenches for the isolation structures and thereafter filling the trenches with the desired insulating material, e.g., silicon dioxide. After the isolation structures were formed, various process operations were performed to manufacture the semiconductor device. In the case of a FinFET device, this involved masking the previously formed isolation structure and etching the trenches in the substrate that defined the fins. As FinFET devices have been scaled to meet ever-increasing performance and size requirements, the width of the fins 14 has become very small, e.g., 6-12 nm, and the fin pitch has also been significantly decreased, e.g., the fin pitch may be on the order of about 30-60 nm.
However, as the dimensions of the fins became smaller, problems arose with manufacturing the isolation structures before the fins were formed. As one example, trying to accurately define very small fins in regions that were separated by relatively large isolation regions was difficult due to the non-uniform spacing between various structures on the substrate. One manufacturing technique that is employed in manufacturing FinFET devices is to initially etch the fin-formation trenches 13 in the substrate 12 to define multiple “fins” that extend across the entire substrate 12 (or area of the substrate where FinFET devices will be formed). Using this type of manufacturing approach, better accuracy and repeatability may be achieved in forming the fins 14 to very small dimensions due to the more uniform environment in which the etching process that forms the fin-formation trenches 13 is performed. After the fin-formation trenches 13 are formed, the isolation material 17 is formed between the fins 14 such that it substantially fills the fin-formation trenches 13. At that point, some portion of some of the fins 14 must be removed or cut to create room for or define the spaces where a device isolation region, e.g., an STI region, will ultimately be formed. This fin cutting process is typically performed by forming two different “fin cut” masking layers and performing a single etching process. After the fins are cut, additional insulation isolation material 17 is formed between the remaining fins 14 and in the spaces that were formerly occupied by the removed fins. Next, a timed recess etching process was then performed on the insulating material 17 so as to “reveal” the desired final fin height of the remaining fins. As a result of these process operations, so-called local isolation regions are formed between the fins 14, and a device isolation region, e.g., an STI region, is formed around the FinFET device so as to electrically isolate the device from adjacent FinFET devices. Importantly, in this prior art process flow, the fin cutting process was performed prior to performing the fin reveal process, i.e., prior to performing the recess etching process on the insulating material 17.
Several acid-based etching or cleaning processes are performed on the product over the course of forming the various structures that make up the FinFET devices. For example, a plurality of wet HF based cleaning processes may be performed at various times to remove an undesirable material, such as native oxide layers, prior to or after performing a process operation. By way of example, such acid-based cleaning processes are typically performed prior to formation of the epi semiconductor materials 30. Unfortunately, the isolation structure 28, which is typically comprised of silicon dioxide, is also subject to attack during these cleaning processes. Additionally, even if an etching or cleaning process is performed that is not purposefully intended to remove silicon dioxide, e.g., a spacer etch process when the spacer material is silicon nitride, the silicon dioxide material 17 in the isolation structure 28 is still subject to some degree of attack. As a result, as shown in
The present disclosure is directed to various novel methods of forming a protection layer on an isolation region of integrated circuit (IC) products comprising FinFET devices and resulting structures that may solve or reduce one or more of the problems identified above.
SUMMARY OF THE INVENTIONThe following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
Generally, the present disclosure is directed to various novel methods of forming a protection layer on an isolation region of integrated circuit (IC) products comprising FinFET devices and the resulting structures. One illustrative method disclosed herein includes, among other things, forming a plurality of trenches in a semiconductor substrate so as to define a plurality of fins, forming a recessed layer of insulating material comprising a first insulating material in the trenches, wherein a portion of each of the plurality of fins is exposed above an upper surface of the recessed layer of insulating material, and masking a first portion of a first fin and performing at least one first etching process to remove at least a portion of an unmasked second fin. In this example, the method further includes forming a device isolation region for the FinFET device that comprises a second insulating material and forming an isolation protection layer above the device isolation region.
One illustrative embodiment of an IC product disclosed herein comprises a FinFET device comprising at least one fin, a gate structure and a sidewall spacer and a device isolation region comprising a first insulating material positioned around a perimeter of the FinFET device. The product also comprises an isolation protection layer positioned above the device isolation region, wherein the isolation protection layer comprises a material that is different than the first insulating material, and wherein a first portion of the isolation protection layer is positioned under a portion of the gate structure and a portion of the sidewall spacer and a second portion of the isolation protection layer is not positioned under the gate structure and not positioned under the sidewall spacer, the first portion of the isolation protection layer having a thickness that is greater than a thickness of the second portion.
The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
Various illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
The present subject matter will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase. As will be readily apparent to those skilled in the art upon a complete reading of the present application, the methods disclosed herein may be employed in manufacturing a variety of different devices, including, but not limited to, logic devices, memory devices, etc., and the devices may be may be either NMOS or PMOS devices.
As will be appreciated by those skilled in the art after a complete reading of the present application, various doped regions, e.g., source/drain regions, halo implant regions, well regions and the like, are not depicted in the attached drawings. Of course, the inventions disclosed herein should not be considered to be limited to the illustrative examples depicted and described herein. The various components and structures of the integrated circuit devices 100 disclosed herein may be formed using a variety of different materials and by performing a variety of known techniques, e.g., a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a thermal growth process, spin-coating techniques, etc. The thicknesses of these various layers of material may also vary depending upon the particular application. With reference to the attached figures, various illustrative embodiments of the methods and devices disclosed herein will now be described in more detail.
With continuing reference to
As shown in
With continuing reference to
Next, a third etching process was performed to remove the exposed portions of the insulation material 108 within the isolation region opening 112. The result of all of these process operations is that the isolation region opening 112 for a device isolation region is formed around the perimeter of the FinFET device and that portions of the upper surface 102S of the substrate 102 is exposed.
Then, another etching process was performed to remove the exposed first portion of the layer of isolation protection material 118. Next, another etching process was performed to remove the exposed portions of the conformal layer of silicon dioxide 116.
At the point of processing depicted in
Next, another etching process was performed to remove the silicon dioxide liner layer 138 and expose the portions of the fins 106 that are to be removed. This latter etching process stops on the portions of the insulation material 108 positioned within the isolation region opening 112. Then, yet another etching process was performed to remove the exposed portions of the fins 106. In the depicted example, the entire vertical height of the exposed portions of the fins 106 was removed. Next, a final etching process was performed to remove the exposed portions of the insulation material 108. The result of all of these process operations is that the isolation region opening 112 for the device isolation region 127 is formed around the perimeter of the FinFET device and exposes portions of the upper surface 102S of the substrate 102.
For example,
The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Note that the use of terms, such as “first,” “second,” “third” or “fourth” to describe various processes or structures in this specification and in the attached claims is only used as a shorthand reference to such steps/structures and does not necessarily imply that such steps/structures are performed/formed in that ordered sequence. Of course, depending upon the exact claim language, an ordered sequence of such processes may or may not be required.
As used herein, spatial references “top,” “bottom,” “upper,” “lower,” “vertical,” “horizontal” and the like may be used for convenience when referring to structures of FET devices. These references are intended to be used in a manner consistent with the drawings only for teaching purposes, and are not intended as absolute references for FET structures. For example, FETs may be oriented spatially in any manner different from the orientations shown in the drawings. Accordingly, the protection sought herein is as set forth in the claims below.
Claims
1. A method of forming a FinFET device, comprising:
- forming a plurality of fin-formation trenches in a semiconductor substrate so as to define a plurality of fins;
- forming a recessed layer of insulating material comprising a first insulating material in said fin-formation trenches, wherein a portion of each of said plurality of fins is exposed above an upper surface of said recessed layer of insulating material;
- after forming said recessed layer of insulating material, masking a first portion of a first fin of said plurality of fins and performing at least one first etching process to remove at least a portion of an unmasked second fin of said plurality of fins;
- after performing said at least one first etching process, forming a device isolation region for said FinFET device that comprises a second insulating material; and
- forming an isolation protection layer above said device isolation region, wherein said isolation protection layer comprises a different material than said second insulating material of said device isolation region.
2. The method of claim 1, wherein said first and second insulating materials comprise silicon dioxide and said isolation protection layer comprises one of silicon nitride, silicon oxynitride or SiBCN.
3. The method of claim 1, wherein forming said isolation protection layer above said device isolation region comprises performing a directional deposition process so as to form said isolation protection layer above said device isolation region.
4. The method of claim 1, wherein forming said isolation protection layer above said device isolation region comprises
- performing a conformal deposition process so as to form a conformal isolation protection layer above said device isolation region;
- masking portions of said conformal isolation protection layer positioned above said device isolation region while exposing other portions of said conformal isolation protection layer; and
- removing said exposed portions of said conformal isolation protection layer.
5. The method of claim 1, wherein masking said first portion of said first fin comprises:
- forming a layer of sacrificial material above said recessed layer of insulating material in said fin-formation trenches and adjacent said first and second fins; and
- removing a first portion of said layer of sacrificial material positioned adjacent said second fin while leaving a second portion of said layer of sacrificial material positioned adjacent said first fin in place wherein said layer of sacrificial material comprises said second portion.
6. The method of claim 1, wherein masking said first portion of said first fin comprises forming a patterned fin masking layer that is at least partially positioned within said fin-formation trenches, wherein said patterned fin masking layer comprises at least one layer of material.
7. The method of claim 1, wherein forming said device isolation region for said FinFET device comprises:
- removing a portion of said recessed layer of insulating material so as to expose a substantially horizontal surface of said substrate and define an isolation region opening;
- filling said isolation region opening with said second insulating material; and
- performing a recess etching process of said second insulating material.
8. The method of claim 1, wherein said at least one first etching process is performed so as to remove an entire vertical height of said unmasked portion of said second fin.
9. The method of claim 1, wherein performing said at least one first etching process comprises performing a single etching process.
10. A method of forming a FinFET device, comprising:
- forming a plurality of fin-formation trenches in a semiconductor substrate so as to define a plurality of fins;
- forming a recessed layer of insulating material comprising a first insulating material in said fin-formation trenches, wherein a portion of each of said plurality of fins is exposed above an upper surface of said recessed layer of insulating material;
- after forming said recessed layer of insulating material, forming a patterned fin masking layer above said substrate that covers a first portion of a first fin of said plurality of fins, exposes a second portion of said first fin and exposes at least a portion of a second fin of said plurality of fins;
- with said patterned fin masking layer in position above said substrate, performing at least one first etching process to remove at least a portion of a vertical height of said exposed portions of said first and second fins;
- after performing said at least one first etching process, forming a device isolation region for said FinFET device that comprises a second insulating material; and
- forming an isolation protection layer above said device isolation region, wherein said isolation protection layer comprises a different material than said second insulating material of said device isolation region.
11. The method of claim 10, wherein said first and second insulating materials comprise different insulating materials and wherein said isolation protection layer comprises a material that is different from both said first and second insulating materials.
12. The method of claim 10, wherein forming said isolation protection layer above said device isolation region comprises:
- performing a directional deposition process so as to form a first portion of said isolation protection layer above said patterned fin masking layer and a second portion of said isolation protection layer above said device isolation region;
- masking said second portion of said isolation protection layer; and
- removing said first portion of said isolation protection layer.
13. The method of claim 10, wherein forming said isolation protection layer above said device isolation region comprises
- performing a conformal deposition process so as to form a conformal isolation protection layer above said patterned fin masking layer and above said device isolation region;
- masking portions of said conformal isolation protection layer positioned above said device isolation region while exposing other portions of said conformal isolation protection layer; and
- removing said exposed portions of said conformal isolation protection layer.
14. The method of claim 10, wherein forming said patterned fin masking layer comprises:
- forming a layer of sacrificial material above said recessed layer of insulating material in said fin-formation trenches and adjacent said first and second fins; and
- removing a first portion of said layer of sacrificial material positioned adjacent said second fin while leaving a second portion of said layer of sacrificial material positioned adjacent said first fin in place, wherein said layer of sacrificial material comprises said second portion.
15. The method of claim 10, wherein forming said patterned fin masking layer comprises:
- forming a first layer of sacrificial material above said recessed layer of insulating material in said fin-formation trenches and adjacent said first and second fins;
- forming a second layer of sacrificial material on said first layer of sacrificial material;
- removing a first portion of said second layer of sacrificial material from above said second fin while leaving a second portion of said second layer of sacrificial material positioned above said first fin; and
- removing a first portion of said first layer of sacrificial material positioned adjacent said second fin while leaving a second portion of said first layer of sacrificial material positioned adjacent said first fin in place, wherein said patterned fin masking layer comprises said second portion of said first layer of sacrificial material and said second portion of said second layer of sacrificial material.
16. The method of claim 15, wherein said first and second layers of sacrificial material comprise different materials.
17. The method of claim 10 wherein forming said device isolation region for said FinFET device comprises:
- after performing said at least one first etching process, and with said patterned fin masking layer in position above said substrate, removing a portion of said recessed layer of insulating material so as to expose a substantially horizontal surface of said substrate and define an isolation region opening;
- filling said isolation region opening with said second insulating material; and
- performing a recess etching process of said second insulating material.
18. An integrated circuit product, comprising:
- a FinFET device comprising at least one fin, a gate structure and a sidewall spacer;
- a device isolation region comprising a first insulating material positioned around a perimeter of said FinFET device;
- an isolation protection layer positioned above said device isolation region, said isolation protection layer comprising a material that is different than said first insulating material, wherein a first portion of said isolation protection layer is positioned under a portion of said gate structure and a portion of said sidewall spacer and a second portion of said isolation protection layer is not positioned under said gate structure and not positioned under said sidewall spacer, said first portion of said isolation protection layer having a thickness that is greater than a thickness of said second portion.
19. The product of claim 18, wherein said first insulating material comprises silicon dioxide and said isolation protection layer comprises one of silicon nitride or silicon oxynitride.
20. The product of claim 18, further comprising a recessed layer of a second insulating material positioned under said gate structure and adjacent said fin.
21. The product of claim 20, wherein said first and second insulating materials comprise silicon dioxide.
22. The product of claim 20, wherein said first and second insulating materials comprise different insulating materials.
23. The product of claim 18, wherein, when viewed in a cross-section taken through said gate structure and said isolation protection layer in a direction corresponding to a gate width direction of said device, said isolation protection layer has a stepped cross-sectional profile.
24. The product of claim 18, wherein, when viewed in a cross-section taken through said gate structure and said isolation protection layer in a direction corresponding to a gate length direction of said device, the isolation protection layer has a stepped cross-sectional profile.
Type: Application
Filed: Jun 30, 2016
Publication Date: Jan 4, 2018
Inventors: Ruilong Xie (Niskayuna, NY), Christopher M. Prindle (Poughkeepsie, NY), Min Gyu Sung (Latham, NY), Tek Po Rinus Lee (Malta, NY)
Application Number: 15/197,944