LED HAVING VERTICAL CONTACTS REDISTRIBUTED FOR FLIP CHIP MOUNTING
A light emitting diode (LED) structure has semiconductor layers, including a p-type layer, an active layer, and an n-type layer. The p-type layer has a bottom surface, and the n-type layer has a top surface though which light is emitted. A copper layer has a first portion electrically connected to and opposing the bottom surface of the p-type layer. A dielectric wall extends through the copper layer to isolate a second portion of the copper layer from the first portion. A metal shunt electrically connects the second portion of the copper layer to the top surface of the n-type layer. P-metal electrodes electrically connect to the first portion, and n-metal electrodes electrically connect to the second portion, wherein the LED structure forms a flip chip. Other embodiments of the methods and structures are also described.
This application is a continuation of U.S. patent application Ser. No. 14/994,106, filed Jan. 12, 2016 and issuing as U.S. Pat. No. 9,722,137 on Aug. 1, 2017, which is a divisional of U.S. application Ser. No. 14/001,878, filed Aug. 28, 2013 and issued as U.S. Pat. No. 9,246,061 on Jan. 26, 2016 , which is a U.S. National Phase application under 35 U.S.C. 371 of International Application No. PCT/IB2012/050915, filed on Feb. 28, 2012, which claims the benefit of U.S. Provisional Application No. 61/452,181, filed on Mar. 14, 2011. These applications are hereby incorporated by reference herein.
FIELD OF THE INVENTIONThis invention relates to light emitting diodes (LEDs) and, in particular, to a technique for forming the LEDs as flip chips, with both electrodes on a bottom surface for direct bonding to submount electrodes.
BACKGROUNDFlip chip LEDs are desirable in many applications since they do not use wire bonding. Both electrodes are located on a bottom surface of the LED for direct bonding to metal pads on a submount. Bonding may be accomplished by ultrasonic bonding, solder, conductive adhesive, or other means. Light exits the surface of the LED opposite the electrodes.
In a typical LED flip chip, the epitaxial p-type layer is the bottom layer and is contacted by the bottom anode electrode. A portion of the p-type layer and active layer must be etched away to expose the underside of the epitaxial n-type layer for being contacted by the bottom cathode electrode. This etching creates distributed vias through the p-type layer that expose the bottom surface of the n-type layer. The via openings are then insulated, and metal is deposited in the openings for contacting the n-type layer.
Such topography is typically achieved by dry-etch of the semiconductor material in a plasma environment with active ionic species. The presence of such structure within a thin film device requires precise control of the plasma etch. Furthermore, the dry etched epitaxial surface, to be interfaced with contact metal, is sensitive to the damage caused by impingement of energetic ionic species in the plasma. From a thermal and mechanical point of view, the corners of such a step structure are prone to becoming failure initiation centers as a result of stress distribution within the sandwiched films. The film growth over the mesa or via structure typically requires a minimum step coverage, leading to higher equipment cost and the requirement of tighter in-line process control.
Accordingly, it would be desirable to avoid such etching of vias to form the flip chip LEDs.
SUMMARYIn one embodiment of the invention, an LED has an n-type layer formed over a sapphire growth substrate, followed by growing an active layer and a p-type layer. Each layer may be a plurality of layers. Many LEDs are grown on the same substrate wafer and will be later singulated. The process described herein is a wafer level process. The below summary describes one embodiment. Other ways to implement the invention are also envisioned.
A copper seed layer is formed overlying the top surface of the p-type layer.
A first dielectric wall is formed around each LED in the wafer where the saw lines will be. At the same time, an inner dielectric wall is formed along one edge of each LED. The area between the walls will eventually be filled with copper to provide an electrical connection between bottom cathode electrode and a top contact to the n-type layer of each LED.
The seed layer is plated with a first copper layer that covers the p-type layer and the area between the dielectric walls.
A dielectric layer portion is then formed on the bottom surface of the copper layer extending from the inner dielectric wall. This dielectric layer portion will eventually support gold bumps electrically connected to the n-type layer.
The sapphire substrate is then removed, and the exposed n-type layer is thinned.
The n-type layer is then etched over and around both dielectric walls to expose the first copper layer between the dielectric walls with the first copper layer as an excellent etch stop. The copper layer can be then removed by wet etch to electrically isolate the p contact. The etching of the n-type layer also separates the n-type layers of the various LEDs on the wafer, forming isolated LED device units across the wafer.
A dielectric layer will then be patterned to protect the side wall and completely cover the exposed p-contact metal of each LED unit.
A suitable n-contact metal (e.g., TiN), and adhesion layer, and copper seed layer are formed over the top surface of the wafer to cover the exposed n-type layer, the dielectric portions, and the copper between the dielectric walls, and a photoresist is formed over the central light-emitting area of the n-type layer but not over its edges and the dielectric portions. The exposed seed layer (forming a ring around each LED area) is then plated with a second copper layer, to form an n-contact, so the portion of the first copper layer on the bottom surface that is isolated between the dielectric walls contacts the second copper layer contacting the top edge of the n-layer.
The exposed n-type layer is roughened to increase light extraction, and a layer of phosphor is deposited over the n-type layer.
The bottom first copper layer is thus divided into sections contacting the p-type layer and sections contacting the n-type layer. Gold bumps are then formed on the n and p-copper sections for bonding to submount electrodes.
The wafer is then scribed and broken or sawed along the outer dielectric wall surrounding each LED area.
Accordingly, in contrast to the prior art LED flip chips where the n-metal electrode contacts the underside of the n-type layer exposed by etching a via through the p-type layer, the n-metal electrode in the present invention contacts the top surface of the n-type layer like a vertical LED.
Multiple LEDs may be connected in series by forming only one dielectric wall per LED to cause the second copper layer contacting the n-type layer of one LED to form an electrical connection to the first copper layer contacting the p-type layer of an adjacent LED.
Other fabrication techniques are also described for forming flip chips by electrically contacting the top surface of the n-type layer rather than contacting the n-type layer through an etched opening in the p-type layer. The conductivity types of the layers may be reversed, depending on the techniques used to grow the LED layers.
Other embodiments of the methods and structures are also described.
Elements labeled with the same numerals in the various figures may be the same or equivalent.
The figures are generally cross-sections of a portion of an LED wafer showing the formation of the right edge of one LED and the left edge of an adjacent LED.
A dielectric layer 82, such as silicon nitride, is deposited over the wafer surface and patterned to expose portions of the conductive guard layer 78. A copper seed layer 86 is formed over the dielectric layer 82 and exposed guard layer 78.
Dielectric walls 88 are then formed for the purpose of isolating the p and n-type layers after a copper layer is subsequently deposited. The walls 88 associated with each LED are formed as a square, assuming the LEDs are square shaped.
The seed layer 86 is plated with copper 90 to a thickness slightly less than the height of the dielectric walls 88. The bottom surface of the copper 90 has a metal barrier layer (not shown) formed over it. Gold contact/electrode pads 94 and 96 or metal bumps are deposited on the barrier layer for the p and n flip chip contacts, respectively. The pads 94 and 96 may be directly bonded to pads of a submount.
Accordingly, various techniques have been described that form flip chip LEDs without the need to form vias through the p-type layer to gain access to an underside of the n-type layer. The access to the n-type layer in the various embodiments is via the top surface of the n-type layer by a metal shunt electrically connected to bottom electrodes for the n-type layer.
Having described the invention in detail, those skilled in the art will appreciate that, given the present disclosure, modifications may be made to the invention without departing from the spirit of the inventive concept described herein. Therefore, it is not intended that the scope of the invention be limited to the specific embodiments illustrated and described.
Claims
1-6. (canceled)
7. A light-emitting device, comprising:
- a first semiconductor structure including a first n-type layer, a first p-type layer, and a first active layer disposed between the first n-type layer and the first p-type layer;
- a second semiconductor structure including a second n-type layer, a second p-type layer, and a second active layer disposed between the second n-type layer and the second p-type layer;
- a first metal layer including a first portion and a second portion that is electrically insulated from the first portion, the first portion being electrically coupled to the first n-type layer and the second portion being electrically coupled to the second n-type layer; and
- a first shunt electrically coupling the first p-type layer to the second portion of the first metal layer;
- a second metal layer that is disposed adjacently to the first metal layer; and
- a second shunt electrically coupling the second p-type layer to the second metal layer.
8. The light-emitting device of claim 7, wherein the first semiconductor structure and the second semiconductor structure are connected in series by the first shunt.
9. The light-emitting device of claim 7, further comprising a dielectric wall separating the first portion of the first metal layer from the second portion of the first metal layer.
10. The light emitting device of claim 7, further comprising a dielectric wall surrounding the first semiconductor structure and the second semiconductor structure, the dielectric wall being arranged to define a saw line for singulating the light-emitting device.
11. The light-emitting device of claim 7, wherein the first metal layer is formed of copper.
12. The light-emitting device of claim 7, wherein the first metal layer includes a first outer surface, and the second metal layer includes a second outer surface that is substantially flush with the first outer surface.
13. The light-emitting device of claim 7, wherein the first semiconductor structure and the second semiconductor structure are arranged in a flip chip configuration.
14. A light-emitting device, comprising:
- a first semiconductor structure including a first n-type layer, a first p-type layer, and a first active layer disposed between the first n-type layer and the first p-type layer;
- a second semiconductor structure including a second n-type layer, a second p-type layer, and a second active layer disposed between the second n-type layer and the second p-type layer;
- a first metal layer including a first portion and a second portion that is electrically insulated from the first portion, the first portion being electrically coupled to the first p-type layer and the second portion being electrically coupled to the second p-type layer; and
- a first shunt electrically coupling the first n-type layer to the second portion of the first metal layer;
- a second metal layer that is disposed adjacently to the first metal layer; and
- a second shunt electrically coupling the second n-type layer to the second metal layer.
15. The light-emitting device of claim 14, wherein the first semiconductor structure and the second semiconductor structure are connected in series by the first shunt.
16. The light-emitting device of claim 14, further comprising a dielectric wall separating the first portion of the first metal layer from the second portion of the first metal layer.
17. The light emitting device of claim 14, further comprising a dielectric wall surrounding the first semiconductor structure and the second semiconductor structure, the dielectric wall being arranged to define a saw line for singulating the light-emitting device.
18. The light-emitting device of claim 14, wherein the first metal layer is formed of copper.
19. The light-emitting device of claim 14, wherein the first metal layer includes a first outer surface, and the second metal layer includes a second outer surface that is substantially flush with the first outer surface.
20. The light-emitting device of claim 14, wherein the first semiconductor structure and the second semiconductor structure are arranged in a flip chip configuration.
21. A method, comprising:
- forming a first semiconductor structure and a second semiconductor structure, each of the first semiconductor structure and the second semiconductor structure including a respective first conductivity layer, a respective second conductivity layer, and a respective active layer disposed between the respective first conductivity layer and the respective second conductivity layer;
- forming a first metal layer including a first portion and a second portion that is electrically insulated from the first portion, the first portion being electrically coupled to the respective first conductivity layer of the first semiconductor structure and the second portion being coupled to the respective first conductivity layer of the second semiconductor structure;
- forming a first shunt that is configured to electrically couple the respective second conductivity layer of the first portion to the second portion of the first metal layer;
- forming a second metal layer adjacently to the first metal layer; and
- forming a second shunt that is configured to electrically couple the second respective conductivity layer of the second semiconductor structure to the second metal layer.
22. The method of claim 21, wherein:
- the respective first conductivity layer of the first semiconductor structure includes a p-type layer;
- the respective first conductivity layer of the second semiconductor structure includes a p-type layer;
- the respective second conductivity layer of the first semiconductor structure includes an n-type layer; and
- the respective second conductivity layer of the second semiconductor structure includes an n-type layer.
23. The method of claim 21, wherein:
- the respective first conductivity layer of the first semiconductor structure includes an n-type layer;
- the respective first conductivity layer of the second semiconductor structure includes an n-type layer;
- the respective second conductivity layer of the first semiconductor structure includes a p-type layer; and
- the respective second conductivity layer of the second semiconductor structure includes a p-type layer.
24. The method of claim 21, wherein the first semiconductor structure and the second semiconductor structure are connected in series by the first shunt.
25. The method of claim 21, further comprising forming a dielectric wall surrounding the first semiconductor structure and the second semiconductor structure.
26. The method of claim 21, wherein the first semiconductor structure and the second semiconductor structure are arranged in a flip chip configuration.
Type: Application
Filed: Jul 31, 2017
Publication Date: Jan 18, 2018
Inventors: Jipu Lei (San Jose, CA), Kwong-Hin Henry Choy (San Jose, CA), Yajun Wei (San Jose, CA), Stefano Schiaffino (San Jose, CA), Daniel Alexander Steigerwald (San Jose, CA)
Application Number: 15/664,651