CLOCK SKEW SUPPRESSION FOR TIME-INTERLEAVED CLOCKS
A time-interleaved clock circuit, including circuitry to provide multiple clock components of a sampling clock. The clock components are corrected by averaging pairs of the multiple clock components in order to output averaged signals. The time-interleaved clock is applied to data conversion in which input signals of the analog signal domain or of the digital signal domain are sampled based on the corrected clock components and converted to the digital signal domain or the analog signal domain, respectively.
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This disclosure generally relates to time-interleaved clocks that suppress clock phase mismatch, and particularly clocks for use in a data converter for high-speed data transmission.
BACKGROUNDInterleaved clocks may suffer from clock phase mismatch, especially as the output frequency increases towards the Nyquist frequency. Thus, there is a need to address this clock phase mismatch in order to insure performance at high frequency.
Possible approaches to solving this clock phase mismatch include using a dedicated circuit block such as a high-speed phase detector or using an injection locking oscillator. However, the inclusion of a high-speed phase detector as a dedicated circuit block adds extra loading on the highest speed clock path for phase correction. In particular, loading can become very high if wide skew correction range is necessary. Such high loading can lead to degradation of clock quality. Also, clock skew correction interrupts the synchronization loop and makes the calibration process complicated if a phase-interpolator is used for the correction block. In addition, the inclusion of a high-speed phase detector adds extra loading on the highest speed clock path for phase detection.
Still further, a high-speed phase detector may have limited performance due to limited bandwidth or offset. Typically, increasing device size in order to reduce offset inflates loading. A conventional current phase detection circuit's sensitivity is limited. Also, the conventional detection circuit typically requires an inductor which consumes a large area.
The alternative solution of using an injection locking oscillator also has several disadvantages. Using an injection locking oscillator may only work for a very narrow frequency range. The rise-time/fall-time of the injection locking oscillator may have large variations over different frequencies. The injection locking oscillator also requires many stages to effectively cancel input clock mismatch. The duty cycle error of a clock may not be corrected and may sometimes increase. Further, the injection locking oscillator involves a difficult circuit layout that easily creates high systematic phase offset.
Furthermore, clock phase itself is difficult to control, and may involve adding a dedicated circuit.
The present disclosure provides solutions to one or more of the above-noted problems in conventional interleaved data converters.
A more complete appreciation of the disclosure and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:
Communications devices may process signals digitally for simplification in processing and reduction in power. Receivers in such communications devices may include an analog-to-digital converter (ADC) to convert the received analog signal to a digital signal for internal processing. Transmitters in such communications devices may include a digital-to-analog converter (DAC) to convert a digital signal to an analog signal for transmission. Such communications devices may include wireline or wireless communications devices as one of ordinary skill would recognize. Devices such as ADC and DAC may be operated by way of interleaved clocks. A clock phase mismatch can arise between a set of interleaved clocks, especially as the output frequency increases towards the Nyquist frequency.
An arrangement according to exemplary aspects, averages pairs of clocks to eliminate mismatch between interleaved clock signals An arrangement may be used to eliminate mismatch where the initial signal has amplitude mismatch, and an arrangement may be used to eliminate mismatch where the initial signal has phase mismatch.
Phase itself is difficult to control and may require a dedicated circuit such as a phase interpolator. However, an amplitude regulator circuit, such as a CMOS inverter, CML inverter, buffer, operational amplifier, can perform amplitude regulation. For example, as illustrated in
An aspect is one or more averaging stages, where each averaging stage converts the type of mismatch. For example, the averaging stages may convert from a phase mismatch to an amplitude mismatch, or convert from an amplitude mismatch to a phase mismatch. A final stage may be an averaging stage that converts to the amplitude mismatch. Any of the averaging stages may include amplitude regulators that reduce or eliminate amplitude mismatch.
In the exemplary aspect, the clock signals for the I channel signal and the Q channel are first passed through respective amplitude regulators 401.1 and 401.2 and combined to obtain an average clock signal of the I channel and the Q channel. Although 401.1, 401.2, 401.3, 401.4 are shown as buffers, any amplitude regulation circuits, such as CMOS inverters, CML inverters, operational amplifiers, may be incorporated as one of ordinary skill would recognize. The averaging of clock signals for I channel and Q channel converts a phase mismatch to an amplitude mismatch. The averaged signal may be passed to amplitude regulator 405.1 which clips the voltage at a threshold amplitude to obtain a clipped voltage signal I′. Also, the clock signals for the Q channel signal and the IB channel signal are first passed through respective amplitude regulators 401.2 and 401.3 and combined to obtain an average clock signal of the Q channel and the IB channel. The averaging of clock signals for Q channel and IB channel converts a phase mismatch to an amplitude mismatch. The averaged signal may be passed to amplitude regulator 405.2 which clips the voltage at a threshold amplitude to obtain a clipped voltage signal Q′. Also, the IB channel signal and the QB channel signal are first passed through respective amplitude regulators 401.3 and 401.4 and combined to obtain an average clock signal of the IB channel and the QB channel The averaging of clock signals of IB channel and QB channel converts a phase mismatch to an amplitude mismatch. The averaged signal may be passed to amplitude regulator 405.3 which clips the voltage at a threshold amplitude to obtain a clipped voltage signal IB′. Also, the clock signals for I channel and the QB channel are first passed through respective amplitude regulators 401.1 and 401.4 and combined to obtain an average clock signal of the I channel and the QB channel The averaging of clock signals of I channel and QB channel converts a phase mismatch to an amplitude mismatch. The averaged signal may be passed to amplitude regulator 405.4 which naturally clips the voltage at a threshold amplitude to obtain a clipped voltage signal QB′.
In the exemplary aspect, the clock signals for I channel and the Q channel are first passed through respective amplitude regulators 501.1 and 501.2 and combined to obtain an average of the clock signals of the I channel and the Q channel. The averaging of clock signals of I channel and Q channel converts an amplitude mismatch to a phase mismatch. The averaged signal may be passed to amplitude regulator 505.1. Also, the clock signals of the Q channel and the IB channel are first passed through respective amplitude regulators 501.2 and 501.3 and combined to obtain an average of the clock signals of the Q channel and the IB channel. The averaging of clock signals for Q channel and IB channel converts an amplitude mismatch to a phase mismatch. The averaged signal may be passed to amplitude regulator 505.2. Also, the clock signals of the IB channel and the QB channel are first passed through respective amplitude regulators 501.3 and 501.4 and combined to obtain an average of the clock signals of the IB channel and the QB channel. The averaging of clock signals of IB channel and QB channel converts an amplitude mismatch to a phase mismatch. The averaged signal may be passed to amplitude regulator 505.3. Also, the clock signals of the I channel and the QB channel are first passed through respective amplitude regulators 501.1 and 501.4 and combined to obtain an average of the clock signals of the I channel and the QB channel. The averaging of clock signals of the I channel and the QB channel converts an amplitude mismatch to a phase mismatch. The averaged signal may be passed to amplitude regulator 505.4.
The signals passed through amplitude regulators 505.1 and 505.2 are combined to obtain an average of the two signals. The averaging of the two signals converts a phase mismatch to an amplitude mismatch. The averaged signal may be passed to amplitude regulator 507.1 which naturally clips the voltage at a threshold amplitude to obtain a clipped voltage signal I′. The signals passed through amplitude regulators 505.2 and 505.3 are combined to obtain an average of the two signals. The averaging of the two signals converts a phase mismatch to an amplitude mismatch. The averaged signal may be passed to amplitude regulator 507.2 which naturally clips the voltage at a threshold amplitude to obtain a clipped voltage signal Q′. The signals passed through amplitude regulators 505.3 and 505.4 are combined to obtain an average of the two signals. The averaging of the two signals converts a phase mismatch to an amplitude mismatch. The averaged signal may be passed to amplitude regulator 507.3 which naturally clips the voltage at a threshold amplitude to obtain a clipped voltage signal IB′. The signals passed through amplitude regulators 505.1 and 505.4 are combined to obtain an average of the two signals. The averaging of the two signals converts a phase mismatch to an amplitude mismatch. The averaged signal may be passed to amplitude regulator 507.4 which naturally clips the voltage at a threshold amplitude to obtain a clipped voltage signal QB′.
Regarding
Data converters may be used to sample a variety of analog waveforms in the form of radio-frequency wave, sound waves, or voltage signals. An interleaved data converter is a core block that enables high-speed reception or transmission of the variety of waveforms. An interleaved data converter achieves high-speed reception or transmission by parallel data converters clocked by interleaved clocks.
Tones created from interleaved clock mismatch degrade the data converter's performance. For example, performance of a quarter-rate digital-to-analog converter (DAC) is degraded by a (Fout−Fs/2) tone when quadrature CK skew is present. Effective number of bits (ENOB) performance of a half-rate DAC with quadrature CK skew is degraded.
Communications devices may process signals digitally for simplification in processing and reduction in power. Receivers in such communications devices may include an analog-to-digital converter (ADC) to convert the received analog signal to a digital signal for internal processing. Transmitters in such communications devices may include a digital-to-analog converter (DAC) to convert a digital signal to an analog signal for transmission. Such communications devices may include wireline or wireless communications devices as one of ordinary skill would recognize.
A time-interleaved data converter is a type of core block that may be used as the ADC and DAC of a communications device that requires high-speed data transmission. A time-interleaved data converter is an effective way to implement a high sampling rate with a set of slow converters arranged in parallel. The set of converters operate at interleaved sampling times as if they were a single converter operating at a higher sampling rate. However, a clock phase mismatch can arise between the set of converters, especially as the output frequency increases towards the Nyquist frequency. In particular, tones created from interleaved clock mismatch degrade the data converter's performance.
The time interleaved ADC system may include an interleaving structure 703, sub-ADCs 705.1 through 705.i, and a switching module 607. The interleaving structure 703 samples the analog input 701 in accordance with multiple phases 0 to N-1 of a sampling clock to separate the analog input 701 into selected analog inputs. Each sub-ADC 705.1 to 705.i operates with one of the phase clocks (CK) 0 to N-1. The digital output samples are output as a single combined signal 709 which acts as though the sub-ADCs are a single ADC converter. A mismatch between clock phases, or phase skew, degrades the time interleaved ADC's performance
The averaging architecture of the present disclosure provides several advantages over other approaches to suppress phase mismatch. The averaging architecture reduces incoming phase skew. Only minimal startup calibration is required for interleaved clock adjustments to achieve ENOB performance
Also, SFDR (Spurious-Free Dynamic Range) is improved. Because a skew correction circuit may not be necessary, area and power for the clock circuits of a converter is significantly reduced. Unlike the case of using a skew correction circuit, there is no loading overhead at the highest frequency clock path.
The averaging architecture is scalable and can accommodate a wide frequency range, on the order of 64 GHz to 108 GHz. The averaging architecture enables data converters with sampling rates of greater than 100 GS/s.
A system which includes the features in the foregoing description provides numerous advantages. In particular, the DAC based transmitter described herein can achieve high speed and high performance simultaneously.
Numerous modifications and variations are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.
Thus, the foregoing discussion discloses and describes merely exemplary embodiments of the present invention. As will be understood by those skilled in the art, the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof Accordingly, the disclosure of the present invention is intended to be illustrative, but not limiting of the scope of the invention, as well as other claims. The disclosure, including any readily discernible variants of the teachings herein, defines, in pan, the scope of the foregoing claim terminology such that no inventive subject matter is dedicated to the public.
Claims
1. An apparatus, comprising:
- circuitry configured to provide multiple clock components of a sampling clock; average a pair of the multiple clock components to generate a first averaged signal; generate a corrected clock component by clipping an amplitude of the first averaged signal; and
- interleave corrected clock components for the respective multiple clock components.
2. An apparatus comprising:
- circuitry configured to provide multiple clock components of a sampling clock average pairs of the multiple clock components to generate first averaged signals; average pairs of the first averaged signals to generate second averaged signals; clip an amplitude of the second averaged signals to generate corrected clock components; and interleave corrected clock components for the respective multiple clock components.
3. The apparatus of claim 2, wherein
- the multiple clock components of the sampling clock have clock phase skew, and the circuitry is further configured to perform the averaging to generate the first averaged signals to convert amplitude mismatch to phase mismatch; perform the averaging to generate the second averaged signals to convert phase mismatch to amplitude mismatch; and clip the second averaged signal to eliminate the amplitude mismatch.
4. The apparatus of claim 1, wherein the clipping performed by the circuitry includes clipping a voltage signal by an amplitude regulator.
5. The apparatus of claim 4, wherein the amplitude regulator is a CMOS inverter.
6. The apparatus of claim 1, wherein the circuitry includes a plurality of analog-to-digital converters.
7. The apparatus of claim 6, wherein the circuitry is further configured to:
- sample an analog input for the corrected clock component to provide a sampled analog input;
- convert, in the plurality of analog-to-digital converters, sampled analog inputs from the analog signal domain to the digital signal domain in response to the sampling clock to provide digital output segments; and
- interleave the digital output segments to produce digital output samples.
8. The apparatus of claim 1, wherein the circuitry is included in a receiver.
9. The apparatus of claim 1, wherein the circuitry is included in a transmitter.
10. The apparatus of claim 1, wherein the circuitry includes a plurality of digital-to-analog converters.
11. The apparatus of claim 10, wherein the circuitry is further configured to:
- sample a digital input for a corresponding corrected clock component generated from the multiple clock components to provide a sampled digital input;
- convert, in parallel, the sampled digital inputs from the digital signal domain to the analog signal domain in response to the sampling clock to provide analog output segments; and
- interleave the analog output segments to produce digital output samples.
12. A method comprising:
- providing multiple clock components of a sampling clock;
- averaging a pair of the multiple clock components to generate a first averaged signal;
- generating a corrected clock component by clipping an amplitude of averaged signal; and
- interleave corrected clock components for the respective multiple clock components.
13. The method of claim 12, further comprising:
- converting an analog input to a digital signal.
14. The method of claim 13, further comprising:
- sampling the analog input for a corresponding corrected clock component generated from the multiple clock components to provide a sampled analog input;
- converting, in parallel, the sampled analog inputs from the analog signal domain to the digital signal domain in response to the sampling clock to provide digital output segments; and
- interleaving the digital output segments to produce digital output samples as the digital signal.
15. The method of claim 12, further comprising:
- converting a digital input to an analog signal.
16. The method of claim 15, further comprising:
- sampling the digital input for a corresponding corrected clock component generated from the multiple clock components to provide a sampled digital input;
- converting, in parallel, the sampled digital inputs from the digital signal domain to the analog signal domain in response to the sampling clock to provide analog output segments; and
- interleaving the analog output segments to produce analog output samples as the analog signal.
17. The method of claim 12, further comprising:
- driving an interleaved digital-to-analog converter by the interleaved corrected clock components.
18. The method of claim 12, further including averaging pairs of the first averaged signals in order to output a second averaged signal, clipping an amplitude of the second averaged signal, and outputting the clipped second averaged signal as the corrected clock component.
19. The method of claim 18, wherein the multiple clock components of the sampling clock have clock phase skew, the first averaging converts amplitude mismatch to phase mismatch, and the second averaging converts phase mismatch to amplitude mismatch, and the second averaged signal is clipped to eliminate the amplitude mismatch.
20. The method of claim 17, further comprising clipping a voltage signal by an amplitude regulator.
Type: Application
Filed: Oct 26, 2017
Publication Date: May 2, 2019
Applicant: Avago Technologies International Sales Pte. Limited (Singapore)
Inventors: Hyo Gyuem RHEW (Irvine, CA), Adesh GARG (Aliso Viejo, CA), Meisam Honarvar NAZARI (Irvine, CA), Jiawen ZHANG (Irvine, CA), Ali NAZEMI (Aliso Viejo, CA), Jun CAO (Irvine, CA)
Application Number: 15/794,667