Vertical FET with Sharp Junctions
VFET devices and techniques for formation thereof having well-defined, sharp source/drain-to-channel junctions are provided. In one aspect, a method of forming a VFET device includes: forming a SiGe layer on a substrate, wherein the SiGe layer as formed on the substrate is undoped; forming an Si layer on the SiGe layer, wherein the Si layer as formed on the SiGe layer is undoped; patterning fins in the Si layer; forming sacrificial spacers along sidewalls of the fins; forming recesses in the SiGe layer between the fins; growing an epitaxial material in the recesses, wherein the epitaxial material grown in the recesses includes a source and drain dopant; annealing the epitaxial material to diffuse the source drain dopant into the SiGe layer under the fins forming bottom source and drains of the VFET device; and removing the sacrificial spacers. A VFET device formed by the method is also provided.
This application is a divisional of U.S. application Ser. No. 15/713,975 filed on Sep. 25, 2017, the contents of which are incorporated by reference herein.
FIELD OF THE INVENTIONThe present invention relates to vertical field-effect transistor (VFET) devices, and more particularly, to VFET devices and techniques for formation thereof having well-defined, sharp source/drain-to-channel junctions.
BACKGROUND OF THE INVENTIONAs opposed to planar complementary metal oxide semiconductor (CMOS) devices, vertical field effect transistors (VFETs) are oriented with a vertical fin channel disposed on a bottom source/drain and a top source/drain disposed on the fin channel. VFETs are being explored as a viable device option for continued CMOS scaling beyond the 7 nanometer (nm) technology node.
A typical VFET device includes a vertical fin that extends upward from the substrate. The fin forms the channel region of the transistor. A source region and a drain region are situated in electrical contact with the top and bottom ends of the channel region, while the gate is disposed on one or more of the fin sidewalls. One challenge for fabricating VFET is to achieve a sharp junction and low extension resistance at the interface between the source/drain and the channel. One approach to form the bottom source/drain in a VFET process flow is via ion implantation. However, implantation of dopant species tends to damage the vertical fin channel.
Another approach to forming a VFET bottom source/drain is by thermally-driven diffusion. While thermally-driven diffusion of dopant species can avoid damaging the fin channel, the diffusion process can be difficult to control to achieve the desired sharp, well-defined junction.
Therefore, techniques are needed for forming a VFET device with sharp, well-defined junctions.
SUMMARY OF THE INVENTIONThe present invention provides vertical field-effect transistor (VFET) devices and techniques for formation thereof having well-defined, sharp source/drain-to-channel junctions. In one aspect of the invention, a method of forming a VFET device is provided. The method includes: forming a silicon germanium (SiGe) layer on a substrate, wherein the SiGe layer as formed on the substrate is undoped; forming a silicon (Si) layer on the SiGe layer, wherein the Si layer as formed on the SiGe layer is undoped; patterning fins in the Si layer; forming sacrificial spacers along sidewalls of the fins; forming recesses in the SiGe layer between the fins; growing an epitaxial material in the recesses, wherein the epitaxial material grown in the recesses includes a source and drain dopant; annealing the epitaxial material to diffuse the source drain dopant into the SiGe layer under the fins forming bottom source and drains of the VFET device; and removing the sacrificial spacers.
In another aspect of the invention, a VFET device is provided. The VFET device includes: a substrate; a SiGe layer disposed on the substrate; fins disposed on the SiGe layer, wherein the fins include undoped Si; recesses in the SiGe layer between the fins; and an epitaxial material in the recesses that includes a source and drain dopant, wherein the SiGe layer under the fins also includes the source and drain dopant and forms bottom source and drains of the VFET device.
A more complete understanding of the present invention, as well as further features and advantages of the present invention, will be obtained by reference to the following detailed description and drawings.
Provided herein are techniques for forming vertical field-effect transistor (FET) devices having well-defined source/drain-to-channel junctions. Of particular focus is the process for forming the bottom source/drain below the vertical channel. Referring to
One parameter for assessing the characteristics of the sharpness of the junction is junction width. See, for example,
As will be described in detail below, the present techniques involve forming the bottom source/drain at the beginning of the process (prior to forming the gate or top source/drain). Namely, following patterning of the fins that will serve as the vertical channels of the device, sacrificial spacers are then used to cover/protect the vertical fin channel while heavily doped epitaxial silicon (Si) is grown in recesses in the bottom source/drain between the fins. This doped epitaxial Si is used to dope the bottom source/drain through drive in diffusion. Due to a faster diffusion rate of dopants through the source/drain (as compared to the Si fin channel), sharp, well-defined junctions are produced.
An exemplary embodiment of the present techniques is now described for achieving the above-described sharp and well-defined source/drain-to-channel junctions is now described by way of reference to
A variety of different substrate 302 configurations can be implemented in accordance with the present techniques. For instance, according to one exemplary embodiment, the starting substrate 302 is a bulk semiconductor wafer, such as a bulk Si, bulk Ge and/or bulk SiGe wafer. Alternatively, the substrate 302 can be a semiconductor-on-insulator (SOI) wafer. In general, a SOI wafer includes a SOI layer separated from an underlying substrate by a buried insulator. When the buried insulator is an oxide it is often referred to as a buried oxide or BOX. The SOI layer can include any suitable semiconductor, such as Si, Ge and/or SiGe.
According to an exemplary embodiment, an epitaxial process is used to grow both the undoped SiGe layer 304 on the substrate 302 and the undoped Si layer 306 on the undoped SiGe layer 304. Accordingly, growth of the (epitaxial) SiGe and Si layers will be templated off of the underlying substrate 302. By way of example only, the undoped SiGe layer 304 is formed on the substrate 302 to a thickness of from about 3 nanometers (nm) to about 30 nm, and ranges therebetween, and the undoped Si layer 306 is formed on the undoped SiGe layer 304 to a thickness of from about 10 nm to about 50 nm, and ranges therebetween.
As will become apparent from the description that follows, the undoped Si layer 306 will be used to form the vertical fin channels, and the undoped SiGe layer 304 will be used to form the bottom source/drain. It is only after the bottom source/drain is formed that the gate and top source/drain will be formed.
Undoped Si layer 306 is then patterned to form at least one vertical fin channel of the VFET device. Standard lithography and etching techniques can be implemented to directly pattern the fins from a patterned fin hardmask. Other patterning techniques are also contemplated herein. For instance, a sidewall image transfer (SIT) technique is shown illustrated in the figures. An advantage to an SIT process is that SIT permits the patterning of feature sizes below that which can be achieved using direct patterning.
For instance, as shown in
Following patterning of the mandrels 402, sidewall spacers 404 are formed on opposite sides of the mandrels. See
Namely, as shown in
As shown in
The next task is to grow heavily doped epitaxial Si in between the fins 602 for source drain doping. However in order to protect the fins 602 during this process, sacrificial spacers 702 are first formed on opposite sides of each of the fins 602 along the sidewalls of the fins 602. See
As shown in
As shown in
Namely, as shown in
A thermally-driven diffusion of the source/drain dopant (e.g., phosphorous) from the source/drain epitaxial material 902 is then used to form source/drain extensions 1002 by diffusing the source/drain dopant into the SiGe layer 304 under the fins 602. See
Advantageously, the faster diffusion rate of the source/drain dopant (e.g., phosphorous) in the source/drain SiGe layer 304 as compared to in the Si of the fins 602 is leveraged to establish a sharp junction under the fins 602. See
By way of example only, the effective diffusivities of arsenic (As) and phosphorous (P) in both Si and SiGe under equilibrium conditions is shown illustrated in
Now that the bottom source/drains have been formed, the process to complete the VFET device involves forming gates alongside the fins 602 and source/drains on top of the fins 602. To enable these further processing steps, the sacrificial spacers 702 are now removed. See
A bottom spacer 1302 is then formed on the bottom source/drain. Bottom spacer 1302 will offset the gate (formed as described below) from the bottom source/drain. A counterpart top spacer will too be formed that separates the gate from the top source/drain. See below. Suitable materials for the bottom spacer 1302 include, but are not limited to, oxide spacer materials such as SiO2 and/or nitride spacer materials such as SiN.
According to an exemplary embodiment, the bottom spacers 1302 are formed using a directional deposition process whereby the spacer material is deposited onto the bottom source/drain and fins 602 with a greater amount of the material being deposited on the horizontal surfaces, as compared to the vertical surfaces. To use an illustrative example, a greater thickness of the spacer material will be deposited on top of the source/drain in between the fins 602 than along the sidewalls of the fins 602. Thus, when an etch is used on the spacer material, the timing of the etch needed to remove the spacer material from the vertical surfaces will leave the bottom spacers 1302 shown in
To form the gates of the VFET device, a gate dielectric 1402 is first deposited onto the fins 602 and bottom spacers 1302, followed by a gate conductor 1404. See
According to an exemplary embodiment, a metal gate is formed wherein the gate conductor 1404 is a metal or combination of metals and the gate dielectric 1402 is a high-κ dielectric. For instance, the gate conductor 1404 is a workfunction setting metal. The particular workfunction metal employed can vary depending on whether an n-type or p-type transistor is desired. Suitable n-type workfunction setting metals include, but are not limited to, titanium nitride (TiN), tantalum nitride (TaN) and/or aluminum (Al)-containing alloys such as titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), titanium aluminum carbide (TiAlC), tantalum aluminide (TaAl), tantalum aluminum nitride (TaAlN), and/or tantalum aluminum carbide (TaAlC). Suitable p-type workfunction setting metals include, but are not limited to, TiN, TaN, and tungsten (W). TiN and TaN are relatively thick (e.g., greater than about 2 nm) when used as p-type workfunction metals. However, very thin TiN or TaN layers (e.g., less than about 2 nm) may also be used beneath Al-containing alloys in n-type workfunction stacks to improve electrical properties such as gate leakage currents. Thus, there is some overlap in the exemplary n- and p-type workfunction metals given above.
The term “high-κ” as used herein refers to a material having a relative dielectric constant κ which is much higher than that of silicon dioxide (e.g., a dielectric constant κ=25 for HfO2 rather than 4 for silicon dioxide). Suitable high-κ gate dielectrics include, but are not limited to, hafnium oxide (HfO2) and/or lanthanum oxide (La2O3).
As shown in
As deposited, the OPL 1502 surrounds and fully covers the fins 602. See
As highlighted above, a counterpart top spacer is needed to offset the gate from the top source/drain. To form the top spacer, a spacer material 1802 is next deposited onto the spacers 404/fin hardmask and (recessed) OPL 1502. See
A planarizing etch such as chemical-mechanical polishing (CMP) is then used to remove the spacers 404/fin hardmask and with it excess spacer material 1802. The result is top spacers 1902 being formed in between the (now exposed) tops of the fins 602. See
In the above example, an n-type dopant (e.g., phosphorous) is used in the top/bottom source/drain to form an n-channel VFET device. As provided above, however, a dopant of the opposite polarity can instead be employed to form a p-channel VFET. The process for forming the p-channel VFET would be the same as that described above, except with a variation in the dopant employed for the source/drain, i.e., a p-type rather than n-type dopant. Suitable p-type dopants include, but are not limited to boron (B). Thus, for instance, as shown in
As provided above, the present techniques result in well-defined, sharp junctions between the bottom source/drain and the vertical fin channel. See, for example,
Although illustrative embodiments of the present invention have been described herein, it is to be understood that the invention is not limited to those precise embodiments, and that various other changes and modifications may be made by one skilled in the art without departing from the scope of the invention.
Claims
1. A vertical field-effect transistor (VFET) device, comprising:
- a substrate;
- a silicon germanium (SiGe) layer disposed on the substrate;
- fins disposed on the SiGe layer, wherein the fins comprise undoped silicon (Si);
- recesses in the SiGe layer between the fins; and
- an epitaxial material in the recesses that comprises a source and drain dopant,
- wherein the SiGe layer under the fins also comprises the source and drain dopant and forms bottom source and drains of the VFET device.
2. The VFET device of claim 1, wherein the source and drain dopant comprises phosphorous (P).
3. The VFET device of claim 2, wherein the epitaxial material in the recesses is selected from the group consisting of: Si:P and Si:C(P).
4. The VFET device of claim 1, wherein the source and drain dopant comprises boron (B).
5. The VFET device of claim 4, wherein the epitaxial material in the recesses comprises SiGe:B.
6. The VFET device of claim 1, wherein the epitaxial material in the recesses comprises the source and drain dopant at a concentration of from about 4×1020 atoms/cm3 to about 2×1021 atoms/cm3 and ranges therebetween.
7. The VFET device of claim 1, further comprising:
- a bottom spacer disposed on the bottom source and drains;
- a gate dielectric disposed on sidewalls of the fins and the bottom spacer;
- a gate conductor disposed on the gate dielectric;
- an organic planarizing layer (OPL) surrounding the fins;
- a top spacer disposed on the OPL in between the tops of the fins; and
- top source and drains of the VFET device formed on the tops of the fins,
- wherein the fins between the bottom source and drains and the top source and drains comprise vertical fin channels of the VFET device.
8. The VFET device of claim 7, wherein a top of the OPL is below tops of the fins.
9. The VFET device of claim 7, wherein the gate dielectric comprises a high-κ dielectric selected from the group consisting of: hafnium oxide (HfO2), lanthanum oxide (La2O3), and combinations thereof.
10. The VFET device of claim 7, wherein the gate conductor comprises a workfunction setting metal selected from the group consisting of: titanium nitride (TiN), tantalum nitride (TaN), an aluminum (Al)-containing alloy, titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), titanium aluminum carbide (TiAlC), tantalum aluminide (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), and combinations thereof.
11. The VFET device of claim 7, wherein the bottom spacer and the top spacer each comprises a material selected from the group consisting of: silicon oxide (SiO2), SiN, and combinations thereof.
12. The VFET device of claim 7, wherein the top source and drains comprise SiGe:P.
13. The VFET device of claim 7, wherein the top source and drains comprise SiGe:B.
14. A VFET device, comprising:
- a substrate;
- a SiGe layer disposed on the substrate;
- fins disposed on the SiGe layer, wherein the fins comprise undoped Si;
- recesses in the SiGe layer between the fins;
- an epitaxial material in the recesses that comprises a source and drain dopant, wherein the SiGe layer under the fins also comprises the source and drain dopant and forms bottom source and drains of the VFET device;
- a bottom spacer disposed on the bottom source and drains;
- a gate dielectric disposed on sidewalls of the fins and the bottom spacer;
- a gate conductor disposed on the gate dielectric;
- an OPL surrounding the fins;
- a top spacer disposed on the OPL in between the tops of the fins; and
- top source and drains of the VFET device formed on the tops of the fins, wherein the fins between the bottom source and drains and the top source and drains comprise vertical fin channels of the VFET device.
15. The VFET device of claim 14, wherein the source and drain dopant comprises phosphorous (P).
16. The VFET device of claim 15, wherein the epitaxial material in the recesses is selected from the group consisting of: Si:P and Si:C(P).
17. The VFET device of claim 14, wherein the source and drain dopant comprises boron (B).
18. The VFET device of claim 17, wherein the epitaxial material in the recesses comprises SiGe:B.
19. The VFET device of claim 14, wherein the epitaxial material in the recesses comprises the source and drain dopant at a concentration of from about 4×1020 atoms/cm3 to about 2×1021 atoms/cm3 and ranges therebetween.
20. The VFET device of claim 14, wherein a top of the OPL is below tops of the fins.
Type: Application
Filed: Jan 28, 2019
Publication Date: May 23, 2019
Inventors: Juntao Li (Cohoes, NY), Kangguo Cheng (Schenectady, NY), Peng Xu (Guilderland, NY), Heng Wu (Guilderland, NY)
Application Number: 16/259,412